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Red Hat Bugzilla – Attachment 669393 Details for
Bug 890434
[abrt] xorg-x11-server-Xorg-1.12.4-1.fc17: Xorg server crashed
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File: Xorg.0.log
Xorg.0.log (text/plain), 1.50 MB, created by
neil
on 2012-12-26 21:21:40 UTC
(
hide
)
Description:
File: Xorg.0.log
Filename:
MIME Type:
Creator:
neil
Created:
2012-12-26 21:21:40 UTC
Size:
1.50 MB
patch
obsolete
>[ 20.549] >X.Org X Server 1.12.4 >Release Date: 2012-08-27 >[ 20.549] X Protocol Version 11, Revision 0 >[ 20.549] Build Operating System: 2.6.32-279.9.1.el6.x86_64 >[ 20.549] Current Operating System: Linux fedora.httl.net 3.6.10-2.fc17.x86_64 #1 SMP Tue Dec 11 18:07:34 UTC 2012 x86_64 >[ 20.549] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.10-2.fc17.x86_64 root=/dev/mapper/vg_fedora-lv_root ro rd.md=0 rd.dm=0 SYSFONT=True rd.lvm.lv=vg_fedora/lv_swap rd.lvm.lv=vg_fedora/lv_root KEYTABLE=uk rd.luks=0 LANG=en_US.UTF-8 rhgb quiet >[ 20.549] Build Date: 28 November 2012 05:10:39PM >[ 20.549] Build ID: xorg-x11-server 1.12.4-1.fc17 >[ 20.549] Current version of pixman: 0.24.4 >[ 20.549] Before reporting problems, check http://wiki.x.org > to make sure that you have the latest version. >[ 20.549] Markers: (--) probed, (**) from config file, (==) default setting, > (++) from command line, (!!) notice, (II) informational, > (WW) warning, (EE) error, (NI) not implemented, (??) unknown. >[ 20.550] (==) Log file: "/var/log/Xorg.0.log", Time: Mon Dec 17 02:16:43 2012 >[ 20.556] (==) Using config directory: "/etc/X11/xorg.conf.d" >[ 20.556] (==) Using system config directory "/usr/share/X11/xorg.conf.d" >[ 20.565] (==) No Layout section. Using the first Screen section. >[ 20.566] (==) No screen section available. Using defaults. >[ 20.566] (**) |-->Screen "Default Screen Section" (0) >[ 20.566] (**) | |-->Monitor "<default monitor>" >[ 20.566] (==) No monitor specified for screen "Default Screen Section". > Using a default monitor configuration. >[ 20.566] (==) Automatically adding devices >[ 20.566] (==) Automatically enabling devices >[ 20.566] (==) FontPath set to: > catalogue:/etc/X11/fontpath.d, > built-ins >[ 20.566] (==) ModulePath set to "/usr/lib64/xorg/modules" >[ 20.566] (II) The server relies on udev to provide the list of input devices. > If no devices become available, reconfigure udev or disable AutoAddDevices. >[ 20.566] (II) Loader magic: 0x7c6ac0 >[ 20.566] (II) Module ABI versions: >[ 20.566] X.Org ANSI C Emulation: 0.4 >[ 20.566] X.Org Video Driver: 12.1 >[ 20.566] X.Org XInput driver : 16.0 >[ 20.566] X.Org Server Extension : 6.0 >[ 20.568] (--) PCI:*(0:1:5:0) 1002:9616:1043:8388 rev 0, Mem @ 0xd0000000/268435456, 0xfeaf0000/65536, 0xfe900000/1048576, I/O @ 0x0000d000/256, BIOS @ 0x????????/131072 >[ 20.569] (II) LoadModule: "extmod" >[ 20.602] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so >[ 20.610] (II) Module extmod: vendor="X.Org Foundation" >[ 20.610] compiled for 1.12.4, module version = 1.0.0 >[ 20.610] Module class: X.Org Server Extension >[ 20.610] ABI class: X.Org Server Extension, version 6.0 >[ 20.610] (II) Loading extension SELinux >[ 20.610] (II) Loading extension MIT-SCREEN-SAVER >[ 20.610] (II) Loading extension XFree86-VidModeExtension >[ 20.610] (II) Loading extension XFree86-DGA >[ 20.610] (II) Loading extension DPMS >[ 20.610] (II) Loading extension XVideo >[ 20.610] (II) Loading extension XVideo-MotionCompensation >[ 20.610] (II) Loading extension X-Resource >[ 20.610] (II) LoadModule: "dbe" >[ 20.610] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so >[ 20.617] (II) Module dbe: vendor="X.Org Foundation" >[ 20.617] compiled for 1.12.4, module version = 1.0.0 >[ 20.617] Module class: X.Org Server Extension >[ 20.617] ABI class: X.Org Server Extension, version 6.0 >[ 20.617] (II) Loading extension DOUBLE-BUFFER >[ 20.617] (II) LoadModule: "glx" >[ 20.617] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so >[ 20.633] (II) Module glx: vendor="X.Org Foundation" >[ 20.633] compiled for 1.12.4, module version = 1.0.0 >[ 20.633] ABI class: X.Org Server Extension, version 6.0 >[ 20.633] (==) AIGLX enabled >[ 20.633] (II) Loading extension GLX >[ 20.633] (II) LoadModule: "record" >[ 20.634] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so >[ 20.676] (II) Module record: vendor="X.Org Foundation" >[ 20.676] compiled for 1.12.4, module version = 1.13.0 >[ 20.676] Module class: X.Org Server Extension >[ 20.676] ABI class: X.Org Server Extension, version 6.0 >[ 20.676] (II) Loading extension RECORD >[ 20.676] (II) LoadModule: "dri" >[ 20.677] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so >[ 20.696] (II) Module dri: vendor="X.Org Foundation" >[ 20.696] compiled for 1.12.4, module version = 1.0.0 >[ 20.696] ABI class: X.Org Server Extension, version 6.0 >[ 20.696] (II) Loading extension XFree86-DRI >[ 20.696] (II) LoadModule: "dri2" >[ 20.698] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so >[ 20.699] (II) Module dri2: vendor="X.Org Foundation" >[ 20.699] compiled for 1.12.4, module version = 1.2.0 >[ 20.699] ABI class: X.Org Server Extension, version 6.0 >[ 20.699] (II) Loading extension DRI2 >[ 20.699] (==) Matched ati as autoconfigured driver 0 >[ 20.699] (==) Matched vesa as autoconfigured driver 1 >[ 20.699] (==) Matched modesetting as autoconfigured driver 2 >[ 20.699] (==) Matched fbdev as autoconfigured driver 3 >[ 20.699] (==) Assigned the driver to the xf86ConfigLayout >[ 20.699] (II) LoadModule: "ati" >[ 20.699] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so >[ 20.699] (II) Module ati: vendor="X.Org Foundation" >[ 20.699] compiled for 1.12.0, module version = 6.14.99 >[ 20.699] Module class: X.Org Video Driver >[ 20.699] ABI class: X.Org Video Driver, version 12.0 >[ 20.699] (II) LoadModule: "radeon" >[ 20.700] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so >[ 20.704] (II) Module radeon: vendor="X.Org Foundation" >[ 20.704] compiled for 1.12.0, module version = 6.14.99 >[ 20.704] Module class: X.Org Video Driver >[ 20.704] ABI class: X.Org Video Driver, version 12.0 >[ 20.704] (II) LoadModule: "vesa" >[ 20.705] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so >[ 20.705] (II) Module vesa: vendor="X.Org Foundation" >[ 20.705] compiled for 1.12.0, module version = 2.3.1 >[ 20.705] Module class: X.Org Video Driver >[ 20.705] ABI class: X.Org Video Driver, version 12.0 >[ 20.705] (II) LoadModule: "modesetting" >[ 20.714] (WW) Warning, couldn't open module modesetting >[ 20.714] (II) UnloadModule: "modesetting" >[ 20.714] (II) Unloading modesetting >[ 20.714] (EE) Failed to load module "modesetting" (module does not exist, 0) >[ 20.714] (II) LoadModule: "fbdev" >[ 20.714] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so >[ 20.714] (II) Module fbdev: vendor="X.Org Foundation" >[ 20.714] compiled for 1.11.99.901, module version = 0.4.2 >[ 20.714] ABI class: X.Org Video Driver, version 12.0 >[ 20.714] (II) RADEON: Driver for ATI Radeon chipsets: > ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI), > ATI Radeon Mobility X300 (M24) 3152 (PCIE), > ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI), > ATI Radeon X600 (RV380) 3E50 (PCIE), > ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136, > ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP), > ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), > ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP), > ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), > ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP), > ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), > ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650, > ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237, > ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336, > ATI Radeon IGP330M/340M/350M (U2) 4337, > ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI), > ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP), > ATI Radeon X800PRO (R420) JI (AGP), > ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), > ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), > ATI Radeon Mobility 9800 (M18) JN (AGP), > ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP), > ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP), > ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP), > ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP), > ATI Radeon Mobility M7 LW (AGP), > ATI Mobility FireGL 7800 M7 LX (AGP), > ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), > ATI FireGL Mobility 9000 (M9) Ld (AGP), > ATI Radeon Mobility 9000 (M9) Lf (AGP), > ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI, > ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), > ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP), > ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), > ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), > ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), > ATI Radeon Mobility 9600 (M10) NQ (AGP), > ATI Radeon Mobility 9600 (M11) NR (AGP), > ATI Radeon Mobility 9600 (M10) NS (AGP), > ATI FireGL Mobility T2 (M10) NT (AGP), > ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP), > ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), > ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), > ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI), > ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI), > ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI), > ATI Radeon Mobility X300 (M22) 5460 (PCIE), > ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE), > ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE), > ATI Radeon X800PRO (R423) UI (PCIE), > ATI Radeon X800LE (R423) UJ (PCIE), > ATI Radeon X800SE (R423) UK (PCIE), > ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE), > ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE), > ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE), > ATI FireGL unknown (R423) UR (PCIE), > ATI FireGL unknown (R423) UT (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility Radeon X700 XL (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834, > ATI Radeon Mobility 9100 IGP (U3) 5835, > ATI Radeon XPRESS 200 5954 (PCIE), > ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP), > ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), > ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI), > ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE), > ATI Radeon XPRESS 200M 5975 (PCIE), > ATI Radeon XPRESS 200 5A41 (PCIE), > ATI Radeon XPRESS 200M 5A42 (PCIE), > ATI Radeon XPRESS 200 5A61 (PCIE), > ATI Radeon XPRESS 200M 5A62 (PCIE), > ATI Radeon X300 (RV370) 5B60 (PCIE), > ATI Radeon X600 (RV370) 5B62 (PCIE), > ATI Radeon X550 (RV370) 5B63 (PCIE), > ATI FireGL V3100 (RV370) 5B64 (PCIE), > ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), > ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), > ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), > ATI Mobility Radeon X800 XT (M28) (PCIE), > ATI Mobility FireGL V5100 (M28) (PCIE), > ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE), > ATI Radeon X850 XT PE (R480) (PCIE), > ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE), > ATI unknown Radeon / FireGL (R480) 5D50 (PCIE), > ATI Radeon X850 XT (R480) (PCIE), > ATI Radeon X800XT (R423) 5D57 (PCIE), > ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE), > ATI Radeon X700 PRO (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800, > ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800, > ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300, > ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800, > ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800, > ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505, > ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL, > ATI Mobility Radeon X1400, ATI Radeon X1300/X1550, > ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Mobility Radeon X1300, > ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300, > ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350, > ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550, > ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450, > ATI Radeon X1300/X1550, ATI Mobility Radeon X2300, > ATI Mobility Radeon X2300, ATI Mobility Radeon X1350, > ATI Mobility Radeon X1350, ATI Mobility Radeon X1450, > ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350, > ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600, > ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600, > ATI Mobility FireGL V5200, ATI Mobility Radeon X1600, > ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600, > ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400, > ATI Mobility FireGL V5250, ATI Mobility Radeon X1700, > ATI Mobility Radeon X1700 XT, ATI FireGL V5200, > ATI Mobility Radeon X1700, ATI Radeon X2300HD, > ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300, > ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900, > ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950, > ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560, > ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400, > ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560, > ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835, > ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200, > ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740, > ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT, > ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT, > ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600, > ATI Radeon 4800 Series, ATI Radeon HD 4870 x2, > ATI Radeon 4800 Series, ATI Radeon HD 4850 x2, > ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL), > ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2, > ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270, > AMD FireStream 9250, ATI FirePro V8700 (FireGL), > ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98, > ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series, > ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98, > ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP), > ATI Mobility Radeon HD 4670, ATI FirePro M5750, > ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP), > ATI RV730XT [Radeon HD 4670], ATI RADEON E4600, > ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650], > ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL), > ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830, > ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740, > ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770, > ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT, > ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000, > ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT, > ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610, > ATI FireMV 2260, ATI RV670, ATI Radeon HD3870, > ATI Mobility Radeon HD 3850, ATI Radeon HD3850, > ATI Mobility Radeon HD 3850 X2, ATI RV670, > ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2, > ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850, > ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550, > ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710, > ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series, > ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series, > ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630, > ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT, > ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP, > ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630, > ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600, > ATI FireGL V3600, ATI Radeon HD 2600 LE, > ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470, > ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series, > ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430, > ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450, > ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series, > ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO, > ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO, > ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670, > ATI Mobility FireGL V5700, ATI Mobility FireGL V5725, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics, > ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics, > ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2, > SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200, > ATI Radeon 4100, ATI Mobility Radeon HD 4200, > ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250, > AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics, > AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics, > AMD Radeon HD 6300 Series Graphics, > AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370, > AMD Firestream 9350, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series, > ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series, > ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series, > ATI Mobility Radeon HD 5800 Series, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, > ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670, > ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD, > ATI Mobility Radeon HD 5000 Series, > ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics, > ATI Mobility Radeon Graphics, CEDAR, > ATI FirePro (FireGL) Graphics Adapter, > ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR, > ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, > AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN, > CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series, > BARTS, BARTS, Mobility Radeon HD 6000 Series, > Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS, > AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series, > AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, > CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA, > ARUBA, ARUBA, ARUBA, ARUBA >[ 20.723] (II) VESA: driver for VESA chipsets: vesa >[ 20.723] (II) FBDEV: driver for framebuffer: fbdev >[ 20.723] (++) using VT number 1 > >[ 20.725] (II) [KMS] Kernel modesetting enabled. >[ 20.725] (WW) Falling back to old probe method for vesa >[ 20.725] (WW) Falling back to old probe method for fbdev >[ 20.725] (II) Loading sub module "fbdevhw" >[ 20.725] (II) LoadModule: "fbdevhw" >[ 20.725] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so >[ 20.725] (II) Module fbdevhw: vendor="X.Org Foundation" >[ 20.725] compiled for 1.12.4, module version = 0.0.2 >[ 20.725] ABI class: X.Org Video Driver, version 12.1 >[ 20.725] (II) RADEON(0): RADEONPreInit_KMS >[ 20.725] (II) RADEON(0): Creating default Display subsection in Screen section > "Default Screen Section" for depth/fbbpp 24/32 >[ 20.725] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32 >[ 20.727] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) >[ 20.727] (==) RADEON(0): Default visual is TrueColor >[ 20.727] (==) RADEON(0): RGB weight 888 >[ 20.727] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) >[ 20.727] (--) RADEON(0): Chipset: "ATI Radeon 3000 Graphics" (ChipID = 0x9616) >[ 20.727] (II) RADEON(0): PCI card detected >[ 20.727] drmOpenDevice: node name is /dev/dri/card0 >[ 20.727] drmOpenDevice: open result is 8, (OK) >[ 20.727] drmOpenByBusid: Searching for BusID pci:0000:01:05.0 >[ 20.727] drmOpenDevice: node name is /dev/dri/card0 >[ 20.727] drmOpenDevice: open result is 8, (OK) >[ 20.727] drmOpenByBusid: drmOpenMinor returns 8 >[ 20.727] drmOpenByBusid: drmGetBusid reports pci:0000:01:05.0 >[ 20.727] (II) Loading sub module "exa" >[ 20.727] (II) LoadModule: "exa" >[ 20.727] (II) Loading /usr/lib64/xorg/modules/libexa.so >[ 20.732] (II) Module exa: vendor="X.Org Foundation" >[ 20.732] compiled for 1.12.4, module version = 2.5.0 >[ 20.732] ABI class: X.Org Video Driver, version 12.1 >[ 20.732] (II) RADEON(0): KMS Color Tiling: enabled >[ 20.732] (II) RADEON(0): KMS Pageflipping: enabled >[ 20.732] (II) RADEON(0): SwapBuffers wait for vsync: enabled >[ 20.763] (II) RADEON(0): Output VGA-0 has no monitor section >[ 20.764] (II) RADEON(0): Output DVI-0 has no monitor section >[ 20.795] (II) RADEON(0): EDID for output VGA-0 >[ 20.795] (II) RADEON(0): Manufacturer: DEL Model: 4025 Serial#: 808862796 >[ 20.795] (II) RADEON(0): Year: 2007 Week: 36 >[ 20.795] (II) RADEON(0): EDID Version: 1.3 >[ 20.795] (II) RADEON(0): Analog Display Input, Input Voltage Level: 0.700/0.700 V >[ 20.795] (II) RADEON(0): Sync: Separate >[ 20.795] (II) RADEON(0): Max Image Size [cm]: horiz.: 38 vert.: 30 >[ 20.795] (II) RADEON(0): Gamma: 2.20 >[ 20.795] (II) RADEON(0): DPMS capabilities: Off; RGB/Color Display >[ 20.795] (II) RADEON(0): Default color space is primary color space >[ 20.795] (II) RADEON(0): First detailed timing is preferred mode >[ 20.795] (II) RADEON(0): redX: 0.640 redY: 0.330 greenX: 0.300 greenY: 0.600 >[ 20.795] (II) RADEON(0): blueX: 0.150 blueY: 0.080 whiteX: 0.313 whiteY: 0.329 >[ 20.795] (II) RADEON(0): Supported established timings: >[ 20.795] (II) RADEON(0): 720x400@70Hz >[ 20.795] (II) RADEON(0): 640x480@60Hz >[ 20.795] (II) RADEON(0): 640x480@75Hz >[ 20.795] (II) RADEON(0): 800x600@60Hz >[ 20.795] (II) RADEON(0): 800x600@75Hz >[ 20.795] (II) RADEON(0): 1024x768@60Hz >[ 20.795] (II) RADEON(0): 1024x768@75Hz >[ 20.795] (II) RADEON(0): 1280x1024@75Hz >[ 20.795] (II) RADEON(0): Manufacturer's mask: 0 >[ 20.795] (II) RADEON(0): Supported standard timings: >[ 20.795] (II) RADEON(0): #0: hsize: 1152 vsize 864 refresh: 75 vid: 20337 >[ 20.795] (II) RADEON(0): #1: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 >[ 20.795] (II) RADEON(0): Supported detailed timing: >[ 20.795] (II) RADEON(0): clock: 108.0 MHz Image Size: 376 x 301 mm >[ 20.795] (II) RADEON(0): h_active: 1280 h_sync: 1328 h_sync_end 1440 h_blank_end 1688 h_border: 0 >[ 20.795] (II) RADEON(0): v_active: 1024 v_sync: 1025 v_sync_end 1028 v_blanking: 1066 v_border: 0 >[ 20.795] (II) RADEON(0): Serial No: UW53879506DL >[ 20.795] (II) RADEON(0): Monitor name: DELL 1908FP >[ 20.795] (II) RADEON(0): Ranges: V min: 56 V max: 76 Hz, H min: 31 H max: 83 kHz, PixClock max 145 MHz >[ 20.795] (II) RADEON(0): EDID (in hex): >[ 20.795] (II) RADEON(0): 00ffffffffffff0010ac25404c443630 >[ 20.796] (II) RADEON(0): 2411010368261e782eeea5a3544c9926 >[ 20.796] (II) RADEON(0): 145054a54b00714f8180010101010101 >[ 20.796] (II) RADEON(0): 010101010101302a009851002a403070 >[ 20.796] (II) RADEON(0): 1300782d1100001e000000ff00555735 >[ 20.796] (II) RADEON(0): 33383739353036444c0a000000fc0044 >[ 20.796] (II) RADEON(0): 454c4c203139303846500a20000000fd >[ 20.796] (II) RADEON(0): 00384c1f530e000a202020202020009c >[ 20.796] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 20.796] (II) RADEON(0): Using EDID range info for horizontal sync >[ 20.796] (II) RADEON(0): Using EDID range info for vertical refresh >[ 20.796] (II) RADEON(0): Printing DDC gathered Modelines: >[ 20.796] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 20.796] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 20.796] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 20.796] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 20.796] (II) RADEON(0): Printing probed modes for output VGA-0 >[ 20.796] (II) RADEON(0): Modeline "1280x1024"x60.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 20.796] (II) RADEON(0): Modeline "1280x1024"x75.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x960"x60.0 108.00 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync (60.0 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x800"x74.9 106.50 1280 1360 1488 1696 800 803 809 838 -hsync +vsync (62.8 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x800"x59.8 83.50 1280 1352 1480 1680 800 803 809 831 +hsync -vsync (49.7 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1152x864"x75.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x768"x74.9 102.25 1280 1360 1488 1696 768 771 778 805 +hsync -vsync (60.3 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1280x768"x59.9 79.50 1280 1344 1472 1664 768 771 778 798 -hsync +vsync (47.8 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x768"x75.1 78.80 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.1 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x768"x70.1 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (56.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 20.796] (II) RADEON(0): Modeline "1024x576"x60.0 46.97 1024 1064 1168 1312 576 577 580 597 -hsync +vsync (35.8 kHz) >[ 20.796] (II) RADEON(0): Modeline "800x600"x72.2 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (48.1 kHz e) >[ 20.796] (II) RADEON(0): Modeline "800x600"x75.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 20.796] (II) RADEON(0): Modeline "800x600"x60.3 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 20.796] (II) RADEON(0): Modeline "800x600"x56.2 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (35.2 kHz e) >[ 20.796] (II) RADEON(0): Modeline "848x480"x60.0 33.75 848 864 976 1088 480 486 494 517 +hsync +vsync (31.0 kHz e) >[ 20.796] (II) RADEON(0): Modeline "640x480"x72.8 31.50 640 664 704 832 480 489 492 520 -hsync -vsync (37.9 kHz e) >[ 20.796] (II) RADEON(0): Modeline "640x480"x75.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "640x480"x60.0 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 20.796] (II) RADEON(0): Modeline "720x400"x70.1 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 20.798] (II) RADEON(0): EDID for output DVI-0 >[ 20.798] (II) RADEON(0): Output VGA-0 connected >[ 20.798] (II) RADEON(0): Output DVI-0 disconnected >[ 20.798] (II) RADEON(0): Using exact sizes for initial modes >[ 20.798] (II) RADEON(0): Output VGA-0 using initial mode 1280x1024 +0+0 >[ 20.798] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated. >[ 20.798] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:10000000 visible:fac0000 >[ 20.798] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM >[ 20.798] (**) RADEON(0): Display dimensions: (380, 300) mm >[ 20.798] (**) RADEON(0): DPI set to (85, 86) >[ 20.798] (II) Loading sub module "fb" >[ 20.798] (II) LoadModule: "fb" >[ 20.798] (II) Loading /usr/lib64/xorg/modules/libfb.so >[ 20.801] (II) Module fb: vendor="X.Org Foundation" >[ 20.801] compiled for 1.12.4, module version = 1.0.0 >[ 20.801] ABI class: X.Org ANSI C Emulation, version 0.4 >[ 20.801] (II) Loading sub module "ramdac" >[ 20.801] (II) LoadModule: "ramdac" >[ 20.801] (II) Module "ramdac" already built-in >[ 20.801] (II) UnloadModule: "vesa" >[ 20.801] (II) Unloading vesa >[ 20.801] (II) UnloadModule: "fbdev" >[ 20.801] (II) Unloading fbdev >[ 20.801] (II) UnloadSubModule: "fbdevhw" >[ 20.801] (II) Unloading fbdevhw >[ 20.801] (--) Depth 24 pixmap format is 32 bpp >[ 20.802] (II) RADEON(0): [DRI2] Setup complete >[ 20.802] (II) RADEON(0): [DRI2] DRI driver: r600 >[ 20.802] (II) RADEON(0): [DRI2] VDPAU driver: r600 >[ 20.802] (II) RADEON(0): Front buffer size: 5120K >[ 20.802] (II) RADEON(0): VRAM usage limit set to 226483K >[ 20.802] (II) RADEON(0): Initializing backing store >[ 20.802] (==) RADEON(0): Backing store disabled >[ 20.802] (II) RADEON(0): Direct rendering enabled >[ 20.802] (II) RADEON(0): Initializing Acceleration >[ 20.802] (II) RADEON(0): Setting EXA maxPitchBytes >[ 20.802] (II) EXA(0): Driver allocated offscreen pixmaps >[ 20.802] (II) EXA(0): Driver registered support for the following operations: >[ 20.803] (II) Solid >[ 20.803] (II) Copy >[ 20.803] (II) Composite (RENDER acceleration) >[ 20.803] (II) UploadToScreen >[ 20.803] (II) DownloadFromScreen >[ 20.803] (II) RADEON(0): Acceleration enabled >[ 20.803] (II) RADEON(0): Initializing DPMS >[ 20.803] (==) RADEON(0): DPMS enabled >[ 20.803] (II) RADEON(0): Initializing Cursor >[ 20.803] (==) RADEON(0): Silken mouse enabled >[ 20.803] (II) RADEON(0): Initializing Xv >[ 20.803] (II) RADEON(0): Set up textured video >[ 20.803] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video. >[ 20.803] (II) RADEON(0): [XvMC] Extension initialized. >[ 20.803] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message. >[ 20.803] (II) RADEON(0): Initializing kms color map >[ 20.803] (II) RADEON(0): RADEONScreenInit finished >[ 20.803] (--) RandR disabled >[ 20.803] (II) Initializing built-in extension Generic Event Extension >[ 20.803] (II) Initializing built-in extension SHAPE >[ 20.803] (II) Initializing built-in extension MIT-SHM >[ 20.803] (II) Initializing built-in extension XInputExtension >[ 20.803] (II) Initializing built-in extension XTEST >[ 20.803] (II) Initializing built-in extension BIG-REQUESTS >[ 20.803] (II) Initializing built-in extension SYNC >[ 20.803] (II) Initializing built-in extension XKEYBOARD >[ 20.803] (II) Initializing built-in extension XC-MISC >[ 20.804] (II) Initializing built-in extension XINERAMA >[ 20.804] (II) Initializing built-in extension XFIXES >[ 20.804] (II) Initializing built-in extension RENDER >[ 20.804] (II) Initializing built-in extension RANDR >[ 20.804] (II) Initializing built-in extension COMPOSITE >[ 20.804] (II) Initializing built-in extension DAMAGE >[ 20.806] (II) SELinux: Disabled by boolean >[ 21.393] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer >[ 21.393] (II) AIGLX: enabled GLX_INTEL_swap_event >[ 21.393] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control >[ 21.393] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects >[ 21.393] (II) AIGLX: Loaded and initialized r600 >[ 21.393] (II) GLX: Initialized DRI2 GL provider for screen 0 >[ 21.394] (II) RADEON(0): Setting screen physical size to 338 x 270 >[ 21.494] (II) XKB: Reusing cached keymap >[ 21.500] (II) config/udev: Adding input device Power Button (/dev/input/event1) >[ 21.500] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 21.500] (II) LoadModule: "evdev" >[ 21.500] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so >[ 21.500] (II) Module evdev: vendor="X.Org Foundation" >[ 21.500] compiled for 1.12.0, module version = 2.7.0 >[ 21.501] Module class: X.Org XInput Driver >[ 21.501] ABI class: X.Org XInput driver, version 16.0 >[ 21.501] (II) Using input driver 'evdev' for 'Power Button' >[ 21.501] Option "XkbRules" "evdev" >[ 21.501] Option "XkbModel" "evdev" >[ 21.501] Option "XkbLayout" "us" >[ 21.501] Option "_source" "server/udev" >[ 21.501] Option "name" "Power Button" >[ 21.501] Option "path" "/dev/input/event1" >[ 21.501] Option "device" "/dev/input/event1" >[ 21.501] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 21.501] Option "driver" "evdev" >[ 21.501] (**) Power Button: always reports core events >[ 21.501] (**) evdev: Power Button: Device: "/dev/input/event1" >[ 21.501] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 21.501] (--) evdev: Power Button: Found keys >[ 21.501] (II) evdev: Power Button: Configuring as keyboard >[ 21.501] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1" >[ 21.501] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6) >[ 21.501] (**) Option "xkb_rules" "evdev" >[ 21.501] (**) Option "xkb_model" "evdev" >[ 21.501] (**) Option "xkb_layout" "us" >[ 21.530] (II) config/udev: Adding input device Power Button (/dev/input/event0) >[ 21.530] (**) Power Button: Applying InputClass "evdev keyboard catchall" >[ 21.530] (II) Using input driver 'evdev' for 'Power Button' >[ 21.530] Option "XkbRules" "evdev" >[ 21.530] Option "XkbModel" "evdev" >[ 21.530] Option "XkbLayout" "us" >[ 21.530] Option "_source" "server/udev" >[ 21.530] Option "name" "Power Button" >[ 21.530] Option "path" "/dev/input/event0" >[ 21.530] Option "device" "/dev/input/event0" >[ 21.530] Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 21.530] Option "driver" "evdev" >[ 21.530] (**) Power Button: always reports core events >[ 21.530] (**) evdev: Power Button: Device: "/dev/input/event0" >[ 21.530] (--) evdev: Power Button: Vendor 0 Product 0x1 >[ 21.530] (--) evdev: Power Button: Found keys >[ 21.530] (II) evdev: Power Button: Configuring as keyboard >[ 21.530] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0" >[ 21.530] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7) >[ 21.530] (**) Option "xkb_rules" "evdev" >[ 21.530] (**) Option "xkb_model" "evdev" >[ 21.530] (**) Option "xkb_layout" "us" >[ 21.530] (II) XKB: Reusing cached keymap >[ 21.531] (II) config/udev: Adding input device HDA ATI HDMI HDMI/DP,pcm=3 (/dev/input/event12) >[ 21.532] (II) No input driver specified, ignoring this device. >[ 21.532] (II) This device may have been added with another device file. >[ 21.532] (II) config/udev: Adding input device USB Optical Mouse (/dev/input/event3) >[ 21.532] (**) USB Optical Mouse: Applying InputClass "evdev pointer catchall" >[ 21.532] (II) Using input driver 'evdev' for 'USB Optical Mouse' >[ 21.532] Option "XkbRules" "evdev" >[ 21.532] Option "XkbModel" "evdev" >[ 21.532] Option "XkbLayout" "us" >[ 21.532] Option "_source" "server/udev" >[ 21.532] Option "name" "USB Optical Mouse" >[ 21.532] Option "path" "/dev/input/event3" >[ 21.532] Option "device" "/dev/input/event3" >[ 21.532] Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.1/usb4/4-2/4-2:1.0/input/input3/event3" >[ 21.532] Option "driver" "evdev" >[ 21.532] (**) USB Optical Mouse: always reports core events >[ 21.532] (**) evdev: USB Optical Mouse: Device: "/dev/input/event3" >[ 21.533] (--) evdev: USB Optical Mouse: absolute axis 0x28 [255..0] >[ 21.533] (--) evdev: USB Optical Mouse: Vendor 0x1bcf Product 0x7 >[ 21.533] (--) evdev: USB Optical Mouse: Found 3 mouse buttons >[ 21.533] (--) evdev: USB Optical Mouse: Found scroll wheel(s) >[ 21.533] (--) evdev: USB Optical Mouse: Found relative axes >[ 21.533] (--) evdev: USB Optical Mouse: Found x and y relative axes >[ 21.533] (--) evdev: USB Optical Mouse: Found absolute axes >[ 21.533] (II) evdev: USB Optical Mouse: Forcing absolute x/y axes to exist. >[ 21.533] (II) evdev: USB Optical Mouse: Configuring as mouse >[ 21.533] (II) evdev: USB Optical Mouse: Adding scrollwheel support >[ 21.533] (**) evdev: USB Optical Mouse: YAxisMapping: buttons 4 and 5 >[ 21.533] (**) evdev: USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200 >[ 21.533] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:12.1/usb4/4-2/4-2:1.0/input/input3/event3" >[ 21.533] (II) XINPUT: Adding extended input device "USB Optical Mouse" (type: MOUSE, id 8) >[ 21.533] (II) evdev: USB Optical Mouse: initialized for relative axes. >[ 21.533] (WW) evdev: USB Optical Mouse: ignoring absolute axes. >[ 21.533] (**) USB Optical Mouse: (accel) keeping acceleration scheme 1 >[ 21.533] (**) USB Optical Mouse: (accel) acceleration profile 0 >[ 21.533] (**) USB Optical Mouse: (accel) acceleration factor: 2.000 >[ 21.533] (**) USB Optical Mouse: (accel) acceleration threshold: 4 >[ 21.533] (II) config/udev: Adding input device USB Optical Mouse (/dev/input/mouse0) >[ 21.533] (II) No input driver specified, ignoring this device. >[ 21.533] (II) This device may have been added with another device file. >[ 21.535] (II) config/udev: Adding input device HDA ATI SB Line Out Surround (/dev/input/event10) >[ 21.535] (II) No input driver specified, ignoring this device. >[ 21.535] (II) This device may have been added with another device file. >[ 21.535] (II) config/udev: Adding input device HDA ATI SB Line Out Front (/dev/input/event11) >[ 21.535] (II) No input driver specified, ignoring this device. >[ 21.535] (II) This device may have been added with another device file. >[ 21.536] (II) config/udev: Adding input device HDA ATI SB Line (/dev/input/event4) >[ 21.536] (II) No input driver specified, ignoring this device. >[ 21.536] (II) This device may have been added with another device file. >[ 21.536] (II) config/udev: Adding input device HDA ATI SB Front Mic (/dev/input/event5) >[ 21.536] (II) No input driver specified, ignoring this device. >[ 21.537] (II) This device may have been added with another device file. >[ 21.537] (II) config/udev: Adding input device HDA ATI SB Rear Mic (/dev/input/event6) >[ 21.537] (II) No input driver specified, ignoring this device. >[ 21.537] (II) This device may have been added with another device file. >[ 21.538] (II) config/udev: Adding input device HDA ATI SB Front Headphone (/dev/input/event7) >[ 21.538] (II) No input driver specified, ignoring this device. >[ 21.538] (II) This device may have been added with another device file. >[ 21.538] (II) config/udev: Adding input device HDA ATI SB Line Out Side (/dev/input/event8) >[ 21.538] (II) No input driver specified, ignoring this device. >[ 21.538] (II) This device may have been added with another device file. >[ 21.539] (II) config/udev: Adding input device HDA ATI SB Line Out CLFE (/dev/input/event9) >[ 21.539] (II) No input driver specified, ignoring this device. >[ 21.539] (II) This device may have been added with another device file. >[ 21.539] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event2) >[ 21.539] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall" >[ 21.539] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard' >[ 21.539] Option "XkbRules" "evdev" >[ 21.539] Option "XkbModel" "evdev" >[ 21.539] Option "XkbLayout" "us" >[ 21.539] Option "_source" "server/udev" >[ 21.539] Option "name" "AT Translated Set 2 keyboard" >[ 21.539] Option "path" "/dev/input/event2" >[ 21.540] Option "device" "/dev/input/event2" >[ 21.540] Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2" >[ 21.540] Option "driver" "evdev" >[ 21.540] (**) AT Translated Set 2 keyboard: always reports core events >[ 21.540] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event2" >[ 21.540] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1 >[ 21.540] (--) evdev: AT Translated Set 2 keyboard: Found keys >[ 21.540] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard >[ 21.540] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input2/event2" >[ 21.540] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 9) >[ 21.540] (**) Option "xkb_rules" "evdev" >[ 21.540] (**) Option "xkb_model" "evdev" >[ 21.540] (**) Option "xkb_layout" "us" >[ 21.540] (II) XKB: Reusing cached keymap >[ 21.547] (II) RADEON(0): RADEONSaveScreen(2) >[ 21.581] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 21.581] (II) RADEON(0): Using hsync ranges from config file >[ 21.581] (II) RADEON(0): Using vrefresh ranges from config file >[ 21.581] (II) RADEON(0): Printing DDC gathered Modelines: >[ 21.581] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 21.581] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 21.581] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 21.581] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 21.581] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 21.581] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 21.581] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 21.581] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 21.581] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 21.581] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 23.176] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 23.176] (II) RADEON(0): Using hsync ranges from config file >[ 23.176] (II) RADEON(0): Using vrefresh ranges from config file >[ 23.176] (II) RADEON(0): Printing DDC gathered Modelines: >[ 23.176] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 23.176] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 23.176] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 23.176] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 23.176] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 23.176] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 23.176] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 23.176] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 23.176] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 23.176] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 25.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd880] >[ 25.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd880] width 1280 pitch 5120 (/4 1280) >[ 25.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd880] >[ 25.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd880] width 1280 pitch 5120 (/4 1280) >[ 25.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bda30] >[ 25.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bda30] width 1280 pitch 5120 (/4 1280) >[ 25.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bda30] >[ 25.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bda30] width 1280 pitch 5120 (/4 1280) >[ 25.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bda30] >[ 25.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bda30] width 1280 pitch 5120 (/4 1280) >[ 25.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd8e0] >[ 25.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd8e0] width 1280 pitch 5120 (/4 1280) >[ 25.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bda30] >[ 25.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bda30] width 1280 pitch 5120 (/4 1280) >[ 25.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 25.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 25.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 25.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 25.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 26.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf850] >[ 26.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf850] width 1280 pitch 5120 (/4 1280) >[ 26.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 26.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 37.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 37.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 38.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd880] >[ 38.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd880] width 1280 pitch 5120 (/4 1280) >[ 98.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 98.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 158.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd880] >[ 158.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd880] width 1280 pitch 5120 (/4 1280) >[ 218.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf7f0] >[ 218.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf7f0] width 1280 pitch 5120 (/4 1280) >[ 278.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bd880] >[ 278.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bd880] width 1280 pitch 5120 (/4 1280) >[ 314.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 314.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 314.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 314.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 314.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 315.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 315.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 315.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 315.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 316.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 316.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 316.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 316.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 316.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 316.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 316.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 316.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 317.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 317.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 317.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 317.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 317.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 317.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 317.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 317.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 318.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 318.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 318.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 318.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 318.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 318.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 318.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 318.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 318.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 318.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 318.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf8a0] >[ 318.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf8a0] width 1280 pitch 5120 (/4 1280) >[ 319.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26bf900] >[ 319.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26bf900] width 1280 pitch 5120 (/4 1280) >[ 321.017] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 321.017] (II) RADEON(0): Using hsync ranges from config file >[ 321.017] (II) RADEON(0): Using vrefresh ranges from config file >[ 321.017] (II) RADEON(0): Printing DDC gathered Modelines: >[ 321.017] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 321.017] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 321.017] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 321.017] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 321.017] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 321.017] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 321.017] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 321.017] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 321.017] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 321.017] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 322.686] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 322.686] (II) RADEON(0): Using hsync ranges from config file >[ 322.686] (II) RADEON(0): Using vrefresh ranges from config file >[ 322.686] (II) RADEON(0): Printing DDC gathered Modelines: >[ 322.686] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 322.686] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 322.686] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 322.686] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 322.686] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 322.686] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 322.686] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 322.686] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 322.686] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 322.686] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 322.751] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 322.751] (II) RADEON(0): Using hsync ranges from config file >[ 322.751] (II) RADEON(0): Using vrefresh ranges from config file >[ 322.751] (II) RADEON(0): Printing DDC gathered Modelines: >[ 322.752] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 322.752] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 322.752] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 322.752] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 322.752] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 322.752] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 322.752] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 322.752] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 322.752] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 322.752] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 329.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31277a0] >[ 329.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31277a0] width 1280 pitch 5120 (/4 1280) >[ 329.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127740] >[ 329.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127740] width 1280 pitch 5120 (/4 1280) >[ 329.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31277a0] >[ 329.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31277a0] width 1280 pitch 5120 (/4 1280) >[ 330.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b3c0] >[ 330.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b3c0] width 1280 pitch 5120 (/4 1280) >[ 332.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 332.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 332.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 332.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 332.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 332.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 332.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 332.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 332.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 332.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 332.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 332.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b400] >[ 333.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b400] width 1280 pitch 5120 (/4 1280) >[ 333.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312bad0] >[ 333.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312bad0] width 1280 pitch 5120 (/4 1280) >[ 333.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b4b0] >[ 333.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b4b0] width 1280 pitch 5120 (/4 1280) >[ 333.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312ce50] >[ 333.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312ce50] width 1280 pitch 5120 (/4 1280) >[ 333.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d1590] >[ 333.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d1590] width 1280 pitch 5120 (/4 1280) >[ 333.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312ce50] >[ 333.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312ce50] width 1280 pitch 5120 (/4 1280) >[ 333.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d1590] >[ 334.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d1590] width 1280 pitch 5120 (/4 1280) >[ 334.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3133990] >[ 334.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3133990] width 1280 pitch 5120 (/4 1280) >[ 334.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 334.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 335.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3378950] >[ 335.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3378950] width 1280 pitch 5120 (/4 1280) >[ 336.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 336.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 337.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 337.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 337.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 337.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 338.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313eff0] >[ 338.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313eff0] width 1280 pitch 5120 (/4 1280) >[ 338.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31314e0] >[ 338.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31314e0] width 1280 pitch 5120 (/4 1280) >[ 340.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314a740] >[ 340.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314a740] width 1280 pitch 5120 (/4 1280) >[ 344.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195690] >[ 344.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195690] width 1280 pitch 5120 (/4 1280) >[ 344.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161ef0] >[ 344.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161ef0] width 1280 pitch 5120 (/4 1280) >[ 344.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195690] >[ 344.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195690] width 1280 pitch 5120 (/4 1280) >[ 344.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 344.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 344.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31285f0] >[ 344.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31285f0] width 1280 pitch 5120 (/4 1280) >[ 344.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 344.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 344.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161ef0] >[ 344.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161ef0] width 1280 pitch 5120 (/4 1280) >[ 344.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 344.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 344.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161ef0] >[ 344.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161ef0] width 1280 pitch 5120 (/4 1280) >[ 344.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 344.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 344.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31285f0] >[ 344.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31285f0] width 1280 pitch 5120 (/4 1280) >[ 344.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 344.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 344.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31285f0] >[ 344.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31285f0] width 1280 pitch 5120 (/4 1280) >[ 344.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195690] >[ 345.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195690] width 1280 pitch 5120 (/4 1280) >[ 345.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 345.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 345.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31379b0] >[ 345.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31379b0] width 1280 pitch 5120 (/4 1280) >[ 345.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3136590] >[ 345.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3136590] width 1280 pitch 5120 (/4 1280) >[ 345.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31912b0] >[ 345.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31912b0] width 1280 pitch 5120 (/4 1280) >[ 345.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163cb0] >[ 345.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163cb0] width 1280 pitch 5120 (/4 1280) >[ 345.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314fb90] >[ 345.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314fb90] width 1280 pitch 5120 (/4 1280) >[ 345.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163cb0] >[ 345.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163cb0] width 1280 pitch 5120 (/4 1280) >[ 345.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314fb90] >[ 345.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314fb90] width 1280 pitch 5120 (/4 1280) >[ 345.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163cb0] >[ 345.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163cb0] width 1280 pitch 5120 (/4 1280) >[ 345.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314fb90] >[ 345.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314fb90] width 1280 pitch 5120 (/4 1280) >[ 345.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163cb0] >[ 345.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163cb0] width 1280 pitch 5120 (/4 1280) >[ 345.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314fb90] >[ 345.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314fb90] width 1280 pitch 5120 (/4 1280) >[ 345.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163cb0] >[ 345.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163cb0] width 1280 pitch 5120 (/4 1280) >[ 345.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31637c0] >[ 346.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31637c0] width 1280 pitch 5120 (/4 1280) >[ 346.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3143b60] >[ 346.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3143b60] width 1280 pitch 5120 (/4 1280) >[ 346.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a3ea0] >[ 346.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a3ea0] width 1280 pitch 5120 (/4 1280) >[ 346.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155100] >[ 346.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155100] width 1280 pitch 5120 (/4 1280) >[ 347.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a73c0] >[ 347.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a73c0] width 1280 pitch 5120 (/4 1280) >[ 347.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 347.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 347.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155100] >[ 348.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155100] width 1280 pitch 5120 (/4 1280) >[ 348.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155100] >[ 348.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155100] width 1280 pitch 5120 (/4 1280) >[ 348.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a59d0] >[ 348.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a59d0] width 1280 pitch 5120 (/4 1280) >[ 348.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 348.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313b470] >[ 348.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313b470] width 1280 pitch 5120 (/4 1280) >[ 348.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 348.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 350.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3154b20] >[ 350.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3154b20] width 1280 pitch 5120 (/4 1280) >[ 350.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195690] >[ 350.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195690] width 1280 pitch 5120 (/4 1280) >[ 352.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155440] >[ 352.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155440] width 1280 pitch 5120 (/4 1280) >[ 353.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a3e30] >[ 353.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a3e30] width 1280 pitch 5120 (/4 1280) >[ 353.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a3ee0] >[ 353.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a3ee0] width 1280 pitch 5120 (/4 1280) >[ 353.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a3e30] >[ 353.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a3e30] width 1280 pitch 5120 (/4 1280) >[ 353.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4e40] >[ 353.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4e40] width 1280 pitch 5120 (/4 1280) >[ 404.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f870] >[ 404.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f870] width 1280 pitch 5120 (/4 1280) >[ 404.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32eede0] >[ 404.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32eede0] width 1280 pitch 5120 (/4 1280) >[ 404.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce4e0] >[ 404.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce4e0] width 1280 pitch 5120 (/4 1280) >[ 404.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f870] >[ 404.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f870] width 1280 pitch 5120 (/4 1280) >[ 404.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322f870] >[ 404.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322f870] width 1280 pitch 5120 (/4 1280) >[ 404.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce230] >[ 404.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce230] width 1280 pitch 5120 (/4 1280) >[ 404.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ef100] >[ 404.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ef100] width 1280 pitch 5120 (/4 1280) >[ 404.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32eedf0] >[ 404.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32eedf0] width 1280 pitch 5120 (/4 1280) >[ 404.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ef100] >[ 404.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ef100] width 1280 pitch 5120 (/4 1280) >[ 404.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32eedf0] >[ 404.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32eedf0] width 1280 pitch 5120 (/4 1280) >[ 404.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ef100] >[ 404.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ef100] width 1280 pitch 5120 (/4 1280) >[ 404.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32eedf0] >[ 404.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32eedf0] width 1280 pitch 5120 (/4 1280) >[ 405.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324a650] >[ 405.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324a650] width 1280 pitch 5120 (/4 1280) >[ 405.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330a280] >[ 405.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330a280] width 1280 pitch 5120 (/4 1280) >[ 405.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d030] >[ 405.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d030] width 1280 pitch 5120 (/4 1280) >[ 405.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bad0] >[ 405.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bad0] width 1280 pitch 5120 (/4 1280) >[ 405.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d030] >[ 405.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d030] width 1280 pitch 5120 (/4 1280) >[ 405.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bad0] >[ 405.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bad0] width 1280 pitch 5120 (/4 1280) >[ 405.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d030] >[ 405.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d030] width 1280 pitch 5120 (/4 1280) >[ 405.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bad0] >[ 405.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bad0] width 1280 pitch 5120 (/4 1280) >[ 405.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d030] >[ 405.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d030] width 1280 pitch 5120 (/4 1280) >[ 405.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bad0] >[ 405.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bad0] width 1280 pitch 5120 (/4 1280) >[ 405.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d890] >[ 405.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d890] width 1280 pitch 5120 (/4 1280) >[ 405.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32abd60] >[ 406.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32abd60] width 1280 pitch 5120 (/4 1280) >[ 406.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d890] >[ 406.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d890] width 1280 pitch 5120 (/4 1280) >[ 406.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32abd60] >[ 406.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32abd60] width 1280 pitch 5120 (/4 1280) >[ 406.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d890] >[ 406.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d890] width 1280 pitch 5120 (/4 1280) >[ 1240.201] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 1240.201] (II) RADEON(0): Using hsync ranges from config file >[ 1240.201] (II) RADEON(0): Using vrefresh ranges from config file >[ 1240.201] (II) RADEON(0): Printing DDC gathered Modelines: >[ 1240.201] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 1240.201] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 1240.201] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 1330.539] (II) RADEON(0): RADEONSaveScreen(2) >[ 1330.539] (II) RADEON(0): RADEONSaveScreen(0) >[ 2805.555] (II) RADEON(0): RADEONSaveScreen(1) >[ 3495.536] (II) RADEON(0): RADEONSaveScreen(2) >[ 3495.536] (II) RADEON(0): RADEONSaveScreen(0) >[ 23994.503] (II) RADEON(0): RADEONSaveScreen(1) >[ 23994.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370d5b0] >[ 23994.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370d5b0] width 1280 pitch 5120 (/4 1280) >[ 23997.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cde90] >[ 23997.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cde90] width 1280 pitch 5120 (/4 1280) >[ 23998.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375b0f0] >[ 23998.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375b0f0] width 1280 pitch 5120 (/4 1280) >[ 23998.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23998.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23998.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23998.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 23998.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23998.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23998.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23998.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 23998.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23998.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23998.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23998.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 23998.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23998.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23999.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23999.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 23999.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23999.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23999.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23999.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 23999.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63650] >[ 23999.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63650] width 1280 pitch 5120 (/4 1280) >[ 23999.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3718990] >[ 23999.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3718990] width 1280 pitch 5120 (/4 1280) >[ 23999.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eef0] >[ 23999.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eef0] width 1280 pitch 5120 (/4 1280) >[ 24000.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c900d0] >[ 24000.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c900d0] width 1280 pitch 5120 (/4 1280) >[ 24000.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90130] >[ 24000.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90130] width 1280 pitch 5120 (/4 1280) >[ 24000.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ee190] >[ 24000.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ee190] width 1280 pitch 5120 (/4 1280) >[ 24000.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4a30] >[ 24000.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4a30] width 1280 pitch 5120 (/4 1280) >[ 24000.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e49d0] >[ 24000.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e49d0] width 1280 pitch 5120 (/4 1280) >[ 24000.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edbe0] >[ 24000.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edbe0] width 1280 pitch 5120 (/4 1280) >[ 24000.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 24000.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 24000.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 24000.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 24000.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 24000.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 24000.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 24000.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 24000.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 24000.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 24000.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24000.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24000.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1de0] >[ 24000.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1de0] width 1280 pitch 5120 (/4 1280) >[ 24001.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90130] >[ 24001.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90130] width 1280 pitch 5120 (/4 1280) >[ 24001.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332a1e0] >[ 24001.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332a1e0] width 1280 pitch 5120 (/4 1280) >[ 24001.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24001.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24001.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24001.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24001.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24001.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24001.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24001.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24001.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24001.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24001.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24001.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24001.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24001.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24001.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24001.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24001.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393a90] >[ 24002.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393a90] width 1280 pitch 5120 (/4 1280) >[ 24002.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24002.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33924a0] >[ 24002.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33924a0] width 1280 pitch 5120 (/4 1280) >[ 24002.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24002.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33924a0] >[ 24002.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33924a0] width 1280 pitch 5120 (/4 1280) >[ 24002.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24002.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33924a0] >[ 24002.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33924a0] width 1280 pitch 5120 (/4 1280) >[ 24002.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24002.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33924a0] >[ 24002.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33924a0] width 1280 pitch 5120 (/4 1280) >[ 24002.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24002.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24002.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24002.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24002.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31110c0] >[ 24002.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31110c0] width 1280 pitch 5120 (/4 1280) >[ 24002.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393270] >[ 24002.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393270] width 1280 pitch 5120 (/4 1280) >[ 24005.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24005.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24005.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24005.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[ 24005.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[ 24005.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24005.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24005.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6190] >[ 24005.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6190] width 1280 pitch 5120 (/4 1280) >[ 24005.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb8650] >[ 24005.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb8650] width 1280 pitch 5120 (/4 1280) >[ 24006.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8d4b0] >[ 24006.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8d4b0] width 1280 pitch 5120 (/4 1280) >[ 24009.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c800e0] >[ 24009.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c800e0] width 1280 pitch 5120 (/4 1280) >[ 24009.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f6d0] >[ 24009.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f6d0] width 1280 pitch 5120 (/4 1280) >[ 24009.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337db00] >[ 24010.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337db00] width 1280 pitch 5120 (/4 1280) >[ 24010.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c82640] >[ 24010.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c82640] width 1280 pitch 5120 (/4 1280) >[ 24655.553] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 24655.554] (II) RADEON(0): Using hsync ranges from config file >[ 24655.554] (II) RADEON(0): Using vrefresh ranges from config file >[ 24655.554] (II) RADEON(0): Printing DDC gathered Modelines: >[ 24655.554] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 24655.554] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 24655.554] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 24745.535] (II) RADEON(0): RADEONSaveScreen(2) >[ 24745.535] (II) RADEON(0): RADEONSaveScreen(0) >[ 26099.628] (II) RADEON(0): RADEONSaveScreen(1) >[ 26102.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c93380] >[ 26102.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c93380] width 1280 pitch 5120 (/4 1280) >[ 26105.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c817a0] >[ 26105.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c817a0] width 1280 pitch 5120 (/4 1280) >[ 26106.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f660] >[ 26106.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f660] width 1280 pitch 5120 (/4 1280) >[ 26106.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64890] >[ 26106.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64890] width 1280 pitch 5120 (/4 1280) >[ 26106.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37323a0] >[ 26106.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37323a0] width 1280 pitch 5120 (/4 1280) >[ 26106.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26106.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26106.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37323a0] >[ 26106.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37323a0] width 1280 pitch 5120 (/4 1280) >[ 26106.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26106.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26106.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37323a0] >[ 26106.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37323a0] width 1280 pitch 5120 (/4 1280) >[ 26106.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c825e0] >[ 26106.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c825e0] width 1280 pitch 5120 (/4 1280) >[ 26106.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c93380] >[ 26106.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c93380] width 1280 pitch 5120 (/4 1280) >[ 26106.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f660] >[ 26106.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f660] width 1280 pitch 5120 (/4 1280) >[ 26107.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c93380] >[ 26107.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c93380] width 1280 pitch 5120 (/4 1280) >[ 26107.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c825e0] >[ 26107.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c825e0] width 1280 pitch 5120 (/4 1280) >[ 26107.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f660] >[ 26107.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f660] width 1280 pitch 5120 (/4 1280) >[ 26107.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26107.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26107.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26107.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65880] >[ 26107.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65880] width 1280 pitch 5120 (/4 1280) >[ 26111.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f660] >[ 26111.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f660] width 1280 pitch 5120 (/4 1280) >[ 26113.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26113.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26113.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3384cf0] >[ 26113.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3384cf0] width 1280 pitch 5120 (/4 1280) >[ 26113.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ac850] >[ 26113.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ac850] width 1280 pitch 5120 (/4 1280) >[ 26113.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161ef0] >[ 26113.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161ef0] width 1280 pitch 5120 (/4 1280) >[ 26113.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314cc40] >[ 26113.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314cc40] width 1280 pitch 5120 (/4 1280) >[ 26113.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3161ef0] >[ 26113.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3161ef0] width 1280 pitch 5120 (/4 1280) >[ 26114.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314cc40] >[ 26114.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314cc40] width 1280 pitch 5120 (/4 1280) >[ 26572.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa9e0] >[ 26572.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa9e0] width 1280 pitch 5120 (/4 1280) >[ 26574.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ad0e0] >[ 26574.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ad0e0] width 1280 pitch 5120 (/4 1280) >[ 26574.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eb00] >[ 26574.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eb00] width 1280 pitch 5120 (/4 1280) >[ 26579.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375eb00] >[ 26579.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375eb00] width 1280 pitch 5120 (/4 1280) >[ 26579.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e3b60] >[ 26579.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e3b60] width 1280 pitch 5120 (/4 1280) >[ 26579.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ef030] >[ 26579.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ef030] width 1280 pitch 5120 (/4 1280) >[ 26579.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eb080] >[ 26579.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eb080] width 1280 pitch 5120 (/4 1280) >[ 26623.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371bcd0] >[ 26623.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371bcd0] width 1280 pitch 5120 (/4 1280) >[ 26624.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344000] >[ 26624.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344000] width 1280 pitch 5120 (/4 1280) >[ 26624.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3256020] >[ 26624.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3256020] width 1280 pitch 5120 (/4 1280) >[ 26624.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344000] >[ 26624.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344000] width 1280 pitch 5120 (/4 1280) >[ 26625.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c65050] >[ 26625.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c65050] width 1280 pitch 5120 (/4 1280) >[ 26625.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[ 26625.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[ 26625.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[ 26625.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[ 26625.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[ 26625.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[ 26626.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e3bd0] >[ 26626.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e3bd0] width 1280 pitch 5120 (/4 1280) >[ 26626.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385a10] >[ 26626.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385a10] width 1280 pitch 5120 (/4 1280) >[ 26626.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d6f70] >[ 26626.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d6f70] width 1280 pitch 5120 (/4 1280) >[ 26626.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d6f70] >[ 26626.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d6f70] width 1280 pitch 5120 (/4 1280) >[ 26679.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[ 26679.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[ 26679.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3760b60] >[ 26679.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3760b60] width 1280 pitch 5120 (/4 1280) >[ 26719.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fdc0] >[ 26719.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fdc0] width 1280 pitch 5120 (/4 1280) >[ 26719.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314ef40] >[ 26719.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314ef40] width 1280 pitch 5120 (/4 1280) >[ 26719.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67860] >[ 26719.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67860] width 1280 pitch 5120 (/4 1280) >[ 26719.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337fdc0] >[ 26719.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337fdc0] width 1280 pitch 5120 (/4 1280) >[ 26728.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33820e0] >[ 26728.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33820e0] width 1280 pitch 5120 (/4 1280) >[ 26728.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30fd9f0] >[ 26728.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30fd9f0] width 1280 pitch 5120 (/4 1280) >[ 26728.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33822c0] >[ 26728.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33822c0] width 1280 pitch 5120 (/4 1280) >[ 26728.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33822c0] >[ 26728.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33822c0] width 1280 pitch 5120 (/4 1280) >[ 26855.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 26855.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 26855.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b1b0] >[ 26855.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b1b0] width 1280 pitch 5120 (/4 1280) >[ 26855.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b1b0] >[ 26855.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b1b0] width 1280 pitch 5120 (/4 1280) >[ 26856.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69710] >[ 26856.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69710] width 1280 pitch 5120 (/4 1280) >[ 26856.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 26856.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 26856.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 26856.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 27498.859] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 27498.859] (II) RADEON(0): Using hsync ranges from config file >[ 27498.859] (II) RADEON(0): Using vrefresh ranges from config file >[ 27498.859] (II) RADEON(0): Printing DDC gathered Modelines: >[ 27498.859] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 27498.859] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 27498.860] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 27589.553] (II) RADEON(0): RADEONSaveScreen(2) >[ 27589.554] (II) RADEON(0): RADEONSaveScreen(0) >[ 32277.107] (II) RADEON(0): RADEONSaveScreen(1) >[ 32277.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3708830] >[ 32277.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3708830] width 1280 pitch 5120 (/4 1280) >[ 32982.537] (II) RADEON(0): RADEONSaveScreen(2) >[ 32982.537] (II) RADEON(0): RADEONSaveScreen(0) >[ 66720.729] (II) RADEON(0): RADEONSaveScreen(1) >[ 66723.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3329f90] >[ 66723.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3329f90] width 1280 pitch 5120 (/4 1280) >[ 66729.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb6050] >[ 66729.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb6050] width 1280 pitch 5120 (/4 1280) >[ 69752.514] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 69752.514] (II) RADEON(0): Using hsync ranges from config file >[ 69752.514] (II) RADEON(0): Using vrefresh ranges from config file >[ 69752.514] (II) RADEON(0): Printing DDC gathered Modelines: >[ 69752.514] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 69752.514] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 69752.514] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 69842.536] (II) RADEON(0): RADEONSaveScreen(2) >[ 69842.536] (II) RADEON(0): RADEONSaveScreen(0) >[ 70085.309] (II) RADEON(0): RADEONSaveScreen(1) >[ 70327.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7ed10] >[ 70327.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7ed10] width 1280 pitch 5120 (/4 1280) >[ 70775.540] (II) RADEON(0): RADEONSaveScreen(2) >[ 70775.540] (II) RADEON(0): RADEONSaveScreen(0) >[ 72098.693] (II) RADEON(0): RADEONSaveScreen(1) >[ 72792.537] (II) RADEON(0): RADEONSaveScreen(2) >[ 72792.537] (II) RADEON(0): RADEONSaveScreen(0) >[ 81260.702] (II) RADEON(0): RADEONSaveScreen(1) >[ 81454.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ae1b0] >[ 81454.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ae1b0] width 1280 pitch 5120 (/4 1280) >[ 81457.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324dc90] >[ 81457.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324dc90] width 1280 pitch 5120 (/4 1280) >[ 81457.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d400] >[ 81457.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d400] width 1280 pitch 5120 (/4 1280) >[ 81457.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324df20] >[ 81457.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324df20] width 1280 pitch 5120 (/4 1280) >[ 81457.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d400] >[ 81457.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d400] width 1280 pitch 5120 (/4 1280) >[ 81457.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324df20] >[ 81457.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324df20] width 1280 pitch 5120 (/4 1280) >[ 81457.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d400] >[ 81457.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d400] width 1280 pitch 5120 (/4 1280) >[ 81457.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324df20] >[ 81457.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324df20] width 1280 pitch 5120 (/4 1280) >[ 81457.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d400] >[ 81457.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d400] width 1280 pitch 5120 (/4 1280) >[ 81457.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cc80] >[ 81457.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cc80] width 1280 pitch 5120 (/4 1280) >[ 81457.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d400] >[ 81457.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d400] width 1280 pitch 5120 (/4 1280) >[ 81457.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cc80] >[ 81457.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cc80] width 1280 pitch 5120 (/4 1280) >[ 81460.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3149ce0] >[ 81460.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3149ce0] width 1280 pitch 5120 (/4 1280) >[ 81460.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3378950] >[ 81460.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3378950] width 1280 pitch 5120 (/4 1280) >[ 81460.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90610] >[ 81460.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90610] width 1280 pitch 5120 (/4 1280) >[ 81460.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 81460.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 81460.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90610] >[ 81460.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90610] width 1280 pitch 5120 (/4 1280) >[ 81460.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 81460.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 81460.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90610] >[ 81460.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90610] width 1280 pitch 5120 (/4 1280) >[ 81460.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 81460.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 81460.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90610] >[ 81460.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90610] width 1280 pitch 5120 (/4 1280) >[ 81460.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 81460.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 81460.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 81460.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 81460.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81460.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81460.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 81461.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 81463.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc7810] >[ 81463.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc7810] width 1280 pitch 5120 (/4 1280) >[ 81464.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81464.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81464.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81464.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81464.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81465.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81465.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81465.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81465.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81465.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81465.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81465.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81465.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81465.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81465.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81465.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81465.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81465.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81465.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81465.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81465.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81465.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81465.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81465.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eac70] >[ 81465.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eac70] width 1280 pitch 5120 (/4 1280) >[ 81466.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3111060] >[ 81466.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3111060] width 1280 pitch 5120 (/4 1280) >[ 81466.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313f830] >[ 81466.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313f830] width 1280 pitch 5120 (/4 1280) >[ 81466.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc7a90] >[ 81466.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc7a90] width 1280 pitch 5120 (/4 1280) >[ 81466.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ad040] >[ 81466.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ad040] width 1280 pitch 5120 (/4 1280) >[ 81466.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc7a90] >[ 81466.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc7a90] width 1280 pitch 5120 (/4 1280) >[ 81466.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ad040] >[ 81466.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ad040] width 1280 pitch 5120 (/4 1280) >[ 81466.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313f090] >[ 81466.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313f090] width 1280 pitch 5120 (/4 1280) >[ 81466.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32acd00] >[ 81466.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32acd00] width 1280 pitch 5120 (/4 1280) >[ 81466.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3740820] >[ 81466.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3740820] width 1280 pitch 5120 (/4 1280) >[ 81466.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32acd00] >[ 81466.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32acd00] width 1280 pitch 5120 (/4 1280) >[ 81466.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3740820] >[ 81466.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3740820] width 1280 pitch 5120 (/4 1280) >[ 81466.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313f090] >[ 81466.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313f090] width 1280 pitch 5120 (/4 1280) >[ 81466.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344af0] >[ 81466.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344af0] width 1280 pitch 5120 (/4 1280) >[ 81466.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313f090] >[ 81466.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313f090] width 1280 pitch 5120 (/4 1280) >[ 81466.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344af0] >[ 81466.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344af0] width 1280 pitch 5120 (/4 1280) >[ 81466.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313f090] >[ 81466.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313f090] width 1280 pitch 5120 (/4 1280) >[ 81468.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71450] >[ 81468.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71450] width 1280 pitch 5120 (/4 1280) >[ 81476.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371b980] >[ 81476.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371b980] width 1280 pitch 5120 (/4 1280) >[ 81476.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31609a0] >[ 81476.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31609a0] width 1280 pitch 5120 (/4 1280) >[ 81476.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313aa50] >[ 81476.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313aa50] width 1280 pitch 5120 (/4 1280) >[ 81476.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314a120] >[ 81476.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314a120] width 1280 pitch 5120 (/4 1280) >[ 81476.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713a0] >[ 81476.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713a0] width 1280 pitch 5120 (/4 1280) >[ 81476.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70740] >[ 81476.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70740] width 1280 pitch 5120 (/4 1280) >[ 81476.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713a0] >[ 81476.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713a0] width 1280 pitch 5120 (/4 1280) >[ 81476.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70740] >[ 81476.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70740] width 1280 pitch 5120 (/4 1280) >[ 81476.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713a0] >[ 81476.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713a0] width 1280 pitch 5120 (/4 1280) >[ 81476.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70740] >[ 81476.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70740] width 1280 pitch 5120 (/4 1280) >[ 81476.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713a0] >[ 81476.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713a0] width 1280 pitch 5120 (/4 1280) >[ 81476.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70740] >[ 81476.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70740] width 1280 pitch 5120 (/4 1280) >[ 81476.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713a0] >[ 81476.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713a0] width 1280 pitch 5120 (/4 1280) >[ 81476.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70740] >[ 81476.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70740] width 1280 pitch 5120 (/4 1280) >[ 81478.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[ 81478.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[ 81479.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3134720] >[ 81479.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3134720] width 1280 pitch 5120 (/4 1280) >[ 81479.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[ 81479.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[ 81479.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81479.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81479.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[ 81479.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[ 81479.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81479.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81479.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[ 81479.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[ 81479.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81479.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81479.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[ 81479.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[ 81479.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81479.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81479.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31345c0] >[ 81479.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31345c0] width 1280 pitch 5120 (/4 1280) >[ 81483.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[ 81483.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[ 81515.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373efa0] >[ 81515.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373efa0] width 1280 pitch 5120 (/4 1280) >[ 81515.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 81515.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 81515.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[ 81515.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[ 81515.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81515.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81894.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d180] >[ 81894.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d180] width 1280 pitch 5120 (/4 1280) >[ 81894.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81894.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81894.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81894.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81894.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81894.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81894.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81894.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81894.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81894.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81894.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81894.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81894.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81894.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81894.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81894.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81894.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81894.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81894.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81894.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81895.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81895.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81895.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81895.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81895.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 81895.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 81896.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[ 81896.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[ 81896.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d180] >[ 81896.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d180] width 1280 pitch 5120 (/4 1280) >[ 81896.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314efc0] >[ 81896.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314efc0] width 1280 pitch 5120 (/4 1280) >[ 81896.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81896.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81896.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314cca0] >[ 81896.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314cca0] width 1280 pitch 5120 (/4 1280) >[ 81896.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[ 81896.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[ 81896.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314cca0] >[ 81896.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314cca0] width 1280 pitch 5120 (/4 1280) >[ 81896.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 81896.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 81933.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314e320] >[ 81933.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314e320] width 1280 pitch 5120 (/4 1280) >[ 81933.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f88a0] >[ 81933.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f88a0] width 1280 pitch 5120 (/4 1280) >[ 81935.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f710] >[ 81935.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f710] width 1280 pitch 5120 (/4 1280) >[ 81935.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[ 81935.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[ 81935.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330f710] >[ 81935.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330f710] width 1280 pitch 5120 (/4 1280) >[ 81936.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3728a60] >[ 81936.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3728a60] width 1280 pitch 5120 (/4 1280) >[ 81936.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 81936.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 81952.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[ 81952.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[ 81952.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32284e0] >[ 81952.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32284e0] width 1280 pitch 5120 (/4 1280) >[ 81952.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3754970] >[ 81952.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3754970] width 1280 pitch 5120 (/4 1280) >[ 81952.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c982c0] >[ 81952.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c982c0] width 1280 pitch 5120 (/4 1280) >[ 82198.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96eb0] >[ 82198.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96eb0] width 1280 pitch 5120 (/4 1280) >[ 82199.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 82199.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 82199.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 82199.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 82199.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3725ec0] >[ 82199.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3725ec0] width 1280 pitch 5120 (/4 1280) >[ 82199.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 82199.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 82740.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3725ec0] >[ 82740.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3725ec0] width 1280 pitch 5120 (/4 1280) >[ 82740.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1d50] >[ 82740.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1d50] width 1280 pitch 5120 (/4 1280) >[ 82740.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3725ec0] >[ 82740.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3725ec0] width 1280 pitch 5120 (/4 1280) >[ 82740.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3725ec0] >[ 82740.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3725ec0] width 1280 pitch 5120 (/4 1280) >[ 82753.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99170] >[ 82754.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99170] width 1280 pitch 5120 (/4 1280) >[ 82754.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[ 82754.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[ 82755.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99170] >[ 82755.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99170] width 1280 pitch 5120 (/4 1280) >[ 82755.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f52b0] >[ 82755.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f52b0] width 1280 pitch 5120 (/4 1280) >[ 82755.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3379f00] >[ 82755.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3379f00] width 1280 pitch 5120 (/4 1280) >[ 82755.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f52b0] >[ 82755.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f52b0] width 1280 pitch 5120 (/4 1280) >[ 82761.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[ 82761.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[ 82761.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9a6e0] >[ 82761.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9a6e0] width 1280 pitch 5120 (/4 1280) >[ 82761.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373be50] >[ 82761.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373be50] width 1280 pitch 5120 (/4 1280) >[ 82761.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[ 82761.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[ 82767.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb14a0] >[ 82767.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb14a0] width 1280 pitch 5120 (/4 1280) >[ 82768.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709560] >[ 82768.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709560] width 1280 pitch 5120 (/4 1280) >[ 82795.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361bdd0] >[ 82795.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361bdd0] width 1280 pitch 5120 (/4 1280) >[ 82795.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373be50] >[ 82795.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373be50] width 1280 pitch 5120 (/4 1280) >[ 82848.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3394100] >[ 82848.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3394100] width 1280 pitch 5120 (/4 1280) >[ 82848.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79500] >[ 82848.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79500] width 1280 pitch 5120 (/4 1280) >[ 82848.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cf500] >[ 82848.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cf500] width 1280 pitch 5120 (/4 1280) >[ 82848.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79500] >[ 82848.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79500] width 1280 pitch 5120 (/4 1280) >[ 82849.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c380] >[ 82849.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c380] width 1280 pitch 5120 (/4 1280) >[ 82849.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0570] >[ 82849.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0570] width 1280 pitch 5120 (/4 1280) >[ 82849.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c380] >[ 82849.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c380] width 1280 pitch 5120 (/4 1280) >[ 82849.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0570] >[ 82849.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0570] width 1280 pitch 5120 (/4 1280) >[ 82850.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c380] >[ 82850.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c380] width 1280 pitch 5120 (/4 1280) >[ 82850.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c380] >[ 82850.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c380] width 1280 pitch 5120 (/4 1280) >[ 82850.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 82850.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 82850.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c380] >[ 82850.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c380] width 1280 pitch 5120 (/4 1280) >[ 82870.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 82870.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 82870.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 82870.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 82870.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3243f10] >[ 82870.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3243f10] width 1280 pitch 5120 (/4 1280) >[ 82870.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 82870.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 82916.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca9ef0] >[ 82916.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca9ef0] width 1280 pitch 5120 (/4 1280) >[ 82916.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 82916.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 82920.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 82920.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 82920.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 82920.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 82920.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733890] >[ 82920.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733890] width 1280 pitch 5120 (/4 1280) >[ 82920.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733890] >[ 82920.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733890] width 1280 pitch 5120 (/4 1280) >[ 82941.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca9ef0] >[ 82941.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca9ef0] width 1280 pitch 5120 (/4 1280) >[ 82941.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 82941.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 82942.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0570] >[ 82942.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0570] width 1280 pitch 5120 (/4 1280) >[ 82942.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[ 82942.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[ 82942.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cbb0] >[ 82942.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cbb0] width 1280 pitch 5120 (/4 1280) >[ 82943.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ebaa0] >[ 82943.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ebaa0] width 1280 pitch 5120 (/4 1280) >[ 82997.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 82997.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 82998.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 82998.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 82998.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 82998.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 82999.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 82999.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 82999.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 82999.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 82999.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 82999.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 83004.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71300] >[ 83004.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71300] width 1280 pitch 5120 (/4 1280) >[ 83004.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83004.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83004.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[ 83004.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[ 83004.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83004.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83010.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83010.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83010.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[ 83010.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[ 83010.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733890] >[ 83010.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733890] width 1280 pitch 5120 (/4 1280) >[ 83011.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[ 83011.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[ 83038.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 83038.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 83038.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 83038.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 83038.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 83038.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 83038.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 83038.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 83047.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79500] >[ 83047.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79500] width 1280 pitch 5120 (/4 1280) >[ 83047.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83047.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83052.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb9d10] >[ 83052.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb9d10] width 1280 pitch 5120 (/4 1280) >[ 83052.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83052.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83052.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 83052.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 83052.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ac410] >[ 83052.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ac410] width 1280 pitch 5120 (/4 1280) >[ 83052.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 83052.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 83052.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83052.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83052.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 83052.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 83053.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 83053.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 83053.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83053.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83053.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373bbd0] >[ 83053.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373bbd0] width 1280 pitch 5120 (/4 1280) >[ 83053.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83053.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83053.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb9d10] >[ 83053.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb9d10] width 1280 pitch 5120 (/4 1280) >[ 83053.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83053.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83053.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb9d10] >[ 83053.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb9d10] width 1280 pitch 5120 (/4 1280) >[ 83053.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[ 83053.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[ 83053.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 83053.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 83053.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[ 83053.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[ 83053.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3711200] >[ 83053.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3711200] width 1280 pitch 5120 (/4 1280) >[ 83054.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb9d10] >[ 83054.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb9d10] width 1280 pitch 5120 (/4 1280) >[ 83054.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e720] >[ 83054.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e720] width 1280 pitch 5120 (/4 1280) >[ 83066.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336d3a0] >[ 83066.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336d3a0] width 1280 pitch 5120 (/4 1280) >[ 83066.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325c70] >[ 83066.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325c70] width 1280 pitch 5120 (/4 1280) >[ 83066.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f7c30] >[ 83066.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f7c30] width 1280 pitch 5120 (/4 1280) >[ 83066.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325c70] >[ 83066.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325c70] width 1280 pitch 5120 (/4 1280) >[ 83084.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372b4e0] >[ 83084.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372b4e0] width 1280 pitch 5120 (/4 1280) >[ 83084.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336bd30] >[ 83084.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336bd30] width 1280 pitch 5120 (/4 1280) >[ 83084.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7160] >[ 83084.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7160] width 1280 pitch 5120 (/4 1280) >[ 83084.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3750290] >[ 83084.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3750290] width 1280 pitch 5120 (/4 1280) >[ 83220.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367d90] >[ 83220.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367d90] width 1280 pitch 5120 (/4 1280) >[ 83220.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69130] >[ 83220.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69130] width 1280 pitch 5120 (/4 1280) >[ 83220.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e08f0] >[ 83220.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e08f0] width 1280 pitch 5120 (/4 1280) >[ 83220.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367d90] >[ 83220.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367d90] width 1280 pitch 5120 (/4 1280) >[ 83230.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5d20] >[ 83230.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5d20] width 1280 pitch 5120 (/4 1280) >[ 83230.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 83230.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 83256.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cad630] >[ 83256.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cad630] width 1280 pitch 5120 (/4 1280) >[ 83256.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733890] >[ 83256.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733890] width 1280 pitch 5120 (/4 1280) >[ 83256.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83256.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83256.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733890] >[ 83256.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733890] width 1280 pitch 5120 (/4 1280) >[ 83313.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d11a0] >[ 83313.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d11a0] width 1280 pitch 5120 (/4 1280) >[ 83313.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336c5f0] >[ 83313.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336c5f0] width 1280 pitch 5120 (/4 1280) >[ 83313.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83313.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83313.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336c5f0] >[ 83313.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336c5f0] width 1280 pitch 5120 (/4 1280) >[ 83380.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 83380.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 83482.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3243ee0] >[ 83482.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3243ee0] width 1280 pitch 5120 (/4 1280) >[ 83482.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373bdb0] >[ 83482.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373bdb0] width 1280 pitch 5120 (/4 1280) >[ 83792.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b50] >[ 83792.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b50] width 1280 pitch 5120 (/4 1280) >[ 83792.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 83792.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 83792.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83792.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83792.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[ 83792.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[ 83793.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c400] >[ 83793.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c400] width 1280 pitch 5120 (/4 1280) >[ 83794.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83794.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 83794.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 83794.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 83794.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1560] >[ 83794.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1560] width 1280 pitch 5120 (/4 1280) >[ 84960.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 84960.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 84960.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84960.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84960.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84960.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84960.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84960.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84960.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84960.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84960.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84960.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84960.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84960.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84960.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84960.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84960.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84960.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84961.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84961.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84961.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84961.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84961.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 84961.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 84961.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 84961.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 84961.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5df0] >[ 84962.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5df0] width 1280 pitch 5120 (/4 1280) >[ 84962.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4ce0] >[ 84962.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4ce0] width 1280 pitch 5120 (/4 1280) >[ 84962.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4d70] >[ 84962.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4d70] width 1280 pitch 5120 (/4 1280) >[ 84962.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4ce0] >[ 84962.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4ce0] width 1280 pitch 5120 (/4 1280) >[ 84962.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4d70] >[ 84962.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4d70] width 1280 pitch 5120 (/4 1280) >[ 84962.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35eddd0] >[ 84962.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35eddd0] width 1280 pitch 5120 (/4 1280) >[ 84962.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35eddd0] >[ 84962.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35eddd0] width 1280 pitch 5120 (/4 1280) >[ 84963.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee5d0] >[ 84963.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee5d0] width 1280 pitch 5120 (/4 1280) >[ 84988.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c9690] >[ 84988.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c9690] width 1280 pitch 5120 (/4 1280) >[ 84991.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c2ec0] >[ 84991.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c2ec0] width 1280 pitch 5120 (/4 1280) >[ 84991.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c9370] >[ 84991.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c9370] width 1280 pitch 5120 (/4 1280) >[ 84991.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8240] >[ 84991.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8240] width 1280 pitch 5120 (/4 1280) >[ 85027.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d7ce0] >[ 85027.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d7ce0] width 1280 pitch 5120 (/4 1280) >[ 85029.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 85029.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 85953.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3344780] >[ 85953.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3344780] width 1280 pitch 5120 (/4 1280) >[ 85953.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 85953.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 85953.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d1350] >[ 85953.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d1350] width 1280 pitch 5120 (/4 1280) >[ 85953.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d300] >[ 85953.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d300] width 1280 pitch 5120 (/4 1280) >[ 85998.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3403050] >[ 85998.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3403050] width 1280 pitch 5120 (/4 1280) >[ 86104.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[ 86104.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[ 86104.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 86104.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 86107.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8fb40] >[ 86107.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8fb40] width 1280 pitch 5120 (/4 1280) >[ 86107.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[ 86107.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[ 86107.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f96f0] >[ 86107.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f96f0] width 1280 pitch 5120 (/4 1280) >[ 86107.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 86107.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 86109.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[ 86110.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[ 86110.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9a240] >[ 86110.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9a240] width 1280 pitch 5120 (/4 1280) >[ 86183.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[ 86183.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[ 86183.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8f00] >[ 86183.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8f00] width 1280 pitch 5120 (/4 1280) >[ 86183.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cb8d0] >[ 86183.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cb8d0] width 1280 pitch 5120 (/4 1280) >[ 86183.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8f00] >[ 86183.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8f00] width 1280 pitch 5120 (/4 1280) >[ 86208.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8f00] >[ 86208.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8f00] width 1280 pitch 5120 (/4 1280) >[ 86208.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3407170] >[ 86208.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3407170] width 1280 pitch 5120 (/4 1280) >[ 86208.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca9ef0] >[ 86208.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca9ef0] width 1280 pitch 5120 (/4 1280) >[ 86208.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[ 86208.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[ 86224.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 86224.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 86224.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3407170] >[ 86224.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3407170] width 1280 pitch 5120 (/4 1280) >[ 86224.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c948e0] >[ 86224.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c948e0] width 1280 pitch 5120 (/4 1280) >[ 86224.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f6080] >[ 86224.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f6080] width 1280 pitch 5120 (/4 1280) >[ 86233.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca9ef0] >[ 86233.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca9ef0] width 1280 pitch 5120 (/4 1280) >[ 86233.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 86233.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 86262.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[ 86262.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[ 86262.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[ 86262.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[ 86262.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ef0c0] >[ 86262.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ef0c0] width 1280 pitch 5120 (/4 1280) >[ 86262.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[ 86262.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[ 86309.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374bcd0] >[ 86309.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374bcd0] width 1280 pitch 5120 (/4 1280) >[ 86309.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3129690] >[ 86309.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3129690] width 1280 pitch 5120 (/4 1280) >[ 86315.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374bcd0] >[ 86315.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374bcd0] width 1280 pitch 5120 (/4 1280) >[ 86316.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 86316.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 86316.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f33b0] >[ 86316.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f33b0] width 1280 pitch 5120 (/4 1280) >[ 86316.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336dee0] >[ 86316.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336dee0] width 1280 pitch 5120 (/4 1280) >[ 86942.968] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[ 86942.968] (II) RADEON(0): Using hsync ranges from config file >[ 86942.968] (II) RADEON(0): Using vrefresh ranges from config file >[ 86942.968] (II) RADEON(0): Printing DDC gathered Modelines: >[ 86942.968] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[ 86942.968] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[ 86942.968] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[ 87033.538] (II) RADEON(0): RADEONSaveScreen(2) >[ 87033.538] (II) RADEON(0): RADEONSaveScreen(0) >[112079.462] (II) RADEON(0): RADEONSaveScreen(1) >[112079.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ffd0] >[112079.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ffd0] width 1280 pitch 5120 (/4 1280) >[112083.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f33b0] >[112083.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f33b0] width 1280 pitch 5120 (/4 1280) >[112084.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f33b0] >[112084.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f33b0] width 1280 pitch 5120 (/4 1280) >[112084.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733520] >[112084.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733520] width 1280 pitch 5120 (/4 1280) >[112084.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f33b0] >[112084.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f33b0] width 1280 pitch 5120 (/4 1280) >[112084.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733520] >[112084.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733520] width 1280 pitch 5120 (/4 1280) >[113246.658] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[113246.658] (II) RADEON(0): Using hsync ranges from config file >[113246.658] (II) RADEON(0): Using vrefresh ranges from config file >[113246.658] (II) RADEON(0): Printing DDC gathered Modelines: >[113246.658] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[113246.658] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[113246.658] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[113246.658] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[113246.659] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[113246.659] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[113246.659] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[113246.659] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[113246.659] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[113246.659] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[113336.555] (II) RADEON(0): RADEONSaveScreen(2) >[113336.555] (II) RADEON(0): RADEONSaveScreen(0) >[149101.074] (II) RADEON(0): RADEONSaveScreen(1) >[149101.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2300] >[149101.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2300] width 1280 pitch 5120 (/4 1280) >[149104.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365e7d0] >[149104.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365e7d0] width 1280 pitch 5120 (/4 1280) >[149105.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365e7d0] >[149105.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365e7d0] width 1280 pitch 5120 (/4 1280) >[149105.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eceb0] >[149105.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eceb0] width 1280 pitch 5120 (/4 1280) >[149105.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365e7d0] >[149105.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365e7d0] width 1280 pitch 5120 (/4 1280) >[149106.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f23e0] >[149106.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f23e0] width 1280 pitch 5120 (/4 1280) >[149129.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[149129.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[150206.137] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[150206.137] (II) RADEON(0): Using hsync ranges from config file >[150206.137] (II) RADEON(0): Using vrefresh ranges from config file >[150206.137] (II) RADEON(0): Printing DDC gathered Modelines: >[150206.138] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[150206.138] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[150206.138] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[150206.138] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[150206.138] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[150206.138] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[150206.138] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[150206.138] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[150206.138] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[150206.138] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[150296.552] (II) RADEON(0): RADEONSaveScreen(2) >[150296.552] (II) RADEON(0): RADEONSaveScreen(0) >[150621.794] (II) RADEON(0): RADEONSaveScreen(1) >[152707.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c08d0] >[152707.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c08d0] width 1280 pitch 5120 (/4 1280) >[153424.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374fdf0] >[153424.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374fdf0] width 1280 pitch 5120 (/4 1280) >[153425.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3da0] >[153425.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3da0] width 1280 pitch 5120 (/4 1280) >[153426.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374fd30] >[153426.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374fd30] width 1280 pitch 5120 (/4 1280) >[153432.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315a760] >[153432.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315a760] width 1280 pitch 5120 (/4 1280) >[153593.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cc090] >[153593.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cc090] width 1280 pitch 5120 (/4 1280) >[153595.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cc090] >[153595.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cc090] width 1280 pitch 5120 (/4 1280) >[153595.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3688a50] >[153595.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3688a50] width 1280 pitch 5120 (/4 1280) >[153595.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c41c00] >[153595.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c41c00] width 1280 pitch 5120 (/4 1280) >[153595.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c41c00] >[153595.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c41c00] width 1280 pitch 5120 (/4 1280) >[153671.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bb00] >[153671.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bb00] width 1280 pitch 5120 (/4 1280) >[153671.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a100] >[153671.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a100] width 1280 pitch 5120 (/4 1280) >[153671.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[153671.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[153671.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a100] >[153671.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a100] width 1280 pitch 5120 (/4 1280) >[157273.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3e190] >[157273.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3e190] width 1280 pitch 5120 (/4 1280) >[157273.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157273.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157273.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157273.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157273.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157273.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b6f0] >[157273.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b6f0] width 1280 pitch 5120 (/4 1280) >[157273.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35080] >[157273.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35080] width 1280 pitch 5120 (/4 1280) >[157980.670] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[157980.671] (II) RADEON(0): Using hsync ranges from config file >[157980.671] (II) RADEON(0): Using vrefresh ranges from config file >[157980.671] (II) RADEON(0): Printing DDC gathered Modelines: >[157980.671] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[157980.671] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[157980.671] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[157980.671] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[157980.671] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[157980.671] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[157980.671] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[157980.671] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[157980.671] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[157980.671] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[160001.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3599a10] >[160001.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3599a10] width 1280 pitch 5120 (/4 1280) >[160003.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160003.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160003.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359bea0] >[160003.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359bea0] width 1280 pitch 5120 (/4 1280) >[160003.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160003.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160003.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359bea0] >[160003.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359bea0] width 1280 pitch 5120 (/4 1280) >[160003.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160003.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160003.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160003.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160003.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160004.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160004.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160004.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160004.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160004.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160004.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160004.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160004.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160004.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160004.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ae450] >[160004.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ae450] width 1280 pitch 5120 (/4 1280) >[160004.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160004.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ae450] >[160004.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ae450] width 1280 pitch 5120 (/4 1280) >[160004.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34c20] >[160004.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34c20] width 1280 pitch 5120 (/4 1280) >[160108.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ae450] >[160108.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ae450] width 1280 pitch 5120 (/4 1280) >[160108.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160108.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160108.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442b0] >[160108.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442b0] width 1280 pitch 5120 (/4 1280) >[160109.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cba5c0] >[160109.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cba5c0] width 1280 pitch 5120 (/4 1280) >[160131.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160131.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160131.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160131.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160131.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160131.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160131.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442b0] >[160131.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442b0] width 1280 pitch 5120 (/4 1280) >[160133.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160133.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160133.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595090] >[160133.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595090] width 1280 pitch 5120 (/4 1280) >[160134.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442b0] >[160134.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442b0] width 1280 pitch 5120 (/4 1280) >[160134.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ae450] >[160134.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ae450] width 1280 pitch 5120 (/4 1280) >[160134.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160134.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160134.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0b50] >[160134.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0b50] width 1280 pitch 5120 (/4 1280) >[160156.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ea00] >[160156.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ea00] width 1280 pitch 5120 (/4 1280) >[160156.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ea00] >[160156.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ea00] width 1280 pitch 5120 (/4 1280) >[160157.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[160158.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[160158.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[160158.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[160158.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f3190] >[160158.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f3190] width 1280 pitch 5120 (/4 1280) >[160158.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dde10] >[160158.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dde10] width 1280 pitch 5120 (/4 1280) >[160158.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c3b60] >[160158.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c3b60] width 1280 pitch 5120 (/4 1280) >[160159.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cf8f0] >[160159.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cf8f0] width 1280 pitch 5120 (/4 1280) >[160159.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2a660] >[160159.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2a660] width 1280 pitch 5120 (/4 1280) >[160163.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[160163.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[160163.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160163.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160163.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[160163.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[160164.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1d40] >[160164.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1d40] width 1280 pitch 5120 (/4 1280) >[160177.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160177.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160177.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160177.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160177.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ae450] >[160177.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ae450] width 1280 pitch 5120 (/4 1280) >[160178.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160178.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160213.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f3190] >[160213.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f3190] width 1280 pitch 5120 (/4 1280) >[160213.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160213.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160213.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cf890] >[160213.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cf890] width 1280 pitch 5120 (/4 1280) >[160213.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33da220] >[160213.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33da220] width 1280 pitch 5120 (/4 1280) >[160316.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c6c0] >[160316.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c6c0] width 1280 pitch 5120 (/4 1280) >[160317.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160317.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160318.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34031f0] >[160318.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34031f0] width 1280 pitch 5120 (/4 1280) >[160318.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34031f0] >[160318.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34031f0] width 1280 pitch 5120 (/4 1280) >[160318.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6c90] >[160318.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6c90] width 1280 pitch 5120 (/4 1280) >[160318.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34031f0] >[160318.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34031f0] width 1280 pitch 5120 (/4 1280) >[160392.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3617ce0] >[160392.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3617ce0] width 1280 pitch 5120 (/4 1280) >[160396.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34224f0] >[160396.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34224f0] width 1280 pitch 5120 (/4 1280) >[160396.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbf480] >[160396.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbf480] width 1280 pitch 5120 (/4 1280) >[160427.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1e0d0] >[160427.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1e0d0] width 1280 pitch 5120 (/4 1280) >[160428.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f1c30] >[160428.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f1c30] width 1280 pitch 5120 (/4 1280) >[160428.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c6c0] >[160428.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c6c0] width 1280 pitch 5120 (/4 1280) >[160428.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3617ce0] >[160428.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3617ce0] width 1280 pitch 5120 (/4 1280) >[160429.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34031f0] >[160429.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34031f0] width 1280 pitch 5120 (/4 1280) >[160429.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c349e0] >[160429.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c349e0] width 1280 pitch 5120 (/4 1280) >[160429.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ec30] >[160429.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ec30] width 1280 pitch 5120 (/4 1280) >[160429.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c6c0] >[160430.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c6c0] width 1280 pitch 5120 (/4 1280) >[160548.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c6c0] >[160548.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c6c0] width 1280 pitch 5120 (/4 1280) >[160548.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cff40] >[160548.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cff40] width 1280 pitch 5120 (/4 1280) >[160548.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1e0d0] >[160548.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1e0d0] width 1280 pitch 5120 (/4 1280) >[160548.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cff40] >[160548.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cff40] width 1280 pitch 5120 (/4 1280) >[160553.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341b900] >[160553.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341b900] width 1280 pitch 5120 (/4 1280) >[160563.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c349e0] >[160563.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c349e0] width 1280 pitch 5120 (/4 1280) >[160563.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59230] >[160563.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59230] width 1280 pitch 5120 (/4 1280) >[160575.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f3190] >[160575.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f3190] width 1280 pitch 5120 (/4 1280) >[160575.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59230] >[160575.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59230] width 1280 pitch 5120 (/4 1280) >[160575.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59230] >[160576.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59230] width 1280 pitch 5120 (/4 1280) >[160576.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341b900] >[160576.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341b900] width 1280 pitch 5120 (/4 1280) >[160584.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593210] >[160584.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593210] width 1280 pitch 5120 (/4 1280) >[160591.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abfb00] >[160591.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abfb00] width 1280 pitch 5120 (/4 1280) >[160602.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb920] >[160602.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb920] width 1280 pitch 5120 (/4 1280) >[160610.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae5b60] >[160610.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae5b60] width 1280 pitch 5120 (/4 1280) >[160610.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160610.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160610.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160610.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160610.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160610.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160610.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160610.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160610.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e8d50] >[160610.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e8d50] width 1280 pitch 5120 (/4 1280) >[160610.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4af0e10] >[160610.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4af0e10] width 1280 pitch 5120 (/4 1280) >[160610.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76e20] >[160610.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76e20] width 1280 pitch 5120 (/4 1280) >[160613.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fa420] >[160613.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fa420] width 1280 pitch 5120 (/4 1280) >[160622.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160622.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160622.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160622.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160622.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d5df0] >[160622.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d5df0] width 1280 pitch 5120 (/4 1280) >[160622.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589340] >[160622.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589340] width 1280 pitch 5120 (/4 1280) >[160628.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c349e0] >[160628.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c349e0] width 1280 pitch 5120 (/4 1280) >[160628.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3664a70] >[160628.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3664a70] width 1280 pitch 5120 (/4 1280) >[160628.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d4f0] >[160628.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d4f0] width 1280 pitch 5120 (/4 1280) >[160628.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a440] >[160628.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a440] width 1280 pitch 5120 (/4 1280) >[160628.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d4f0] >[160628.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d4f0] width 1280 pitch 5120 (/4 1280) >[160628.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc7280] >[160628.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc7280] width 1280 pitch 5120 (/4 1280) >[160688.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c349e0] >[160688.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c349e0] width 1280 pitch 5120 (/4 1280) >[160704.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c6c0] >[160704.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c6c0] width 1280 pitch 5120 (/4 1280) >[160711.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[160711.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[160711.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa160] >[160711.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa160] width 1280 pitch 5120 (/4 1280) >[160711.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d180] >[160711.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d180] width 1280 pitch 5120 (/4 1280) >[160711.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709f60] >[160711.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709f60] width 1280 pitch 5120 (/4 1280) >[160711.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[160711.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[160711.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[160711.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[160711.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[160711.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[160711.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cb650] >[160711.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cb650] width 1280 pitch 5120 (/4 1280) >[160711.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[160711.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[160736.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[160736.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[160736.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[160736.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[160736.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[160736.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[160736.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[160736.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[160737.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314d3a0] >[160737.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314d3a0] width 1280 pitch 5120 (/4 1280) >[160737.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371af40] >[160737.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371af40] width 1280 pitch 5120 (/4 1280) >[160747.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160747.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160747.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160747.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160747.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[160748.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[160748.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160748.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160748.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[160748.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[160749.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160749.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160749.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385510] >[160749.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385510] width 1280 pitch 5120 (/4 1280) >[160749.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160749.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160749.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[160749.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[160749.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385510] >[160749.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385510] width 1280 pitch 5120 (/4 1280) >[160749.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[160749.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[160765.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337d340] >[160765.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337d340] width 1280 pitch 5120 (/4 1280) >[160770.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3247100] >[160770.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3247100] width 1280 pitch 5120 (/4 1280) >[160774.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b180] >[160774.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b180] width 1280 pitch 5120 (/4 1280) >[160819.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[160819.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[160826.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[160826.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[160837.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f8a0] >[160837.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f8a0] width 1280 pitch 5120 (/4 1280) >[160837.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1d30] >[160837.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1d30] width 1280 pitch 5120 (/4 1280) >[160837.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337f8a0] >[160837.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337f8a0] width 1280 pitch 5120 (/4 1280) >[160837.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3333a50] >[160837.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3333a50] width 1280 pitch 5120 (/4 1280) >[160837.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c1ea0] >[160837.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c1ea0] width 1280 pitch 5120 (/4 1280) >[160837.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3264690] >[160837.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3264690] width 1280 pitch 5120 (/4 1280) >[160837.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3333a50] >[160837.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3333a50] width 1280 pitch 5120 (/4 1280) >[160837.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[160837.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[160837.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb1d30] >[160837.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb1d30] width 1280 pitch 5120 (/4 1280) >[160837.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee9a0] >[160837.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee9a0] width 1280 pitch 5120 (/4 1280) >[160837.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3361070] >[160837.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3361070] width 1280 pitch 5120 (/4 1280) >[160838.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160838.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4c40] >[160838.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4c40] width 1280 pitch 5120 (/4 1280) >[160838.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336df60] >[160838.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336df60] width 1280 pitch 5120 (/4 1280) >[160849.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314ba20] >[160849.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314ba20] width 1280 pitch 5120 (/4 1280) >[160953.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373c790] >[160953.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373c790] width 1280 pitch 5120 (/4 1280) >[160953.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb920] >[160953.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb920] width 1280 pitch 5120 (/4 1280) >[160953.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c43bd0] >[160953.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c43bd0] width 1280 pitch 5120 (/4 1280) >[160953.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c43b70] >[160953.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c43b70] width 1280 pitch 5120 (/4 1280) >[160970.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[160970.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[160972.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f16a0] >[160972.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f16a0] width 1280 pitch 5120 (/4 1280) >[160972.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb7690] >[160972.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb7690] width 1280 pitch 5120 (/4 1280) >[160972.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f16a0] >[160972.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f16a0] width 1280 pitch 5120 (/4 1280) >[160973.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbf7a0] >[160973.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbf7a0] width 1280 pitch 5120 (/4 1280) >[160973.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312f070] >[160973.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312f070] width 1280 pitch 5120 (/4 1280) >[161022.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314bba0] >[161022.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314bba0] width 1280 pitch 5120 (/4 1280) >[161029.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3383210] >[161029.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3383210] width 1280 pitch 5120 (/4 1280) >[161029.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3383210] >[161029.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3383210] width 1280 pitch 5120 (/4 1280) >[161029.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa160] >[161029.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa160] width 1280 pitch 5120 (/4 1280) >[161030.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3383210] >[161030.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3383210] width 1280 pitch 5120 (/4 1280) >[161041.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[161041.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[161041.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385510] >[161041.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385510] width 1280 pitch 5120 (/4 1280) >[161041.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad020] >[161041.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad020] width 1280 pitch 5120 (/4 1280) >[161041.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385510] >[161041.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385510] width 1280 pitch 5120 (/4 1280) >[161043.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d0d90] >[161043.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d0d90] width 1280 pitch 5120 (/4 1280) >[161045.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385d20] >[161045.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385d20] width 1280 pitch 5120 (/4 1280) >[161045.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3385d20] >[161046.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3385d20] width 1280 pitch 5120 (/4 1280) >[161046.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331aa30] >[161046.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331aa30] width 1280 pitch 5120 (/4 1280) >[161046.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c58210] >[161046.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c58210] width 1280 pitch 5120 (/4 1280) >[161064.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[161064.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[161065.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[161065.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[161065.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[161065.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[161065.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[161065.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[161065.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3247100] >[161065.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3247100] width 1280 pitch 5120 (/4 1280) >[161067.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[161067.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[161069.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[161069.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[161069.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[161069.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[161069.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[161069.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[161087.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[161087.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[161087.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2643080] >[161087.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2643080] width 1280 pitch 5120 (/4 1280) >[161087.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[161087.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[161087.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cb650] >[161087.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cb650] width 1280 pitch 5120 (/4 1280) >[161088.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991a0] >[161088.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991a0] width 1280 pitch 5120 (/4 1280) >[161088.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[161088.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[161088.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[161088.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[161088.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312c510] >[161088.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312c510] width 1280 pitch 5120 (/4 1280) >[161088.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[161088.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[161089.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x312b830] >[161089.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x312b830] width 1280 pitch 5120 (/4 1280) >[161089.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[161089.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[161089.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[161089.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[161090.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbf7a0] >[161090.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbf7a0] width 1280 pitch 5120 (/4 1280) >[161090.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[161090.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[161095.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbf7a0] >[161095.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbf7a0] width 1280 pitch 5120 (/4 1280) >[161095.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3311370] >[161095.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3311370] width 1280 pitch 5120 (/4 1280) >[161095.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[161095.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[161095.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[161095.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[161338.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e7c0] >[161338.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e7c0] width 1280 pitch 5120 (/4 1280) >[161338.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31346c0] >[161338.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31346c0] width 1280 pitch 5120 (/4 1280) >[161684.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cbc20] >[161684.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cbc20] width 1280 pitch 5120 (/4 1280) >[161685.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8e20] >[161685.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8e20] width 1280 pitch 5120 (/4 1280) >[161685.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d180] >[161685.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d180] width 1280 pitch 5120 (/4 1280) >[161685.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e8e20] >[161685.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e8e20] width 1280 pitch 5120 (/4 1280) >[161720.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[161720.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[161720.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3729ca0] >[161720.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3729ca0] width 1280 pitch 5120 (/4 1280) >[161814.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32533b0] >[161814.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32533b0] width 1280 pitch 5120 (/4 1280) >[161814.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[161814.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[161814.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa160] >[161814.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa160] width 1280 pitch 5120 (/4 1280) >[161814.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[161814.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[162290.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[162290.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[162369.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162369.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162369.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162369.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162369.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162369.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162369.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162369.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162369.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162369.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162369.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162369.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162369.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162369.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162369.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162369.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162369.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162369.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162369.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162369.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162370.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162370.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162370.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162370.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162370.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162370.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162372.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162372.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162372.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162372.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162372.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162372.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162372.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162372.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162372.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162372.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162372.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162372.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162372.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162372.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162372.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162372.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162372.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc8e0] >[162372.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc8e0] width 1280 pitch 5120 (/4 1280) >[162372.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[162372.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[162455.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d180] >[162455.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d180] width 1280 pitch 5120 (/4 1280) >[162458.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e2010] >[162458.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e2010] width 1280 pitch 5120 (/4 1280) >[162465.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f41b0] >[162465.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f41b0] width 1280 pitch 5120 (/4 1280) >[162480.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cabba0] >[162480.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cabba0] width 1280 pitch 5120 (/4 1280) >[162480.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[162480.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[162480.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cabba0] >[162480.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cabba0] width 1280 pitch 5120 (/4 1280) >[162480.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[162480.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[162480.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cabba0] >[162480.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cabba0] width 1280 pitch 5120 (/4 1280) >[162480.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[162480.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[162480.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33beb50] >[162480.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33beb50] width 1280 pitch 5120 (/4 1280) >[162480.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7eb90] >[162481.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7eb90] width 1280 pitch 5120 (/4 1280) >[162481.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[162481.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[162483.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322fc60] >[162483.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322fc60] width 1280 pitch 5120 (/4 1280) >[162484.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322fc60] >[162484.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322fc60] width 1280 pitch 5120 (/4 1280) >[162484.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[162484.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[162484.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322fc60] >[162484.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322fc60] width 1280 pitch 5120 (/4 1280) >[162582.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1ac0] >[162582.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1ac0] width 1280 pitch 5120 (/4 1280) >[162593.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31262e0] >[162593.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31262e0] width 1280 pitch 5120 (/4 1280) >[162594.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124f90] >[162594.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124f90] width 1280 pitch 5120 (/4 1280) >[162595.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406650] >[162595.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406650] width 1280 pitch 5120 (/4 1280) >[162596.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[162596.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[162596.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339ae40] >[162596.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339ae40] width 1280 pitch 5120 (/4 1280) >[162596.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[162596.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[162604.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e7c0] >[162604.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e7c0] width 1280 pitch 5120 (/4 1280) >[162604.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63dd0] >[162604.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63dd0] width 1280 pitch 5120 (/4 1280) >[162604.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e7c0] >[162604.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e7c0] width 1280 pitch 5120 (/4 1280) >[162605.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e7c0] >[162605.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e7c0] width 1280 pitch 5120 (/4 1280) >[162609.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[162609.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[162609.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406220] >[162609.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406220] width 1280 pitch 5120 (/4 1280) >[162611.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[162611.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[162611.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cbc20] >[162611.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cbc20] width 1280 pitch 5120 (/4 1280) >[162611.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31346c0] >[162611.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31346c0] width 1280 pitch 5120 (/4 1280) >[162611.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709f60] >[162611.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709f60] width 1280 pitch 5120 (/4 1280) >[162611.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709f60] >[162611.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709f60] width 1280 pitch 5120 (/4 1280) >[162612.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31346c0] >[162612.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31346c0] width 1280 pitch 5120 (/4 1280) >[162612.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33beb50] >[162612.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33beb50] width 1280 pitch 5120 (/4 1280) >[162613.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31346c0] >[162613.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31346c0] width 1280 pitch 5120 (/4 1280) >[162616.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cbc20] >[162616.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cbc20] width 1280 pitch 5120 (/4 1280) >[162616.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33beb50] >[162617.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33beb50] width 1280 pitch 5120 (/4 1280) >[162617.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[162617.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[162617.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a2300] >[162617.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a2300] width 1280 pitch 5120 (/4 1280) >[162622.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253430] >[162622.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253430] width 1280 pitch 5120 (/4 1280) >[162622.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253430] >[162622.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253430] width 1280 pitch 5120 (/4 1280) >[162622.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d5c0] >[162622.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d5c0] width 1280 pitch 5120 (/4 1280) >[162622.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253430] >[162622.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253430] width 1280 pitch 5120 (/4 1280) >[162645.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[162645.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[162645.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[162645.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[162645.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4190] >[162645.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4190] width 1280 pitch 5120 (/4 1280) >[162646.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[162646.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[162649.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[162649.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[162649.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[162649.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[162649.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1950] >[162649.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1950] width 1280 pitch 5120 (/4 1280) >[162649.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[162649.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[162662.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[162662.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[162662.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d5c0] >[162662.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d5c0] width 1280 pitch 5120 (/4 1280) >[162662.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2030] >[162662.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2030] width 1280 pitch 5120 (/4 1280) >[162662.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d5c0] >[162662.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d5c0] width 1280 pitch 5120 (/4 1280) >[162671.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c67e0] >[162671.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c67e0] width 1280 pitch 5120 (/4 1280) >[162672.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b0810] >[162672.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b0810] width 1280 pitch 5120 (/4 1280) >[162672.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338bc00] >[162672.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338bc00] width 1280 pitch 5120 (/4 1280) >[162672.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b0810] >[162672.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b0810] width 1280 pitch 5120 (/4 1280) >[162697.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d5c0] >[162697.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d5c0] width 1280 pitch 5120 (/4 1280) >[162697.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad290] >[162697.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad290] width 1280 pitch 5120 (/4 1280) >[162697.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[162697.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[162697.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad290] >[162697.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad290] width 1280 pitch 5120 (/4 1280) >[162699.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3dd0] >[162699.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3dd0] width 1280 pitch 5120 (/4 1280) >[162699.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3dd0] >[162699.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3dd0] width 1280 pitch 5120 (/4 1280) >[162699.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[162699.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[162699.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3dd0] >[162699.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3dd0] width 1280 pitch 5120 (/4 1280) >[162729.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330d5c0] >[162729.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330d5c0] width 1280 pitch 5120 (/4 1280) >[162729.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad290] >[162730.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad290] width 1280 pitch 5120 (/4 1280) >[162730.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b0030] >[162730.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b0030] width 1280 pitch 5120 (/4 1280) >[162730.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad290] >[162730.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad290] width 1280 pitch 5120 (/4 1280) >[162732.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25bad30] >[162732.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25bad30] width 1280 pitch 5120 (/4 1280) >[162900.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[162900.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbca30] >[162900.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbca30] width 1280 pitch 5120 (/4 1280) >[162900.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a640] >[162900.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a640] width 1280 pitch 5120 (/4 1280) >[164156.634] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[164156.634] (II) RADEON(0): Using hsync ranges from config file >[164156.634] (II) RADEON(0): Using vrefresh ranges from config file >[164156.634] (II) RADEON(0): Printing DDC gathered Modelines: >[164156.634] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[164156.634] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[164156.634] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[164156.634] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[164156.634] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[164156.634] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[164156.634] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[164156.634] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[164156.634] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[164156.634] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[166210.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324d1a0] >[166210.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324d1a0] width 1280 pitch 5120 (/4 1280) >[167801.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b380] >[167801.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b380] width 1280 pitch 5120 (/4 1280) >[167802.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406220] >[167802.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406220] width 1280 pitch 5120 (/4 1280) >[167802.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371d220] >[167802.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371d220] width 1280 pitch 5120 (/4 1280) >[167802.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406220] >[167802.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406220] width 1280 pitch 5120 (/4 1280) >[167878.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332fc20] >[167878.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332fc20] width 1280 pitch 5120 (/4 1280) >[167878.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32570a0] >[167878.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32570a0] width 1280 pitch 5120 (/4 1280) >[167940.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167940.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167940.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167940.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167940.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167940.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167940.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167940.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167940.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167940.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167940.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167940.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167940.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167940.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167941.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167941.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167941.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167941.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167941.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167941.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167941.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f470] >[167941.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f470] width 1280 pitch 5120 (/4 1280) >[167942.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1f90] >[167942.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1f90] width 1280 pitch 5120 (/4 1280) >[167942.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336d3b0] >[167942.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336d3b0] width 1280 pitch 5120 (/4 1280) >[167942.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167942.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[167942.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336d3b0] >[167942.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336d3b0] width 1280 pitch 5120 (/4 1280) >[167942.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1f90] >[167942.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1f90] width 1280 pitch 5120 (/4 1280) >[167942.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336d3b0] >[167942.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336d3b0] width 1280 pitch 5120 (/4 1280) >[167942.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1f90] >[167942.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1f90] width 1280 pitch 5120 (/4 1280) >[167942.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3257380] >[167942.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3257380] width 1280 pitch 5120 (/4 1280) >[168161.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358c6e0] >[168161.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358c6e0] width 1280 pitch 5120 (/4 1280) >[168161.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ecf80] >[168161.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ecf80] width 1280 pitch 5120 (/4 1280) >[168161.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[168161.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[168161.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c1e0] >[168161.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c1e0] width 1280 pitch 5120 (/4 1280) >[168185.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ada0] >[168185.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ada0] width 1280 pitch 5120 (/4 1280) >[168185.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c1e0] >[168185.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c1e0] width 1280 pitch 5120 (/4 1280) >[168185.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339d4e0] >[168185.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339d4e0] width 1280 pitch 5120 (/4 1280) >[168185.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c1e0] >[168185.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c1e0] width 1280 pitch 5120 (/4 1280) >[168191.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361e390] >[168191.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361e390] width 1280 pitch 5120 (/4 1280) >[168191.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322fc60] >[168191.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322fc60] width 1280 pitch 5120 (/4 1280) >[168191.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c55350] >[168191.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c55350] width 1280 pitch 5120 (/4 1280) >[168191.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361e040] >[168191.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361e040] width 1280 pitch 5120 (/4 1280) >[168194.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c4020] >[168194.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c4020] width 1280 pitch 5120 (/4 1280) >[168194.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326120] >[168194.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326120] width 1280 pitch 5120 (/4 1280) >[168194.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x322fc60] >[168194.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x322fc60] width 1280 pitch 5120 (/4 1280) >[168194.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326120] >[168194.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326120] width 1280 pitch 5120 (/4 1280) >[168233.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326120] >[168233.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326120] width 1280 pitch 5120 (/4 1280) >[168233.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bb6e0] >[168233.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bb6e0] width 1280 pitch 5120 (/4 1280) >[168233.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a15a0] >[168233.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a15a0] width 1280 pitch 5120 (/4 1280) >[168233.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361a900] >[168233.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361a900] width 1280 pitch 5120 (/4 1280) >[168235.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ecf80] >[168236.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ecf80] width 1280 pitch 5120 (/4 1280) >[168236.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33358a0] >[168236.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33358a0] width 1280 pitch 5120 (/4 1280) >[168236.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[168236.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[168236.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f18b0] >[168236.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f18b0] width 1280 pitch 5120 (/4 1280) >[168236.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c92370] >[168236.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c92370] width 1280 pitch 5120 (/4 1280) >[168237.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c58d70] >[168237.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c58d70] width 1280 pitch 5120 (/4 1280) >[168237.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[168237.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[168237.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c58d70] >[168237.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c58d70] width 1280 pitch 5120 (/4 1280) >[168326.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[168326.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[168326.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[168326.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[168326.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d870] >[168326.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d870] width 1280 pitch 5120 (/4 1280) >[168326.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[168326.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[168329.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713490] >[168329.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713490] width 1280 pitch 5120 (/4 1280) >[168423.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37188c0] >[168423.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37188c0] width 1280 pitch 5120 (/4 1280) >[168423.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e640] >[168423.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e640] width 1280 pitch 5120 (/4 1280) >[168423.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371e640] >[168423.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371e640] width 1280 pitch 5120 (/4 1280) >[168423.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d7d0] >[168423.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d7d0] width 1280 pitch 5120 (/4 1280) >[168439.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37188c0] >[168439.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37188c0] width 1280 pitch 5120 (/4 1280) >[168440.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d870] >[168440.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d870] width 1280 pitch 5120 (/4 1280) >[168440.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3354790] >[168440.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3354790] width 1280 pitch 5120 (/4 1280) >[168440.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37188c0] >[168440.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37188c0] width 1280 pitch 5120 (/4 1280) >[168440.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c657e0] >[168440.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c657e0] width 1280 pitch 5120 (/4 1280) >[168440.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37188c0] >[168440.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37188c0] width 1280 pitch 5120 (/4 1280) >[168993.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[168993.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[168994.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[168994.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[168994.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[168994.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[168994.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c657e0] >[168994.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c657e0] width 1280 pitch 5120 (/4 1280) >[169140.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[169140.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[169546.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[169546.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[169547.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22750] >[169547.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22750] width 1280 pitch 5120 (/4 1280) >[169547.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c38060] >[169547.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c38060] width 1280 pitch 5120 (/4 1280) >[169547.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[169547.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[169547.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c38060] >[169547.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c38060] width 1280 pitch 5120 (/4 1280) >[169548.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[169549.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[169549.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[169549.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[169549.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373d400] >[169549.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373d400] width 1280 pitch 5120 (/4 1280) >[169549.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[169549.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[169553.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358beb0] >[169553.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358beb0] width 1280 pitch 5120 (/4 1280) >[169631.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325fd30] >[169632.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325fd30] width 1280 pitch 5120 (/4 1280) >[169632.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[169632.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[169632.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed610] >[169632.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed610] width 1280 pitch 5120 (/4 1280) >[169632.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[169632.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[169636.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333bfd0] >[169636.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333bfd0] width 1280 pitch 5120 (/4 1280) >[169659.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589a70] >[169659.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589a70] width 1280 pitch 5120 (/4 1280) >[169659.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8070] >[169659.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8070] width 1280 pitch 5120 (/4 1280) >[169659.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3589a70] >[169659.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3589a70] width 1280 pitch 5120 (/4 1280) >[169659.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8070] >[169659.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8070] width 1280 pitch 5120 (/4 1280) >[169659.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[169659.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[169660.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8070] >[169660.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8070] width 1280 pitch 5120 (/4 1280) >[169669.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[169669.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[169669.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[169669.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[169669.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c36a90] >[169669.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c36a90] width 1280 pitch 5120 (/4 1280) >[169669.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333bc90] >[169669.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333bc90] width 1280 pitch 5120 (/4 1280) >[169669.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d430] >[169669.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d430] width 1280 pitch 5120 (/4 1280) >[169669.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba1b0] >[169669.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba1b0] width 1280 pitch 5120 (/4 1280) >[169677.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1650] >[169677.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1650] width 1280 pitch 5120 (/4 1280) >[169677.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[169677.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[169677.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[169677.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[169677.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1650] >[169677.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1650] width 1280 pitch 5120 (/4 1280) >[169680.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8070] >[169680.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8070] width 1280 pitch 5120 (/4 1280) >[169680.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[169680.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[169680.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[169680.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[169680.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[169680.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[169695.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[169695.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[169695.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606fe0] >[169695.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606fe0] width 1280 pitch 5120 (/4 1280) >[169695.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[169695.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[169695.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606fe0] >[169695.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606fe0] width 1280 pitch 5120 (/4 1280) >[169696.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606fe0] >[169696.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606fe0] width 1280 pitch 5120 (/4 1280) >[169696.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[169696.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[169697.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606fe0] >[169697.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606fe0] width 1280 pitch 5120 (/4 1280) >[169697.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ae50] >[169697.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ae50] width 1280 pitch 5120 (/4 1280) >[169697.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[169697.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[169697.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[169697.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[169697.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[169697.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[169717.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37549f0] >[169717.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37549f0] width 1280 pitch 5120 (/4 1280) >[169719.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[169719.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[169719.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee80] >[169719.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee80] width 1280 pitch 5120 (/4 1280) >[169719.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[169719.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[169886.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee80] >[169886.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee80] width 1280 pitch 5120 (/4 1280) >[169886.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[169886.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[169886.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35899f0] >[169886.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35899f0] width 1280 pitch 5120 (/4 1280) >[169886.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[169886.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[169889.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[169889.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[169889.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b4b0] >[169889.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b4b0] width 1280 pitch 5120 (/4 1280) >[169889.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[169889.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[169889.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b4b0] >[169889.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b4b0] width 1280 pitch 5120 (/4 1280) >[169909.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[169909.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[169910.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[169910.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[169910.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[169910.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[169910.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[169910.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[170009.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76510] >[170009.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76510] width 1280 pitch 5120 (/4 1280) >[170014.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f50] >[170014.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f50] width 1280 pitch 5120 (/4 1280) >[170023.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[170023.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[170023.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3585fb0] >[170023.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3585fb0] width 1280 pitch 5120 (/4 1280) >[170023.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3585fb0] >[170023.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3585fb0] width 1280 pitch 5120 (/4 1280) >[170024.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261830] >[170024.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261830] width 1280 pitch 5120 (/4 1280) >[170024.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[170024.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[170024.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0bf0] >[170025.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0bf0] width 1280 pitch 5120 (/4 1280) >[170025.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[170025.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[170025.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0bf0] >[170025.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0bf0] width 1280 pitch 5120 (/4 1280) >[170046.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a1ba0] >[170046.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a1ba0] width 1280 pitch 5120 (/4 1280) >[170046.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[170046.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[170046.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609620] >[170046.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609620] width 1280 pitch 5120 (/4 1280) >[170046.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352170] >[170046.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352170] width 1280 pitch 5120 (/4 1280) >[170048.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31280] >[170048.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31280] width 1280 pitch 5120 (/4 1280) >[170094.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ca60] >[170094.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ca60] width 1280 pitch 5120 (/4 1280) >[170094.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3261a60] >[170094.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3261a60] width 1280 pitch 5120 (/4 1280) >[170094.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170094.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170094.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359ea00] >[170094.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359ea00] width 1280 pitch 5120 (/4 1280) >[170154.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33408b0] >[170154.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33408b0] width 1280 pitch 5120 (/4 1280) >[170154.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170154.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170154.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[170154.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[170154.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[170154.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[170241.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170241.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170241.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b580] >[170241.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b580] width 1280 pitch 5120 (/4 1280) >[170241.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170241.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170242.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333b580] >[170242.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333b580] width 1280 pitch 5120 (/4 1280) >[170246.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170246.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170246.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170246.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170246.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170246.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170246.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170246.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170625.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607ce0] >[170625.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607ce0] width 1280 pitch 5120 (/4 1280) >[170626.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[170626.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[170626.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607ce0] >[170626.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607ce0] width 1280 pitch 5120 (/4 1280) >[170626.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[170626.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[170651.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[170651.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[170651.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253430] >[170652.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253430] width 1280 pitch 5120 (/4 1280) >[170652.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[170652.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[170652.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[170652.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[170652.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[170652.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[170656.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358c6c0] >[170656.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358c6c0] width 1280 pitch 5120 (/4 1280) >[170657.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170657.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170657.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170657.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170661.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33408b0] >[170661.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33408b0] width 1280 pitch 5120 (/4 1280) >[170662.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[170662.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[170662.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170662.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170662.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[170662.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[170666.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[170667.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[170692.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170692.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170692.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353a10] >[170692.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353a10] width 1280 pitch 5120 (/4 1280) >[170693.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170693.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170693.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170693.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170693.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[170693.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[170693.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170693.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170697.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170697.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170697.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170697.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170697.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170697.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170697.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170697.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170697.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170697.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170697.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[170697.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[170697.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[170697.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[170697.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[170697.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[170698.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a2300] >[170698.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a2300] width 1280 pitch 5120 (/4 1280) >[170698.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[170698.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[170698.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[170698.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[170700.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e9270] >[170700.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e9270] width 1280 pitch 5120 (/4 1280) >[170700.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330bbf0] >[170700.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330bbf0] width 1280 pitch 5120 (/4 1280) >[170700.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48a50] >[170700.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48a50] width 1280 pitch 5120 (/4 1280) >[170700.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bf720] >[170700.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bf720] width 1280 pitch 5120 (/4 1280) >[170700.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48a50] >[170700.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48a50] width 1280 pitch 5120 (/4 1280) >[170700.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368e560] >[170700.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368e560] width 1280 pitch 5120 (/4 1280) >[170700.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338ab30] >[170700.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338ab30] width 1280 pitch 5120 (/4 1280) >[170700.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3317b90] >[170700.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3317b90] width 1280 pitch 5120 (/4 1280) >[170700.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3317b90] >[170700.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3317b90] width 1280 pitch 5120 (/4 1280) >[170700.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3749f70] >[170700.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3749f70] width 1280 pitch 5120 (/4 1280) >[170728.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bba50] >[170728.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bba50] width 1280 pitch 5120 (/4 1280) >[170729.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c448c0] >[170729.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c448c0] width 1280 pitch 5120 (/4 1280) >[170729.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338ab30] >[170729.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338ab30] width 1280 pitch 5120 (/4 1280) >[170730.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b1d90] >[170730.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b1d90] width 1280 pitch 5120 (/4 1280) >[170745.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3239240] >[170745.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3239240] width 1280 pitch 5120 (/4 1280) >[170747.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611fd0] >[170747.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611fd0] width 1280 pitch 5120 (/4 1280) >[170747.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611fd0] >[170747.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611fd0] width 1280 pitch 5120 (/4 1280) >[170747.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338ab30] >[170747.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338ab30] width 1280 pitch 5120 (/4 1280) >[170747.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611840] >[170747.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611840] width 1280 pitch 5120 (/4 1280) >[170793.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4540] >[170793.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4540] width 1280 pitch 5120 (/4 1280) >[170822.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7890] >[170822.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7890] width 1280 pitch 5120 (/4 1280) >[170824.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338ab30] >[170824.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338ab30] width 1280 pitch 5120 (/4 1280) >[170824.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c448c0] >[170824.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c448c0] width 1280 pitch 5120 (/4 1280) >[170824.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338ab30] >[170824.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338ab30] width 1280 pitch 5120 (/4 1280) >[170853.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323dcc0] >[170853.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323dcc0] width 1280 pitch 5120 (/4 1280) >[170855.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611fd0] >[170855.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611fd0] width 1280 pitch 5120 (/4 1280) >[170855.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3612450] >[170855.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3612450] width 1280 pitch 5120 (/4 1280) >[170855.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36123f0] >[170855.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36123f0] width 1280 pitch 5120 (/4 1280) >[170889.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c7050] >[170889.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c7050] width 1280 pitch 5120 (/4 1280) >[170891.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3611fd0] >[170891.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3611fd0] width 1280 pitch 5120 (/4 1280) >[171020.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332bc90] >[171020.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332bc90] width 1280 pitch 5120 (/4 1280) >[171022.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[171022.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[171022.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[171022.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[171022.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263bc0] >[171022.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263bc0] width 1280 pitch 5120 (/4 1280) >[171028.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332bc90] >[171028.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332bc90] width 1280 pitch 5120 (/4 1280) >[171028.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332bc90] >[171028.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332bc90] width 1280 pitch 5120 (/4 1280) >[171028.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[171028.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[171029.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[171029.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[171030.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ce00] >[171030.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ce00] width 1280 pitch 5120 (/4 1280) >[171030.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[171030.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[171030.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359ea00] >[171030.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359ea00] width 1280 pitch 5120 (/4 1280) >[171030.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[171031.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[171035.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331fc90] >[171035.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331fc90] width 1280 pitch 5120 (/4 1280) >[171035.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358ab10] >[171035.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358ab10] width 1280 pitch 5120 (/4 1280) >[171035.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[171035.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[171035.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358ab10] >[171035.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358ab10] width 1280 pitch 5120 (/4 1280) >[171040.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a2300] >[171040.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a2300] width 1280 pitch 5120 (/4 1280) >[171040.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab8f0] >[171040.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab8f0] width 1280 pitch 5120 (/4 1280) >[171040.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358ab10] >[171040.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358ab10] width 1280 pitch 5120 (/4 1280) >[171040.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c600] >[171040.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c600] width 1280 pitch 5120 (/4 1280) >[171043.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[171043.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[171043.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[171043.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[171047.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36df3f0] >[171047.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36df3f0] width 1280 pitch 5120 (/4 1280) >[171047.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[171047.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[171047.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368e820] >[171047.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368e820] width 1280 pitch 5120 (/4 1280) >[171047.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bdbc0] >[171047.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bdbc0] width 1280 pitch 5120 (/4 1280) >[171104.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[171104.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[171104.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[171105.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[171105.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[171105.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[171105.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[171105.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[171105.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[171105.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[171105.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[171105.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[171105.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[171105.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[171105.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[171105.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[171107.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf5a0] >[171107.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf5a0] width 1280 pitch 5120 (/4 1280) >[171107.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bf5a0] >[171107.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bf5a0] width 1280 pitch 5120 (/4 1280) >[171107.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[171107.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[171107.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[171107.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[171285.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[171285.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[171286.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359eb50] >[171286.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359eb50] width 1280 pitch 5120 (/4 1280) >[171286.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33855f0] >[171286.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33855f0] width 1280 pitch 5120 (/4 1280) >[171286.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359eb50] >[171286.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359eb50] width 1280 pitch 5120 (/4 1280) >[171476.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37183e0] >[171476.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37183e0] width 1280 pitch 5120 (/4 1280) >[171543.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368d9e0] >[171543.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368d9e0] width 1280 pitch 5120 (/4 1280) >[171549.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c24a00] >[171549.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c24a00] width 1280 pitch 5120 (/4 1280) >[171549.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c24a00] >[171549.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c24a00] width 1280 pitch 5120 (/4 1280) >[171549.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353a10] >[171549.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353a10] width 1280 pitch 5120 (/4 1280) >[171549.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0250] >[171549.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0250] width 1280 pitch 5120 (/4 1280) >[171587.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32be360] >[171587.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32be360] width 1280 pitch 5120 (/4 1280) >[171589.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598560] >[171589.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598560] width 1280 pitch 5120 (/4 1280) >[171590.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598560] >[171590.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598560] width 1280 pitch 5120 (/4 1280) >[171590.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca62f0] >[171590.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca62f0] width 1280 pitch 5120 (/4 1280) >[171590.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca62f0] >[171590.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca62f0] width 1280 pitch 5120 (/4 1280) >[171600.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b2780] >[171600.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b2780] width 1280 pitch 5120 (/4 1280) >[171603.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca62f0] >[171603.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca62f0] width 1280 pitch 5120 (/4 1280) >[171603.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1850] >[171603.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1850] width 1280 pitch 5120 (/4 1280) >[171603.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cbc20] >[171603.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cbc20] width 1280 pitch 5120 (/4 1280) >[171617.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598c40] >[171618.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598c40] width 1280 pitch 5120 (/4 1280) >[171618.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4100] >[171618.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4100] width 1280 pitch 5120 (/4 1280) >[171618.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359e790] >[171618.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359e790] width 1280 pitch 5120 (/4 1280) >[171618.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359e790] >[171618.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359e790] width 1280 pitch 5120 (/4 1280) >[171688.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3695060] >[171688.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3695060] width 1280 pitch 5120 (/4 1280) >[171690.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259990] >[171690.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259990] width 1280 pitch 5120 (/4 1280) >[171691.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d5a0] >[171691.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d5a0] width 1280 pitch 5120 (/4 1280) >[171691.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32314b0] >[171691.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32314b0] width 1280 pitch 5120 (/4 1280) >[171715.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8830] >[171715.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8830] width 1280 pitch 5120 (/4 1280) >[171716.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50880] >[171716.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50880] width 1280 pitch 5120 (/4 1280) >[171733.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a600] >[171733.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a600] width 1280 pitch 5120 (/4 1280) >[171733.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3110] >[171733.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3110] width 1280 pitch 5120 (/4 1280) >[171733.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5bf90] >[171733.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5bf90] width 1280 pitch 5120 (/4 1280) >[171733.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3110] >[171733.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3110] width 1280 pitch 5120 (/4 1280) >[171786.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b85b0] >[171786.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b85b0] width 1280 pitch 5120 (/4 1280) >[171792.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0300] >[171792.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0300] width 1280 pitch 5120 (/4 1280) >[171792.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ba070] >[171792.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ba070] width 1280 pitch 5120 (/4 1280) >[171792.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cf550] >[171792.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cf550] width 1280 pitch 5120 (/4 1280) >[171792.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ba070] >[171792.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ba070] width 1280 pitch 5120 (/4 1280) >[172003.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca17e0] >[172003.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca17e0] width 1280 pitch 5120 (/4 1280) >[172030.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ebb0] >[172031.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ebb0] width 1280 pitch 5120 (/4 1280) >[172031.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339290] >[172031.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339290] width 1280 pitch 5120 (/4 1280) >[172031.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4e80] >[172031.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4e80] width 1280 pitch 5120 (/4 1280) >[172031.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d04d0] >[172031.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d04d0] width 1280 pitch 5120 (/4 1280) >[172608.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f10] >[172608.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f10] width 1280 pitch 5120 (/4 1280) >[172609.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f10] >[172609.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f10] width 1280 pitch 5120 (/4 1280) >[172609.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdd30] >[172609.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdd30] width 1280 pitch 5120 (/4 1280) >[172609.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f10] >[172609.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f10] width 1280 pitch 5120 (/4 1280) >[172617.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdd30] >[172617.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdd30] width 1280 pitch 5120 (/4 1280) >[172618.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f10] >[172618.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f10] width 1280 pitch 5120 (/4 1280) >[172618.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[172618.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[172618.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[172618.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[172620.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[172620.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[172620.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[172620.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[172620.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[172620.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[172620.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[172620.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[176211.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2970] >[176211.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2970] width 1280 pitch 5120 (/4 1280) >[176211.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[176211.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[176211.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[176211.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[176211.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[176211.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[176211.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[176211.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[176211.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[176211.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[176211.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[176211.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[176211.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[176211.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[176211.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[176211.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[176211.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[176211.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177031.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177031.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177031.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177031.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177031.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177032.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177032.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177032.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177032.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177032.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177032.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177032.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177032.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177032.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177032.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177032.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177032.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177032.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177036.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177036.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177036.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177036.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177036.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177036.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177036.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177036.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177036.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177036.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177036.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177036.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177036.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177036.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177036.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177036.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177036.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177036.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177037.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177037.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177037.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177037.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177037.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177037.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177037.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177037.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177037.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177037.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177037.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177037.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177037.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177037.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[177037.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[177037.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[177037.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[177037.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197930.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334880] >[197930.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334880] width 1280 pitch 5120 (/4 1280) >[197930.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197930.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197997.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c365d0] >[197997.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c365d0] width 1280 pitch 5120 (/4 1280) >[197998.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197998.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197998.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e0100] >[197998.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e0100] width 1280 pitch 5120 (/4 1280) >[197998.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[197998.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[197998.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b45f0] >[197998.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b45f0] width 1280 pitch 5120 (/4 1280) >[197998.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3d60] >[197998.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3d60] width 1280 pitch 5120 (/4 1280) >[198169.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3260ba0] >[198169.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3260ba0] width 1280 pitch 5120 (/4 1280) >[198169.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3260ba0] >[198169.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3260ba0] width 1280 pitch 5120 (/4 1280) >[198786.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c303b0] >[198786.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c303b0] width 1280 pitch 5120 (/4 1280) >[198787.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b88e0] >[198787.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b88e0] width 1280 pitch 5120 (/4 1280) >[198787.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdd30] >[198787.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdd30] width 1280 pitch 5120 (/4 1280) >[198787.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b88e0] >[198787.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b88e0] width 1280 pitch 5120 (/4 1280) >[198790.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[198790.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[198790.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ed90] >[198790.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ed90] width 1280 pitch 5120 (/4 1280) >[198790.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cedf0] >[198790.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cedf0] width 1280 pitch 5120 (/4 1280) >[198790.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ceed0] >[198790.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ceed0] width 1280 pitch 5120 (/4 1280) >[198794.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2770] >[198794.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2770] width 1280 pitch 5120 (/4 1280) >[199049.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ed90] >[199049.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ed90] width 1280 pitch 5120 (/4 1280) >[199050.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[199050.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[199050.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332f0b0] >[199050.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332f0b0] width 1280 pitch 5120 (/4 1280) >[199050.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[199050.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[199834.511] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[199834.511] (II) RADEON(0): Using hsync ranges from config file >[199834.511] (II) RADEON(0): Using vrefresh ranges from config file >[199834.511] (II) RADEON(0): Printing DDC gathered Modelines: >[199834.511] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[199834.511] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[199834.511] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[199834.511] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[199834.511] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[199834.511] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[199834.511] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[199834.511] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[199834.511] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[199834.511] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[199924.555] (II) RADEON(0): RADEONSaveScreen(2) >[199924.555] (II) RADEON(0): RADEONSaveScreen(0) >[201093.013] (II) RADEON(0): RADEONSaveScreen(1) >[201783.535] (II) RADEON(0): RADEONSaveScreen(2) >[201783.535] (II) RADEON(0): RADEONSaveScreen(0) >[202034.272] (II) RADEON(0): RADEONSaveScreen(1) >[202724.542] (II) RADEON(0): RADEONSaveScreen(2) >[202724.543] (II) RADEON(0): RADEONSaveScreen(0) >[202750.457] (II) RADEON(0): RADEONSaveScreen(1) >[202830.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c179e0] >[202830.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c179e0] width 1280 pitch 5120 (/4 1280) >[203440.536] (II) RADEON(0): RADEONSaveScreen(2) >[203440.536] (II) RADEON(0): RADEONSaveScreen(0) >[232748.475] (II) RADEON(0): RADEONSaveScreen(1) >[233497.543] (II) RADEON(0): RADEONSaveScreen(2) >[233497.543] (II) RADEON(0): RADEONSaveScreen(0) >[235099.316] (II) RADEON(0): RADEONSaveScreen(1) >[235104.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3233d30] >[235104.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3233d30] width 1280 pitch 5120 (/4 1280) >[235105.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368d1b0] >[235105.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368d1b0] width 1280 pitch 5120 (/4 1280) >[235105.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[235105.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[235105.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368d1b0] >[235105.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368d1b0] width 1280 pitch 5120 (/4 1280) >[235105.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368d1b0] >[235105.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368d1b0] width 1280 pitch 5120 (/4 1280) >[235109.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2bc0] >[235109.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2bc0] width 1280 pitch 5120 (/4 1280) >[235114.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3c90] >[235114.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3c90] width 1280 pitch 5120 (/4 1280) >[235119.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cec80] >[235119.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cec80] width 1280 pitch 5120 (/4 1280) >[235119.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[235119.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[235119.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ceed0] >[235119.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ceed0] width 1280 pitch 5120 (/4 1280) >[235141.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3190] >[235141.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3190] width 1280 pitch 5120 (/4 1280) >[235198.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369ef50] >[235198.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369ef50] width 1280 pitch 5120 (/4 1280) >[236046.889] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[236046.889] (II) RADEON(0): Using hsync ranges from config file >[236046.889] (II) RADEON(0): Using vrefresh ranges from config file >[236046.889] (II) RADEON(0): Printing DDC gathered Modelines: >[236046.889] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[236046.889] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[236046.889] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[236046.889] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[236046.889] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[236046.889] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[236046.889] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[236046.889] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[236046.889] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[236046.889] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[236137.535] (II) RADEON(0): RADEONSaveScreen(2) >[236137.535] (II) RADEON(0): RADEONSaveScreen(0) >[239653.407] (II) RADEON(0): RADEONSaveScreen(1) >[239653.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3190] >[239653.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3190] width 1280 pitch 5120 (/4 1280) >[239657.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239657.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239665.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[239665.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[239665.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369b870] >[239665.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369b870] width 1280 pitch 5120 (/4 1280) >[239665.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239665.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239665.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239665.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239665.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239665.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239665.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239665.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239665.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239665.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239665.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239665.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239665.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239665.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239665.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239665.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239665.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239666.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239666.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239666.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239666.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239666.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239666.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d0090] >[239666.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d0090] width 1280 pitch 5120 (/4 1280) >[239668.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca4f0] >[239668.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca4f0] width 1280 pitch 5120 (/4 1280) >[239668.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239668.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239668.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca4f0] >[239668.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca4f0] width 1280 pitch 5120 (/4 1280) >[239668.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239668.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239668.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fc980] >[239668.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fc980] width 1280 pitch 5120 (/4 1280) >[239668.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fc7d0] >[239668.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fc7d0] width 1280 pitch 5120 (/4 1280) >[239668.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239668.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239668.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239668.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239668.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239669.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239669.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239669.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239669.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239669.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239669.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239669.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239669.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239669.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239669.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239669.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239669.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239669.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239669.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239669.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239669.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239669.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239670.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239670.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fcac0] >[239670.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fcac0] width 1280 pitch 5120 (/4 1280) >[239670.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[239670.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[239670.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239670.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[239670.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[239670.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239670.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[239670.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[239670.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239670.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[239670.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[239670.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239670.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[239670.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[239670.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239670.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239671.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4579230] >[239672.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4579230] width 1280 pitch 5120 (/4 1280) >[239673.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba5a20] >[239673.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba5a20] width 1280 pitch 5120 (/4 1280) >[239673.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676440] >[239674.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676440] width 1280 pitch 5120 (/4 1280) >[239674.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3675760] >[239674.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3675760] width 1280 pitch 5120 (/4 1280) >[239674.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679f80] >[239674.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679f80] width 1280 pitch 5120 (/4 1280) >[239776.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459d2a0] >[239776.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459d2a0] width 1280 pitch 5120 (/4 1280) >[239779.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3614fd0] >[239779.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3614fd0] width 1280 pitch 5120 (/4 1280) >[239785.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab4530] >[239785.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab4530] width 1280 pitch 5120 (/4 1280) >[239785.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369a4d0] >[239785.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369a4d0] width 1280 pitch 5120 (/4 1280) >[239785.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4accfb0] >[239785.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4accfb0] width 1280 pitch 5120 (/4 1280) >[239785.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369ef50] >[239785.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369ef50] width 1280 pitch 5120 (/4 1280) >[239785.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[239785.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[239796.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[239796.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[239796.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3614660] >[239796.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3614660] width 1280 pitch 5120 (/4 1280) >[239796.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[239796.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[239796.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[239796.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[239853.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe530] >[239853.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe530] width 1280 pitch 5120 (/4 1280) >[239857.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c13690] >[239857.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c13690] width 1280 pitch 5120 (/4 1280) >[239857.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e33f0] >[239857.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e33f0] width 1280 pitch 5120 (/4 1280) >[239857.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e33f0] >[239857.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e33f0] width 1280 pitch 5120 (/4 1280) >[239857.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf2b0] >[239857.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf2b0] width 1280 pitch 5120 (/4 1280) >[239873.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[239873.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[239873.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[239873.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[239873.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ffe10] >[239873.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ffe10] width 1280 pitch 5120 (/4 1280) >[239873.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbfec0] >[239873.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbfec0] width 1280 pitch 5120 (/4 1280) >[239906.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c9d90] >[239906.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c9d90] width 1280 pitch 5120 (/4 1280) >[239906.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c9d90] >[239906.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c9d90] width 1280 pitch 5120 (/4 1280) >[239915.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3588a40] >[239915.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3588a40] width 1280 pitch 5120 (/4 1280) >[239915.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32363e0] >[239915.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32363e0] width 1280 pitch 5120 (/4 1280) >[239915.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b4cf0] >[239915.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b4cf0] width 1280 pitch 5120 (/4 1280) >[239915.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369de30] >[239915.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369de30] width 1280 pitch 5120 (/4 1280) >[239930.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[239930.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[239931.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32363e0] >[239931.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32363e0] width 1280 pitch 5120 (/4 1280) >[239931.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e33f0] >[239931.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e33f0] width 1280 pitch 5120 (/4 1280) >[239931.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32363e0] >[239931.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32363e0] width 1280 pitch 5120 (/4 1280) >[239964.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323b1b0] >[239964.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323b1b0] width 1280 pitch 5120 (/4 1280) >[239964.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323b1b0] >[239964.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323b1b0] width 1280 pitch 5120 (/4 1280) >[239964.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239964.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239964.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36974a0] >[239964.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36974a0] width 1280 pitch 5120 (/4 1280) >[239966.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676440] >[239966.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676440] width 1280 pitch 5120 (/4 1280) >[239966.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239966.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239966.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239966.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239966.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239966.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239966.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239966.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239966.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239966.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239966.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239966.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239966.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239966.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239966.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239966.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239966.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[239966.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[239966.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a4d50] >[239966.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a4d50] width 1280 pitch 5120 (/4 1280) >[239966.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369b870] >[239966.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369b870] width 1280 pitch 5120 (/4 1280) >[240005.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1d90] >[240005.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1d90] width 1280 pitch 5120 (/4 1280) >[240010.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[240010.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[240010.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676440] >[240010.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676440] width 1280 pitch 5120 (/4 1280) >[240010.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[240010.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[240010.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676440] >[240010.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676440] width 1280 pitch 5120 (/4 1280) >[240231.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[240231.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[240232.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[240232.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[240232.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3a40] >[240232.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3a40] width 1280 pitch 5120 (/4 1280) >[240247.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9510] >[240247.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9510] width 1280 pitch 5120 (/4 1280) >[240247.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b94b0] >[240247.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b94b0] width 1280 pitch 5120 (/4 1280) >[240252.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35da420] >[240252.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35da420] width 1280 pitch 5120 (/4 1280) >[240252.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b4150] >[240252.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b4150] width 1280 pitch 5120 (/4 1280) >[240252.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[240252.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[240252.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[240252.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[240266.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[240266.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[240267.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3391470] >[240267.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3391470] width 1280 pitch 5120 (/4 1280) >[240267.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323afd0] >[240267.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323afd0] width 1280 pitch 5120 (/4 1280) >[240267.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e3000] >[240267.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e3000] width 1280 pitch 5120 (/4 1280) >[240271.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[240271.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[240271.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8d20] >[240271.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8d20] width 1280 pitch 5120 (/4 1280) >[240271.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704f10] >[240271.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704f10] width 1280 pitch 5120 (/4 1280) >[240271.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8d20] >[240271.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8d20] width 1280 pitch 5120 (/4 1280) >[240275.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8d20] >[240275.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8d20] width 1280 pitch 5120 (/4 1280) >[240275.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c790] >[240275.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c790] width 1280 pitch 5120 (/4 1280) >[240275.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8f30] >[240275.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8f30] width 1280 pitch 5120 (/4 1280) >[240276.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b4cf0] >[240276.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b4cf0] width 1280 pitch 5120 (/4 1280) >[240360.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca4f0] >[240360.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca4f0] width 1280 pitch 5120 (/4 1280) >[240360.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[240360.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[240360.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca4f0] >[240360.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca4f0] width 1280 pitch 5120 (/4 1280) >[240361.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[240361.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[240361.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[240361.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[240361.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[240361.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[240362.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33408b0] >[240362.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33408b0] width 1280 pitch 5120 (/4 1280) >[240362.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[240362.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[240362.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f16a0] >[240362.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f16a0] width 1280 pitch 5120 (/4 1280) >[240365.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1f80] >[240365.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1f80] width 1280 pitch 5120 (/4 1280) >[240367.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361c770] >[240367.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361c770] width 1280 pitch 5120 (/4 1280) >[240369.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc230] >[240369.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc230] width 1280 pitch 5120 (/4 1280) >[240369.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302b80] >[240369.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302b80] width 1280 pitch 5120 (/4 1280) >[240369.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc230] >[240369.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc230] width 1280 pitch 5120 (/4 1280) >[240369.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302b80] >[240369.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302b80] width 1280 pitch 5120 (/4 1280) >[240377.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f14d0] >[240377.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f14d0] width 1280 pitch 5120 (/4 1280) >[240377.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf340] >[240377.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf340] width 1280 pitch 5120 (/4 1280) >[240377.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fced0] >[240377.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fced0] width 1280 pitch 5120 (/4 1280) >[240377.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf340] >[240377.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf340] width 1280 pitch 5120 (/4 1280) >[240378.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf340] >[240378.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf340] width 1280 pitch 5120 (/4 1280) >[240378.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[240378.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[240378.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b4cf0] >[240378.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b4cf0] width 1280 pitch 5120 (/4 1280) >[240378.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[240378.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[240966.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3733940] >[240966.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3733940] width 1280 pitch 5120 (/4 1280) >[241211.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1d70] >[241211.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1d70] width 1280 pitch 5120 (/4 1280) >[241216.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ab70] >[241216.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ab70] width 1280 pitch 5120 (/4 1280) >[241216.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a0c20] >[241217.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a0c20] width 1280 pitch 5120 (/4 1280) >[241217.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ab70] >[241217.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ab70] width 1280 pitch 5120 (/4 1280) >[241217.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a0c20] >[241217.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a0c20] width 1280 pitch 5120 (/4 1280) >[241805.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ff180] >[241805.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ff180] width 1280 pitch 5120 (/4 1280) >[241806.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d64d0] >[241806.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d64d0] width 1280 pitch 5120 (/4 1280) >[241806.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bbab0] >[241806.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bbab0] width 1280 pitch 5120 (/4 1280) >[241806.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ff180] >[241806.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ff180] width 1280 pitch 5120 (/4 1280) >[241806.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d64d0] >[241806.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d64d0] width 1280 pitch 5120 (/4 1280) >[241806.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bbab0] >[241806.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bbab0] width 1280 pitch 5120 (/4 1280) >[242079.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3200] >[242080.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3200] width 1280 pitch 5120 (/4 1280) >[242080.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0d10] >[242080.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0d10] width 1280 pitch 5120 (/4 1280) >[242080.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340a000] >[242080.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340a000] width 1280 pitch 5120 (/4 1280) >[242080.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1ac0] >[242080.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1ac0] width 1280 pitch 5120 (/4 1280) >[242215.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a30d0] >[242215.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a30d0] width 1280 pitch 5120 (/4 1280) >[242215.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375be80] >[242215.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375be80] width 1280 pitch 5120 (/4 1280) >[242215.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242215.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242215.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[242215.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[242246.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242246.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242247.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242247.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242247.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c50c0] >[242247.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c50c0] width 1280 pitch 5120 (/4 1280) >[242247.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242247.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242248.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[242248.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[242248.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[242248.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[242253.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[242253.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[242254.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca4f0] >[242254.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca4f0] width 1280 pitch 5120 (/4 1280) >[242254.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ed540] >[242254.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ed540] width 1280 pitch 5120 (/4 1280) >[242254.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d8e00] >[242254.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d8e00] width 1280 pitch 5120 (/4 1280) >[242662.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3685900] >[242662.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3685900] width 1280 pitch 5120 (/4 1280) >[242668.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9000] >[242668.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9000] width 1280 pitch 5120 (/4 1280) >[242668.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acfbc0] >[242668.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acfbc0] width 1280 pitch 5120 (/4 1280) >[242668.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[242668.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[242668.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acfbc0] >[242668.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acfbc0] width 1280 pitch 5120 (/4 1280) >[242669.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[242669.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[242669.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242669.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242669.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[242669.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[242669.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acfd20] >[242669.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acfd20] width 1280 pitch 5120 (/4 1280) >[242669.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9000] >[242669.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9000] width 1280 pitch 5120 (/4 1280) >[242669.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b8f0] >[242669.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b8f0] width 1280 pitch 5120 (/4 1280) >[242671.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[242671.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[242671.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb4d0] >[242671.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb4d0] width 1280 pitch 5120 (/4 1280) >[242671.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb4d0] >[242671.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb4d0] width 1280 pitch 5120 (/4 1280) >[242677.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[242677.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[242678.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[242678.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[242678.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367fcf0] >[242678.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367fcf0] width 1280 pitch 5120 (/4 1280) >[242678.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[242678.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[242678.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4584bc0] >[242678.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4584bc0] width 1280 pitch 5120 (/4 1280) >[242678.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c7ef0] >[242678.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c7ef0] width 1280 pitch 5120 (/4 1280) >[242679.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3b00] >[242679.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3b00] width 1280 pitch 5120 (/4 1280) >[242679.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd0f0] >[242679.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd0f0] width 1280 pitch 5120 (/4 1280) >[242680.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ceeb0] >[242680.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ceeb0] width 1280 pitch 5120 (/4 1280) >[242680.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683210] >[242680.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683210] width 1280 pitch 5120 (/4 1280) >[242680.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676310] >[242681.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676310] width 1280 pitch 5120 (/4 1280) >[242704.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[242704.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[242704.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[242704.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[242704.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32bab80] >[242704.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32bab80] width 1280 pitch 5120 (/4 1280) >[242704.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[242704.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[242705.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[242705.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[242705.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[242705.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[242705.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b890] >[242705.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b890] width 1280 pitch 5120 (/4 1280) >[242705.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676180] >[242705.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676180] width 1280 pitch 5120 (/4 1280) >[242705.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3410] >[242705.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3410] width 1280 pitch 5120 (/4 1280) >[242705.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3b00] >[242705.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3b00] width 1280 pitch 5120 (/4 1280) >[242790.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[242790.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[242790.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ed60] >[242790.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ed60] width 1280 pitch 5120 (/4 1280) >[242790.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367fcf0] >[242790.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367fcf0] width 1280 pitch 5120 (/4 1280) >[242790.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683210] >[242790.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683210] width 1280 pitch 5120 (/4 1280) >[242791.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3372ff0] >[242791.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3372ff0] width 1280 pitch 5120 (/4 1280) >[242791.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[242791.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[242791.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36258e0] >[242791.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36258e0] width 1280 pitch 5120 (/4 1280) >[242791.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683210] >[242791.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683210] width 1280 pitch 5120 (/4 1280) >[242801.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361f430] >[242801.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361f430] width 1280 pitch 5120 (/4 1280) >[242801.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361f430] >[242801.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361f430] width 1280 pitch 5120 (/4 1280) >[242801.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[242801.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[242801.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361f430] >[242801.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361f430] width 1280 pitch 5120 (/4 1280) >[242801.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[242801.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[242801.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9000] >[242801.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9000] width 1280 pitch 5120 (/4 1280) >[242801.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[242801.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[242801.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9000] >[242801.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9000] width 1280 pitch 5120 (/4 1280) >[242802.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c10450] >[242802.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c10450] width 1280 pitch 5120 (/4 1280) >[242802.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[242802.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[242819.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694e00] >[242819.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694e00] width 1280 pitch 5120 (/4 1280) >[242820.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315e000] >[242820.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315e000] width 1280 pitch 5120 (/4 1280) >[242820.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676180] >[242820.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676180] width 1280 pitch 5120 (/4 1280) >[242820.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c00d30] >[242820.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c00d30] width 1280 pitch 5120 (/4 1280) >[242820.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676180] >[242820.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676180] width 1280 pitch 5120 (/4 1280) >[242824.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[242824.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[242824.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[242824.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[242824.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb4d0] >[242824.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb4d0] width 1280 pitch 5120 (/4 1280) >[242824.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[242824.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[242824.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb4d0] >[242824.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb4d0] width 1280 pitch 5120 (/4 1280) >[242825.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315e000] >[242825.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315e000] width 1280 pitch 5120 (/4 1280) >[242825.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242825.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242825.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[242825.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[242825.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[242825.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[242827.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[242827.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[242827.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315e000] >[242827.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315e000] width 1280 pitch 5120 (/4 1280) >[242827.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[242828.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[243306.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[243306.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[243306.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367fcf0] >[243306.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367fcf0] width 1280 pitch 5120 (/4 1280) >[243306.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[243306.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[243306.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367fcf0] >[243306.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367fcf0] width 1280 pitch 5120 (/4 1280) >[243307.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361f430] >[243307.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361f430] width 1280 pitch 5120 (/4 1280) >[243307.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[243307.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[243307.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c7b80] >[243307.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c7b80] width 1280 pitch 5120 (/4 1280) >[243307.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c7b80] >[243307.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c7b80] width 1280 pitch 5120 (/4 1280) >[244017.530] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[244017.530] (II) RADEON(0): Using hsync ranges from config file >[244017.530] (II) RADEON(0): Using vrefresh ranges from config file >[244017.530] (II) RADEON(0): Printing DDC gathered Modelines: >[244017.530] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[244017.530] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[244017.530] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[244017.530] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[244017.530] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[244017.531] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[244017.531] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[244017.531] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[244017.531] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[244017.531] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[244107.536] (II) RADEON(0): RADEONSaveScreen(2) >[244107.536] (II) RADEON(0): RADEONSaveScreen(0) >[245136.393] (II) RADEON(0): RADEONSaveScreen(1) >[245144.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3672710] >[245144.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3672710] width 1280 pitch 5120 (/4 1280) >[245161.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3625350] >[245161.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3625350] width 1280 pitch 5120 (/4 1280) >[245161.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361fe80] >[245161.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361fe80] width 1280 pitch 5120 (/4 1280) >[245162.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d9960] >[245162.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d9960] width 1280 pitch 5120 (/4 1280) >[245163.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358f340] >[245163.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358f340] width 1280 pitch 5120 (/4 1280) >[245163.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3625350] >[245163.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3625350] width 1280 pitch 5120 (/4 1280) >[245163.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cbef0] >[245163.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cbef0] width 1280 pitch 5120 (/4 1280) >[245171.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a3570] >[245171.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a3570] width 1280 pitch 5120 (/4 1280) >[245172.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a3570] >[245172.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a3570] width 1280 pitch 5120 (/4 1280) >[245172.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[245172.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[245172.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[245172.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[245172.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[245172.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[245172.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341efa0] >[245172.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341efa0] width 1280 pitch 5120 (/4 1280) >[245223.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9000] >[245223.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9000] width 1280 pitch 5120 (/4 1280) >[245224.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa4a0] >[245224.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa4a0] width 1280 pitch 5120 (/4 1280) >[245224.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa4a0] >[245224.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa4a0] width 1280 pitch 5120 (/4 1280) >[245224.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[245224.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[245224.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa4a0] >[245224.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa4a0] width 1280 pitch 5120 (/4 1280) >[245225.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa4a0] >[245225.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa4a0] width 1280 pitch 5120 (/4 1280) >[245225.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[245225.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[245225.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a90] >[245225.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a90] width 1280 pitch 5120 (/4 1280) >[245225.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[245225.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[245231.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36727c0] >[245232.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36727c0] width 1280 pitch 5120 (/4 1280) >[245232.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a50d0] >[245232.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a50d0] width 1280 pitch 5120 (/4 1280) >[245232.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[245232.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[245232.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a50d0] >[245232.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a50d0] width 1280 pitch 5120 (/4 1280) >[245232.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab5920] >[245233.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab5920] width 1280 pitch 5120 (/4 1280) >[245233.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a50d0] >[245233.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a50d0] width 1280 pitch 5120 (/4 1280) >[245466.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[245466.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[245467.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[245467.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[245467.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[245467.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[245467.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[245467.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[245467.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1290] >[245467.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1290] width 1280 pitch 5120 (/4 1280) >[245467.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ea60] >[245467.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ea60] width 1280 pitch 5120 (/4 1280) >[245585.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341efa0] >[245585.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341efa0] width 1280 pitch 5120 (/4 1280) >[245586.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3303170] >[245586.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3303170] width 1280 pitch 5120 (/4 1280) >[245586.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[245586.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[245586.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3303170] >[245586.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3303170] width 1280 pitch 5120 (/4 1280) >[245593.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367e230] >[245593.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367e230] width 1280 pitch 5120 (/4 1280) >[245712.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab5920] >[245712.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab5920] width 1280 pitch 5120 (/4 1280) >[245712.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a90] >[245712.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a90] width 1280 pitch 5120 (/4 1280) >[245712.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620f90] >[245712.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620f90] width 1280 pitch 5120 (/4 1280) >[245712.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a90] >[245712.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a90] width 1280 pitch 5120 (/4 1280) >[245713.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[245713.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[245714.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[245714.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[245714.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[245714.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[245714.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a90] >[245714.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a90] width 1280 pitch 5120 (/4 1280) >[246361.045] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[246361.045] (II) RADEON(0): Using hsync ranges from config file >[246361.045] (II) RADEON(0): Using vrefresh ranges from config file >[246361.045] (II) RADEON(0): Printing DDC gathered Modelines: >[246361.045] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[246361.045] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[246361.045] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[246361.045] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[246361.045] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[246361.045] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[246361.046] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[246361.046] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[246361.046] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[246361.046] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[246372.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36859f0] >[246372.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36859f0] width 1280 pitch 5120 (/4 1280) >[246904.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b0720] >[246904.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b0720] width 1280 pitch 5120 (/4 1280) >[247386.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34558d0] >[247387.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34558d0] width 1280 pitch 5120 (/4 1280) >[247387.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[247387.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[247387.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[247387.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[247387.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[247387.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[247455.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc860] >[247455.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc860] width 1280 pitch 5120 (/4 1280) >[247818.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3699330] >[247818.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3699330] width 1280 pitch 5120 (/4 1280) >[247819.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3699330] >[247819.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3699330] width 1280 pitch 5120 (/4 1280) >[247820.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33891f0] >[247820.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33891f0] width 1280 pitch 5120 (/4 1280) >[247820.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe430] >[247820.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe430] width 1280 pitch 5120 (/4 1280) >[247820.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3699330] >[247820.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3699330] width 1280 pitch 5120 (/4 1280) >[247820.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe430] >[247820.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe430] width 1280 pitch 5120 (/4 1280) >[247823.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3699330] >[247823.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3699330] width 1280 pitch 5120 (/4 1280) >[247823.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe430] >[247823.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe430] width 1280 pitch 5120 (/4 1280) >[247823.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2dc0] >[247823.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2dc0] width 1280 pitch 5120 (/4 1280) >[247823.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe430] >[247823.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe430] width 1280 pitch 5120 (/4 1280) >[248049.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a380] >[248049.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a380] width 1280 pitch 5120 (/4 1280) >[248050.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248050.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248050.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[248050.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[248050.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248050.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248484.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248484.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248484.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248484.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248484.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248484.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248484.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248484.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248484.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248485.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248485.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[248485.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[248485.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248485.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248485.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[248485.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[248485.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248485.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248485.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[248485.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[248485.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[248485.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[248485.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34558d0] >[248485.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34558d0] width 1280 pitch 5120 (/4 1280) >[248485.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ee50] >[248485.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ee50] width 1280 pitch 5120 (/4 1280) >[248485.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34558d0] >[248485.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34558d0] width 1280 pitch 5120 (/4 1280) >[248485.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ee50] >[248485.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ee50] width 1280 pitch 5120 (/4 1280) >[248485.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34558d0] >[248485.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34558d0] width 1280 pitch 5120 (/4 1280) >[248485.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371ee50] >[248485.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371ee50] width 1280 pitch 5120 (/4 1280) >[248485.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34558d0] >[248485.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34558d0] width 1280 pitch 5120 (/4 1280) >[248485.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35903c0] >[248485.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35903c0] width 1280 pitch 5120 (/4 1280) >[248485.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b040] >[248485.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b040] width 1280 pitch 5120 (/4 1280) >[248485.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[248485.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[248485.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[248485.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[248485.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[248485.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[248485.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[248485.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[248485.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[248485.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[248485.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[248485.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[248485.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[248485.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[248485.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[248485.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[248485.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[248486.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[248487.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3732ac0] >[248487.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3732ac0] width 1280 pitch 5120 (/4 1280) >[248546.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dd80] >[248546.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dd80] width 1280 pitch 5120 (/4 1280) >[248546.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4320] >[248546.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4320] width 1280 pitch 5120 (/4 1280) >[248546.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248546.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248546.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa35b0] >[248546.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa35b0] width 1280 pitch 5120 (/4 1280) >[248558.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248558.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248558.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[248559.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[248559.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3684340] >[248559.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3684340] width 1280 pitch 5120 (/4 1280) >[248559.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[248559.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[248569.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[248569.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[248570.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248570.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248570.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371f0e0] >[248570.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371f0e0] width 1280 pitch 5120 (/4 1280) >[248570.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248570.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248570.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36727c0] >[248570.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36727c0] width 1280 pitch 5120 (/4 1280) >[248570.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c4f0] >[248570.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c4f0] width 1280 pitch 5120 (/4 1280) >[248572.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[248572.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[248572.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[248572.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[248572.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7610] >[248572.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7610] width 1280 pitch 5120 (/4 1280) >[248572.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[248572.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[248621.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375de80] >[248621.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375de80] width 1280 pitch 5120 (/4 1280) >[248622.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248622.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248622.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36727c0] >[248622.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36727c0] width 1280 pitch 5120 (/4 1280) >[248622.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c5f80] >[248622.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c5f80] width 1280 pitch 5120 (/4 1280) >[248625.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36727c0] >[248625.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36727c0] width 1280 pitch 5120 (/4 1280) >[248625.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371d030] >[248625.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371d030] width 1280 pitch 5120 (/4 1280) >[248625.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a90] >[248625.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a90] width 1280 pitch 5120 (/4 1280) >[248625.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbdbc0] >[248625.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbdbc0] width 1280 pitch 5120 (/4 1280) >[248633.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248633.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248634.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248634.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248634.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35903c0] >[248634.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35903c0] width 1280 pitch 5120 (/4 1280) >[248634.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[248634.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[248637.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[248637.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[248637.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248637.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248637.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[248637.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[248637.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248637.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248637.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[248637.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[248637.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248637.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248637.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[248637.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[248637.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248637.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248638.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417670] >[248638.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417670] width 1280 pitch 5120 (/4 1280) >[248638.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4320] >[248638.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4320] width 1280 pitch 5120 (/4 1280) >[248638.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417670] >[248638.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417670] width 1280 pitch 5120 (/4 1280) >[248638.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4320] >[248638.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4320] width 1280 pitch 5120 (/4 1280) >[248638.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417670] >[248638.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417670] width 1280 pitch 5120 (/4 1280) >[248638.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4320] >[248638.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4320] width 1280 pitch 5120 (/4 1280) >[248638.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417670] >[248638.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417670] width 1280 pitch 5120 (/4 1280) >[248638.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4320] >[248638.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4320] width 1280 pitch 5120 (/4 1280) >[248638.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248638.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248733.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[248733.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[248733.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248733.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248733.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3726e70] >[248733.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3726e70] width 1280 pitch 5120 (/4 1280) >[248733.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[248733.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[248758.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a380] >[248758.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a380] width 1280 pitch 5120 (/4 1280) >[248758.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[248758.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[248758.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[248758.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[248759.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[248759.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[249337.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249338.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249432.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249432.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249435.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249435.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249435.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249435.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249435.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abc070] >[249435.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abc070] width 1280 pitch 5120 (/4 1280) >[249435.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249435.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249515.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c2f70] >[249515.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c2f70] width 1280 pitch 5120 (/4 1280) >[249628.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a4f00] >[249628.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a4f00] width 1280 pitch 5120 (/4 1280) >[249628.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325a380] >[249628.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325a380] width 1280 pitch 5120 (/4 1280) >[249631.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d390] >[249631.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d390] width 1280 pitch 5120 (/4 1280) >[249631.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[249631.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[249631.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a2e0] >[249632.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a2e0] width 1280 pitch 5120 (/4 1280) >[249632.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[249632.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[249633.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459aa40] >[249634.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459aa40] width 1280 pitch 5120 (/4 1280) >[249634.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499f60] >[249634.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499f60] width 1280 pitch 5120 (/4 1280) >[249641.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[249641.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[249641.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34090a0] >[249641.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34090a0] width 1280 pitch 5120 (/4 1280) >[249641.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a7500] >[249641.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a7500] width 1280 pitch 5120 (/4 1280) >[249641.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3241ad0] >[249641.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3241ad0] width 1280 pitch 5120 (/4 1280) >[250306.803] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[250306.803] (II) RADEON(0): Using hsync ranges from config file >[250306.803] (II) RADEON(0): Using vrefresh ranges from config file >[250306.803] (II) RADEON(0): Printing DDC gathered Modelines: >[250306.803] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[250306.803] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[250306.803] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[250306.803] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[250306.803] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[250306.803] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[250306.804] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[250306.804] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[250306.804] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[250306.804] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[250396.554] (II) RADEON(0): RADEONSaveScreen(2) >[250396.554] (II) RADEON(0): RADEONSaveScreen(0) >[253969.259] (II) RADEON(0): RADEONSaveScreen(1) >[254862.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bc940] >[254862.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bc940] width 1280 pitch 5120 (/4 1280) >[254997.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c48c0] >[254997.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c48c0] width 1280 pitch 5120 (/4 1280) >[254997.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336db20] >[254997.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336db20] width 1280 pitch 5120 (/4 1280) >[254997.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590ff0] >[254997.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590ff0] width 1280 pitch 5120 (/4 1280) >[254997.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499f80] >[254997.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499f80] width 1280 pitch 5120 (/4 1280) >[254997.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590ff0] >[254997.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590ff0] width 1280 pitch 5120 (/4 1280) >[255003.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bc940] >[255003.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bc940] width 1280 pitch 5120 (/4 1280) >[255003.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa35b0] >[255003.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa35b0] width 1280 pitch 5120 (/4 1280) >[255003.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bc940] >[255003.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bc940] width 1280 pitch 5120 (/4 1280) >[255003.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459aa40] >[255003.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459aa40] width 1280 pitch 5120 (/4 1280) >[255007.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255007.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255008.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255008.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255008.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bc940] >[255008.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bc940] width 1280 pitch 5120 (/4 1280) >[255008.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255008.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255020.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255020.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255020.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459aa40] >[255020.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459aa40] width 1280 pitch 5120 (/4 1280) >[255020.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a74a0] >[255020.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a74a0] width 1280 pitch 5120 (/4 1280) >[255020.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459aa40] >[255020.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459aa40] width 1280 pitch 5120 (/4 1280) >[255031.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458f390] >[255031.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458f390] width 1280 pitch 5120 (/4 1280) >[255031.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32421e0] >[255031.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32421e0] width 1280 pitch 5120 (/4 1280) >[255031.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458f390] >[255031.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458f390] width 1280 pitch 5120 (/4 1280) >[255031.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32421e0] >[255031.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32421e0] width 1280 pitch 5120 (/4 1280) >[255053.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3671580] >[255053.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3671580] width 1280 pitch 5120 (/4 1280) >[255053.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255053.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255053.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3671580] >[255053.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3671580] width 1280 pitch 5120 (/4 1280) >[255053.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255053.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255064.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3170] >[255064.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3170] width 1280 pitch 5120 (/4 1280) >[255064.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31db000] >[255064.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31db000] width 1280 pitch 5120 (/4 1280) >[255064.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255064.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255064.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31db000] >[255064.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31db000] width 1280 pitch 5120 (/4 1280) >[255096.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255096.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255096.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31db000] >[255096.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31db000] width 1280 pitch 5120 (/4 1280) >[255096.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255096.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255096.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31db000] >[255096.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31db000] width 1280 pitch 5120 (/4 1280) >[255104.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d98d0] >[255104.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d98d0] width 1280 pitch 5120 (/4 1280) >[255104.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371c120] >[255104.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371c120] width 1280 pitch 5120 (/4 1280) >[255139.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2c30] >[255139.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2c30] width 1280 pitch 5120 (/4 1280) >[255139.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acab80] >[255139.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acab80] width 1280 pitch 5120 (/4 1280) >[255139.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c7a0] >[255139.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c7a0] width 1280 pitch 5120 (/4 1280) >[255139.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[255139.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[255151.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d98d0] >[255151.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d98d0] width 1280 pitch 5120 (/4 1280) >[255152.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336db20] >[255152.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336db20] width 1280 pitch 5120 (/4 1280) >[255253.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3671250] >[255253.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3671250] width 1280 pitch 5120 (/4 1280) >[255720.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4594830] >[255720.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4594830] width 1280 pitch 5120 (/4 1280) >[255725.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37150d0] >[255725.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37150d0] width 1280 pitch 5120 (/4 1280) >[255725.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325b2c0] >[255725.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325b2c0] width 1280 pitch 5120 (/4 1280) >[255725.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358fc40] >[255725.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358fc40] width 1280 pitch 5120 (/4 1280) >[255725.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c99c0] >[255725.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c99c0] width 1280 pitch 5120 (/4 1280) >[256028.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3614e70] >[256028.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3614e70] width 1280 pitch 5120 (/4 1280) >[256028.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4598b60] >[256028.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4598b60] width 1280 pitch 5120 (/4 1280) >[256028.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4598b60] >[256028.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4598b60] width 1280 pitch 5120 (/4 1280) >[256041.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8a00] >[256041.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8a00] width 1280 pitch 5120 (/4 1280) >[256041.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37145c0] >[256041.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37145c0] width 1280 pitch 5120 (/4 1280) >[256041.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3336ee0] >[256041.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3336ee0] width 1280 pitch 5120 (/4 1280) >[256041.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37145c0] >[256041.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37145c0] width 1280 pitch 5120 (/4 1280) >[256045.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3692190] >[256045.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3692190] width 1280 pitch 5120 (/4 1280) >[256045.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ab40] >[256045.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ab40] width 1280 pitch 5120 (/4 1280) >[256045.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d32f0] >[256045.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d32f0] width 1280 pitch 5120 (/4 1280) >[256045.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ab40] >[256045.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ab40] width 1280 pitch 5120 (/4 1280) >[256306.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[256306.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[256306.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d32f0] >[256306.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d32f0] width 1280 pitch 5120 (/4 1280) >[256306.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1de0] >[256306.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1de0] width 1280 pitch 5120 (/4 1280) >[256306.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d32f0] >[256306.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d32f0] width 1280 pitch 5120 (/4 1280) >[256322.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bded0] >[256322.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bded0] width 1280 pitch 5120 (/4 1280) >[256326.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04fe0] >[256326.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04fe0] width 1280 pitch 5120 (/4 1280) >[256326.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36843f0] >[256326.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36843f0] width 1280 pitch 5120 (/4 1280) >[256326.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498e20] >[256326.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498e20] width 1280 pitch 5120 (/4 1280) >[256326.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498e20] >[256326.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498e20] width 1280 pitch 5120 (/4 1280) >[256971.678] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[256971.678] (II) RADEON(0): Using hsync ranges from config file >[256971.678] (II) RADEON(0): Using vrefresh ranges from config file >[256971.678] (II) RADEON(0): Printing DDC gathered Modelines: >[256971.678] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[256971.678] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[256971.678] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[256971.678] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[256971.678] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[256971.678] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[256971.678] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[256971.678] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[256971.678] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[256971.678] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[257061.537] (II) RADEON(0): RADEONSaveScreen(2) >[257061.537] (II) RADEON(0): RADEONSaveScreen(0) >[257960.995] (II) RADEON(0): RADEONSaveScreen(1) >[257964.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d7a0] >[257964.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d7a0] width 1280 pitch 5120 (/4 1280) >[257968.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[257968.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[257968.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360da70] >[257968.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360da70] width 1280 pitch 5120 (/4 1280) >[257968.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[257968.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[257968.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360da70] >[257968.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360da70] width 1280 pitch 5120 (/4 1280) >[257968.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[257968.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[257968.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360da70] >[257968.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360da70] width 1280 pitch 5120 (/4 1280) >[257968.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[257968.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[257968.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360da70] >[257968.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360da70] width 1280 pitch 5120 (/4 1280) >[257969.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257969.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257970.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257970.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257970.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca2480] >[257970.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca2480] width 1280 pitch 5120 (/4 1280) >[257970.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257970.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257970.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca2480] >[257970.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca2480] width 1280 pitch 5120 (/4 1280) >[257970.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257970.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257970.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca2480] >[257970.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca2480] width 1280 pitch 5120 (/4 1280) >[257970.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257970.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257970.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca2480] >[257971.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca2480] width 1280 pitch 5120 (/4 1280) >[257971.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257971.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257971.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca2480] >[257971.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca2480] width 1280 pitch 5120 (/4 1280) >[257976.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257976.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257976.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257976.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257976.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[257976.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[257976.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[257976.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[257978.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[257978.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[257978.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ece80] >[257978.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ece80] width 1280 pitch 5120 (/4 1280) >[257979.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257979.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257979.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257979.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257979.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257979.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257979.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257979.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257979.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257979.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257979.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257979.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257979.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257979.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257979.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a070] >[257979.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a070] width 1280 pitch 5120 (/4 1280) >[257979.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257979.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257980.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[257980.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[257980.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257980.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257981.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[257981.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[257981.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3723270] >[257981.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3723270] width 1280 pitch 5120 (/4 1280) >[257981.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257981.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257981.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3723270] >[257981.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3723270] width 1280 pitch 5120 (/4 1280) >[257981.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257981.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257981.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3723270] >[257981.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3723270] width 1280 pitch 5120 (/4 1280) >[257981.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257981.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257981.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3723270] >[257981.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3723270] width 1280 pitch 5120 (/4 1280) >[257981.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c06500] >[257981.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c06500] width 1280 pitch 5120 (/4 1280) >[257982.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[257982.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[257982.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[257982.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[257982.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[257982.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[257982.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[257982.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[258019.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c50c0] >[258019.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c50c0] width 1280 pitch 5120 (/4 1280) >[258019.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339e500] >[258019.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339e500] width 1280 pitch 5120 (/4 1280) >[258021.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c0b0] >[258021.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c0b0] width 1280 pitch 5120 (/4 1280) >[258021.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[258021.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[258021.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cdb50] >[258021.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cdb50] width 1280 pitch 5120 (/4 1280) >[258021.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[258021.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[258021.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cdb50] >[258021.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cdb50] width 1280 pitch 5120 (/4 1280) >[258021.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[258021.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[258021.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cdb50] >[258021.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cdb50] width 1280 pitch 5120 (/4 1280) >[258021.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[258021.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[258021.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cdb50] >[258021.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cdb50] width 1280 pitch 5120 (/4 1280) >[258021.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9ac0] >[258021.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9ac0] width 1280 pitch 5120 (/4 1280) >[258022.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35903c0] >[258022.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35903c0] width 1280 pitch 5120 (/4 1280) >[258023.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae78b0] >[258023.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae78b0] width 1280 pitch 5120 (/4 1280) >[258023.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[258023.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[258024.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[258024.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[258024.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c50c0] >[258024.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c50c0] width 1280 pitch 5120 (/4 1280) >[258024.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360d770] >[258024.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360d770] width 1280 pitch 5120 (/4 1280) >[258024.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b29d0] >[258024.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b29d0] width 1280 pitch 5120 (/4 1280) >[258024.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e660] >[258024.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e660] width 1280 pitch 5120 (/4 1280) >[258024.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332dea0] >[258024.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332dea0] width 1280 pitch 5120 (/4 1280) >[258024.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f8660] >[258024.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f8660] width 1280 pitch 5120 (/4 1280) >[258025.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f8480] >[258025.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f8480] width 1280 pitch 5120 (/4 1280) >[258025.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f8660] >[258025.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f8660] width 1280 pitch 5120 (/4 1280) >[258025.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f8480] >[258025.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f8480] width 1280 pitch 5120 (/4 1280) >[258025.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f8660] >[258025.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f8660] width 1280 pitch 5120 (/4 1280) >[258052.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4578450] >[258052.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4578450] width 1280 pitch 5120 (/4 1280) >[258055.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1840] >[258055.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1840] width 1280 pitch 5120 (/4 1280) >[258055.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8310] >[258055.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8310] width 1280 pitch 5120 (/4 1280) >[258055.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4578300] >[258055.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4578300] width 1280 pitch 5120 (/4 1280) >[258055.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8310] >[258055.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8310] width 1280 pitch 5120 (/4 1280) >[258107.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8ac0] >[258107.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8ac0] width 1280 pitch 5120 (/4 1280) >[258111.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[258111.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[258111.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a02e0] >[258111.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a02e0] width 1280 pitch 5120 (/4 1280) >[258111.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[258111.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[258111.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc9430] >[258111.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc9430] width 1280 pitch 5120 (/4 1280) >[258114.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1d00] >[258114.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1d00] width 1280 pitch 5120 (/4 1280) >[258114.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a02e0] >[258114.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a02e0] width 1280 pitch 5120 (/4 1280) >[258114.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e660] >[258114.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e660] width 1280 pitch 5120 (/4 1280) >[258114.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a02e0] >[258114.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a02e0] width 1280 pitch 5120 (/4 1280) >[258114.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e660] >[258114.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e660] width 1280 pitch 5120 (/4 1280) >[258721.595] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[258721.595] (II) RADEON(0): Using hsync ranges from config file >[258721.595] (II) RADEON(0): Using vrefresh ranges from config file >[258721.595] (II) RADEON(0): Printing DDC gathered Modelines: >[258721.595] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[258721.596] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[258721.596] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[258721.596] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[258721.596] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[258721.596] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[258721.596] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[258721.596] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[258721.596] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[258721.596] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[258811.535] (II) RADEON(0): RADEONSaveScreen(2) >[258811.535] (II) RADEON(0): RADEONSaveScreen(0) >[284630.204] (II) RADEON(0): RADEONSaveScreen(1) >[284630.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c5120] >[284630.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c5120] width 1280 pitch 5120 (/4 1280) >[284648.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35903c0] >[284648.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35903c0] width 1280 pitch 5120 (/4 1280) >[284930.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[284930.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[284930.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cdb50] >[284930.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cdb50] width 1280 pitch 5120 (/4 1280) >[284930.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[284930.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[284930.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[284930.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[284990.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d55d0] >[284990.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d55d0] width 1280 pitch 5120 (/4 1280) >[285293.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b8e0] >[285293.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b8e0] width 1280 pitch 5120 (/4 1280) >[285293.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[285293.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[285293.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[285293.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[285293.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[285293.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[285317.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[285317.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[285317.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[285317.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[285317.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c6da0] >[285317.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c6da0] width 1280 pitch 5120 (/4 1280) >[285317.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[285317.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[285354.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ba70] >[285354.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ba70] width 1280 pitch 5120 (/4 1280) >[285354.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ba70] >[285354.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ba70] width 1280 pitch 5120 (/4 1280) >[285354.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[285354.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[285354.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ba70] >[285354.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ba70] width 1280 pitch 5120 (/4 1280) >[285355.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[285355.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[285420.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[285420.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[285420.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4b20] >[285420.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4b20] width 1280 pitch 5120 (/4 1280) >[285421.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[285421.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[285421.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[285421.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[285421.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad2ec0] >[285421.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad2ec0] width 1280 pitch 5120 (/4 1280) >[285421.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334fb90] >[285421.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334fb90] width 1280 pitch 5120 (/4 1280) >[286528.902] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[286528.902] (II) RADEON(0): Using hsync ranges from config file >[286528.902] (II) RADEON(0): Using vrefresh ranges from config file >[286528.902] (II) RADEON(0): Printing DDC gathered Modelines: >[286528.902] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[286528.902] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[286528.902] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[286528.902] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[286528.902] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[286528.902] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[286528.902] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[286528.902] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[286528.902] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[286528.902] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[286619.555] (II) RADEON(0): RADEONSaveScreen(2) >[286619.555] (II) RADEON(0): RADEONSaveScreen(0) >[327712.633] (II) RADEON(0): RADEONSaveScreen(1) >[327712.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3494230] >[327712.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3494230] width 1280 pitch 5120 (/4 1280) >[327715.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de190] >[327715.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de190] width 1280 pitch 5120 (/4 1280) >[327716.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0640] >[327716.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0640] width 1280 pitch 5120 (/4 1280) >[327716.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e450] >[327716.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e450] width 1280 pitch 5120 (/4 1280) >[327716.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0640] >[327716.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0640] width 1280 pitch 5120 (/4 1280) >[327716.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e450] >[327716.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e450] width 1280 pitch 5120 (/4 1280) >[328176.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[328176.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[328176.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630000] >[328176.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630000] width 1280 pitch 5120 (/4 1280) >[328176.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3bf0] >[328176.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3bf0] width 1280 pitch 5120 (/4 1280) >[328176.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cde40] >[328176.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cde40] width 1280 pitch 5120 (/4 1280) >[328190.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[328190.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[328191.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[328191.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[328191.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ba70] >[328191.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ba70] width 1280 pitch 5120 (/4 1280) >[328191.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[328191.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[328230.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[328230.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[328230.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4d20] >[328230.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4d20] width 1280 pitch 5120 (/4 1280) >[328230.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3bf0] >[328230.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3bf0] width 1280 pitch 5120 (/4 1280) >[328230.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c16ea0] >[328230.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c16ea0] width 1280 pitch 5120 (/4 1280) >[328246.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328246.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328246.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[328246.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[328264.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23830] >[328264.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23830] width 1280 pitch 5120 (/4 1280) >[328264.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[328264.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[328285.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371190] >[328285.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371190] width 1280 pitch 5120 (/4 1280) >[328296.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[328296.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[328296.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3596fd0] >[328296.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3596fd0] width 1280 pitch 5120 (/4 1280) >[328296.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[328296.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[328296.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[328296.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[328316.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[328316.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[328316.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[328317.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[328317.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76430] >[328317.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76430] width 1280 pitch 5120 (/4 1280) >[328317.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[328317.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[328318.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[328318.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[328318.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2f10] >[328318.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2f10] width 1280 pitch 5120 (/4 1280) >[328318.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[328318.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[328318.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2f10] >[328318.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2f10] width 1280 pitch 5120 (/4 1280) >[328325.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328325.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328325.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328325.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328325.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328325.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328325.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0dc30] >[328325.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0dc30] width 1280 pitch 5120 (/4 1280) >[328326.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328326.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328326.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328326.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328326.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45926d0] >[328326.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45926d0] width 1280 pitch 5120 (/4 1280) >[328326.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328326.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328340.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[328340.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[328340.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22690] >[328340.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22690] width 1280 pitch 5120 (/4 1280) >[328340.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d2f0] >[328340.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d2f0] width 1280 pitch 5120 (/4 1280) >[328340.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d2f0] >[328340.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d2f0] width 1280 pitch 5120 (/4 1280) >[328341.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[328341.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[328341.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[328341.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[328341.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc9b0] >[328341.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc9b0] width 1280 pitch 5120 (/4 1280) >[328356.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[328356.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[328356.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417be0] >[328356.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417be0] width 1280 pitch 5120 (/4 1280) >[328357.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417be0] >[328357.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417be0] width 1280 pitch 5120 (/4 1280) >[328358.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417be0] >[328358.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417be0] width 1280 pitch 5120 (/4 1280) >[328358.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a40] >[328358.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a40] width 1280 pitch 5120 (/4 1280) >[328358.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417be0] >[328358.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417be0] width 1280 pitch 5120 (/4 1280) >[328396.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328396.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328396.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3621a40] >[328396.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3621a40] width 1280 pitch 5120 (/4 1280) >[328396.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6f10] >[328396.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6f10] width 1280 pitch 5120 (/4 1280) >[328396.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[328396.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[328398.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[328398.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[328398.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1d00] >[328398.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1d00] width 1280 pitch 5120 (/4 1280) >[328402.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[328402.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[328402.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0dc30] >[328402.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0dc30] width 1280 pitch 5120 (/4 1280) >[328402.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[328402.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[328402.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[328402.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[328403.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328403.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328403.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[328403.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[328403.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[328403.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[328403.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[328403.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[328465.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328465.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328465.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328465.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328465.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328465.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328465.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328465.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328466.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360eac0] >[328466.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360eac0] width 1280 pitch 5120 (/4 1280) >[328466.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328466.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328466.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[328466.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[328466.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328466.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328771.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[328771.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[328772.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[328772.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[328772.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3423d50] >[328772.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3423d50] width 1280 pitch 5120 (/4 1280) >[328773.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[328773.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[328773.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[328773.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[328773.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360eac0] >[328773.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360eac0] width 1280 pitch 5120 (/4 1280) >[328778.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7080] >[328778.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7080] width 1280 pitch 5120 (/4 1280) >[328802.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[328802.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[328802.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328802.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[328802.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[328802.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328802.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[328802.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[328802.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328802.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328802.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328802.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328802.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328802.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328802.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328802.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[328802.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[328802.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328802.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328806.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[328806.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[328806.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266e6b0] >[328806.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266e6b0] width 1280 pitch 5120 (/4 1280) >[328806.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bd230] >[328806.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bd230] width 1280 pitch 5120 (/4 1280) >[328806.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266e6b0] >[328806.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266e6b0] width 1280 pitch 5120 (/4 1280) >[328807.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[328807.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[328807.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ed760] >[328807.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ed760] width 1280 pitch 5120 (/4 1280) >[328807.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3980] >[328807.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3980] width 1280 pitch 5120 (/4 1280) >[328807.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328807.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328807.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3980] >[328807.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3980] width 1280 pitch 5120 (/4 1280) >[328807.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33879a0] >[328807.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33879a0] width 1280 pitch 5120 (/4 1280) >[328807.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cde40] >[328807.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cde40] width 1280 pitch 5120 (/4 1280) >[328807.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ed760] >[328808.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ed760] width 1280 pitch 5120 (/4 1280) >[328808.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[328808.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[328808.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[328808.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[328814.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[328814.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[328814.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cde40] >[328814.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cde40] width 1280 pitch 5120 (/4 1280) >[328815.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae78b0] >[328815.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae78b0] width 1280 pitch 5120 (/4 1280) >[328815.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae78b0] >[328815.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae78b0] width 1280 pitch 5120 (/4 1280) >[328815.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aaa0] >[328816.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aaa0] width 1280 pitch 5120 (/4 1280) >[328816.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae78b0] >[328816.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae78b0] width 1280 pitch 5120 (/4 1280) >[328829.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1d00] >[328829.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1d00] width 1280 pitch 5120 (/4 1280) >[328829.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8a00] >[328829.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8a00] width 1280 pitch 5120 (/4 1280) >[328829.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ced10] >[328829.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ced10] width 1280 pitch 5120 (/4 1280) >[328829.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36cf7d0] >[328829.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36cf7d0] width 1280 pitch 5120 (/4 1280) >[328853.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c10e20] >[328853.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c10e20] width 1280 pitch 5120 (/4 1280) >[328883.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[328883.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[328883.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c1e0] >[328883.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c1e0] width 1280 pitch 5120 (/4 1280) >[328884.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[328884.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[328886.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[328886.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[328886.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c6da0] >[328886.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c6da0] width 1280 pitch 5120 (/4 1280) >[328888.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[328888.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[328888.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3752ca0] >[328888.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3752ca0] width 1280 pitch 5120 (/4 1280) >[328888.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369d920] >[328888.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369d920] width 1280 pitch 5120 (/4 1280) >[328888.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323ca70] >[328888.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323ca70] width 1280 pitch 5120 (/4 1280) >[328910.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328910.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328911.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328911.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328911.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[328911.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[328911.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231fd0] >[328911.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231fd0] width 1280 pitch 5120 (/4 1280) >[328911.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[328911.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[328911.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231fd0] >[328911.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231fd0] width 1280 pitch 5120 (/4 1280) >[328911.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[328911.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[328911.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328911.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328912.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301140] >[328912.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301140] width 1280 pitch 5120 (/4 1280) >[328913.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609290] >[328913.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609290] width 1280 pitch 5120 (/4 1280) >[328913.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca8e0] >[328913.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca8e0] width 1280 pitch 5120 (/4 1280) >[328913.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[328913.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[328913.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328913.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328913.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[328913.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[328913.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328913.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328913.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3752ca0] >[328913.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3752ca0] width 1280 pitch 5120 (/4 1280) >[328913.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37319a0] >[328913.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37319a0] width 1280 pitch 5120 (/4 1280) >[328913.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3752ca0] >[328913.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3752ca0] width 1280 pitch 5120 (/4 1280) >[328913.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609290] >[328913.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609290] width 1280 pitch 5120 (/4 1280) >[328916.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3312320] >[328916.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3312320] width 1280 pitch 5120 (/4 1280) >[328916.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee240] >[328916.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee240] width 1280 pitch 5120 (/4 1280) >[328917.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367de90] >[328917.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367de90] width 1280 pitch 5120 (/4 1280) >[328923.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328923.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328923.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328923.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328923.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328923.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328923.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328923.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328923.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1020] >[328923.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1020] width 1280 pitch 5120 (/4 1280) >[328923.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1020] >[328923.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1020] width 1280 pitch 5120 (/4 1280) >[328923.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1020] >[328923.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1020] width 1280 pitch 5120 (/4 1280) >[328923.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328923.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328923.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1020] >[328923.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1020] width 1280 pitch 5120 (/4 1280) >[328923.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328923.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328924.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9dd0] >[328924.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9dd0] width 1280 pitch 5120 (/4 1280) >[328924.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328924.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328924.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9dd0] >[328924.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9dd0] width 1280 pitch 5120 (/4 1280) >[328924.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328924.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328924.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9dd0] >[328924.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9dd0] width 1280 pitch 5120 (/4 1280) >[328924.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328924.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328924.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9dd0] >[328924.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9dd0] width 1280 pitch 5120 (/4 1280) >[328924.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad20] >[328924.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad20] width 1280 pitch 5120 (/4 1280) >[328925.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328925.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328925.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328925.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328925.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2e40] >[328925.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2e40] width 1280 pitch 5120 (/4 1280) >[328925.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328925.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328925.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a65c0] >[328925.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a65c0] width 1280 pitch 5120 (/4 1280) >[328925.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0ab0] >[328925.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0ab0] width 1280 pitch 5120 (/4 1280) >[328925.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6530] >[328925.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6530] width 1280 pitch 5120 (/4 1280) >[328925.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334750] >[328925.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334750] width 1280 pitch 5120 (/4 1280) >[328925.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a0e80] >[328926.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a0e80] width 1280 pitch 5120 (/4 1280) >[328926.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a0e80] >[328926.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a0e80] width 1280 pitch 5120 (/4 1280) >[328926.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a0e80] >[328926.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a0e80] width 1280 pitch 5120 (/4 1280) >[328926.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a0e80] >[328926.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a0e80] width 1280 pitch 5120 (/4 1280) >[328926.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a110] >[328926.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a110] width 1280 pitch 5120 (/4 1280) >[328926.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328926.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a110] >[328926.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a110] width 1280 pitch 5120 (/4 1280) >[328926.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1200] >[328926.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1200] width 1280 pitch 5120 (/4 1280) >[328931.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367a0c0] >[328931.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367a0c0] width 1280 pitch 5120 (/4 1280) >[328931.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367a0c0] >[328931.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367a0c0] width 1280 pitch 5120 (/4 1280) >[328931.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2ab80] >[328931.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2ab80] width 1280 pitch 5120 (/4 1280) >[328932.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2ab80] >[328932.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2ab80] width 1280 pitch 5120 (/4 1280) >[328932.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34be530] >[328932.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34be530] width 1280 pitch 5120 (/4 1280) >[329568.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3336ee0] >[329568.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3336ee0] width 1280 pitch 5120 (/4 1280) >[329568.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21470] >[329568.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21470] width 1280 pitch 5120 (/4 1280) >[329568.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329568.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329568.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329569.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329569.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329569.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329569.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329569.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329569.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329569.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329569.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329569.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329569.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329569.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329569.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329569.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1160] >[329569.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1160] width 1280 pitch 5120 (/4 1280) >[329569.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329569.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329570.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c57a0] >[329570.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c57a0] width 1280 pitch 5120 (/4 1280) >[329570.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630c30] >[329570.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630c30] width 1280 pitch 5120 (/4 1280) >[329570.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3336ee0] >[329570.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3336ee0] width 1280 pitch 5120 (/4 1280) >[329570.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630c30] >[329570.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630c30] width 1280 pitch 5120 (/4 1280) >[329570.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3336ee0] >[329570.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3336ee0] width 1280 pitch 5120 (/4 1280) >[329570.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca000] >[329570.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca000] width 1280 pitch 5120 (/4 1280) >[329570.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3336ee0] >[329570.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3336ee0] width 1280 pitch 5120 (/4 1280) >[329570.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca000] >[329570.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca000] width 1280 pitch 5120 (/4 1280) >[329570.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329570.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329570.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca000] >[329570.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca000] width 1280 pitch 5120 (/4 1280) >[329570.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e6c0] >[329570.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e6c0] width 1280 pitch 5120 (/4 1280) >[329570.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca000] >[329570.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca000] width 1280 pitch 5120 (/4 1280) >[329570.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b4cf0] >[329570.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b4cf0] width 1280 pitch 5120 (/4 1280) >[330403.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330403.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330403.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330403.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330404.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330404.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330404.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330404.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330404.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330404.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330404.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330404.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330404.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330404.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330404.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330404.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330404.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330404.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330405.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330405.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330408.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330408.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330408.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330408.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330408.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330408.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330408.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330409.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330409.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330409.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330409.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330409.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330409.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330409.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330409.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330409.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330409.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330409.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330409.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330409.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330409.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330409.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330409.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330409.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330416.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380] >[330417.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1280 pitch 5120 (/4 1280) >[330417.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[330417.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[330417.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1b8b0] >[330417.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1b8b0] width 1280 pitch 5120 (/4 1280) >[330417.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[330417.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[330417.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330417.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330417.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[330417.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[330417.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330417.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330417.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[330418.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[330418.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330418.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330418.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[330418.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[330418.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330418.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330418.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676370] >[330418.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676370] width 1280 pitch 5120 (/4 1280) >[330419.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[330419.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[330420.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3303170] >[330420.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3303170] width 1280 pitch 5120 (/4 1280) >[330420.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1b8b0] >[330420.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1b8b0] width 1280 pitch 5120 (/4 1280) >[330420.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3303170] >[330420.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3303170] width 1280 pitch 5120 (/4 1280) >[330421.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c042d0] >[330421.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c042d0] width 1280 pitch 5120 (/4 1280) >[330421.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330421.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330421.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c042d0] >[330421.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c042d0] width 1280 pitch 5120 (/4 1280) >[330421.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330421.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330422.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c37210] >[330423.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c37210] width 1280 pitch 5120 (/4 1280) >[330424.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330424.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330424.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32af8c0] >[330424.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32af8c0] width 1280 pitch 5120 (/4 1280) >[330424.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4360] >[330424.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4360] width 1280 pitch 5120 (/4 1280) >[330424.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263350] >[330424.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263350] width 1280 pitch 5120 (/4 1280) >[330424.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cda0] >[330424.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cda0] width 1280 pitch 5120 (/4 1280) >[330424.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3228d70] >[330424.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3228d70] width 1280 pitch 5120 (/4 1280) >[330424.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36faf30] >[330424.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36faf30] width 1280 pitch 5120 (/4 1280) >[330424.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be3b00] >[330424.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be3b00] width 1280 pitch 5120 (/4 1280) >[330424.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2c60] >[330424.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2c60] width 1280 pitch 5120 (/4 1280) >[330444.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2c60] >[330444.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2c60] width 1280 pitch 5120 (/4 1280) >[330448.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7540] >[330448.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7540] width 1280 pitch 5120 (/4 1280) >[330448.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2a20] >[330448.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2a20] width 1280 pitch 5120 (/4 1280) >[330448.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c13590] >[330448.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c13590] width 1280 pitch 5120 (/4 1280) >[330448.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341e9f0] >[330448.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341e9f0] width 1280 pitch 5120 (/4 1280) >[330448.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347c130] >[330448.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347c130] width 1280 pitch 5120 (/4 1280) >[330448.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341e9f0] >[330448.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341e9f0] width 1280 pitch 5120 (/4 1280) >[330448.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347c130] >[330448.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347c130] width 1280 pitch 5120 (/4 1280) >[330449.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2b00] >[330449.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2b00] width 1280 pitch 5120 (/4 1280) >[330449.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333c9f0] >[330449.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333c9f0] width 1280 pitch 5120 (/4 1280) >[330449.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32af8c0] >[330449.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32af8c0] width 1280 pitch 5120 (/4 1280) >[330449.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[330449.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[330449.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32af8c0] >[330449.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32af8c0] width 1280 pitch 5120 (/4 1280) >[330449.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c139b0] >[330449.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c139b0] width 1280 pitch 5120 (/4 1280) >[330449.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c89380] >[330449.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c89380] width 1280 pitch 5120 (/4 1280) >[330481.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0c30] >[330482.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0c30] width 1280 pitch 5120 (/4 1280) >[330482.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae7ca0] >[330482.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae7ca0] width 1280 pitch 5120 (/4 1280) >[330484.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0c30] >[330484.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0c30] width 1280 pitch 5120 (/4 1280) >[330484.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae7ca0] >[330484.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae7ca0] width 1280 pitch 5120 (/4 1280) >[330484.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330484.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330485.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330485.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330485.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330485.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330485.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330485.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330485.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330485.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330485.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330485.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330485.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330485.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330485.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330485.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330485.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330485.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330485.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330485.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330486.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330486.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330486.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330486.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330486.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330486.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330486.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330486.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330486.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330486.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330486.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330486.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330486.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330486.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe690] >[330486.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe690] width 1280 pitch 5120 (/4 1280) >[330551.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a4750] >[330551.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a4750] width 1280 pitch 5120 (/4 1280) >[330555.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[330555.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[330555.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a4750] >[330555.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a4750] width 1280 pitch 5120 (/4 1280) >[330555.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[330555.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[330555.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a4750] >[330555.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a4750] width 1280 pitch 5120 (/4 1280) >[330565.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4599460] >[330565.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4599460] width 1280 pitch 5120 (/4 1280) >[330565.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361c580] >[330565.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361c580] width 1280 pitch 5120 (/4 1280) >[330565.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371cfd0] >[330565.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371cfd0] width 1280 pitch 5120 (/4 1280) >[330565.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361c580] >[330565.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361c580] width 1280 pitch 5120 (/4 1280) >[330582.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330582.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330582.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd1f0] >[330582.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd1f0] width 1280 pitch 5120 (/4 1280) >[330582.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a9490] >[330582.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a9490] width 1280 pitch 5120 (/4 1280) >[330582.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd1f0] >[330582.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd1f0] width 1280 pitch 5120 (/4 1280) >[330583.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fb590] >[330584.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fb590] width 1280 pitch 5120 (/4 1280) >[330584.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e900] >[330585.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e900] width 1280 pitch 5120 (/4 1280) >[330585.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fb590] >[330585.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fb590] width 1280 pitch 5120 (/4 1280) >[330585.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e900] >[330585.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e900] width 1280 pitch 5120 (/4 1280) >[330585.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[330585.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[330585.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e900] >[330585.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e900] width 1280 pitch 5120 (/4 1280) >[330585.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[330585.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[330585.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[330585.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[330585.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1fc0] >[330585.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1fc0] width 1280 pitch 5120 (/4 1280) >[330586.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[330586.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[330588.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[330588.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[330588.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330588.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330588.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330588.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330588.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330588.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330588.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330588.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330588.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330588.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330588.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330588.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330588.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330588.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330588.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330589.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330589.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330589.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330589.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330589.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330589.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330589.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330589.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330589.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330589.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330590.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330590.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330590.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330590.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330590.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330590.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330590.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330590.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330590.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330590.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330590.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330590.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330590.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330590.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[330590.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[330590.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[330590.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361def0] >[330590.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361def0] width 1280 pitch 5120 (/4 1280) >[333325.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[333325.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[333326.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[333326.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[333326.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[333326.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[333330.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371cfd0] >[333330.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371cfd0] width 1280 pitch 5120 (/4 1280) >[333331.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371cfd0] >[333331.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371cfd0] width 1280 pitch 5120 (/4 1280) >[333331.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c4b20] >[333331.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c4b20] width 1280 pitch 5120 (/4 1280) >[333331.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371cfd0] >[333331.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371cfd0] width 1280 pitch 5120 (/4 1280) >[333590.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[333590.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[333590.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[333590.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[333590.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21f50] >[333590.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21f50] width 1280 pitch 5120 (/4 1280) >[333590.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22690] >[333590.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22690] width 1280 pitch 5120 (/4 1280) >[333596.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcc610] >[333596.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcc610] width 1280 pitch 5120 (/4 1280) >[333596.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bffd40] >[333596.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bffd40] width 1280 pitch 5120 (/4 1280) >[333596.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c16ea0] >[333596.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c16ea0] width 1280 pitch 5120 (/4 1280) >[333596.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[333596.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[333596.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[333596.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[333596.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33600c0] >[333596.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33600c0] width 1280 pitch 5120 (/4 1280) >[333596.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33600c0] >[333596.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33600c0] width 1280 pitch 5120 (/4 1280) >[333596.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ce00] >[333596.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ce00] width 1280 pitch 5120 (/4 1280) >[333603.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ce00] >[333603.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ce00] width 1280 pitch 5120 (/4 1280) >[333614.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a9490] >[333614.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a9490] width 1280 pitch 5120 (/4 1280) >[333614.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a4750] >[333614.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a4750] width 1280 pitch 5120 (/4 1280) >[333614.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a9490] >[333614.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a9490] width 1280 pitch 5120 (/4 1280) >[333614.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a4750] >[333614.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a4750] width 1280 pitch 5120 (/4 1280) >[333621.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371cfd0] >[333621.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371cfd0] width 1280 pitch 5120 (/4 1280) >[333621.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd1f0] >[333621.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd1f0] width 1280 pitch 5120 (/4 1280) >[333621.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e900] >[333621.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e900] width 1280 pitch 5120 (/4 1280) >[333621.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c07a0] >[333621.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c07a0] width 1280 pitch 5120 (/4 1280) >[333646.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333646.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333653.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333653.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333653.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333653.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333653.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333653.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333653.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333653.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333653.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333653.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333653.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333653.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333653.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333653.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333653.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333653.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333654.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333654.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[333654.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[333654.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[333654.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[333972.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323f420] >[333972.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323f420] width 1280 pitch 5120 (/4 1280) >[333972.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c10a0] >[333972.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c10a0] width 1280 pitch 5120 (/4 1280) >[334063.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[334063.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[334064.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[334064.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[334064.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de220] >[334064.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de220] width 1280 pitch 5120 (/4 1280) >[334064.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[334064.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[334065.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[334065.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[334065.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aaa0] >[334065.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aaa0] width 1280 pitch 5120 (/4 1280) >[334065.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c22d0] >[334065.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c22d0] width 1280 pitch 5120 (/4 1280) >[334065.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aaa0] >[334065.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aaa0] width 1280 pitch 5120 (/4 1280) >[334071.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c16ea0] >[334071.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c16ea0] width 1280 pitch 5120 (/4 1280) >[334077.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[334077.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[334077.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4dc0] >[334077.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4dc0] width 1280 pitch 5120 (/4 1280) >[334077.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[334077.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[334078.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4dc0] >[334078.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4dc0] width 1280 pitch 5120 (/4 1280) >[334083.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4dc0] >[334083.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4dc0] width 1280 pitch 5120 (/4 1280) >[334083.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acb380] >[334083.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acb380] width 1280 pitch 5120 (/4 1280) >[334083.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c22690] >[334083.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c22690] width 1280 pitch 5120 (/4 1280) >[334083.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c22d0] >[334083.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c22d0] width 1280 pitch 5120 (/4 1280) >[334105.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d5470] >[334105.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d5470] width 1280 pitch 5120 (/4 1280) >[334105.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3659200] >[334105.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3659200] width 1280 pitch 5120 (/4 1280) >[334130.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424660] >[334130.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424660] width 1280 pitch 5120 (/4 1280) >[334130.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ef30] >[334130.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ef30] width 1280 pitch 5120 (/4 1280) >[334130.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf4e0] >[334130.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf4e0] width 1280 pitch 5120 (/4 1280) >[334130.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[334130.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[334262.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b1e80] >[334262.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b1e80] width 1280 pitch 5120 (/4 1280) >[334277.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23b10] >[334277.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23b10] width 1280 pitch 5120 (/4 1280) >[334279.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2250] >[334279.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2250] width 1280 pitch 5120 (/4 1280) >[334279.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356d640] >[334280.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356d640] width 1280 pitch 5120 (/4 1280) >[334280.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368e8e0] >[334280.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368e8e0] width 1280 pitch 5120 (/4 1280) >[334280.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c19090] >[334280.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c19090] width 1280 pitch 5120 (/4 1280) >[334280.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c6d60] >[334280.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c6d60] width 1280 pitch 5120 (/4 1280) >[334280.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356d640] >[334280.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356d640] width 1280 pitch 5120 (/4 1280) >[334280.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333a780] >[334280.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333a780] width 1280 pitch 5120 (/4 1280) >[334280.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356d640] >[334281.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356d640] width 1280 pitch 5120 (/4 1280) >[334281.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3401e90] >[334281.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3401e90] width 1280 pitch 5120 (/4 1280) >[334281.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0df00] >[334281.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0df00] width 1280 pitch 5120 (/4 1280) >[334281.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a13e0] >[334281.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a13e0] width 1280 pitch 5120 (/4 1280) >[334286.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c1400] >[334286.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c1400] width 1280 pitch 5120 (/4 1280) >[334286.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331e0e0] >[334286.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331e0e0] width 1280 pitch 5120 (/4 1280) >[334302.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd00c0] >[334302.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd00c0] width 1280 pitch 5120 (/4 1280) >[334302.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359cc50] >[334302.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359cc50] width 1280 pitch 5120 (/4 1280) >[334302.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9f40] >[334302.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9f40] width 1280 pitch 5120 (/4 1280) >[334302.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9f40] >[334302.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9f40] width 1280 pitch 5120 (/4 1280) >[334303.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9f40] >[334303.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9f40] width 1280 pitch 5120 (/4 1280) >[334303.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8260] >[334303.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8260] width 1280 pitch 5120 (/4 1280) >[334303.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cff20] >[334303.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cff20] width 1280 pitch 5120 (/4 1280) >[334303.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8260] >[334303.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8260] width 1280 pitch 5120 (/4 1280) >[334305.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8260] >[334305.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8260] width 1280 pitch 5120 (/4 1280) >[334306.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e7bf0] >[334306.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e7bf0] width 1280 pitch 5120 (/4 1280) >[334306.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ee10] >[334306.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ee10] width 1280 pitch 5120 (/4 1280) >[334309.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358fd90] >[334309.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358fd90] width 1280 pitch 5120 (/4 1280) >[334309.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c5e0] >[334309.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c5e0] width 1280 pitch 5120 (/4 1280) >[334309.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d990] >[334309.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d990] width 1280 pitch 5120 (/4 1280) >[334311.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c4f80] >[334311.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c4f80] width 1280 pitch 5120 (/4 1280) >[334311.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341120] >[334311.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341120] width 1280 pitch 5120 (/4 1280) >[334337.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d4330] >[334337.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d4330] width 1280 pitch 5120 (/4 1280) >[334337.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7830] >[334337.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7830] width 1280 pitch 5120 (/4 1280) >[334337.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd00c0] >[334337.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd00c0] width 1280 pitch 5120 (/4 1280) >[334337.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9f40] >[334337.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9f40] width 1280 pitch 5120 (/4 1280) >[334338.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7830] >[334338.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7830] width 1280 pitch 5120 (/4 1280) >[334339.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7830] >[334339.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7830] width 1280 pitch 5120 (/4 1280) >[334339.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7830] >[334339.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7830] width 1280 pitch 5120 (/4 1280) >[334339.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cba0] >[334339.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cba0] width 1280 pitch 5120 (/4 1280) >[334339.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e7830] >[334339.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e7830] width 1280 pitch 5120 (/4 1280) >[334343.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358fd90] >[334343.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358fd90] width 1280 pitch 5120 (/4 1280) >[334343.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abd420] >[334343.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abd420] width 1280 pitch 5120 (/4 1280) >[334345.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[334345.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[334345.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa160] >[334345.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa160] width 1280 pitch 5120 (/4 1280) >[334345.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347fba0] >[334345.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347fba0] width 1280 pitch 5120 (/4 1280) >[334348.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35db7c0] >[334348.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35db7c0] width 1280 pitch 5120 (/4 1280) >[334349.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3375480] >[334349.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3375480] width 1280 pitch 5120 (/4 1280) >[334349.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706950] >[334349.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706950] width 1280 pitch 5120 (/4 1280) >[334360.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33610a0] >[334360.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33610a0] width 1280 pitch 5120 (/4 1280) >[334360.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3732170] >[334360.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3732170] width 1280 pitch 5120 (/4 1280) >[334390.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36edca0] >[334390.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36edca0] width 1280 pitch 5120 (/4 1280) >[334390.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c43bd0] >[334390.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c43bd0] width 1280 pitch 5120 (/4 1280) >[334390.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c51ae0] >[334390.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c51ae0] width 1280 pitch 5120 (/4 1280) >[334390.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[334390.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[334783.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c26340] >[334783.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c26340] width 1280 pitch 5120 (/4 1280) >[334784.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c26340] >[334784.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c26340] width 1280 pitch 5120 (/4 1280) >[334784.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371f290] >[334784.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371f290] width 1280 pitch 5120 (/4 1280) >[334784.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c26340] >[334784.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c26340] width 1280 pitch 5120 (/4 1280) >[334786.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371f290] >[334786.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371f290] width 1280 pitch 5120 (/4 1280) >[334786.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35978c0] >[334786.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35978c0] width 1280 pitch 5120 (/4 1280) >[334786.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3425980] >[334786.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3425980] width 1280 pitch 5120 (/4 1280) >[334786.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35978c0] >[334786.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35978c0] width 1280 pitch 5120 (/4 1280) >[335056.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3675d00] >[335056.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3675d00] width 1280 pitch 5120 (/4 1280) >[335065.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32482e0] >[335065.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32482e0] width 1280 pitch 5120 (/4 1280) >[335065.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f33f0] >[335065.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f33f0] width 1280 pitch 5120 (/4 1280) >[335065.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d45e0] >[335065.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d45e0] width 1280 pitch 5120 (/4 1280) >[335065.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371fcc0] >[335065.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371fcc0] width 1280 pitch 5120 (/4 1280) >[335077.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d45e0] >[335077.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d45e0] width 1280 pitch 5120 (/4 1280) >[335077.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3338a50] >[335077.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3338a50] width 1280 pitch 5120 (/4 1280) >[335077.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe720] >[335077.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe720] width 1280 pitch 5120 (/4 1280) >[335077.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3338a50] >[335077.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3338a50] width 1280 pitch 5120 (/4 1280) >[335096.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[335096.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[335098.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50bf0] >[335098.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50bf0] width 1280 pitch 5120 (/4 1280) >[335098.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50bf0] >[335098.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50bf0] width 1280 pitch 5120 (/4 1280) >[335099.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50bf0] >[335099.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50bf0] width 1280 pitch 5120 (/4 1280) >[335099.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371fd20] >[335099.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371fd20] width 1280 pitch 5120 (/4 1280) >[335099.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfd0f0] >[335099.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfd0f0] width 1280 pitch 5120 (/4 1280) >[335099.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[335099.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[335113.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359f060] >[335113.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359f060] width 1280 pitch 5120 (/4 1280) >[335113.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[335113.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[335113.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8a10] >[335113.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8a10] width 1280 pitch 5120 (/4 1280) >[335113.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bf870] >[335113.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bf870] width 1280 pitch 5120 (/4 1280) >[338703.338] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[338703.338] (II) RADEON(0): Using hsync ranges from config file >[338703.338] (II) RADEON(0): Using vrefresh ranges from config file >[338703.338] (II) RADEON(0): Printing DDC gathered Modelines: >[338703.338] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[338703.338] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[338703.338] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[338703.338] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[338703.338] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[338703.338] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[338703.338] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[338703.338] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[338703.338] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[338703.338] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[338715.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1330] >[338715.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1330] width 1280 pitch 5120 (/4 1280) >[340046.548] (II) RADEON(0): RADEONSaveScreen(2) >[340046.548] (II) RADEON(0): RADEONSaveScreen(0) >[340066.727] (II) RADEON(0): RADEONSaveScreen(1) >[340756.537] (II) RADEON(0): RADEONSaveScreen(2) >[340756.537] (II) RADEON(0): RADEONSaveScreen(0) >[340768.163] (II) RADEON(0): RADEONSaveScreen(1) >[341089.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341089.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338eeb0] >[341094.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338eeb0] width 1280 pitch 5120 (/4 1280) >[341094.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338eeb0] >[341094.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338eeb0] width 1280 pitch 5120 (/4 1280) >[341094.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338eeb0] >[341094.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338eeb0] width 1280 pitch 5120 (/4 1280) >[341094.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341094.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341094.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341094.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341094.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341094.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341094.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341094.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341094.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341094.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341094.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341095.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341095.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341095.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341095.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341095.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341095.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341095.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341095.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b8cd0] >[341095.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b8cd0] width 1280 pitch 5120 (/4 1280) >[341095.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b07f0] >[341095.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b07f0] width 1280 pitch 5120 (/4 1280) >[341095.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a48c0] >[341095.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a48c0] width 1280 pitch 5120 (/4 1280) >[341095.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4593040] >[341095.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4593040] width 1280 pitch 5120 (/4 1280) >[341095.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe720] >[341095.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe720] width 1280 pitch 5120 (/4 1280) >[341095.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3338a50] >[341095.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3338a50] width 1280 pitch 5120 (/4 1280) >[341129.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e940] >[341129.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e940] width 1280 pitch 5120 (/4 1280) >[341129.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d0c0] >[341129.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d0c0] width 1280 pitch 5120 (/4 1280) >[341129.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3592550] >[341129.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3592550] width 1280 pitch 5120 (/4 1280) >[341129.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d0c0] >[341129.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d0c0] width 1280 pitch 5120 (/4 1280) >[341139.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e940] >[341139.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e940] width 1280 pitch 5120 (/4 1280) >[341139.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d0c0] >[341139.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d0c0] width 1280 pitch 5120 (/4 1280) >[341139.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2e940] >[341139.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2e940] width 1280 pitch 5120 (/4 1280) >[341139.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3338a50] >[341139.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3338a50] width 1280 pitch 5120 (/4 1280) >[341758.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bf1e0] >[341758.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bf1e0] width 1280 pitch 5120 (/4 1280) >[341759.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f36d0] >[341759.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f36d0] width 1280 pitch 5120 (/4 1280) >[341759.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f36d0] >[341759.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f36d0] width 1280 pitch 5120 (/4 1280) >[341759.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4566a80] >[341759.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4566a80] width 1280 pitch 5120 (/4 1280) >[341768.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da8a0] >[341768.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da8a0] width 1280 pitch 5120 (/4 1280) >[341804.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341804.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341804.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac7da0] >[341804.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac7da0] width 1280 pitch 5120 (/4 1280) >[341804.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5460] >[341804.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5460] width 1280 pitch 5120 (/4 1280) >[341804.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365e3a0] >[341804.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365e3a0] width 1280 pitch 5120 (/4 1280) >[341806.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713c00] >[341806.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713c00] width 1280 pitch 5120 (/4 1280) >[341806.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341806.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341806.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713c00] >[341806.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713c00] width 1280 pitch 5120 (/4 1280) >[341807.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341807.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341844.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3232c60] >[341844.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3232c60] width 1280 pitch 5120 (/4 1280) >[341844.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352fc0] >[341844.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352fc0] width 1280 pitch 5120 (/4 1280) >[341844.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341844.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341844.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352fc0] >[341844.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352fc0] width 1280 pitch 5120 (/4 1280) >[341845.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352fc0] >[341845.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352fc0] width 1280 pitch 5120 (/4 1280) >[341845.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341845.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341845.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3677350] >[341845.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3677350] width 1280 pitch 5120 (/4 1280) >[341845.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341845.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341847.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341847.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341847.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341847.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341847.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e4f00] >[341847.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e4f00] width 1280 pitch 5120 (/4 1280) >[341847.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259d40] >[341847.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259d40] width 1280 pitch 5120 (/4 1280) >[341867.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374e650] >[341867.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374e650] width 1280 pitch 5120 (/4 1280) >[341867.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1380] >[341867.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1380] width 1280 pitch 5120 (/4 1280) >[341867.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4566a80] >[341867.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4566a80] width 1280 pitch 5120 (/4 1280) >[341867.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1380] >[341867.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1380] width 1280 pitch 5120 (/4 1280) >[342034.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3320130] >[342034.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3320130] width 1280 pitch 5120 (/4 1280) >[342034.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359710] >[342034.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359710] width 1280 pitch 5120 (/4 1280) >[342034.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[342034.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[342034.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359710] >[342034.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359710] width 1280 pitch 5120 (/4 1280) >[342305.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5460] >[342305.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5460] width 1280 pitch 5120 (/4 1280) >[342306.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aed550] >[342306.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aed550] width 1280 pitch 5120 (/4 1280) >[342306.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[342306.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[342306.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aed550] >[342306.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aed550] width 1280 pitch 5120 (/4 1280) >[342328.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae78b0] >[342329.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae78b0] width 1280 pitch 5120 (/4 1280) >[342341.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c92370] >[342341.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c92370] width 1280 pitch 5120 (/4 1280) >[342341.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c92370] >[342341.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c92370] width 1280 pitch 5120 (/4 1280) >[342341.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[342341.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[342341.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713d70] >[342341.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713d70] width 1280 pitch 5120 (/4 1280) >[342351.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[342351.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[342356.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[342356.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[342395.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[342395.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[342398.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[342398.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[342555.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[342555.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[342555.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[342555.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[342555.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[342555.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[342555.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[342555.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[342632.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[342633.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[342633.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[342633.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[342633.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[342633.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[342633.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[342633.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[342658.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[342658.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[342658.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[342658.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[342658.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[342658.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[342658.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[342658.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[342663.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[342663.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[342663.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[342663.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[342663.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[342663.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[342663.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[342663.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[342665.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713d70] >[342665.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713d70] width 1280 pitch 5120 (/4 1280) >[342666.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[342666.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[342666.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[342666.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[342666.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[342666.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[343190.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[343190.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[343245.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[343245.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[343245.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[343245.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[343245.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3423d50] >[343245.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3423d50] width 1280 pitch 5120 (/4 1280) >[343245.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3423d50] >[343245.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3423d50] width 1280 pitch 5120 (/4 1280) >[343304.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[343304.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[343304.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[343304.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[343304.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[343304.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[343304.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[343304.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[343356.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[343356.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[343356.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[343356.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[343356.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[343356.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[343356.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[343356.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[343361.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a9490] >[343361.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a9490] width 1280 pitch 5120 (/4 1280) >[343361.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[343361.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[343361.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[343361.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[343361.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[343361.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[343369.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[343369.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[343369.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[343369.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[343369.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[343369.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[343369.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e940] >[343370.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e940] width 1280 pitch 5120 (/4 1280) >[343390.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[343390.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[343390.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[343390.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[343390.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[343390.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[343390.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409870] >[343390.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409870] width 1280 pitch 5120 (/4 1280) >[343579.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[343579.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[343579.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[343579.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[343579.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f5b40] >[343579.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f5b40] width 1280 pitch 5120 (/4 1280) >[343579.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[343579.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[343839.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca8e0] >[343839.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca8e0] width 1280 pitch 5120 (/4 1280) >[343839.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[343839.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[343839.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c92370] >[343839.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c92370] width 1280 pitch 5120 (/4 1280) >[343839.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3a20] >[343839.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3a20] width 1280 pitch 5120 (/4 1280) >[343852.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[343852.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[343852.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[343852.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[343852.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[343852.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[343852.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f4f10] >[343852.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f4f10] width 1280 pitch 5120 (/4 1280) >[343874.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[343874.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[343874.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[343874.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[343874.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a9490] >[343874.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a9490] width 1280 pitch 5120 (/4 1280) >[343874.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[343874.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[344230.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[344230.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[344234.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[344234.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[344234.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[344234.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[344234.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[344234.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[344234.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[344234.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[344387.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301e50] >[344387.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301e50] width 1280 pitch 5120 (/4 1280) >[344387.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[344387.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[344387.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339bdc0] >[344387.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339bdc0] width 1280 pitch 5120 (/4 1280) >[344387.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[344387.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[344389.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359690] >[344389.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359690] width 1280 pitch 5120 (/4 1280) >[344389.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713d70] >[344389.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713d70] width 1280 pitch 5120 (/4 1280) >[344389.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3761680] >[344389.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3761680] width 1280 pitch 5120 (/4 1280) >[344389.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713d70] >[344389.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713d70] width 1280 pitch 5120 (/4 1280) >[344541.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f5b40] >[344541.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f5b40] width 1280 pitch 5120 (/4 1280) >[344544.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[344544.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[344544.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[344544.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[344544.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[344544.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[344802.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[344802.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[344802.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[344802.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[344802.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[344802.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[344802.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[344802.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[344802.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[344802.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[344802.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[344802.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[344802.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[344802.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[344802.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36fb4c0] >[344802.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36fb4c0] width 1280 pitch 5120 (/4 1280) >[344802.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[344802.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[344803.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370050] >[344803.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370050] width 1280 pitch 5120 (/4 1280) >[344803.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[344803.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[344803.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366d9b0] >[344803.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366d9b0] width 1280 pitch 5120 (/4 1280) >[344803.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ba80] >[344803.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ba80] width 1280 pitch 5120 (/4 1280) >[344803.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[344803.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[344803.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36994d0] >[344803.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36994d0] width 1280 pitch 5120 (/4 1280) >[344803.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458e420] >[344803.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458e420] width 1280 pitch 5120 (/4 1280) >[344803.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c664e0] >[344803.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c664e0] width 1280 pitch 5120 (/4 1280) >[344803.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[344803.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[344804.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c664e0] >[344804.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c664e0] width 1280 pitch 5120 (/4 1280) >[344804.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323bc40] >[344804.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323bc40] width 1280 pitch 5120 (/4 1280) >[344836.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48960] >[344836.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48960] width 1280 pitch 5120 (/4 1280) >[344838.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3322a40] >[344838.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3322a40] width 1280 pitch 5120 (/4 1280) >[344838.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b930] >[344838.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b930] width 1280 pitch 5120 (/4 1280) >[344838.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1840] >[344838.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1840] width 1280 pitch 5120 (/4 1280) >[344863.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331bfc0] >[344863.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331bfc0] width 1280 pitch 5120 (/4 1280) >[344864.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263b60] >[344865.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263b60] width 1280 pitch 5120 (/4 1280) >[344865.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1a5e0] >[344865.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1a5e0] width 1280 pitch 5120 (/4 1280) >[344865.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c40a0] >[344865.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c40a0] width 1280 pitch 5120 (/4 1280) >[344899.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c000] >[344899.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c000] width 1280 pitch 5120 (/4 1280) >[344901.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3695450] >[344901.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3695450] width 1280 pitch 5120 (/4 1280) >[344901.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3322a40] >[344901.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3322a40] width 1280 pitch 5120 (/4 1280) >[344901.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3263b60] >[344901.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3263b60] width 1280 pitch 5120 (/4 1280) >[344926.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3480870] >[344926.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3480870] width 1280 pitch 5120 (/4 1280) >[344930.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3695450] >[344930.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3695450] width 1280 pitch 5120 (/4 1280) >[344930.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d7760] >[344930.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d7760] width 1280 pitch 5120 (/4 1280) >[344930.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3480810] >[344930.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3480810] width 1280 pitch 5120 (/4 1280) >[344931.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3322a40] >[344931.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3322a40] width 1280 pitch 5120 (/4 1280) >[344972.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3680] >[344972.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3680] width 1280 pitch 5120 (/4 1280) >[344975.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c1e0] >[344975.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c1e0] width 1280 pitch 5120 (/4 1280) >[345752.692] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[345752.692] (II) RADEON(0): Using hsync ranges from config file >[345752.692] (II) RADEON(0): Using vrefresh ranges from config file >[345752.692] (II) RADEON(0): Printing DDC gathered Modelines: >[345752.692] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[345752.692] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[345752.692] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[345752.692] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[345752.692] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[345752.692] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[345752.692] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[345752.692] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[345752.692] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[345752.692] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[345842.555] (II) RADEON(0): RADEONSaveScreen(2) >[345842.555] (II) RADEON(0): RADEONSaveScreen(0) >[346177.027] (II) RADEON(0): RADEONSaveScreen(1) >[346867.560] (II) RADEON(0): RADEONSaveScreen(2) >[346867.560] (II) RADEON(0): RADEONSaveScreen(0) >[371503.646] (II) RADEON(0): RADEONSaveScreen(1) >[371503.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3321230] >[371503.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3321230] width 1280 pitch 5120 (/4 1280) >[371509.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac8820] >[371509.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac8820] width 1280 pitch 5120 (/4 1280) >[371512.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36994d0] >[371512.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36994d0] width 1280 pitch 5120 (/4 1280) >[371512.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[371512.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[371512.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36994d0] >[371512.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36994d0] width 1280 pitch 5120 (/4 1280) >[371512.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[371512.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[371512.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36994d0] >[371512.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36994d0] width 1280 pitch 5120 (/4 1280) >[371512.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b6c0] >[371512.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b6c0] width 1280 pitch 5120 (/4 1280) >[371512.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716cb0] >[371512.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716cb0] width 1280 pitch 5120 (/4 1280) >[371512.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b6c0] >[371512.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b6c0] width 1280 pitch 5120 (/4 1280) >[371512.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716cb0] >[371512.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716cb0] width 1280 pitch 5120 (/4 1280) >[371512.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b6c0] >[371512.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b6c0] width 1280 pitch 5120 (/4 1280) >[371512.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716cb0] >[371512.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716cb0] width 1280 pitch 5120 (/4 1280) >[371512.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b6c0] >[371512.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b6c0] width 1280 pitch 5120 (/4 1280) >[371512.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716cb0] >[371512.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716cb0] width 1280 pitch 5120 (/4 1280) >[371512.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b6c0] >[371512.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b6c0] width 1280 pitch 5120 (/4 1280) >[371659.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[371659.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[371659.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[371659.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[371659.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ba00] >[371659.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ba00] width 1280 pitch 5120 (/4 1280) >[371659.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[371659.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[371740.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[371740.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[371740.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713d70] >[371740.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713d70] width 1280 pitch 5120 (/4 1280) >[371740.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c7840] >[371740.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c7840] width 1280 pitch 5120 (/4 1280) >[371740.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aed550] >[371740.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aed550] width 1280 pitch 5120 (/4 1280) >[372861.916] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[372861.916] (II) RADEON(0): Using hsync ranges from config file >[372861.916] (II) RADEON(0): Using vrefresh ranges from config file >[372861.916] (II) RADEON(0): Printing DDC gathered Modelines: >[372861.916] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[372861.916] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[372861.916] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[372861.916] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[372861.916] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[372861.916] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[372861.916] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[372861.916] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[372861.916] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[372861.916] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[372952.555] (II) RADEON(0): RADEONSaveScreen(2) >[372952.555] (II) RADEON(0): RADEONSaveScreen(0) >[374936.579] (II) RADEON(0): RADEONSaveScreen(1) >[375861.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80ca0] >[375861.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80ca0] width 1280 pitch 5120 (/4 1280) >[376224.535] (II) RADEON(0): RADEONSaveScreen(2) >[376224.535] (II) RADEON(0): RADEONSaveScreen(0) >[383607.279] (II) RADEON(0): RADEONSaveScreen(1) >[384297.553] (II) RADEON(0): RADEONSaveScreen(2) >[384297.553] (II) RADEON(0): RADEONSaveScreen(0) >[385099.671] (II) RADEON(0): RADEONSaveScreen(1) >[385790.539] (II) RADEON(0): RADEONSaveScreen(2) >[385790.539] (II) RADEON(0): RADEONSaveScreen(0) >[396137.514] (II) RADEON(0): RADEONSaveScreen(1) >[396827.537] (II) RADEON(0): RADEONSaveScreen(2) >[396827.537] (II) RADEON(0): RADEONSaveScreen(0) >[397049.865] (II) RADEON(0): RADEONSaveScreen(1) >[397740.563] (II) RADEON(0): RADEONSaveScreen(2) >[397740.563] (II) RADEON(0): RADEONSaveScreen(0) >[405181.837] (II) RADEON(0): RADEONSaveScreen(1) >[406484.536] (II) RADEON(0): RADEONSaveScreen(2) >[406484.536] (II) RADEON(0): RADEONSaveScreen(0) >[407487.347] (II) RADEON(0): RADEONSaveScreen(1) >[407490.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a0f0] >[407490.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a0f0] width 1280 pitch 5120 (/4 1280) >[408125.732] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[408125.732] (II) RADEON(0): Using hsync ranges from config file >[408125.732] (II) RADEON(0): Using vrefresh ranges from config file >[408125.732] (II) RADEON(0): Printing DDC gathered Modelines: >[408125.732] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[408125.732] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[408125.732] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[408125.732] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[408125.732] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[408125.732] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[408125.732] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[408125.732] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[408125.732] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[408125.732] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[408215.540] (II) RADEON(0): RADEONSaveScreen(2) >[408215.540] (II) RADEON(0): RADEONSaveScreen(0) >[411911.637] (II) RADEON(0): RADEONSaveScreen(1) >[411911.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caff90] >[411911.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caff90] width 1280 pitch 5120 (/4 1280) >[411915.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368ba70] >[411915.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368ba70] width 1280 pitch 5120 (/4 1280) >[411916.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347ef60] >[411916.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347ef60] width 1280 pitch 5120 (/4 1280) >[411916.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353330] >[411916.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353330] width 1280 pitch 5120 (/4 1280) >[411916.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347ef60] >[411916.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347ef60] width 1280 pitch 5120 (/4 1280) >[411916.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353330] >[411916.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353330] width 1280 pitch 5120 (/4 1280) >[411926.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458cb70] >[411926.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458cb70] width 1280 pitch 5120 (/4 1280) >[412175.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412175.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412176.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3358400] >[412176.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3358400] width 1280 pitch 5120 (/4 1280) >[412176.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f15c0] >[412176.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f15c0] width 1280 pitch 5120 (/4 1280) >[412176.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3358400] >[412176.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3358400] width 1280 pitch 5120 (/4 1280) >[412186.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412186.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412187.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[412187.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[412187.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8100] >[412187.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8100] width 1280 pitch 5120 (/4 1280) >[412190.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ca8e0] >[412190.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ca8e0] width 1280 pitch 5120 (/4 1280) >[412190.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[412190.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[412190.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3770] >[412191.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3770] width 1280 pitch 5120 (/4 1280) >[412191.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259170] >[412191.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259170] width 1280 pitch 5120 (/4 1280) >[412193.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4567960] >[412193.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4567960] width 1280 pitch 5120 (/4 1280) >[412206.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3850] >[412206.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3850] width 1280 pitch 5120 (/4 1280) >[412220.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374cc80] >[412220.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374cc80] width 1280 pitch 5120 (/4 1280) >[412221.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99570] >[412221.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99570] width 1280 pitch 5120 (/4 1280) >[412222.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99570] >[412222.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99570] width 1280 pitch 5120 (/4 1280) >[412222.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a16c0] >[412222.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a16c0] width 1280 pitch 5120 (/4 1280) >[412222.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99570] >[412222.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99570] width 1280 pitch 5120 (/4 1280) >[412223.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c50c0] >[412223.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c50c0] width 1280 pitch 5120 (/4 1280) >[412223.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412223.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412223.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[412223.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[412223.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412223.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412224.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[412224.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[412224.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412224.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412225.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[412225.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[412225.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412225.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412225.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412225.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412225.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717330] >[412225.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717330] width 1280 pitch 5120 (/4 1280) >[412225.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412225.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412225.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4588e80] >[412225.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4588e80] width 1280 pitch 5120 (/4 1280) >[412232.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412232.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412232.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412232.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412232.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ed30] >[412232.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ed30] width 1280 pitch 5120 (/4 1280) >[412232.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412232.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412233.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[412233.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[412233.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412233.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412233.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[412233.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[412233.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412233.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412233.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3143080] >[412233.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3143080] width 1280 pitch 5120 (/4 1280) >[412233.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157c00] >[412233.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157c00] width 1280 pitch 5120 (/4 1280) >[412239.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412239.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412239.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1840] >[412239.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1840] width 1280 pitch 5120 (/4 1280) >[412241.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37330d0] >[412241.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37330d0] width 1280 pitch 5120 (/4 1280) >[412241.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37330d0] >[412241.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37330d0] width 1280 pitch 5120 (/4 1280) >[412242.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412242.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412242.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357de20] >[412242.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357de20] width 1280 pitch 5120 (/4 1280) >[412244.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c19590] >[412244.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c19590] width 1280 pitch 5120 (/4 1280) >[412244.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ae620] >[412244.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ae620] width 1280 pitch 5120 (/4 1280) >[412356.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4280] >[412356.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4280] width 1280 pitch 5120 (/4 1280) >[412356.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591740] >[412356.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591740] width 1280 pitch 5120 (/4 1280) >[412356.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c63b0] >[412356.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c63b0] width 1280 pitch 5120 (/4 1280) >[412356.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591740] >[412356.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591740] width 1280 pitch 5120 (/4 1280) >[412357.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7540] >[412357.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7540] width 1280 pitch 5120 (/4 1280) >[412357.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412357.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412357.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412357.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412357.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412357.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412358.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302ea0] >[412358.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302ea0] width 1280 pitch 5120 (/4 1280) >[412358.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412358.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412362.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412362.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412362.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7540] >[412362.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7540] width 1280 pitch 5120 (/4 1280) >[412366.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ae620] >[412366.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ae620] width 1280 pitch 5120 (/4 1280) >[412366.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302ea0] >[412366.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302ea0] width 1280 pitch 5120 (/4 1280) >[412366.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3324750] >[412366.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3324750] width 1280 pitch 5120 (/4 1280) >[412366.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f36a0] >[412366.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f36a0] width 1280 pitch 5120 (/4 1280) >[412366.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3757310] >[412366.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3757310] width 1280 pitch 5120 (/4 1280) >[412367.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3757310] >[412367.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3757310] width 1280 pitch 5120 (/4 1280) >[412368.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412368.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412369.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3757310] >[412369.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3757310] width 1280 pitch 5120 (/4 1280) >[412369.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370ac40] >[412369.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370ac40] width 1280 pitch 5120 (/4 1280) >[412369.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370ac40] >[412369.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370ac40] width 1280 pitch 5120 (/4 1280) >[412369.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa7fe0] >[412369.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa7fe0] width 1280 pitch 5120 (/4 1280) >[412369.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ae620] >[412369.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ae620] width 1280 pitch 5120 (/4 1280) >[412396.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458ca90] >[412396.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458ca90] width 1280 pitch 5120 (/4 1280) >[412396.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ebc0] >[412396.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ebc0] width 1280 pitch 5120 (/4 1280) >[412396.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x266ec60] >[412396.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x266ec60] width 1280 pitch 5120 (/4 1280) >[412396.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ebc0] >[412397.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ebc0] width 1280 pitch 5120 (/4 1280) >[412397.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[412397.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[412397.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c612c0] >[412397.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c612c0] width 1280 pitch 5120 (/4 1280) >[412397.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c563a0] >[412397.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c563a0] width 1280 pitch 5120 (/4 1280) >[412397.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d3500] >[412397.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d3500] width 1280 pitch 5120 (/4 1280) >[412398.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb920] >[412398.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb920] width 1280 pitch 5120 (/4 1280) >[412398.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c32810] >[412398.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c32810] width 1280 pitch 5120 (/4 1280) >[412400.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458cb70] >[412400.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458cb70] width 1280 pitch 5120 (/4 1280) >[412400.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606770] >[412400.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606770] width 1280 pitch 5120 (/4 1280) >[412400.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300b30] >[412400.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300b30] width 1280 pitch 5120 (/4 1280) >[412400.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3cb0] >[412400.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3cb0] width 1280 pitch 5120 (/4 1280) >[412685.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359840] >[412685.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359840] width 1280 pitch 5120 (/4 1280) >[412685.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373c220] >[412685.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373c220] width 1280 pitch 5120 (/4 1280) >[412685.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b470] >[412685.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b470] width 1280 pitch 5120 (/4 1280) >[412685.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df2c0] >[412685.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df2c0] width 1280 pitch 5120 (/4 1280) >[412686.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b470] >[412686.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b470] width 1280 pitch 5120 (/4 1280) >[412686.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[412686.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[412686.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c7d70] >[412686.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c7d70] width 1280 pitch 5120 (/4 1280) >[412686.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348cd30] >[412686.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348cd30] width 1280 pitch 5120 (/4 1280) >[412857.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332cd70] >[412857.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332cd70] width 1280 pitch 5120 (/4 1280) >[412873.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4566e90] >[412873.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4566e90] width 1280 pitch 5120 (/4 1280) >[412873.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332860] >[412873.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332860] width 1280 pitch 5120 (/4 1280) >[412873.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242300] >[412873.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242300] width 1280 pitch 5120 (/4 1280) >[412873.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332860] >[412873.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332860] width 1280 pitch 5120 (/4 1280) >[412873.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242300] >[412873.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242300] width 1280 pitch 5120 (/4 1280) >[412873.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332860] >[412873.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332860] width 1280 pitch 5120 (/4 1280) >[412873.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242300] >[412873.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242300] width 1280 pitch 5120 (/4 1280) >[412873.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332860] >[412873.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332860] width 1280 pitch 5120 (/4 1280) >[412873.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242300] >[412873.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242300] width 1280 pitch 5120 (/4 1280) >[412873.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341e9f0] >[412873.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341e9f0] width 1280 pitch 5120 (/4 1280) >[412873.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c13590] >[412873.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c13590] width 1280 pitch 5120 (/4 1280) >[412873.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341e9f0] >[412873.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341e9f0] width 1280 pitch 5120 (/4 1280) >[412873.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c13590] >[412874.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c13590] width 1280 pitch 5120 (/4 1280) >[412876.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f3bd0] >[412876.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f3bd0] width 1280 pitch 5120 (/4 1280) >[412886.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfd4b0] >[412886.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfd4b0] width 1280 pitch 5120 (/4 1280) >[412886.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45f90] >[412886.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45f90] width 1280 pitch 5120 (/4 1280) >[412892.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d100] >[412892.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d100] width 1280 pitch 5120 (/4 1280) >[412893.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bea870] >[412893.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bea870] width 1280 pitch 5120 (/4 1280) >[412968.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458f450] >[412968.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458f450] width 1280 pitch 5120 (/4 1280) >[412970.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a7a0] >[412970.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a7a0] width 1280 pitch 5120 (/4 1280) >[412970.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[412970.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[412970.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a7a0] >[412970.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a7a0] width 1280 pitch 5120 (/4 1280) >[412970.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[412970.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[412970.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a7a0] >[412970.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a7a0] width 1280 pitch 5120 (/4 1280) >[412970.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dba20] >[412970.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dba20] width 1280 pitch 5120 (/4 1280) >[412970.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3660e50] >[412970.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3660e50] width 1280 pitch 5120 (/4 1280) >[412970.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315dd80] >[412970.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315dd80] width 1280 pitch 5120 (/4 1280) >[412970.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3660e50] >[412970.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3660e50] width 1280 pitch 5120 (/4 1280) >[412970.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b17a0] >[412970.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b17a0] width 1280 pitch 5120 (/4 1280) >[412970.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3660e50] >[412970.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3660e50] width 1280 pitch 5120 (/4 1280) >[412970.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b17a0] >[412970.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b17a0] width 1280 pitch 5120 (/4 1280) >[412970.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d670] >[412970.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d670] width 1280 pitch 5120 (/4 1280) >[412970.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270] >[412970.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1280 pitch 5120 (/4 1280) >[412970.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375f700] >[412970.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375f700] width 1280 pitch 5120 (/4 1280) >[412970.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4760] >[412970.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4760] width 1280 pitch 5120 (/4 1280) >[412970.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e1c0] >[412970.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e1c0] width 1280 pitch 5120 (/4 1280) >[412970.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375f700] >[412970.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375f700] width 1280 pitch 5120 (/4 1280) >[412970.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375f700] >[412970.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375f700] width 1280 pitch 5120 (/4 1280) >[412970.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3692080] >[412971.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3692080] width 1280 pitch 5120 (/4 1280) >[412971.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3304730] >[412971.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3304730] width 1280 pitch 5120 (/4 1280) >[412990.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324c240] >[412990.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324c240] width 1280 pitch 5120 (/4 1280) >[412992.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d0c0] >[412992.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d0c0] width 1280 pitch 5120 (/4 1280) >[412992.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d5c0] >[412992.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d5c0] width 1280 pitch 5120 (/4 1280) >[412992.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d0c0] >[412992.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d0c0] width 1280 pitch 5120 (/4 1280) >[412992.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d5c0] >[412992.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d5c0] width 1280 pitch 5120 (/4 1280) >[412992.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606900] >[412992.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606900] width 1280 pitch 5120 (/4 1280) >[412992.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7e40] >[412993.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7e40] width 1280 pitch 5120 (/4 1280) >[412993.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606900] >[412993.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606900] width 1280 pitch 5120 (/4 1280) >[412993.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7e40] >[412993.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7e40] width 1280 pitch 5120 (/4 1280) >[412993.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606900] >[412993.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606900] width 1280 pitch 5120 (/4 1280) >[412993.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7e40] >[412993.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7e40] width 1280 pitch 5120 (/4 1280) >[412993.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606900] >[412993.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606900] width 1280 pitch 5120 (/4 1280) >[412993.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b7e40] >[412993.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b7e40] width 1280 pitch 5120 (/4 1280) >[413035.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c37c0] >[413035.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c37c0] width 1280 pitch 5120 (/4 1280) >[413035.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369e640] >[413035.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369e640] width 1280 pitch 5120 (/4 1280) >[413035.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7c20] >[413035.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7c20] width 1280 pitch 5120 (/4 1280) >[413035.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302690] >[413035.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302690] width 1280 pitch 5120 (/4 1280) >[413035.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7c20] >[413035.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7c20] width 1280 pitch 5120 (/4 1280) >[413035.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31b90] >[413035.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31b90] width 1280 pitch 5120 (/4 1280) >[413035.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a6b0] >[413035.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a6b0] width 1280 pitch 5120 (/4 1280) >[413035.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33affd0] >[413035.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33affd0] width 1280 pitch 5120 (/4 1280) >[413035.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7c20] >[413035.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7c20] width 1280 pitch 5120 (/4 1280) >[413055.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6100] >[413055.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6100] width 1280 pitch 5120 (/4 1280) >[413119.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3455600] >[413119.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3455600] width 1280 pitch 5120 (/4 1280) >[413121.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[413121.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[413121.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[413121.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[413121.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ba80] >[413121.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ba80] width 1280 pitch 5120 (/4 1280) >[413121.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[413121.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[413121.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[413121.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[413121.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[413121.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[413121.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3225890] >[413121.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3225890] width 1280 pitch 5120 (/4 1280) >[413121.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[413121.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[413122.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab36a0] >[413122.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab36a0] width 1280 pitch 5120 (/4 1280) >[413122.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606660] >[413122.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606660] width 1280 pitch 5120 (/4 1280) >[413122.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360b6c0] >[413122.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360b6c0] width 1280 pitch 5120 (/4 1280) >[413122.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367010] >[413122.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367010] width 1280 pitch 5120 (/4 1280) >[413122.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d4920] >[413122.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d4920] width 1280 pitch 5120 (/4 1280) >[413122.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3757820] >[413122.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3757820] width 1280 pitch 5120 (/4 1280) >[413122.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b9300] >[413123.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b9300] width 1280 pitch 5120 (/4 1280) >[413123.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4587b50] >[413123.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4587b50] width 1280 pitch 5120 (/4 1280) >[413123.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361de90] >[413123.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361de90] width 1280 pitch 5120 (/4 1280) >[413264.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721dc0] >[413264.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721dc0] width 1280 pitch 5120 (/4 1280) >[413266.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a7b00] >[413266.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a7b00] width 1280 pitch 5120 (/4 1280) >[413266.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d8680] >[413266.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d8680] width 1280 pitch 5120 (/4 1280) >[413266.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a7b00] >[413266.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a7b00] width 1280 pitch 5120 (/4 1280) >[413266.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d8680] >[413266.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d8680] width 1280 pitch 5120 (/4 1280) >[413266.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a7b00] >[413266.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a7b00] width 1280 pitch 5120 (/4 1280) >[413266.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d8680] >[413266.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d8680] width 1280 pitch 5120 (/4 1280) >[413266.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a7b00] >[413266.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a7b00] width 1280 pitch 5120 (/4 1280) >[413266.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e5a0] >[413266.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e5a0] width 1280 pitch 5120 (/4 1280) >[413266.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[413266.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[413266.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e5a0] >[413266.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e5a0] width 1280 pitch 5120 (/4 1280) >[413266.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33aa0d0] >[413266.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33aa0d0] width 1280 pitch 5120 (/4 1280) >[413266.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375e5a0] >[413266.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375e5a0] width 1280 pitch 5120 (/4 1280) >[413266.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35db690] >[413266.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35db690] width 1280 pitch 5120 (/4 1280) >[413266.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd2c0] >[413266.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd2c0] width 1280 pitch 5120 (/4 1280) >[413266.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d5150] >[413266.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d5150] width 1280 pitch 5120 (/4 1280) >[413266.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ba0c0] >[413266.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ba0c0] width 1280 pitch 5120 (/4 1280) >[413266.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3755c20] >[413266.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3755c20] width 1280 pitch 5120 (/4 1280) >[413267.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9f810] >[413267.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9f810] width 1280 pitch 5120 (/4 1280) >[413267.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3755c20] >[413267.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3755c20] width 1280 pitch 5120 (/4 1280) >[413267.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9f810] >[413267.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9f810] width 1280 pitch 5120 (/4 1280) >[413267.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3353780] >[413267.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3353780] width 1280 pitch 5120 (/4 1280) >[413422.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3250ac0] >[413422.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3250ac0] width 1280 pitch 5120 (/4 1280) >[413423.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[413423.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[413423.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[413423.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[413423.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[413423.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[413423.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[413424.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[413424.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[413424.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[413424.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[413424.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[413424.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[413424.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[413424.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[413424.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[413424.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[413424.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[413424.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[413424.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[413424.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fd2c0] >[413424.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fd2c0] width 1280 pitch 5120 (/4 1280) >[413424.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0c70] >[413424.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0c70] width 1280 pitch 5120 (/4 1280) >[413424.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[413424.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[413433.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413433.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31364b0] >[413433.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31364b0] width 1280 pitch 5120 (/4 1280) >[413433.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1a00] >[413433.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1a00] width 1280 pitch 5120 (/4 1280) >[413464.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[413464.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[413464.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372a7a0] >[413464.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372a7a0] width 1280 pitch 5120 (/4 1280) >[414170.777] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[414170.777] (II) RADEON(0): Using hsync ranges from config file >[414170.777] (II) RADEON(0): Using vrefresh ranges from config file >[414170.777] (II) RADEON(0): Printing DDC gathered Modelines: >[414170.777] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[414170.777] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[414170.777] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[414170.777] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[414170.777] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[414170.777] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[414170.777] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[414170.777] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[414170.777] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[414170.777] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[414260.535] (II) RADEON(0): RADEONSaveScreen(2) >[414260.535] (II) RADEON(0): RADEONSaveScreen(0) >[415081.094] (II) RADEON(0): RADEONSaveScreen(1) >[415084.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3732e90] >[415084.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3732e90] width 1280 pitch 5120 (/4 1280) >[415087.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459e210] >[415087.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459e210] width 1280 pitch 5120 (/4 1280) >[415470.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415470.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415470.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6f70] >[415470.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6f70] width 1280 pitch 5120 (/4 1280) >[415470.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415470.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415470.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6f70] >[415470.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6f70] width 1280 pitch 5120 (/4 1280) >[415470.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415470.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415470.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f6f70] >[415470.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f6f70] width 1280 pitch 5120 (/4 1280) >[415470.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415470.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415470.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[415470.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[415470.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415470.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415470.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[415470.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[415470.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415471.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415471.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[415471.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[415471.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242180] >[415471.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242180] width 1280 pitch 5120 (/4 1280) >[415471.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[415471.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[415471.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32471b0] >[415471.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32471b0] width 1280 pitch 5120 (/4 1280) >[415471.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336aee0] >[415471.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336aee0] width 1280 pitch 5120 (/4 1280) >[415472.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb300] >[415472.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb300] width 1280 pitch 5120 (/4 1280) >[415473.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359fdc0] >[415473.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359fdc0] width 1280 pitch 5120 (/4 1280) >[415474.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371abc0] >[415474.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371abc0] width 1280 pitch 5120 (/4 1280) >[415474.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[415474.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[415474.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[415474.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[415474.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[415474.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[415474.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d5c0] >[415474.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d5c0] width 1280 pitch 5120 (/4 1280) >[415474.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[415474.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[415474.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9d5c0] >[415474.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9d5c0] width 1280 pitch 5120 (/4 1280) >[415474.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[415474.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[415475.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3618a30] >[415475.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3618a30] width 1280 pitch 5120 (/4 1280) >[415491.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f47d0] >[415491.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f47d0] width 1280 pitch 5120 (/4 1280) >[415492.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6f80] >[415492.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6f80] width 1280 pitch 5120 (/4 1280) >[415492.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6f80] >[415492.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6f80] width 1280 pitch 5120 (/4 1280) >[415492.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a9740] >[415492.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a9740] width 1280 pitch 5120 (/4 1280) >[415524.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c41540] >[415524.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c41540] width 1280 pitch 5120 (/4 1280) >[415526.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d1a0] >[415526.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d1a0] width 1280 pitch 5120 (/4 1280) >[415526.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d1a0] >[415526.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d1a0] width 1280 pitch 5120 (/4 1280) >[415526.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b140] >[415526.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b140] width 1280 pitch 5120 (/4 1280) >[415526.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d1a0] >[415526.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d1a0] width 1280 pitch 5120 (/4 1280) >[415574.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5fc0] >[415574.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5fc0] width 1280 pitch 5120 (/4 1280) >[415582.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336fda0] >[415582.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336fda0] width 1280 pitch 5120 (/4 1280) >[417151.166] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[417151.166] (II) RADEON(0): Using hsync ranges from config file >[417151.166] (II) RADEON(0): Using vrefresh ranges from config file >[417151.166] (II) RADEON(0): Printing DDC gathered Modelines: >[417151.166] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[417151.166] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[417151.166] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[417151.166] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[417151.166] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[417151.166] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[417151.166] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[417151.166] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[417151.166] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[417151.166] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[417241.536] (II) RADEON(0): RADEONSaveScreen(2) >[417241.536] (II) RADEON(0): RADEONSaveScreen(0) >[420270.698] (II) RADEON(0): RADEONSaveScreen(1) >[420270.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338aeb0] >[420270.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338aeb0] width 1280 pitch 5120 (/4 1280) >[420273.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab5190] >[420273.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab5190] width 1280 pitch 5120 (/4 1280) >[420277.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe9b0] >[420277.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe9b0] width 1280 pitch 5120 (/4 1280) >[420277.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[420277.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[420277.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe9b0] >[420277.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe9b0] width 1280 pitch 5120 (/4 1280) >[420278.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33785b0] >[420278.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33785b0] width 1280 pitch 5120 (/4 1280) >[420293.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606900] >[420293.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606900] width 1280 pitch 5120 (/4 1280) >[420300.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7b70] >[420301.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7b70] width 1280 pitch 5120 (/4 1280) >[420313.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3660e50] >[420313.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3660e50] width 1280 pitch 5120 (/4 1280) >[420313.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32471b0] >[420313.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32471b0] width 1280 pitch 5120 (/4 1280) >[420313.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c006a0] >[420313.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c006a0] width 1280 pitch 5120 (/4 1280) >[420313.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[420313.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[420313.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c006a0] >[420313.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c006a0] width 1280 pitch 5120 (/4 1280) >[420313.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32eebf0] >[420313.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32eebf0] width 1280 pitch 5120 (/4 1280) >[420313.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2cc0] >[420313.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2cc0] width 1280 pitch 5120 (/4 1280) >[420313.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[420313.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[420313.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8280] >[420314.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8280] width 1280 pitch 5120 (/4 1280) >[420314.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[420314.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[420314.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336b4b0] >[420314.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336b4b0] width 1280 pitch 5120 (/4 1280) >[420315.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420315.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341cb70] >[420315.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341cb70] width 1280 pitch 5120 (/4 1280) >[420315.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6550] >[420315.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6550] width 1280 pitch 5120 (/4 1280) >[420317.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c19880] >[420317.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c19880] width 1280 pitch 5120 (/4 1280) >[420317.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3625de0] >[420317.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3625de0] width 1280 pitch 5120 (/4 1280) >[420317.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c19880] >[420317.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c19880] width 1280 pitch 5120 (/4 1280) >[420317.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3625de0] >[420317.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3625de0] width 1280 pitch 5120 (/4 1280) >[420318.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b14d0] >[420318.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b14d0] width 1280 pitch 5120 (/4 1280) >[420319.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b98c0] >[420319.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b98c0] width 1280 pitch 5120 (/4 1280) >[420319.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ab2b0] >[420319.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ab2b0] width 1280 pitch 5120 (/4 1280) >[420319.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c41a0] >[420319.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c41a0] width 1280 pitch 5120 (/4 1280) >[420925.075] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[420925.075] (II) RADEON(0): Using hsync ranges from config file >[420925.075] (II) RADEON(0): Using vrefresh ranges from config file >[420925.075] (II) RADEON(0): Printing DDC gathered Modelines: >[420925.075] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[420925.075] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[420925.075] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[420925.075] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[420925.075] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[420925.075] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[420925.075] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[420925.075] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[420925.075] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[420925.075] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[421015.555] (II) RADEON(0): RADEONSaveScreen(2) >[421015.555] (II) RADEON(0): RADEONSaveScreen(0) >[426789.315] (II) RADEON(0): RADEONSaveScreen(1) >[426789.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1f40] >[426789.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1f40] width 1280 pitch 5120 (/4 1280) >[426792.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a5b70] >[426792.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a5b70] width 1280 pitch 5120 (/4 1280) >[427557.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3306470] >[427557.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3306470] width 1280 pitch 5120 (/4 1280) >[427558.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab10] >[427558.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab10] width 1280 pitch 5120 (/4 1280) >[427558.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33500f0] >[427558.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33500f0] width 1280 pitch 5120 (/4 1280) >[427558.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab10] >[427558.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab10] width 1280 pitch 5120 (/4 1280) >[427559.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33500f0] >[427559.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33500f0] width 1280 pitch 5120 (/4 1280) >[427559.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab10] >[427559.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab10] width 1280 pitch 5120 (/4 1280) >[427578.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459dd80] >[427578.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459dd80] width 1280 pitch 5120 (/4 1280) >[427578.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab10] >[427578.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab10] width 1280 pitch 5120 (/4 1280) >[427578.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d08d0] >[427578.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d08d0] width 1280 pitch 5120 (/4 1280) >[427579.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x340ab10] >[427579.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x340ab10] width 1280 pitch 5120 (/4 1280) >[427635.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad36f0] >[427635.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad36f0] width 1280 pitch 5120 (/4 1280) >[427635.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ba420] >[427635.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ba420] width 1280 pitch 5120 (/4 1280) >[427636.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ba420] >[427636.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ba420] width 1280 pitch 5120 (/4 1280) >[427636.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64150] >[427636.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64150] width 1280 pitch 5120 (/4 1280) >[427636.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624bf0] >[427636.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624bf0] width 1280 pitch 5120 (/4 1280) >[427636.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624cc0] >[427636.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624cc0] width 1280 pitch 5120 (/4 1280) >[427637.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427637.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427638.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427638.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427638.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64150] >[427638.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64150] width 1280 pitch 5120 (/4 1280) >[427638.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427638.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427672.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[427672.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[427673.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64150] >[427673.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64150] width 1280 pitch 5120 (/4 1280) >[427673.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[427673.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[427673.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64150] >[427673.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64150] width 1280 pitch 5120 (/4 1280) >[427674.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[427674.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[427674.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427674.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427674.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3399780] >[427674.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3399780] width 1280 pitch 5120 (/4 1280) >[427674.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427674.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427674.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad80] >[427674.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad80] width 1280 pitch 5120 (/4 1280) >[427674.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfc8b0] >[427674.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfc8b0] width 1280 pitch 5120 (/4 1280) >[427674.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad80] >[427674.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad80] width 1280 pitch 5120 (/4 1280) >[427674.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad80] >[427674.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad80] width 1280 pitch 5120 (/4 1280) >[427704.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4577770] >[427704.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4577770] width 1280 pitch 5120 (/4 1280) >[427704.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324ad30] >[427705.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324ad30] width 1280 pitch 5120 (/4 1280) >[427705.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427705.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427705.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324ad30] >[427705.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324ad30] width 1280 pitch 5120 (/4 1280) >[427705.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427705.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427705.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324ad30] >[427705.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324ad30] width 1280 pitch 5120 (/4 1280) >[427705.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427705.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427705.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427705.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427705.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427705.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427705.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427705.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427706.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427706.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427706.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427706.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427706.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427706.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427706.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427706.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427706.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427706.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427706.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427706.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427706.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427706.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427706.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135cb0] >[427706.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135cb0] width 1280 pitch 5120 (/4 1280) >[427706.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124f00] >[427706.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124f00] width 1280 pitch 5120 (/4 1280) >[427706.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c245d0] >[427706.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c245d0] width 1280 pitch 5120 (/4 1280) >[427718.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c972e0] >[427719.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c972e0] width 1280 pitch 5120 (/4 1280) >[427719.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cafb50] >[427719.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cafb50] width 1280 pitch 5120 (/4 1280) >[427719.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32af520] >[427719.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32af520] width 1280 pitch 5120 (/4 1280) >[427719.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cafb50] >[427719.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cafb50] width 1280 pitch 5120 (/4 1280) >[428745.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c453b0] >[428745.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c453b0] width 1280 pitch 5120 (/4 1280) >[428746.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bf850] >[428746.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bf850] width 1280 pitch 5120 (/4 1280) >[428746.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c453b0] >[428746.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c453b0] width 1280 pitch 5120 (/4 1280) >[428746.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bf850] >[428746.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bf850] width 1280 pitch 5120 (/4 1280) >[428746.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64150] >[428746.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64150] width 1280 pitch 5120 (/4 1280) >[428746.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bf850] >[428746.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bf850] width 1280 pitch 5120 (/4 1280) >[428855.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba610] >[428855.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba610] width 1280 pitch 5120 (/4 1280) >[428856.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7220] >[428856.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7220] width 1280 pitch 5120 (/4 1280) >[428856.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9aba0] >[428856.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9aba0] width 1280 pitch 5120 (/4 1280) >[428856.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7220] >[428856.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7220] width 1280 pitch 5120 (/4 1280) >[429680.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75d30] >[429680.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75d30] width 1280 pitch 5120 (/4 1280) >[429680.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3396de0] >[429680.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3396de0] width 1280 pitch 5120 (/4 1280) >[429687.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db010] >[429687.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db010] width 1280 pitch 5120 (/4 1280) >[429691.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db780] >[429691.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db780] width 1280 pitch 5120 (/4 1280) >[429691.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32498c0] >[429691.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32498c0] width 1280 pitch 5120 (/4 1280) >[429691.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fa2e0] >[429691.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fa2e0] width 1280 pitch 5120 (/4 1280) >[429691.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32498c0] >[429691.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32498c0] width 1280 pitch 5120 (/4 1280) >[429700.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6910] >[429700.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6910] width 1280 pitch 5120 (/4 1280) >[429702.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bf920] >[429702.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bf920] width 1280 pitch 5120 (/4 1280) >[429707.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3596fe0] >[429707.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3596fe0] width 1280 pitch 5120 (/4 1280) >[429707.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493230] >[429708.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493230] width 1280 pitch 5120 (/4 1280) >[429708.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6910] >[429708.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6910] width 1280 pitch 5120 (/4 1280) >[429708.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a340] >[429708.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a340] width 1280 pitch 5120 (/4 1280) >[429722.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf9aa0] >[429722.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf9aa0] width 1280 pitch 5120 (/4 1280) >[429725.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3588510] >[429725.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3588510] width 1280 pitch 5120 (/4 1280) >[429725.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429725.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429726.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ec350] >[429726.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ec350] width 1280 pitch 5120 (/4 1280) >[429753.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429753.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429754.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429754.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429754.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362c830] >[429754.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362c830] width 1280 pitch 5120 (/4 1280) >[429754.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c455c0] >[429754.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c455c0] width 1280 pitch 5120 (/4 1280) >[429755.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3fd20] >[429756.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3fd20] width 1280 pitch 5120 (/4 1280) >[429757.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429757.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429757.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bcc60] >[429757.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bcc60] width 1280 pitch 5120 (/4 1280) >[429757.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429757.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db390] >[429757.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db390] width 1280 pitch 5120 (/4 1280) >[429757.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429757.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429757.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429757.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429757.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429757.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429757.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429757.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429757.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429757.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429757.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429757.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429757.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1d10] >[429757.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1d10] width 1280 pitch 5120 (/4 1280) >[429758.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8280] >[429758.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8280] width 1280 pitch 5120 (/4 1280) >[429758.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237400] >[429758.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237400] width 1280 pitch 5120 (/4 1280) >[429759.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8280] >[429759.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8280] width 1280 pitch 5120 (/4 1280) >[429759.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8280] >[429759.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8280] width 1280 pitch 5120 (/4 1280) >[429759.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b0c0] >[429759.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b0c0] width 1280 pitch 5120 (/4 1280) >[429759.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[429759.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[429759.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[429759.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[429759.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[429759.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf39f0] >[429759.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf39f0] width 1280 pitch 5120 (/4 1280) >[429759.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36478d0] >[429759.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36478d0] width 1280 pitch 5120 (/4 1280) >[430009.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b0c0] >[430009.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b0c0] width 1280 pitch 5120 (/4 1280) >[430009.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9aba0] >[430009.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9aba0] width 1280 pitch 5120 (/4 1280) >[430009.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa8280] >[430009.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa8280] width 1280 pitch 5120 (/4 1280) >[430009.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bcc60] >[430009.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bcc60] width 1280 pitch 5120 (/4 1280) >[430017.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47ce0] >[430017.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47ce0] width 1280 pitch 5120 (/4 1280) >[430017.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bcc60] >[430017.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bcc60] width 1280 pitch 5120 (/4 1280) >[430017.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a1a0] >[430017.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a1a0] width 1280 pitch 5120 (/4 1280) >[430017.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bcc60] >[430017.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bcc60] width 1280 pitch 5120 (/4 1280) >[430018.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a1a0] >[430018.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a1a0] width 1280 pitch 5120 (/4 1280) >[430018.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bcc60] >[430018.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bcc60] width 1280 pitch 5120 (/4 1280) >[430018.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370efd0] >[430018.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370efd0] width 1280 pitch 5120 (/4 1280) >[430019.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458a1a0] >[430019.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458a1a0] width 1280 pitch 5120 (/4 1280) >[430019.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b0c0] >[430019.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b0c0] width 1280 pitch 5120 (/4 1280) >[430019.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947a0] >[430019.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947a0] width 1280 pitch 5120 (/4 1280) >[430019.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679f20] >[430019.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679f20] width 1280 pitch 5120 (/4 1280) >[430019.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947a0] >[430019.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947a0] width 1280 pitch 5120 (/4 1280) >[431230.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33737a0] >[431230.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33737a0] width 1280 pitch 5120 (/4 1280) >[431231.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947a0] >[431231.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947a0] width 1280 pitch 5120 (/4 1280) >[431231.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947a0] >[431231.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947a0] width 1280 pitch 5120 (/4 1280) >[431231.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33af720] >[431231.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33af720] width 1280 pitch 5120 (/4 1280) >[431232.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366f200] >[431232.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366f200] width 1280 pitch 5120 (/4 1280) >[431232.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db410] >[431232.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db410] width 1280 pitch 5120 (/4 1280) >[431232.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1780] >[431232.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1780] width 1280 pitch 5120 (/4 1280) >[431232.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5040] >[431232.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5040] width 1280 pitch 5120 (/4 1280) >[431232.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0310] >[431232.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0310] width 1280 pitch 5120 (/4 1280) >[431232.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a25e0] >[431232.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a25e0] width 1280 pitch 5120 (/4 1280) >[431232.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db360] >[431232.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db360] width 1280 pitch 5120 (/4 1280) >[431232.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a25e0] >[431232.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a25e0] width 1280 pitch 5120 (/4 1280) >[431233.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5040] >[431233.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5040] width 1280 pitch 5120 (/4 1280) >[431233.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c460d0] >[431233.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c460d0] width 1280 pitch 5120 (/4 1280) >[431233.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a25e0] >[431233.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a25e0] width 1280 pitch 5120 (/4 1280) >[431233.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c460d0] >[431233.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c460d0] width 1280 pitch 5120 (/4 1280) >[431235.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db2a0] >[431235.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db2a0] width 1280 pitch 5120 (/4 1280) >[431235.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33006e0] >[431235.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33006e0] width 1280 pitch 5120 (/4 1280) >[431235.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c7a90] >[431235.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c7a90] width 1280 pitch 5120 (/4 1280) >[431235.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33006e0] >[431235.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33006e0] width 1280 pitch 5120 (/4 1280) >[431235.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697900] >[431235.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697900] width 1280 pitch 5120 (/4 1280) >[431235.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33002d0] >[431235.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33002d0] width 1280 pitch 5120 (/4 1280) >[431235.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3710220] >[431235.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3710220] width 1280 pitch 5120 (/4 1280) >[431235.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33002d0] >[431235.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33002d0] width 1280 pitch 5120 (/4 1280) >[431235.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c17bb0] >[431235.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c17bb0] width 1280 pitch 5120 (/4 1280) >[431277.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478480] >[431277.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478480] width 1280 pitch 5120 (/4 1280) >[431279.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33002d0] >[431279.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33002d0] width 1280 pitch 5120 (/4 1280) >[431279.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2d070] >[431279.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2d070] width 1280 pitch 5120 (/4 1280) >[431279.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc410] >[431280.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc410] width 1280 pitch 5120 (/4 1280) >[431280.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2d070] >[431280.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2d070] width 1280 pitch 5120 (/4 1280) >[431372.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae3fe0] >[431372.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae3fe0] width 1280 pitch 5120 (/4 1280) >[431375.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f9dc0] >[431375.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f9dc0] width 1280 pitch 5120 (/4 1280) >[431375.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258e80] >[431375.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258e80] width 1280 pitch 5120 (/4 1280) >[431375.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad7c0] >[431375.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad7c0] width 1280 pitch 5120 (/4 1280) >[431380.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45823a0] >[431380.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45823a0] width 1280 pitch 5120 (/4 1280) >[431383.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3573790] >[431383.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3573790] width 1280 pitch 5120 (/4 1280) >[431384.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2d770] >[431384.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2d770] width 1280 pitch 5120 (/4 1280) >[431384.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db410] >[431384.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db410] width 1280 pitch 5120 (/4 1280) >[431384.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33737a0] >[431384.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33737a0] width 1280 pitch 5120 (/4 1280) >[431384.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db410] >[431384.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db410] width 1280 pitch 5120 (/4 1280) >[432812.190] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[432812.190] (II) RADEON(0): Using hsync ranges from config file >[432812.190] (II) RADEON(0): Using vrefresh ranges from config file >[432812.190] (II) RADEON(0): Printing DDC gathered Modelines: >[432812.190] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[432812.190] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[432812.190] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[432812.190] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[432812.190] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[432812.190] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[432812.190] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[432812.190] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[432812.190] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[432812.190] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[432902.554] (II) RADEON(0): RADEONSaveScreen(2) >[432902.555] (II) RADEON(0): RADEONSaveScreen(0) >[467790.717] (II) RADEON(0): RADEONSaveScreen(1) >[467790.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ac90] >[467790.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ac90] width 1280 pitch 5120 (/4 1280) >[467796.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33947a0] >[467796.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33947a0] width 1280 pitch 5120 (/4 1280) >[467799.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6300] >[467799.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6300] width 1280 pitch 5120 (/4 1280) >[467799.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467799.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[467799.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2d70] >[467799.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2d70] width 1280 pitch 5120 (/4 1280) >[467799.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467799.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[467799.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2d70] >[467799.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2d70] width 1280 pitch 5120 (/4 1280) >[467799.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467799.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[467799.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2d70] >[467800.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2d70] width 1280 pitch 5120 (/4 1280) >[467800.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467800.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[467800.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2d70] >[467800.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2d70] width 1280 pitch 5120 (/4 1280) >[467800.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467800.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[467800.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2d70] >[467800.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2d70] width 1280 pitch 5120 (/4 1280) >[467859.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47ce0] >[467859.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47ce0] width 1280 pitch 5120 (/4 1280) >[467937.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaa20] >[467937.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaa20] width 1280 pitch 5120 (/4 1280) >[468274.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35991a0] >[468274.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35991a0] width 1280 pitch 5120 (/4 1280) >[468275.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35991a0] >[468275.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35991a0] width 1280 pitch 5120 (/4 1280) >[468275.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330af40] >[468275.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330af40] width 1280 pitch 5120 (/4 1280) >[468275.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35991a0] >[468275.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35991a0] width 1280 pitch 5120 (/4 1280) >[469742.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3670] >[469742.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3670] width 1280 pitch 5120 (/4 1280) >[469742.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348dc60] >[469742.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348dc60] width 1280 pitch 5120 (/4 1280) >[469742.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cf120] >[469742.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cf120] width 1280 pitch 5120 (/4 1280) >[469742.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3312a90] >[469742.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3312a90] width 1280 pitch 5120 (/4 1280) >[470240.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d1d30] >[470240.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d1d30] width 1280 pitch 5120 (/4 1280) >[470241.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cf120] >[470241.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cf120] width 1280 pitch 5120 (/4 1280) >[470241.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[470241.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[470241.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab6790] >[470241.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab6790] width 1280 pitch 5120 (/4 1280) >[470402.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd45b0] >[470402.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd45b0] width 1280 pitch 5120 (/4 1280) >[470403.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab6790] >[470403.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab6790] width 1280 pitch 5120 (/4 1280) >[470403.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33afc80] >[470403.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33afc80] width 1280 pitch 5120 (/4 1280) >[470403.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33afc80] >[470403.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33afc80] width 1280 pitch 5120 (/4 1280) >[471124.222] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[471124.222] (II) RADEON(0): Using hsync ranges from config file >[471124.222] (II) RADEON(0): Using vrefresh ranges from config file >[471124.222] (II) RADEON(0): Printing DDC gathered Modelines: >[471124.222] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[471124.222] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[471124.222] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[471124.222] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[471124.222] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[471124.222] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[471124.222] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[471124.222] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[471124.222] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[471124.222] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[471214.539] (II) RADEON(0): RADEONSaveScreen(2) >[471214.539] (II) RADEON(0): RADEONSaveScreen(0) >[474787.541] (II) RADEON(0): RADEONSaveScreen(1) >[474787.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34548d0] >[474787.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34548d0] width 1280 pitch 5120 (/4 1280) >[474790.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0fca0] >[474790.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0fca0] width 1280 pitch 5120 (/4 1280) >[474791.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad7c0] >[474791.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad7c0] width 1280 pitch 5120 (/4 1280) >[474791.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5ed0] >[474791.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5ed0] width 1280 pitch 5120 (/4 1280) >[474791.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad7c0] >[474791.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad7c0] width 1280 pitch 5120 (/4 1280) >[474792.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5ed0] >[474792.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5ed0] width 1280 pitch 5120 (/4 1280) >[474797.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c01230] >[474797.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c01230] width 1280 pitch 5120 (/4 1280) >[474797.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0fce0] >[474797.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0fce0] width 1280 pitch 5120 (/4 1280) >[474797.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd45b0] >[474797.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd45b0] width 1280 pitch 5120 (/4 1280) >[474797.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0fce0] >[474797.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0fce0] width 1280 pitch 5120 (/4 1280) >[474804.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582040] >[474804.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582040] width 1280 pitch 5120 (/4 1280) >[474805.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33193c0] >[474805.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33193c0] width 1280 pitch 5120 (/4 1280) >[474805.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c778c0] >[474805.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c778c0] width 1280 pitch 5120 (/4 1280) >[474805.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33193c0] >[474805.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33193c0] width 1280 pitch 5120 (/4 1280) >[474809.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7050] >[474809.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7050] width 1280 pitch 5120 (/4 1280) >[474809.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d720] >[474809.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d720] width 1280 pitch 5120 (/4 1280) >[474809.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0fce0] >[474809.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0fce0] width 1280 pitch 5120 (/4 1280) >[474809.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d720] >[474809.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d720] width 1280 pitch 5120 (/4 1280) >[474816.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1b30] >[474816.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1b30] width 1280 pitch 5120 (/4 1280) >[474816.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3307900] >[474816.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3307900] width 1280 pitch 5120 (/4 1280) >[474817.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d7ad0] >[474817.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d7ad0] width 1280 pitch 5120 (/4 1280) >[474817.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d780] >[474817.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d780] width 1280 pitch 5120 (/4 1280) >[474817.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd45b0] >[474817.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd45b0] width 1280 pitch 5120 (/4 1280) >[474817.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[474817.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475100.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ef50] >[475100.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ef50] width 1280 pitch 5120 (/4 1280) >[475100.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b07e0] >[475100.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b07e0] width 1280 pitch 5120 (/4 1280) >[475120.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bdbc0] >[475120.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bdbc0] width 1280 pitch 5120 (/4 1280) >[475240.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a5d0] >[475240.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a5d0] width 1280 pitch 5120 (/4 1280) >[475242.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475242.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475242.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475242.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475242.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475242.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475242.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475242.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475242.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475242.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475242.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475242.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475242.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475242.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475242.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31e20] >[475242.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31e20] width 1280 pitch 5120 (/4 1280) >[475242.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bad500] >[475242.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bad500] width 1280 pitch 5120 (/4 1280) >[475242.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c31e20] >[475242.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c31e20] width 1280 pitch 5120 (/4 1280) >[475245.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475245.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475245.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475245.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475245.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475372.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33193c0] >[475372.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33193c0] width 1280 pitch 5120 (/4 1280) >[475372.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475372.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475372.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d1d30] >[475372.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d1d30] width 1280 pitch 5120 (/4 1280) >[475372.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475372.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475374.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd83d0] >[475374.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd83d0] width 1280 pitch 5120 (/4 1280) >[475374.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f7f60] >[475374.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f7f60] width 1280 pitch 5120 (/4 1280) >[475374.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358ebe0] >[475374.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358ebe0] width 1280 pitch 5120 (/4 1280) >[475374.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f7f60] >[475374.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f7f60] width 1280 pitch 5120 (/4 1280) >[475463.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363efa0] >[475463.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363efa0] width 1280 pitch 5120 (/4 1280) >[475463.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360ad50] >[475463.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360ad50] width 1280 pitch 5120 (/4 1280) >[475483.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365d660] >[475483.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365d660] width 1280 pitch 5120 (/4 1280) >[475515.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3361ff0] >[475515.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3361ff0] width 1280 pitch 5120 (/4 1280) >[475516.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f7f60] >[475516.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f7f60] width 1280 pitch 5120 (/4 1280) >[475516.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363efa0] >[475516.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363efa0] width 1280 pitch 5120 (/4 1280) >[475516.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475516.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475516.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c938e0] >[475516.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c938e0] width 1280 pitch 5120 (/4 1280) >[475516.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475516.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475516.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475516.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475516.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475516.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475516.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475516.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475516.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475516.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475516.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475516.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475518.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475518.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[475518.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[475518.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475518.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475561.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35edf00] >[475561.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35edf00] width 1280 pitch 5120 (/4 1280) >[475561.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebc40] >[475561.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebc40] width 1280 pitch 5120 (/4 1280) >[475582.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd2f0] >[475582.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd2f0] width 1280 pitch 5120 (/4 1280) >[475609.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3681cb0] >[475609.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3681cb0] width 1280 pitch 5120 (/4 1280) >[475611.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a1bf0] >[475611.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a1bf0] width 1280 pitch 5120 (/4 1280) >[475611.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[475611.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[475611.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475611.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475611.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475611.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475611.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475611.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475611.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475611.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475611.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475611.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475611.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475611.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475613.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475613.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475613.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475613.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475613.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475613.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475613.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475613.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475614.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[475614.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[475614.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475614.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475630.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348f210] >[475631.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348f210] width 1280 pitch 5120 (/4 1280) >[475631.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[475631.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[475712.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c190] >[475712.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c190] width 1280 pitch 5120 (/4 1280) >[475714.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ab770] >[475714.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ab770] width 1280 pitch 5120 (/4 1280) >[475714.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459ad30] >[475714.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459ad30] width 1280 pitch 5120 (/4 1280) >[475714.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ab770] >[475714.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ab770] width 1280 pitch 5120 (/4 1280) >[475732.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3454ee0] >[475732.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3454ee0] width 1280 pitch 5120 (/4 1280) >[475795.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d6010] >[475795.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d6010] width 1280 pitch 5120 (/4 1280) >[475795.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc090] >[475795.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc090] width 1280 pitch 5120 (/4 1280) >[475795.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e30] >[475795.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e30] width 1280 pitch 5120 (/4 1280) >[475795.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba060] >[475795.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba060] width 1280 pitch 5120 (/4 1280) >[475795.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e30] >[475795.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e30] width 1280 pitch 5120 (/4 1280) >[475795.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba060] >[475795.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba060] width 1280 pitch 5120 (/4 1280) >[475795.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e30] >[475795.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e30] width 1280 pitch 5120 (/4 1280) >[475795.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba060] >[475795.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba060] width 1280 pitch 5120 (/4 1280) >[475795.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e30] >[475795.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e30] width 1280 pitch 5120 (/4 1280) >[475795.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba060] >[475795.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba060] width 1280 pitch 5120 (/4 1280) >[475795.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e30] >[475795.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e30] width 1280 pitch 5120 (/4 1280) >[475795.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba060] >[475795.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba060] width 1280 pitch 5120 (/4 1280) >[475796.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b9350] >[475796.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b9350] width 1280 pitch 5120 (/4 1280) >[475797.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[475797.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[475797.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[475798.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[475798.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[475798.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[475798.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f7f60] >[475798.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f7f60] width 1280 pitch 5120 (/4 1280) >[475798.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[475798.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[475798.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3371b80] >[475798.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3371b80] width 1280 pitch 5120 (/4 1280) >[475798.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[475798.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[475798.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475798.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475798.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[475798.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[475798.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[475798.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[475798.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[475798.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[475803.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[475803.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[475803.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[475803.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[475803.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5620] >[475803.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5620] width 1280 pitch 5120 (/4 1280) >[475803.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[475803.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[475803.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[475803.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[476404.051] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[476404.051] (II) RADEON(0): Using hsync ranges from config file >[476404.051] (II) RADEON(0): Using vrefresh ranges from config file >[476404.051] (II) RADEON(0): Printing DDC gathered Modelines: >[476404.051] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[476404.051] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[476404.051] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[476404.051] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[476404.051] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[476404.051] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[476404.051] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[476404.051] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[476404.051] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[476404.051] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[476494.539] (II) RADEON(0): RADEONSaveScreen(2) >[476494.539] (II) RADEON(0): RADEONSaveScreen(0) >[477337.109] (II) RADEON(0): RADEONSaveScreen(1) >[477340.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45809f0] >[477340.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45809f0] width 1280 pitch 5120 (/4 1280) >[477354.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348f210] >[477354.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348f210] width 1280 pitch 5120 (/4 1280) >[477354.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[477354.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[477354.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab1ed0] >[477354.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab1ed0] width 1280 pitch 5120 (/4 1280) >[477354.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[477354.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[477358.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[477358.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[477359.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[477359.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[477379.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c938e0] >[477379.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c938e0] width 1280 pitch 5120 (/4 1280) >[477379.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477379.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477379.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[477379.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[477380.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477380.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477381.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[477381.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[477381.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[477381.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[477381.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[477381.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[477381.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c938e0] >[477381.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c938e0] width 1280 pitch 5120 (/4 1280) >[477502.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[477502.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[477502.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[477502.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[477502.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab1ed0] >[477502.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab1ed0] width 1280 pitch 5120 (/4 1280) >[477502.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[477502.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[477504.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[477504.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[477504.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[477504.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[477504.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab1ed0] >[477504.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab1ed0] width 1280 pitch 5120 (/4 1280) >[477504.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[477504.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[477519.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[477519.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[477519.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[477519.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[477519.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[477519.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[477519.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[477519.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[477522.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[477522.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[477522.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[477522.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[477522.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf2180] >[477522.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf2180] width 1280 pitch 5120 (/4 1280) >[477522.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[477522.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[477640.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[477640.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[477640.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348f210] >[477640.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348f210] width 1280 pitch 5120 (/4 1280) >[477640.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[477640.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[477641.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348f210] >[477641.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348f210] width 1280 pitch 5120 (/4 1280) >[477641.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[477641.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[477642.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477642.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477642.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f120] >[477642.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f120] width 1280 pitch 5120 (/4 1280) >[477642.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477642.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477761.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[477761.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[477761.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[477761.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[477761.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417320] >[477761.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417320] width 1280 pitch 5120 (/4 1280) >[477761.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[477761.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[477772.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477772.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477772.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477772.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[477772.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[477772.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[477772.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[477772.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[478088.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[478088.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[478088.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478088.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478088.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[478088.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[478088.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478088.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478093.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478093.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478093.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5620] >[478093.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5620] width 1280 pitch 5120 (/4 1280) >[478093.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478093.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478093.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5620] >[478093.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5620] width 1280 pitch 5120 (/4 1280) >[478095.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478095.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478095.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478095.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478095.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d90f0] >[478096.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d90f0] width 1280 pitch 5120 (/4 1280) >[478096.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478096.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478099.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478099.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478099.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478099.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478099.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[478099.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[478099.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478099.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478106.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[478106.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[478106.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478106.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478106.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fe00] >[478106.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fe00] width 1280 pitch 5120 (/4 1280) >[478106.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478106.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478107.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb890] >[478107.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb890] width 1280 pitch 5120 (/4 1280) >[478107.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478107.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478107.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[478107.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[478107.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478107.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478139.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[478139.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[478139.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[478139.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[478139.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[478139.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[478140.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[478140.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[478141.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab1ed0] >[478141.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab1ed0] width 1280 pitch 5120 (/4 1280) >[478141.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[478141.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[478141.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478141.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478141.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34192c0] >[478141.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34192c0] width 1280 pitch 5120 (/4 1280) >[478205.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c938e0] >[478205.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c938e0] width 1280 pitch 5120 (/4 1280) >[478205.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[478205.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[478205.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[478205.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[478205.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[478205.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[478207.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[478207.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[478207.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e98f0] >[478208.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e98f0] width 1280 pitch 5120 (/4 1280) >[478208.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[478208.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[478208.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e98f0] >[478208.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e98f0] width 1280 pitch 5120 (/4 1280) >[478325.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45809f0] >[478325.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45809f0] width 1280 pitch 5120 (/4 1280) >[478325.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[478325.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[478325.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d90f0] >[478325.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d90f0] width 1280 pitch 5120 (/4 1280) >[478325.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45809f0] >[478325.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45809f0] width 1280 pitch 5120 (/4 1280) >[478332.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[478332.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[478332.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[478332.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[478332.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[478332.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[478332.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[478332.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[478339.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644cf0] >[478339.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644cf0] width 1280 pitch 5120 (/4 1280) >[478340.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34802a0] >[478340.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34802a0] width 1280 pitch 5120 (/4 1280) >[478340.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[478340.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[478340.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[478340.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[478564.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366ce20] >[478564.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366ce20] width 1280 pitch 5120 (/4 1280) >[478847.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab1ed0] >[478847.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab1ed0] width 1280 pitch 5120 (/4 1280) >[478848.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[478848.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[478848.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36174d0] >[478848.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36174d0] width 1280 pitch 5120 (/4 1280) >[478849.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d90f0] >[478849.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d90f0] width 1280 pitch 5120 (/4 1280) >[478850.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478850.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478850.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478850.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478850.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689e30] >[478850.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689e30] width 1280 pitch 5120 (/4 1280) >[478850.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1db0] >[478850.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1db0] width 1280 pitch 5120 (/4 1280) >[478853.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45809f0] >[478853.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45809f0] width 1280 pitch 5120 (/4 1280) >[478853.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[478853.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[478853.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2870] >[478853.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2870] width 1280 pitch 5120 (/4 1280) >[478853.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3651ac0] >[478853.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3651ac0] width 1280 pitch 5120 (/4 1280) >[478884.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[478884.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[478885.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c938e0] >[478885.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c938e0] width 1280 pitch 5120 (/4 1280) >[478886.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5620] >[478886.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5620] width 1280 pitch 5120 (/4 1280) >[478886.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[478886.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[478900.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[478900.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[478900.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36524a0] >[478900.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36524a0] width 1280 pitch 5120 (/4 1280) >[478902.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[478902.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[478902.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36524a0] >[478902.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36524a0] width 1280 pitch 5120 (/4 1280) >[478902.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f620] >[478902.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f620] width 1280 pitch 5120 (/4 1280) >[478902.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[478902.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[478914.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478914.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478914.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478914.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478914.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[478915.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[478915.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478915.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478916.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0570] >[478916.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0570] width 1280 pitch 5120 (/4 1280) >[478916.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[478916.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[478916.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36524a0] >[478917.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36524a0] width 1280 pitch 5120 (/4 1280) >[478917.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[478917.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[478918.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3583dd0] >[478918.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3583dd0] width 1280 pitch 5120 (/4 1280) >[478918.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478918.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478918.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f620] >[478918.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f620] width 1280 pitch 5120 (/4 1280) >[478918.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478918.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478919.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36524a0] >[478919.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36524a0] width 1280 pitch 5120 (/4 1280) >[478919.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f620] >[478919.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f620] width 1280 pitch 5120 (/4 1280) >[478919.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3323f40] >[478919.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3323f40] width 1280 pitch 5120 (/4 1280) >[478919.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f620] >[478919.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f620] width 1280 pitch 5120 (/4 1280) >[478953.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[478953.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[478953.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[478953.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[478971.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0570] >[478971.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0570] width 1280 pitch 5120 (/4 1280) >[478971.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3583dd0] >[478971.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3583dd0] width 1280 pitch 5120 (/4 1280) >[478971.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478971.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478971.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[478971.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[478980.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[478980.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[478980.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478980.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478985.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[478985.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[478985.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478985.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[478985.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[478985.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[478985.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a8040] >[478985.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a8040] width 1280 pitch 5120 (/4 1280) >[479006.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[479006.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[479006.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[479006.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[479006.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcabc0] >[479006.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcabc0] width 1280 pitch 5120 (/4 1280) >[479006.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[479006.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[479031.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[479031.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[479031.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[479031.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[479031.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[479031.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[479031.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8aed0] >[479031.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8aed0] width 1280 pitch 5120 (/4 1280) >[479038.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f0e0] >[479038.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f0e0] width 1280 pitch 5120 (/4 1280) >[479038.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4578450] >[479038.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4578450] width 1280 pitch 5120 (/4 1280) >[479038.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c9120] >[479038.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c9120] width 1280 pitch 5120 (/4 1280) >[479038.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4578450] >[479038.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4578450] width 1280 pitch 5120 (/4 1280) >[479638.083] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[479638.083] (II) RADEON(0): Using hsync ranges from config file >[479638.083] (II) RADEON(0): Using vrefresh ranges from config file >[479638.083] (II) RADEON(0): Printing DDC gathered Modelines: >[479638.083] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[479638.083] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[479638.083] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[479638.083] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[479638.083] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[479638.083] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[479638.083] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[479638.083] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[479638.083] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[479638.083] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[479728.537] (II) RADEON(0): RADEONSaveScreen(2) >[479728.537] (II) RADEON(0): RADEONSaveScreen(0) >[482126.266] (II) RADEON(0): RADEONSaveScreen(1) >[482130.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0c6e0] >[482130.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0c6e0] width 1280 pitch 5120 (/4 1280) >[482137.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b1500] >[482137.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b1500] width 1280 pitch 5120 (/4 1280) >[482139.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c78c0] >[482139.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c78c0] width 1280 pitch 5120 (/4 1280) >[482142.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333f0e0] >[482142.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333f0e0] width 1280 pitch 5120 (/4 1280) >[482142.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[482142.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[482142.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349da10] >[482142.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349da10] width 1280 pitch 5120 (/4 1280) >[482164.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342b2f0] >[482164.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342b2f0] width 1280 pitch 5120 (/4 1280) >[482201.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156c0] >[482201.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156c0] width 1280 pitch 5120 (/4 1280) >[482201.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365c4b0] >[482201.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365c4b0] width 1280 pitch 5120 (/4 1280) >[482201.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357f110] >[482201.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357f110] width 1280 pitch 5120 (/4 1280) >[482201.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af48b0] >[482201.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af48b0] width 1280 pitch 5120 (/4 1280) >[482203.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0c6e0] >[482203.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0c6e0] width 1280 pitch 5120 (/4 1280) >[482203.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0350] >[482203.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0350] width 1280 pitch 5120 (/4 1280) >[482203.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e9b0] >[482203.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e9b0] width 1280 pitch 5120 (/4 1280) >[482203.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0350] >[482203.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0350] width 1280 pitch 5120 (/4 1280) >[482203.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e9b0] >[482203.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e9b0] width 1280 pitch 5120 (/4 1280) >[482209.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[482209.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[482209.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[482209.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[482209.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[482209.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[482209.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[482209.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[482210.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[482210.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[482210.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0350] >[482210.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0350] width 1280 pitch 5120 (/4 1280) >[482210.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[482210.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[482218.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[482219.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[482219.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[482219.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[482219.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[482219.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[482219.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[482219.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[482220.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[482220.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[482220.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fa510] >[482220.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fa510] width 1280 pitch 5120 (/4 1280) >[482220.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[482220.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[482220.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[482220.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[482220.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0350] >[482220.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0350] width 1280 pitch 5120 (/4 1280) >[482220.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[482220.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[482262.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1380] >[482262.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1380] width 1280 pitch 5120 (/4 1280) >[482262.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0350] >[482262.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0350] width 1280 pitch 5120 (/4 1280) >[482262.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498540] >[482262.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498540] width 1280 pitch 5120 (/4 1280) >[482262.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[482262.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[482863.931] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[482863.931] (II) RADEON(0): Using hsync ranges from config file >[482863.931] (II) RADEON(0): Using vrefresh ranges from config file >[482863.931] (II) RADEON(0): Printing DDC gathered Modelines: >[482863.931] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[482863.931] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[482863.931] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[482863.931] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[482863.931] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[482863.931] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[482863.931] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[482863.931] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[482863.932] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[482863.932] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[482954.555] (II) RADEON(0): RADEONSaveScreen(2) >[482954.555] (II) RADEON(0): RADEONSaveScreen(0) >[483881.969] (II) RADEON(0): RADEONSaveScreen(1) >[483884.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b4e10] >[483884.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b4e10] width 1280 pitch 5120 (/4 1280) >[484515.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595ee0] >[484515.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595ee0] width 1280 pitch 5120 (/4 1280) >[484516.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3596060] >[484516.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3596060] width 1280 pitch 5120 (/4 1280) >[484516.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[484516.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[484516.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[484516.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[484516.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[484516.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[484561.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[484561.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[484561.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[484561.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[484561.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ef80] >[484562.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ef80] width 1280 pitch 5120 (/4 1280) >[484562.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3596060] >[484562.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3596060] width 1280 pitch 5120 (/4 1280) >[484932.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad490] >[484932.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad490] width 1280 pitch 5120 (/4 1280) >[484933.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[484933.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[484933.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[484933.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[484933.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e9840] >[484933.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e9840] width 1280 pitch 5120 (/4 1280) >[484933.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35070] >[484933.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35070] width 1280 pitch 5120 (/4 1280) >[484933.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e9840] >[484933.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e9840] width 1280 pitch 5120 (/4 1280) >[484971.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe880] >[484971.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe880] width 1280 pitch 5120 (/4 1280) >[484971.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eba0] >[484971.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eba0] width 1280 pitch 5120 (/4 1280) >[484971.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad490] >[484971.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad490] width 1280 pitch 5120 (/4 1280) >[484971.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ad490] >[484971.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ad490] width 1280 pitch 5120 (/4 1280) >[485612.111] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[485612.111] (II) RADEON(0): Using hsync ranges from config file >[485612.111] (II) RADEON(0): Using vrefresh ranges from config file >[485612.111] (II) RADEON(0): Printing DDC gathered Modelines: >[485612.111] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[485612.111] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[485612.111] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[485612.111] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[485612.111] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[485612.111] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[485612.111] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[485612.111] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[485612.111] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[485612.111] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[485702.536] (II) RADEON(0): RADEONSaveScreen(2) >[485702.536] (II) RADEON(0): RADEONSaveScreen(0) >[493964.366] (II) RADEON(0): RADEONSaveScreen(1) >[493964.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x347e300] >[493964.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x347e300] width 1280 pitch 5120 (/4 1280) >[493967.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35070] >[493967.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35070] width 1280 pitch 5120 (/4 1280) >[494006.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e49e0] >[494006.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e49e0] width 1280 pitch 5120 (/4 1280) >[494007.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156e0] >[494007.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156e0] width 1280 pitch 5120 (/4 1280) >[494007.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[494007.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[494007.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156e0] >[494007.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156e0] width 1280 pitch 5120 (/4 1280) >[494105.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156e0] >[494105.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156e0] width 1280 pitch 5120 (/4 1280) >[494105.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[494106.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[494106.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babae0] >[494106.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babae0] width 1280 pitch 5120 (/4 1280) >[494106.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba1e40] >[494106.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba1e40] width 1280 pitch 5120 (/4 1280) >[494127.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494127.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494127.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494127.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494127.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[494127.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[494127.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494127.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494127.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[494127.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[494127.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[494127.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[494127.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3642640] >[494127.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3642640] width 1280 pitch 5120 (/4 1280) >[494127.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494128.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494128.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c3470] >[494128.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c3470] width 1280 pitch 5120 (/4 1280) >[494128.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494128.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494128.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[494128.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[494128.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6150] >[494128.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6150] width 1280 pitch 5120 (/4 1280) >[494128.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4f0] >[494128.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4f0] width 1280 pitch 5120 (/4 1280) >[494144.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372d030] >[494144.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372d030] width 1280 pitch 5120 (/4 1280) >[494148.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[494148.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[494149.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a8110] >[494149.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a8110] width 1280 pitch 5120 (/4 1280) >[494164.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593750] >[494164.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593750] width 1280 pitch 5120 (/4 1280) >[494164.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3a00] >[494164.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3a00] width 1280 pitch 5120 (/4 1280) >[494164.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d7090] >[494164.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d7090] width 1280 pitch 5120 (/4 1280) >[494164.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3a00] >[494164.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3a00] width 1280 pitch 5120 (/4 1280) >[494252.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3654ce0] >[494252.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3654ce0] width 1280 pitch 5120 (/4 1280) >[494275.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498a30] >[494275.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498a30] width 1280 pitch 5120 (/4 1280) >[494276.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0670] >[494276.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0670] width 1280 pitch 5120 (/4 1280) >[494276.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c50d0] >[494276.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c50d0] width 1280 pitch 5120 (/4 1280) >[494276.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0670] >[494276.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0670] width 1280 pitch 5120 (/4 1280) >[495093.896] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[495093.896] (II) RADEON(0): Using hsync ranges from config file >[495093.896] (II) RADEON(0): Using vrefresh ranges from config file >[495093.896] (II) RADEON(0): Printing DDC gathered Modelines: >[495093.896] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[495093.896] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[495093.896] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[495093.896] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[495093.896] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[495093.896] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[495093.896] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[495093.896] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[495093.896] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[495093.896] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[497025.535] (II) RADEON(0): RADEONSaveScreen(2) >[497025.535] (II) RADEON(0): RADEONSaveScreen(0) >[497034.797] (II) RADEON(0): RADEONSaveScreen(1) >[497750.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486600] >[497750.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486600] width 1280 pitch 5120 (/4 1280) >[498569.550] (II) RADEON(0): RADEONSaveScreen(2) >[498569.550] (II) RADEON(0): RADEONSaveScreen(0) >[499240.703] (II) RADEON(0): RADEONSaveScreen(1) >[499959.543] (II) RADEON(0): RADEONSaveScreen(2) >[499959.543] (II) RADEON(0): RADEONSaveScreen(0) >[501095.027] (II) RADEON(0): RADEONSaveScreen(1) >[501107.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf9410] >[501107.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf9410] width 1280 pitch 5120 (/4 1280) >[501113.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501114.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501114.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34720c0] >[501114.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34720c0] width 1280 pitch 5120 (/4 1280) >[501114.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be60a0] >[501114.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be60a0] width 1280 pitch 5120 (/4 1280) >[501114.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be66e0] >[501114.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be66e0] width 1280 pitch 5120 (/4 1280) >[501114.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34879b0] >[501114.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34879b0] width 1280 pitch 5120 (/4 1280) >[501114.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d640] >[501114.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d640] width 1280 pitch 5120 (/4 1280) >[501114.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34879b0] >[501114.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34879b0] width 1280 pitch 5120 (/4 1280) >[501114.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d640] >[501114.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d640] width 1280 pitch 5120 (/4 1280) >[501124.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259c10] >[501124.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259c10] width 1280 pitch 5120 (/4 1280) >[501125.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259c10] >[501125.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259c10] width 1280 pitch 5120 (/4 1280) >[501125.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486880] >[501125.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486880] width 1280 pitch 5120 (/4 1280) >[501125.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259c10] >[501125.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259c10] width 1280 pitch 5120 (/4 1280) >[501162.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501162.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501162.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501162.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501162.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501162.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501162.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501162.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501164.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a3100] >[501164.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a3100] width 1280 pitch 5120 (/4 1280) >[501239.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e8b0] >[501239.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e8b0] width 1280 pitch 5120 (/4 1280) >[501239.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501239.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501240.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e8b0] >[501240.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e8b0] width 1280 pitch 5120 (/4 1280) >[501240.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501240.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501241.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ccde0] >[501241.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ccde0] width 1280 pitch 5120 (/4 1280) >[501241.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501241.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501241.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cc8a0] >[501241.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cc8a0] width 1280 pitch 5120 (/4 1280) >[501241.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486880] >[501241.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486880] width 1280 pitch 5120 (/4 1280) >[501451.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3654f00] >[501451.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3654f00] width 1280 pitch 5120 (/4 1280) >[501451.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf36a0] >[501451.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf36a0] width 1280 pitch 5120 (/4 1280) >[501451.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ccde0] >[501451.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ccde0] width 1280 pitch 5120 (/4 1280) >[501451.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501451.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501576.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9f70] >[501576.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9f70] width 1280 pitch 5120 (/4 1280) >[501576.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9f70] >[501576.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9f70] width 1280 pitch 5120 (/4 1280) >[501576.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3595a70] >[501576.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3595a70] width 1280 pitch 5120 (/4 1280) >[501576.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d640] >[501576.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d640] width 1280 pitch 5120 (/4 1280) >[501587.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501587.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501587.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e1c0] >[501587.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e1c0] width 1280 pitch 5120 (/4 1280) >[501587.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3487cf0] >[501587.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3487cf0] width 1280 pitch 5120 (/4 1280) >[501587.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e1c0] >[501587.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e1c0] width 1280 pitch 5120 (/4 1280) >[501650.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36551a0] >[501650.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36551a0] width 1280 pitch 5120 (/4 1280) >[501650.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b6740] >[501650.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b6740] width 1280 pitch 5120 (/4 1280) >[501650.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6530] >[501650.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6530] width 1280 pitch 5120 (/4 1280) >[501650.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362ab10] >[501650.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362ab10] width 1280 pitch 5120 (/4 1280) >[501784.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2a50] >[501784.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2a50] width 1280 pitch 5120 (/4 1280) >[501784.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362ab10] >[501784.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362ab10] width 1280 pitch 5120 (/4 1280) >[501784.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501784.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501784.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362ab10] >[501784.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362ab10] width 1280 pitch 5120 (/4 1280) >[501787.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501787.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501787.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501787.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501787.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501787.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501787.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496530] >[501787.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496530] width 1280 pitch 5120 (/4 1280) >[501789.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501789.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501789.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32484d0] >[501789.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32484d0] width 1280 pitch 5120 (/4 1280) >[501790.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3422c80] >[501790.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3422c80] width 1280 pitch 5120 (/4 1280) >[501790.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2aa0] >[501790.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2aa0] width 1280 pitch 5120 (/4 1280) >[501790.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501790.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501790.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2aa0] >[501790.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2aa0] width 1280 pitch 5120 (/4 1280) >[501798.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501798.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501798.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501798.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501798.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501799.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501799.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501799.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501799.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501799.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501799.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501799.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501799.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653e00] >[501799.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653e00] width 1280 pitch 5120 (/4 1280) >[501799.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653e00] >[501799.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653e00] width 1280 pitch 5120 (/4 1280) >[501799.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653e00] >[501799.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653e00] width 1280 pitch 5120 (/4 1280) >[501799.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653e00] >[501799.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653e00] width 1280 pitch 5120 (/4 1280) >[501799.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501799.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501799.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501800.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501801.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653e00] >[501801.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653e00] width 1280 pitch 5120 (/4 1280) >[501801.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501801.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501801.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8dc0] >[501801.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8dc0] width 1280 pitch 5120 (/4 1280) >[501801.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501801.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501801.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3653130] >[501801.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3653130] width 1280 pitch 5120 (/4 1280) >[501801.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3616370] >[501802.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3616370] width 1280 pitch 5120 (/4 1280) >[501802.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501802.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501802.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3616370] >[501802.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3616370] width 1280 pitch 5120 (/4 1280) >[501827.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501827.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501827.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341a630] >[501827.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341a630] width 1280 pitch 5120 (/4 1280) >[501827.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501827.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501827.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36790a0] >[501827.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36790a0] width 1280 pitch 5120 (/4 1280) >[501828.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36790a0] >[501828.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36790a0] width 1280 pitch 5120 (/4 1280) >[501828.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36790a0] >[501828.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36790a0] width 1280 pitch 5120 (/4 1280) >[501828.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[501828.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[501828.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36790a0] >[501829.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36790a0] width 1280 pitch 5120 (/4 1280) >[501866.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501866.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501867.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501867.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501867.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501867.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501867.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[501867.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[501932.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362a850] >[501932.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362a850] width 1280 pitch 5120 (/4 1280) >[501932.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8b70] >[501932.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8b70] width 1280 pitch 5120 (/4 1280) >[501932.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8b10] >[501932.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8b10] width 1280 pitch 5120 (/4 1280) >[501932.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8b70] >[501932.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8b70] width 1280 pitch 5120 (/4 1280) >[501933.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501933.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501937.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501937.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501937.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b6740] >[501937.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b6740] width 1280 pitch 5120 (/4 1280) >[501938.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[501938.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[501939.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[501939.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[501939.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a8d00] >[501939.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a8d00] width 1280 pitch 5120 (/4 1280) >[501939.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610fe0] >[501939.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610fe0] width 1280 pitch 5120 (/4 1280) >[501984.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3616750] >[501984.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3616750] width 1280 pitch 5120 (/4 1280) >[501984.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abbba0] >[501984.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abbba0] width 1280 pitch 5120 (/4 1280) >[501984.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5080] >[501984.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5080] width 1280 pitch 5120 (/4 1280) >[501984.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abbba0] >[501984.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abbba0] width 1280 pitch 5120 (/4 1280) >[501985.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3616750] >[501985.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3616750] width 1280 pitch 5120 (/4 1280) >[501985.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345fd40] >[501985.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345fd40] width 1280 pitch 5120 (/4 1280) >[501985.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2aa0] >[501985.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2aa0] width 1280 pitch 5120 (/4 1280) >[501986.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345fd40] >[501986.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345fd40] width 1280 pitch 5120 (/4 1280) >[502089.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf7040] >[502089.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf7040] width 1280 pitch 5120 (/4 1280) >[502089.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf7040] >[502089.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf7040] width 1280 pitch 5120 (/4 1280) >[502090.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345fd40] >[502090.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345fd40] width 1280 pitch 5120 (/4 1280) >[502090.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf7040] >[502090.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf7040] width 1280 pitch 5120 (/4 1280) >[502091.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf7040] >[502091.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf7040] width 1280 pitch 5120 (/4 1280) >[502091.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345fd40] >[502091.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345fd40] width 1280 pitch 5120 (/4 1280) >[502091.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644fd0] >[502091.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644fd0] width 1280 pitch 5120 (/4 1280) >[502091.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644fd0] >[502091.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644fd0] width 1280 pitch 5120 (/4 1280) >[502175.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644fd0] >[502175.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644fd0] width 1280 pitch 5120 (/4 1280) >[502175.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[502175.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[502175.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3616320] >[502175.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3616320] width 1280 pitch 5120 (/4 1280) >[502175.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[502175.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[502175.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[502175.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[502176.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593d60] >[502176.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593d60] width 1280 pitch 5120 (/4 1280) >[502176.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f190] >[502176.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f190] width 1280 pitch 5120 (/4 1280) >[502176.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34865e0] >[502176.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34865e0] width 1280 pitch 5120 (/4 1280) >[502721.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[502721.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[502722.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502722.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502722.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502722.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502722.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[502722.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[502722.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502722.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502723.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[502723.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[502723.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[502723.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[502723.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502723.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502723.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36534c0] >[502723.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36534c0] width 1280 pitch 5120 (/4 1280) >[502782.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[502782.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[502782.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[502782.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[502782.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502782.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502782.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[502782.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[502793.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36543d0] >[502793.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36543d0] width 1280 pitch 5120 (/4 1280) >[502825.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366bd00] >[502825.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366bd00] width 1280 pitch 5120 (/4 1280) >[502825.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34963f0] >[502825.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34963f0] width 1280 pitch 5120 (/4 1280) >[502825.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34963f0] >[502825.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34963f0] width 1280 pitch 5120 (/4 1280) >[502825.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34963f0] >[502825.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34963f0] width 1280 pitch 5120 (/4 1280) >[502825.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502825.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502825.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502825.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502825.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502825.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502825.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502825.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502825.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502825.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502826.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502826.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502826.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502826.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502826.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502826.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502826.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31920c0] >[502826.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31920c0] width 1280 pitch 5120 (/4 1280) >[502826.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36156a0] >[502826.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36156a0] width 1280 pitch 5120 (/4 1280) >[502826.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502826.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf96c0] >[502826.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf96c0] width 1280 pitch 5120 (/4 1280) >[502826.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502826.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502827.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf96c0] >[502827.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf96c0] width 1280 pitch 5120 (/4 1280) >[502830.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502830.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502831.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2e30] >[502831.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2e30] width 1280 pitch 5120 (/4 1280) >[502831.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502831.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502831.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2e30] >[502831.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2e30] width 1280 pitch 5120 (/4 1280) >[502833.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2e30] >[502833.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2e30] width 1280 pitch 5120 (/4 1280) >[502833.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502833.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502833.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502833.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502833.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502833.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502838.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34909e0] >[502838.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34909e0] width 1280 pitch 5120 (/4 1280) >[502838.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3191f50] >[502838.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3191f50] width 1280 pitch 5120 (/4 1280) >[502840.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34865b0] >[502840.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34865b0] width 1280 pitch 5120 (/4 1280) >[502840.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34865b0] >[502840.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34865b0] width 1280 pitch 5120 (/4 1280) >[502840.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502840.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502840.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502840.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502849.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502849.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502849.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502849.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502849.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502849.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502849.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502849.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502850.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502850.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502850.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502850.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502850.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[502850.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[502850.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502850.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502853.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3488860] >[502853.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3488860] width 1280 pitch 5120 (/4 1280) >[502853.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e8b0] >[502853.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e8b0] width 1280 pitch 5120 (/4 1280) >[502863.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486460] >[502863.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486460] width 1280 pitch 5120 (/4 1280) >[502863.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2e30] >[502863.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2e30] width 1280 pitch 5120 (/4 1280) >[502870.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2fc0] >[502870.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2fc0] width 1280 pitch 5120 (/4 1280) >[502870.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2f60] >[502870.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2f60] width 1280 pitch 5120 (/4 1280) >[502871.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626b00] >[502871.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626b00] width 1280 pitch 5120 (/4 1280) >[502871.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8720] >[502871.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8720] width 1280 pitch 5120 (/4 1280) >[502879.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d6320] >[502879.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d6320] width 1280 pitch 5120 (/4 1280) >[502879.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3488860] >[502880.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3488860] width 1280 pitch 5120 (/4 1280) >[502884.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6f40] >[502884.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6f40] width 1280 pitch 5120 (/4 1280) >[502884.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e8e0] >[502884.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e8e0] width 1280 pitch 5120 (/4 1280) >[502884.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580260] >[502884.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580260] width 1280 pitch 5120 (/4 1280) >[502884.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e8e0] >[502884.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e8e0] width 1280 pitch 5120 (/4 1280) >[502923.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2aa0] >[502923.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2aa0] width 1280 pitch 5120 (/4 1280) >[502923.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2e30] >[502923.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2e30] width 1280 pitch 5120 (/4 1280) >[502923.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8720] >[502923.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8720] width 1280 pitch 5120 (/4 1280) >[502923.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[502923.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[502924.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486500] >[502924.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486500] width 1280 pitch 5120 (/4 1280) >[503002.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475600] >[503002.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475600] width 1280 pitch 5120 (/4 1280) >[503009.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcb310] >[503009.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcb310] width 1280 pitch 5120 (/4 1280) >[503009.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abb310] >[503009.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abb310] width 1280 pitch 5120 (/4 1280) >[503009.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcb310] >[503009.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcb310] width 1280 pitch 5120 (/4 1280) >[503009.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[503009.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[503460.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[503460.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[503461.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[503461.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[503461.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32afa90] >[503461.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32afa90] width 1280 pitch 5120 (/4 1280) >[503461.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[503461.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[503513.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32aff80] >[503513.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32aff80] width 1280 pitch 5120 (/4 1280) >[503514.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cf00] >[503514.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cf00] width 1280 pitch 5120 (/4 1280) >[503514.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34975d0] >[503514.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34975d0] width 1280 pitch 5120 (/4 1280) >[503514.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3cf00] >[503514.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3cf00] width 1280 pitch 5120 (/4 1280) >[503536.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd04f0] >[503536.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd04f0] width 1280 pitch 5120 (/4 1280) >[503538.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8920] >[503538.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8920] width 1280 pitch 5120 (/4 1280) >[503538.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8920] >[503538.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8920] width 1280 pitch 5120 (/4 1280) >[503538.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eea0] >[503538.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eea0] width 1280 pitch 5120 (/4 1280) >[503538.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8920] >[503538.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8920] width 1280 pitch 5120 (/4 1280) >[503566.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8920] >[503566.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8920] width 1280 pitch 5120 (/4 1280) >[503566.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eea0] >[503566.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eea0] width 1280 pitch 5120 (/4 1280) >[503566.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5170] >[503566.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5170] width 1280 pitch 5120 (/4 1280) >[503566.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34978a0] >[503566.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34978a0] width 1280 pitch 5120 (/4 1280) >[503620.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eea0] >[503620.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eea0] width 1280 pitch 5120 (/4 1280) >[503621.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34978a0] >[503621.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34978a0] width 1280 pitch 5120 (/4 1280) >[503621.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x337eea0] >[503621.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x337eea0] width 1280 pitch 5120 (/4 1280) >[503621.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486550] >[503621.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486550] width 1280 pitch 5120 (/4 1280) >[503621.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475600] >[503621.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475600] width 1280 pitch 5120 (/4 1280) >[503621.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3486550] >[503621.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3486550] width 1280 pitch 5120 (/4 1280) >[504221.768] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[504221.768] (II) RADEON(0): Using hsync ranges from config file >[504221.768] (II) RADEON(0): Using vrefresh ranges from config file >[504221.768] (II) RADEON(0): Printing DDC gathered Modelines: >[504221.768] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[504221.768] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[504221.768] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[504221.768] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[504221.768] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[504221.768] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[504221.768] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[504221.768] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[504221.768] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[504221.768] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[504311.536] (II) RADEON(0): RADEONSaveScreen(2) >[504311.536] (II) RADEON(0): RADEONSaveScreen(0) >[504466.203] (II) RADEON(0): RADEONSaveScreen(1) >[504470.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d310] >[504470.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d310] width 1280 pitch 5120 (/4 1280) >[504573.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d65e0] >[504573.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d65e0] width 1280 pitch 5120 (/4 1280) >[504573.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424ba0] >[504573.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424ba0] width 1280 pitch 5120 (/4 1280) >[504573.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[504574.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[504574.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424ba0] >[504574.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424ba0] width 1280 pitch 5120 (/4 1280) >[505179.390] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[505179.391] (II) RADEON(0): Using hsync ranges from config file >[505179.391] (II) RADEON(0): Using vrefresh ranges from config file >[505179.391] (II) RADEON(0): Printing DDC gathered Modelines: >[505179.391] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[505179.391] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[505179.391] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[505179.391] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[505179.391] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[505179.391] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[505179.391] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[505179.391] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[505179.391] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[505179.391] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[505269.555] (II) RADEON(0): RADEONSaveScreen(2) >[505269.555] (II) RADEON(0): RADEONSaveScreen(0) >[512062.259] (II) RADEON(0): RADEONSaveScreen(1) >[512062.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c099b0] >[512062.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c099b0] width 1280 pitch 5120 (/4 1280) >[512134.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c01880] >[512135.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c01880] width 1280 pitch 5120 (/4 1280) >[512136.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[512136.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[512516.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334bf90] >[512516.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334bf90] width 1280 pitch 5120 (/4 1280) >[512612.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499fe0] >[512612.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499fe0] width 1280 pitch 5120 (/4 1280) >[512613.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36512f0] >[512613.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36512f0] width 1280 pitch 5120 (/4 1280) >[512613.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2a40] >[512613.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2a40] width 1280 pitch 5120 (/4 1280) >[512613.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36512f0] >[512613.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36512f0] width 1280 pitch 5120 (/4 1280) >[512613.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e910] >[512613.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e910] width 1280 pitch 5120 (/4 1280) >[512613.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c109d0] >[512613.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c109d0] width 1280 pitch 5120 (/4 1280) >[512613.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36305a0] >[512613.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36305a0] width 1280 pitch 5120 (/4 1280) >[512620.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3610d80] >[512620.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3610d80] width 1280 pitch 5120 (/4 1280) >[512858.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3429340] >[512858.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3429340] width 1280 pitch 5120 (/4 1280) >[512858.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd750] >[512859.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd750] width 1280 pitch 5120 (/4 1280) >[512859.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3429340] >[512859.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3429340] width 1280 pitch 5120 (/4 1280) >[512859.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd750] >[512859.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd750] width 1280 pitch 5120 (/4 1280) >[512861.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd750] >[512861.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd750] width 1280 pitch 5120 (/4 1280) >[512861.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48040] >[512861.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48040] width 1280 pitch 5120 (/4 1280) >[512861.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34882e0] >[512861.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34882e0] width 1280 pitch 5120 (/4 1280) >[512862.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48040] >[512862.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48040] width 1280 pitch 5120 (/4 1280) >[512971.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593d60] >[512971.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593d60] width 1280 pitch 5120 (/4 1280) >[512971.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593d60] >[512971.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593d60] width 1280 pitch 5120 (/4 1280) >[512971.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8390] >[512971.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8390] width 1280 pitch 5120 (/4 1280) >[512971.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593d60] >[512971.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593d60] width 1280 pitch 5120 (/4 1280) >[512977.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593d60] >[512977.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593d60] width 1280 pitch 5120 (/4 1280) >[512977.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8390] >[512977.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8390] width 1280 pitch 5120 (/4 1280) >[512977.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e250] >[512977.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e250] width 1280 pitch 5120 (/4 1280) >[512977.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8390] >[512977.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8390] width 1280 pitch 5120 (/4 1280) >[513214.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af56a0] >[513214.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af56a0] width 1280 pitch 5120 (/4 1280) >[513214.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363db20] >[513214.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363db20] width 1280 pitch 5120 (/4 1280) >[513214.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08f70] >[513214.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08f70] width 1280 pitch 5120 (/4 1280) >[513214.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3479be0] >[513214.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3479be0] width 1280 pitch 5120 (/4 1280) >[513219.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74ed0] >[513219.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74ed0] width 1280 pitch 5120 (/4 1280) >[513219.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ef10] >[513219.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ef10] width 1280 pitch 5120 (/4 1280) >[513219.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74c50] >[513219.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74c50] width 1280 pitch 5120 (/4 1280) >[513219.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ef10] >[513219.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ef10] width 1280 pitch 5120 (/4 1280) >[513369.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fb200] >[513369.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fb200] width 1280 pitch 5120 (/4 1280) >[513369.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f850] >[513369.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f850] width 1280 pitch 5120 (/4 1280) >[513369.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475d50] >[513369.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475d50] width 1280 pitch 5120 (/4 1280) >[513370.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[513370.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[513370.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0c4e0] >[513370.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0c4e0] width 1280 pitch 5120 (/4 1280) >[513370.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[513370.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[513371.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342a3b0] >[513371.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342a3b0] width 1280 pitch 5120 (/4 1280) >[513371.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0c4e0] >[513371.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0c4e0] width 1280 pitch 5120 (/4 1280) >[513371.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0c4e0] >[513371.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0c4e0] width 1280 pitch 5120 (/4 1280) >[513375.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[513375.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[513375.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf89d0] >[513375.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf89d0] width 1280 pitch 5120 (/4 1280) >[513375.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b42a0] >[513375.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b42a0] width 1280 pitch 5120 (/4 1280) >[513375.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf89d0] >[513375.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf89d0] width 1280 pitch 5120 (/4 1280) >[513376.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac70] >[513376.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac70] width 1280 pitch 5120 (/4 1280) >[513376.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c4d80] >[513376.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c4d80] width 1280 pitch 5120 (/4 1280) >[513376.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370af00] >[513376.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370af00] width 1280 pitch 5120 (/4 1280) >[513376.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c4d80] >[513376.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c4d80] width 1280 pitch 5120 (/4 1280) >[513377.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c4d80] >[513377.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c4d80] width 1280 pitch 5120 (/4 1280) >[513377.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33053f0] >[513377.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33053f0] width 1280 pitch 5120 (/4 1280) >[513377.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb4e0] >[513377.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb4e0] width 1280 pitch 5120 (/4 1280) >[513378.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33053f0] >[513378.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33053f0] width 1280 pitch 5120 (/4 1280) >[513384.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c11840] >[513384.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c11840] width 1280 pitch 5120 (/4 1280) >[513384.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e4e0] >[513384.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e4e0] width 1280 pitch 5120 (/4 1280) >[513395.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3422aa0] >[513395.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3422aa0] width 1280 pitch 5120 (/4 1280) >[513396.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c01880] >[513396.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c01880] width 1280 pitch 5120 (/4 1280) >[513396.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be9050] >[513396.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be9050] width 1280 pitch 5120 (/4 1280) >[513396.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c01880] >[513396.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c01880] width 1280 pitch 5120 (/4 1280) >[513397.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0a910] >[513397.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0a910] width 1280 pitch 5120 (/4 1280) >[513397.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c230e0] >[513397.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c230e0] width 1280 pitch 5120 (/4 1280) >[513439.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f850] >[513439.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f850] width 1280 pitch 5120 (/4 1280) >[513439.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c230e0] >[513439.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c230e0] width 1280 pitch 5120 (/4 1280) >[513439.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3693d40] >[513439.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3693d40] width 1280 pitch 5120 (/4 1280) >[513439.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3498a40] >[513439.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3498a40] width 1280 pitch 5120 (/4 1280) >[513443.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e9b90] >[513443.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e9b90] width 1280 pitch 5120 (/4 1280) >[513443.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e9b90] >[513443.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e9b90] width 1280 pitch 5120 (/4 1280) >[513443.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364dd80] >[513443.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364dd80] width 1280 pitch 5120 (/4 1280) >[513443.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f850] >[513443.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f850] width 1280 pitch 5120 (/4 1280) >[513457.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fb200] >[513457.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fb200] width 1280 pitch 5120 (/4 1280) >[513457.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f850] >[513457.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f850] width 1280 pitch 5120 (/4 1280) >[513457.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c482c0] >[513457.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c482c0] width 1280 pitch 5120 (/4 1280) >[513457.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364f850] >[513457.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364f850] width 1280 pitch 5120 (/4 1280) >[513458.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c482c0] >[513458.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c482c0] width 1280 pitch 5120 (/4 1280) >[513458.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c482c0] >[513458.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c482c0] width 1280 pitch 5120 (/4 1280) >[513459.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda7c0] >[513459.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda7c0] width 1280 pitch 5120 (/4 1280) >[513459.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c482c0] >[513459.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c482c0] width 1280 pitch 5120 (/4 1280) >[513459.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd5ae0] >[513459.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd5ae0] width 1280 pitch 5120 (/4 1280) >[513459.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c482c0] >[513459.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c482c0] width 1280 pitch 5120 (/4 1280) >[513523.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21420] >[513523.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21420] width 1280 pitch 5120 (/4 1280) >[513531.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e200] >[513532.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e200] width 1280 pitch 5120 (/4 1280) >[513534.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0240] >[513534.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0240] width 1280 pitch 5120 (/4 1280) >[513534.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21420] >[513534.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21420] width 1280 pitch 5120 (/4 1280) >[513534.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0240] >[513534.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0240] width 1280 pitch 5120 (/4 1280) >[513534.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21420] >[513534.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21420] width 1280 pitch 5120 (/4 1280) >[513538.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3440] >[513538.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3440] width 1280 pitch 5120 (/4 1280) >[513538.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21420] >[513538.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21420] width 1280 pitch 5120 (/4 1280) >[513538.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[513538.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[513538.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21420] >[513538.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21420] width 1280 pitch 5120 (/4 1280) >[513539.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3481cd0] >[513539.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3481cd0] width 1280 pitch 5120 (/4 1280) >[513539.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c211a0] >[513539.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c211a0] width 1280 pitch 5120 (/4 1280) >[513546.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0a910] >[513546.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0a910] width 1280 pitch 5120 (/4 1280) >[513547.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513547.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513548.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0a910] >[513548.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0a910] width 1280 pitch 5120 (/4 1280) >[513548.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[513548.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[513549.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477060] >[513549.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477060] width 1280 pitch 5120 (/4 1280) >[513550.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bee630] >[513550.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bee630] width 1280 pitch 5120 (/4 1280) >[513550.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdeec0] >[513550.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdeec0] width 1280 pitch 5120 (/4 1280) >[513552.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0a910] >[513552.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0a910] width 1280 pitch 5120 (/4 1280) >[513553.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdeec0] >[513553.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdeec0] width 1280 pitch 5120 (/4 1280) >[513595.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333e900] >[513595.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333e900] width 1280 pitch 5120 (/4 1280) >[513595.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367ebc0] >[513595.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367ebc0] width 1280 pitch 5120 (/4 1280) >[513595.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[513595.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[513596.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[513596.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[513597.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477060] >[513597.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477060] width 1280 pitch 5120 (/4 1280) >[513597.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08d00] >[513597.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08d00] width 1280 pitch 5120 (/4 1280) >[513597.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482da0] >[513597.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482da0] width 1280 pitch 5120 (/4 1280) >[513597.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34797b0] >[513597.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34797b0] width 1280 pitch 5120 (/4 1280) >[513597.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcfd30] >[513597.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcfd30] width 1280 pitch 5120 (/4 1280) >[513598.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513598.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513601.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513601.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513601.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[513601.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[513601.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba48a0] >[513601.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba48a0] width 1280 pitch 5120 (/4 1280) >[513662.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[513662.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[513662.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcfda0] >[513662.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcfda0] width 1280 pitch 5120 (/4 1280) >[513662.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722c80] >[513662.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722c80] width 1280 pitch 5120 (/4 1280) >[513666.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3482740] >[513666.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3482740] width 1280 pitch 5120 (/4 1280) >[513667.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427f00] >[513667.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427f00] width 1280 pitch 5120 (/4 1280) >[513667.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513667.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513667.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427f00] >[513667.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427f00] width 1280 pitch 5120 (/4 1280) >[513678.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebe50] >[513678.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebe50] width 1280 pitch 5120 (/4 1280) >[513678.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513678.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513678.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[513678.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[513678.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[513678.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[513687.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebe50] >[513687.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebe50] width 1280 pitch 5120 (/4 1280) >[513688.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebe50] >[513688.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebe50] width 1280 pitch 5120 (/4 1280) >[513688.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0240] >[513688.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0240] width 1280 pitch 5120 (/4 1280) >[513688.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebe50] >[513688.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebe50] width 1280 pitch 5120 (/4 1280) >[513690.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f000] >[513690.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f000] width 1280 pitch 5120 (/4 1280) >[513690.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebe50] >[513690.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebe50] width 1280 pitch 5120 (/4 1280) >[513698.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34225e0] >[513698.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34225e0] width 1280 pitch 5120 (/4 1280) >[513698.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3473ad0] >[513698.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3473ad0] width 1280 pitch 5120 (/4 1280) >[513698.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91510] >[513698.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91510] width 1280 pitch 5120 (/4 1280) >[513698.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba48a0] >[513698.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba48a0] width 1280 pitch 5120 (/4 1280) >[513725.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475d50] >[513725.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475d50] width 1280 pitch 5120 (/4 1280) >[513725.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475d50] >[513725.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475d50] width 1280 pitch 5120 (/4 1280) >[513725.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91510] >[513726.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91510] width 1280 pitch 5120 (/4 1280) >[513726.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9950] >[513726.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9950] width 1280 pitch 5120 (/4 1280) >[513753.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427f00] >[513753.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427f00] width 1280 pitch 5120 (/4 1280) >[513754.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9950] >[513754.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9950] width 1280 pitch 5120 (/4 1280) >[513754.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33313e0] >[513754.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33313e0] width 1280 pitch 5120 (/4 1280) >[513754.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9950] >[513754.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9950] width 1280 pitch 5120 (/4 1280) >[513810.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3473ad0] >[513810.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3473ad0] width 1280 pitch 5120 (/4 1280) >[513811.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3484660] >[513811.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3484660] width 1280 pitch 5120 (/4 1280) >[513811.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b4820] >[513811.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b4820] width 1280 pitch 5120 (/4 1280) >[513811.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5170] >[513811.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5170] width 1280 pitch 5120 (/4 1280) >[513811.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b4820] >[513811.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b4820] width 1280 pitch 5120 (/4 1280) >[514174.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd8f50] >[514174.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd8f50] width 1280 pitch 5120 (/4 1280) >[514202.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345d750] >[514202.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345d750] width 1280 pitch 5120 (/4 1280) >[514465.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514465.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514466.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[514466.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[514466.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514466.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514466.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[514466.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[514467.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514467.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514467.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[514467.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[514467.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514467.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514467.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[514467.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[514467.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514467.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514467.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[514467.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[514467.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514467.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514468.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca820] >[514468.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca820] width 1280 pitch 5120 (/4 1280) >[514468.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[514468.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[514468.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca820] >[514468.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca820] width 1280 pitch 5120 (/4 1280) >[514478.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345bc60] >[514478.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345bc60] width 1280 pitch 5120 (/4 1280) >[514480.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a3840] >[514480.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a3840] width 1280 pitch 5120 (/4 1280) >[514480.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b930] >[514480.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b930] width 1280 pitch 5120 (/4 1280) >[514480.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bcb70] >[514480.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bcb70] width 1280 pitch 5120 (/4 1280) >[514480.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b930] >[514480.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b930] width 1280 pitch 5120 (/4 1280) >[514480.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bca80] >[514480.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bca80] width 1280 pitch 5120 (/4 1280) >[514480.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330b930] >[514480.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330b930] width 1280 pitch 5120 (/4 1280) >[514481.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaccf0] >[514481.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaccf0] width 1280 pitch 5120 (/4 1280) >[514481.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf16f0] >[514481.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf16f0] width 1280 pitch 5120 (/4 1280) >[514481.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf00e0] >[514481.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf00e0] width 1280 pitch 5120 (/4 1280) >[514501.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4573ba0] >[514501.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4573ba0] width 1280 pitch 5120 (/4 1280) >[514507.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bbec0] >[514507.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bbec0] width 1280 pitch 5120 (/4 1280) >[514507.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5290] >[514507.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5290] width 1280 pitch 5120 (/4 1280) >[514581.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4570190] >[514581.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4570190] width 1280 pitch 5120 (/4 1280) >[514582.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4570190] >[514582.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4570190] width 1280 pitch 5120 (/4 1280) >[514582.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a050] >[514582.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a050] width 1280 pitch 5120 (/4 1280) >[514582.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4570190] >[514582.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4570190] width 1280 pitch 5120 (/4 1280) >[514616.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427f00] >[514616.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427f00] width 1280 pitch 5120 (/4 1280) >[514616.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427f00] >[514616.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427f00] width 1280 pitch 5120 (/4 1280) >[514724.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469dd0] >[514724.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469dd0] width 1280 pitch 5120 (/4 1280) >[514724.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a050] >[514724.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a050] width 1280 pitch 5120 (/4 1280) >[514725.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befed0] >[514725.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befed0] width 1280 pitch 5120 (/4 1280) >[514784.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3483ca0] >[514784.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3483ca0] width 1280 pitch 5120 (/4 1280) >[514816.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd8f50] >[514816.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd8f50] width 1280 pitch 5120 (/4 1280) >[514816.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475d50] >[514816.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475d50] width 1280 pitch 5120 (/4 1280) >[514822.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ba8e0] >[514822.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ba8e0] width 1280 pitch 5120 (/4 1280) >[514824.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5170] >[514824.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5170] width 1280 pitch 5120 (/4 1280) >[514824.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ed10] >[514824.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ed10] width 1280 pitch 5120 (/4 1280) >[514829.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5bf0] >[514829.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5bf0] width 1280 pitch 5120 (/4 1280) >[515008.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34aab30] >[515008.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34aab30] width 1280 pitch 5120 (/4 1280) >[515008.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd8f50] >[515008.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd8f50] width 1280 pitch 5120 (/4 1280) >[515008.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5de80] >[515008.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5de80] width 1280 pitch 5120 (/4 1280) >[515008.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c109d0] >[515008.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c109d0] width 1280 pitch 5120 (/4 1280) >[515430.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0f90] >[515430.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0f90] width 1280 pitch 5120 (/4 1280) >[515432.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515432.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515432.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c542d0] >[515432.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c542d0] width 1280 pitch 5120 (/4 1280) >[515432.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c542d0] >[515432.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c542d0] width 1280 pitch 5120 (/4 1280) >[515439.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515439.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515439.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515439.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515441.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0470] >[515441.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0470] width 1280 pitch 5120 (/4 1280) >[515441.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c542d0] >[515441.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c542d0] width 1280 pitch 5120 (/4 1280) >[515441.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515441.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515441.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0470] >[515441.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0470] width 1280 pitch 5120 (/4 1280) >[515441.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515441.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515441.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0470] >[515441.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0470] width 1280 pitch 5120 (/4 1280) >[515441.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515441.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515441.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0470] >[515441.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0470] width 1280 pitch 5120 (/4 1280) >[515441.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515441.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515442.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515442.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515444.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c542d0] >[515444.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c542d0] width 1280 pitch 5120 (/4 1280) >[515444.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515444.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515445.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515445.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515448.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515448.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515448.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515448.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515449.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea650] >[515449.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea650] width 1280 pitch 5120 (/4 1280) >[515449.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3467ce0] >[515449.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3467ce0] width 1280 pitch 5120 (/4 1280) >[515449.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf5290] >[515449.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf5290] width 1280 pitch 5120 (/4 1280) >[515450.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3467ce0] >[515450.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3467ce0] width 1280 pitch 5120 (/4 1280) >[515451.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9030] >[515451.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9030] width 1280 pitch 5120 (/4 1280) >[515451.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456ee10] >[515451.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456ee10] width 1280 pitch 5120 (/4 1280) >[515451.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bac540] >[515451.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bac540] width 1280 pitch 5120 (/4 1280) >[515451.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d380] >[515451.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d380] width 1280 pitch 5120 (/4 1280) >[515451.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34693e0] >[515451.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34693e0] width 1280 pitch 5120 (/4 1280) >[515451.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d380] >[515451.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d380] width 1280 pitch 5120 (/4 1280) >[515451.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d380] >[515451.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d380] width 1280 pitch 5120 (/4 1280) >[515451.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4572240] >[515451.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4572240] width 1280 pitch 5120 (/4 1280) >[515451.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d380] >[515451.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d380] width 1280 pitch 5120 (/4 1280) >[515486.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff5c0] >[515486.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff5c0] width 1280 pitch 5120 (/4 1280) >[515488.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515488.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515488.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff720] >[515488.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff720] width 1280 pitch 5120 (/4 1280) >[515488.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457e850] >[515488.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457e850] width 1280 pitch 5120 (/4 1280) >[515508.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc1f40] >[515508.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc1f40] width 1280 pitch 5120 (/4 1280) >[515510.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515510.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515510.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bd1d0] >[515510.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bd1d0] width 1280 pitch 5120 (/4 1280) >[515510.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4580260] >[515510.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4580260] width 1280 pitch 5120 (/4 1280) >[515538.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4add960] >[515538.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4add960] width 1280 pitch 5120 (/4 1280) >[515539.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4add960] >[515539.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4add960] width 1280 pitch 5120 (/4 1280) >[515540.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2230] >[515540.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2230] width 1280 pitch 5120 (/4 1280) >[515540.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3460720] >[515540.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3460720] width 1280 pitch 5120 (/4 1280) >[515619.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4ad0] >[515619.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4ad0] width 1280 pitch 5120 (/4 1280) >[515623.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adbdd0] >[515623.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adbdd0] width 1280 pitch 5120 (/4 1280) >[515623.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc22d0] >[515623.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc22d0] width 1280 pitch 5120 (/4 1280) >[515623.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bac540] >[515623.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bac540] width 1280 pitch 5120 (/4 1280) >[515623.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc22d0] >[515623.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc22d0] width 1280 pitch 5120 (/4 1280) >[515623.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c232b0] >[515623.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c232b0] width 1280 pitch 5120 (/4 1280) >[515635.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457fc00] >[515635.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457fc00] width 1280 pitch 5120 (/4 1280) >[515636.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515636.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515636.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c91140] >[515636.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c91140] width 1280 pitch 5120 (/4 1280) >[515636.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326b30] >[515636.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326b30] width 1280 pitch 5120 (/4 1280) >[515637.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457fc00] >[515637.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457fc00] width 1280 pitch 5120 (/4 1280) >[515638.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74b30] >[515638.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74b30] width 1280 pitch 5120 (/4 1280) >[516616.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de050] >[516616.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de050] width 1280 pitch 5120 (/4 1280) >[516990.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4add370] >[516990.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4add370] width 1280 pitch 5120 (/4 1280) >[516990.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0240] >[516990.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0240] width 1280 pitch 5120 (/4 1280) >[517189.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341bba0] >[517189.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341bba0] width 1280 pitch 5120 (/4 1280) >[517189.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[517189.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[517189.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[517189.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[517189.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a3ee0] >[517189.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a3ee0] width 1280 pitch 5120 (/4 1280) >[517190.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a260] >[517190.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a260] width 1280 pitch 5120 (/4 1280) >[517190.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f1cd0] >[517190.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f1cd0] width 1280 pitch 5120 (/4 1280) >[517190.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1ad0] >[517190.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1ad0] width 1280 pitch 5120 (/4 1280) >[517190.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3588510] >[517190.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3588510] width 1280 pitch 5120 (/4 1280) >[517190.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adbad0] >[517190.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adbad0] width 1280 pitch 5120 (/4 1280) >[517190.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adbdd0] >[517190.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adbdd0] width 1280 pitch 5120 (/4 1280) >[517196.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457fdb0] >[517196.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457fdb0] width 1280 pitch 5120 (/4 1280) >[517210.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fe530] >[517210.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fe530] width 1280 pitch 5120 (/4 1280) >[517210.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[517210.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[517210.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[517210.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[517210.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[517210.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34940b0] >[517210.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34940b0] width 1280 pitch 5120 (/4 1280) >[517210.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64d00] >[517210.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64d00] width 1280 pitch 5120 (/4 1280) >[520806.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b97a40] >[520806.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b97a40] width 1280 pitch 5120 (/4 1280) >[530956.516] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[530956.516] (II) RADEON(0): Using hsync ranges from config file >[530956.516] (II) RADEON(0): Using vrefresh ranges from config file >[530956.516] (II) RADEON(0): Printing DDC gathered Modelines: >[530956.516] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[530956.516] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[530956.516] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[530956.516] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[530956.516] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[530956.516] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[530956.516] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[530956.516] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[530956.516] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[530956.516] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[531046.551] (II) RADEON(0): RADEONSaveScreen(2) >[531046.551] (II) RADEON(0): RADEONSaveScreen(0) >[532097.374] (II) RADEON(0): RADEONSaveScreen(1) >[551519.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0080] >[551519.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0080] width 1280 pitch 5120 (/4 1280) >[551522.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365c210] >[551522.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365c210] width 1280 pitch 5120 (/4 1280) >[551522.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30d0f70] >[551522.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30d0f70] width 1280 pitch 5120 (/4 1280) >[551522.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365bf70] >[551522.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365bf70] width 1280 pitch 5120 (/4 1280) >[551523.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3f40] >[551523.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3f40] width 1280 pitch 5120 (/4 1280) >[551523.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[551523.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[551523.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359fdc0] >[551523.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359fdc0] width 1280 pitch 5120 (/4 1280) >[551523.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33562a0] >[551523.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33562a0] width 1280 pitch 5120 (/4 1280) >[551523.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359fdc0] >[551523.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359fdc0] width 1280 pitch 5120 (/4 1280) >[551526.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362cfe0] >[551526.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362cfe0] width 1280 pitch 5120 (/4 1280) >[551526.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3478a00] >[551526.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3478a00] width 1280 pitch 5120 (/4 1280) >[551526.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b68e0] >[551526.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b68e0] width 1280 pitch 5120 (/4 1280) >[551526.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[551526.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[551669.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b6a0] >[551669.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b6a0] width 1280 pitch 5120 (/4 1280) >[554498.761] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[554498.761] (II) RADEON(0): Using hsync ranges from config file >[554498.761] (II) RADEON(0): Using vrefresh ranges from config file >[554498.761] (II) RADEON(0): Printing DDC gathered Modelines: >[554498.761] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[554498.761] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[554498.761] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[554498.761] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[554498.761] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[554498.761] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[554498.761] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[554498.761] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[554498.761] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[554498.761] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[554588.553] (II) RADEON(0): RADEONSaveScreen(2) >[554588.554] (II) RADEON(0): RADEONSaveScreen(0) >[554632.549] (II) RADEON(0): RADEONSaveScreen(1) >[555996.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aae860] >[555996.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aae860] width 1280 pitch 5120 (/4 1280) >[556461.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b8a20] >[556461.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b8a20] width 1280 pitch 5120 (/4 1280) >[556463.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d010] >[556463.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d010] width 1280 pitch 5120 (/4 1280) >[556463.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[556463.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[556463.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d010] >[556463.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d010] width 1280 pitch 5120 (/4 1280) >[556463.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0700] >[556463.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0700] width 1280 pitch 5120 (/4 1280) >[556511.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253430] >[556511.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253430] width 1280 pitch 5120 (/4 1280) >[556511.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556511.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c2c60] >[556511.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c2c60] width 1280 pitch 5120 (/4 1280) >[556511.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345e610] >[556511.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345e610] width 1280 pitch 5120 (/4 1280) >[556513.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4bb0] >[556513.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4bb0] width 1280 pitch 5120 (/4 1280) >[556513.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b2c00] >[556513.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b2c00] width 1280 pitch 5120 (/4 1280) >[556513.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f4bb0] >[556513.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f4bb0] width 1280 pitch 5120 (/4 1280) >[556515.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3141420] >[556515.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3141420] width 1280 pitch 5120 (/4 1280) >[556524.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331d5f0] >[556524.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331d5f0] width 1280 pitch 5120 (/4 1280) >[556529.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c563a0] >[556529.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c563a0] width 1280 pitch 5120 (/4 1280) >[556529.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e8cf0] >[556529.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e8cf0] width 1280 pitch 5120 (/4 1280) >[556529.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357a780] >[556529.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357a780] width 1280 pitch 5120 (/4 1280) >[556529.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33419c0] >[556529.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33419c0] width 1280 pitch 5120 (/4 1280) >[556531.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325fc00] >[556531.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325fc00] width 1280 pitch 5120 (/4 1280) >[556531.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90660] >[556531.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90660] width 1280 pitch 5120 (/4 1280) >[556531.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3492050] >[556531.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3492050] width 1280 pitch 5120 (/4 1280) >[556536.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32626d0] >[556536.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32626d0] width 1280 pitch 5120 (/4 1280) >[556536.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3732f20] >[556536.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3732f20] width 1280 pitch 5120 (/4 1280) >[556536.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360b6c0] >[556536.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360b6c0] width 1280 pitch 5120 (/4 1280) >[556536.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a2c0] >[556536.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a2c0] width 1280 pitch 5120 (/4 1280) >[556536.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358a2c0] >[556536.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358a2c0] width 1280 pitch 5120 (/4 1280) >[556536.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e8f0] >[556536.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e8f0] width 1280 pitch 5120 (/4 1280) >[556536.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20890] >[556536.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20890] width 1280 pitch 5120 (/4 1280) >[556536.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c208f0] >[556536.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c208f0] width 1280 pitch 5120 (/4 1280) >[556536.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20890] >[556536.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20890] width 1280 pitch 5120 (/4 1280) >[556536.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c208f0] >[556536.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c208f0] width 1280 pitch 5120 (/4 1280) >[556536.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20890] >[556536.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20890] width 1280 pitch 5120 (/4 1280) >[556540.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369a310] >[556540.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369a310] width 1280 pitch 5120 (/4 1280) >[556540.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340810] >[556540.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340810] width 1280 pitch 5120 (/4 1280) >[556540.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556540.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556540.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340810] >[556540.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340810] width 1280 pitch 5120 (/4 1280) >[556540.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556540.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556540.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340810] >[556540.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340810] width 1280 pitch 5120 (/4 1280) >[556540.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556540.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556540.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340810] >[556540.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340810] width 1280 pitch 5120 (/4 1280) >[556540.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556540.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556540.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3340810] >[556540.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3340810] width 1280 pitch 5120 (/4 1280) >[556540.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556540.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556541.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369a310] >[556541.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369a310] width 1280 pitch 5120 (/4 1280) >[556541.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c07820] >[556541.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c07820] width 1280 pitch 5120 (/4 1280) >[556541.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a390] >[556541.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a390] width 1280 pitch 5120 (/4 1280) >[556541.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c24a0] >[556542.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c24a0] width 1280 pitch 5120 (/4 1280) >[556542.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338f600] >[556542.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338f600] width 1280 pitch 5120 (/4 1280) >[556542.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3608b50] >[556542.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3608b50] width 1280 pitch 5120 (/4 1280) >[556542.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a340] >[556542.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a340] width 1280 pitch 5120 (/4 1280) >[556542.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca4ff0] >[556542.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca4ff0] width 1280 pitch 5120 (/4 1280) >[556542.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c24a0] >[556542.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c24a0] width 1280 pitch 5120 (/4 1280) >[556551.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b0e30] >[556551.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b0e30] width 1280 pitch 5120 (/4 1280) >[556720.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33408b0] >[556720.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33408b0] width 1280 pitch 5120 (/4 1280) >[556720.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556720.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556720.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c24a0] >[556720.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c24a0] width 1280 pitch 5120 (/4 1280) >[556720.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556720.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556720.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33408b0] >[556720.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33408b0] width 1280 pitch 5120 (/4 1280) >[556720.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556720.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556720.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c24a0] >[556720.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c24a0] width 1280 pitch 5120 (/4 1280) >[556720.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556720.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556720.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556720.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556720.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358b830] >[556720.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358b830] width 1280 pitch 5120 (/4 1280) >[556720.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556720.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556721.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556721.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556721.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5d80] >[556721.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5d80] width 1280 pitch 5120 (/4 1280) >[556721.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556721.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556721.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5d80] >[556721.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5d80] width 1280 pitch 5120 (/4 1280) >[556721.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374a920] >[556721.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374a920] width 1280 pitch 5120 (/4 1280) >[556722.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ed690] >[556722.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ed690] width 1280 pitch 5120 (/4 1280) >[556722.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3705d30] >[556722.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3705d30] width 1280 pitch 5120 (/4 1280) >[556722.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3587160] >[556722.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3587160] width 1280 pitch 5120 (/4 1280) >[556723.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3242300] >[556723.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3242300] width 1280 pitch 5120 (/4 1280) >[556723.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3369960] >[556723.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3369960] width 1280 pitch 5120 (/4 1280) >[556723.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556723.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[556723.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[556723.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556723.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[556723.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[556723.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556723.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[556723.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[556723.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556723.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[556723.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[556723.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556723.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3313f60] >[556723.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3313f60] width 1280 pitch 5120 (/4 1280) >[556723.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3395fd0] >[556723.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3395fd0] width 1280 pitch 5120 (/4 1280) >[556726.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5620] >[556726.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5620] width 1280 pitch 5120 (/4 1280) >[556727.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c50c0] >[556727.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c50c0] width 1280 pitch 5120 (/4 1280) >[556728.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cfa40] >[556728.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cfa40] width 1280 pitch 5120 (/4 1280) >[556728.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f5c50] >[556728.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f5c50] width 1280 pitch 5120 (/4 1280) >[556730.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457fdb0] >[556730.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457fdb0] width 1280 pitch 5120 (/4 1280) >[556731.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b68e0] >[556731.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b68e0] width 1280 pitch 5120 (/4 1280) >[556731.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[556731.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[556731.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[556731.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[556731.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[556731.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[556731.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[556731.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[556731.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[556731.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[556731.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c713f0] >[556731.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c713f0] width 1280 pitch 5120 (/4 1280) >[556731.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20540] >[556731.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20540] width 1280 pitch 5120 (/4 1280) >[556731.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b1c80] >[556731.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b1c80] width 1280 pitch 5120 (/4 1280) >[556731.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6bb0] >[556731.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6bb0] width 1280 pitch 5120 (/4 1280) >[556901.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331c390] >[556901.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331c390] width 1280 pitch 5120 (/4 1280) >[556901.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cdeb0] >[556901.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cdeb0] width 1280 pitch 5120 (/4 1280) >[556901.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c30c20] >[556901.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c30c20] width 1280 pitch 5120 (/4 1280) >[556901.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d8470] >[556901.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d8470] width 1280 pitch 5120 (/4 1280) >[556901.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3040] >[556901.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3040] width 1280 pitch 5120 (/4 1280) >[556901.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3321aa0] >[556901.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3321aa0] width 1280 pitch 5120 (/4 1280) >[556902.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3321aa0] >[556902.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3321aa0] width 1280 pitch 5120 (/4 1280) >[556902.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709ba0] >[556902.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709ba0] width 1280 pitch 5120 (/4 1280) >[556902.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3321aa0] >[556902.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3321aa0] width 1280 pitch 5120 (/4 1280) >[556902.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709ba0] >[556902.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709ba0] width 1280 pitch 5120 (/4 1280) >[556902.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3321aa0] >[556902.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3321aa0] width 1280 pitch 5120 (/4 1280) >[556902.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709ba0] >[556902.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709ba0] width 1280 pitch 5120 (/4 1280) >[556902.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[556902.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[556902.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709ba0] >[556902.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709ba0] width 1280 pitch 5120 (/4 1280) >[556902.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[556902.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[556902.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709ba0] >[556902.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709ba0] width 1280 pitch 5120 (/4 1280) >[556902.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[556902.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[556902.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[556902.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[557048.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[557048.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[557048.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3716090] >[557048.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3716090] width 1280 pitch 5120 (/4 1280) >[557049.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35afbb0] >[557049.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35afbb0] width 1280 pitch 5120 (/4 1280) >[557049.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3359850] >[557049.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3359850] width 1280 pitch 5120 (/4 1280) >[557049.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3496040] >[557049.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3496040] width 1280 pitch 5120 (/4 1280) >[557073.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35afbb0] >[557073.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35afbb0] width 1280 pitch 5120 (/4 1280) >[557073.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35afbb0] >[557073.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35afbb0] width 1280 pitch 5120 (/4 1280) >[557074.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163750] >[557074.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163750] width 1280 pitch 5120 (/4 1280) >[557074.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163750] >[557074.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163750] width 1280 pitch 5120 (/4 1280) >[557074.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3581050] >[557074.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3581050] width 1280 pitch 5120 (/4 1280) >[557074.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a6690] >[557074.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a6690] width 1280 pitch 5120 (/4 1280) >[557074.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebe40] >[557074.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebe40] width 1280 pitch 5120 (/4 1280) >[557074.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a6690] >[557074.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a6690] width 1280 pitch 5120 (/4 1280) >[557074.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebe40] >[557074.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebe40] width 1280 pitch 5120 (/4 1280) >[557074.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a6690] >[557074.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a6690] width 1280 pitch 5120 (/4 1280) >[557074.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebe40] >[557074.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebe40] width 1280 pitch 5120 (/4 1280) >[557076.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[557076.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[557076.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebe40] >[557076.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebe40] width 1280 pitch 5120 (/4 1280) >[557076.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[557076.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[557077.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a66b0] >[557077.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a66b0] width 1280 pitch 5120 (/4 1280) >[557078.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163750] >[557079.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163750] width 1280 pitch 5120 (/4 1280) >[557079.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20840] >[557079.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20840] width 1280 pitch 5120 (/4 1280) >[557079.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb2950] >[557079.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb2950] width 1280 pitch 5120 (/4 1280) >[557079.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4589260] >[557079.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4589260] width 1280 pitch 5120 (/4 1280) >[557079.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341c5a0] >[557079.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341c5a0] width 1280 pitch 5120 (/4 1280) >[557079.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35df850] >[557079.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35df850] width 1280 pitch 5120 (/4 1280) >[557079.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c3960] >[557079.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c3960] width 1280 pitch 5120 (/4 1280) >[557079.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362eef0] >[557079.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362eef0] width 1280 pitch 5120 (/4 1280) >[557079.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362eef0] >[557079.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362eef0] width 1280 pitch 5120 (/4 1280) >[557099.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20840] >[557099.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20840] width 1280 pitch 5120 (/4 1280) >[557102.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255b30] >[557102.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255b30] width 1280 pitch 5120 (/4 1280) >[557102.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3ec0] >[557102.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3ec0] width 1280 pitch 5120 (/4 1280) >[557102.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3ec0] >[557102.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3ec0] width 1280 pitch 5120 (/4 1280) >[557102.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3ec0] >[557102.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3ec0] width 1280 pitch 5120 (/4 1280) >[557102.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3ec0] >[557102.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3ec0] width 1280 pitch 5120 (/4 1280) >[557102.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557102.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557102.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3ec0] >[557102.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3ec0] width 1280 pitch 5120 (/4 1280) >[557102.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360e460] >[557102.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360e460] width 1280 pitch 5120 (/4 1280) >[557108.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3571490] >[557108.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3571490] width 1280 pitch 5120 (/4 1280) >[557111.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717e30] >[557111.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717e30] width 1280 pitch 5120 (/4 1280) >[557111.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ceb0] >[557111.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ceb0] width 1280 pitch 5120 (/4 1280) >[557111.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557111.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557111.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335ceb0] >[557111.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335ceb0] width 1280 pitch 5120 (/4 1280) >[557318.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d65e0] >[557318.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d65e0] width 1280 pitch 5120 (/4 1280) >[557318.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d65e0] >[557318.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d65e0] width 1280 pitch 5120 (/4 1280) >[557318.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324abf0] >[557318.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324abf0] width 1280 pitch 5120 (/4 1280) >[557445.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c51e0] >[557445.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c51e0] width 1280 pitch 5120 (/4 1280) >[557445.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324abf0] >[557445.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324abf0] width 1280 pitch 5120 (/4 1280) >[557445.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557445.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557445.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a1bb0] >[557445.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a1bb0] width 1280 pitch 5120 (/4 1280) >[557446.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324abf0] >[557446.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324abf0] width 1280 pitch 5120 (/4 1280) >[557446.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324abf0] >[557446.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324abf0] width 1280 pitch 5120 (/4 1280) >[557446.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557446.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557446.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35afbb0] >[557446.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35afbb0] width 1280 pitch 5120 (/4 1280) >[557446.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369c0e0] >[557446.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369c0e0] width 1280 pitch 5120 (/4 1280) >[557446.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c51e0] >[557446.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c51e0] width 1280 pitch 5120 (/4 1280) >[557508.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630a40] >[557508.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630a40] width 1280 pitch 5120 (/4 1280) >[557508.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630a40] >[557508.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630a40] width 1280 pitch 5120 (/4 1280) >[557508.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c8a40] >[557508.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c8a40] width 1280 pitch 5120 (/4 1280) >[557529.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c25520] >[557529.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c25520] width 1280 pitch 5120 (/4 1280) >[557529.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee850] >[557529.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee850] width 1280 pitch 5120 (/4 1280) >[557530.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1baf0] >[557530.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1baf0] width 1280 pitch 5120 (/4 1280) >[557530.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x360e460] >[557530.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x360e460] width 1280 pitch 5120 (/4 1280) >[557534.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3587220] >[557534.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3587220] width 1280 pitch 5120 (/4 1280) >[557534.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c51e0] >[557534.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c51e0] width 1280 pitch 5120 (/4 1280) >[557699.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee850] >[557699.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee850] width 1280 pitch 5120 (/4 1280) >[557699.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aebda0] >[557699.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aebda0] width 1280 pitch 5120 (/4 1280) >[557699.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c5130] >[557699.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c5130] width 1280 pitch 5120 (/4 1280) >[557790.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ad80] >[557790.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ad80] width 1280 pitch 5120 (/4 1280) >[557791.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d65e0] >[557791.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d65e0] width 1280 pitch 5120 (/4 1280) >[557884.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e890] >[557884.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e890] width 1280 pitch 5120 (/4 1280) >[557884.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca1b40] >[557884.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca1b40] width 1280 pitch 5120 (/4 1280) >[558185.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ee850] >[558185.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ee850] width 1280 pitch 5120 (/4 1280) >[558185.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23970] >[558185.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23970] width 1280 pitch 5120 (/4 1280) >[558292.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[558292.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[558338.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5c90] >[558338.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5c90] width 1280 pitch 5120 (/4 1280) >[558338.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cbc00] >[558338.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cbc00] width 1280 pitch 5120 (/4 1280) >[558338.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5c90] >[558338.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5c90] width 1280 pitch 5120 (/4 1280) >[558338.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[558338.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[558338.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ede30] >[558338.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ede30] width 1280 pitch 5120 (/4 1280) >[558338.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[558338.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[558338.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96000] >[558338.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96000] width 1280 pitch 5120 (/4 1280) >[558338.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[558338.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[558338.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8d30] >[558338.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8d30] width 1280 pitch 5120 (/4 1280) >[558339.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca730] >[558339.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca730] width 1280 pitch 5120 (/4 1280) >[558339.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8230] >[558339.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8230] width 1280 pitch 5120 (/4 1280) >[558339.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717ed0] >[558339.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717ed0] width 1280 pitch 5120 (/4 1280) >[558818.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ae970] >[558818.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ae970] width 1280 pitch 5120 (/4 1280) >[558818.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3360250] >[558818.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3360250] width 1280 pitch 5120 (/4 1280) >[558819.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36db840] >[558819.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36db840] width 1280 pitch 5120 (/4 1280) >[558819.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ab80] >[558819.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ab80] width 1280 pitch 5120 (/4 1280) >[558827.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35810f0] >[558827.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35810f0] width 1280 pitch 5120 (/4 1280) >[558827.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6150] >[558827.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6150] width 1280 pitch 5120 (/4 1280) >[558829.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709e40] >[558829.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709e40] width 1280 pitch 5120 (/4 1280) >[558829.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709e40] >[558829.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709e40] width 1280 pitch 5120 (/4 1280) >[558832.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336fe30] >[558832.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336fe30] width 1280 pitch 5120 (/4 1280) >[558833.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3655210] >[558833.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3655210] width 1280 pitch 5120 (/4 1280) >[558833.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2a10] >[558833.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2a10] width 1280 pitch 5120 (/4 1280) >[558835.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2a10] >[558835.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2a10] width 1280 pitch 5120 (/4 1280) >[558835.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be9e90] >[558835.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be9e90] width 1280 pitch 5120 (/4 1280) >[558835.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365cf80] >[558835.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365cf80] width 1280 pitch 5120 (/4 1280) >[558835.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ab80] >[558835.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ab80] width 1280 pitch 5120 (/4 1280) >[558874.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[558874.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[558874.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[558874.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[558886.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[558886.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[558886.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ae970] >[558886.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ae970] width 1280 pitch 5120 (/4 1280) >[558886.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36567a0] >[558886.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36567a0] width 1280 pitch 5120 (/4 1280) >[558886.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[558886.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[558895.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3655210] >[558895.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3655210] width 1280 pitch 5120 (/4 1280) >[558895.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[558895.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[558900.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca82f0] >[558900.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca82f0] width 1280 pitch 5120 (/4 1280) >[558900.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362c2c0] >[558900.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362c2c0] width 1280 pitch 5120 (/4 1280) >[558907.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0c10] >[558907.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0c10] width 1280 pitch 5120 (/4 1280) >[558907.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363ffa0] >[558907.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363ffa0] width 1280 pitch 5120 (/4 1280) >[558922.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3155600] >[558922.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3155600] width 1280 pitch 5120 (/4 1280) >[558922.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3676820] >[558922.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3676820] width 1280 pitch 5120 (/4 1280) >[558922.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365cf80] >[558922.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365cf80] width 1280 pitch 5120 (/4 1280) >[558922.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31416c0] >[558922.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31416c0] width 1280 pitch 5120 (/4 1280) >[558937.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8ae0] >[558937.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8ae0] width 1280 pitch 5120 (/4 1280) >[558937.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363ffa0] >[558937.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363ffa0] width 1280 pitch 5120 (/4 1280) >[558945.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d7e0] >[558945.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d7e0] width 1280 pitch 5120 (/4 1280) >[558945.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[558945.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[558945.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32fbc90] >[558945.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32fbc90] width 1280 pitch 5120 (/4 1280) >[558946.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37220c0] >[558946.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37220c0] width 1280 pitch 5120 (/4 1280) >[558950.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d7e0] >[558950.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d7e0] width 1280 pitch 5120 (/4 1280) >[558950.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257bdc0] >[558950.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257bdc0] width 1280 pitch 5120 (/4 1280) >[558957.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3671730] >[558957.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3671730] width 1280 pitch 5120 (/4 1280) >[558957.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d7e0] >[558957.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d7e0] width 1280 pitch 5120 (/4 1280) >[558957.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e490] >[558957.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e490] width 1280 pitch 5120 (/4 1280) >[558957.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ab80] >[558957.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ab80] width 1280 pitch 5120 (/4 1280) >[558969.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d7e0] >[558969.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d7e0] width 1280 pitch 5120 (/4 1280) >[558969.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257bdc0] >[558969.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257bdc0] width 1280 pitch 5120 (/4 1280) >[558980.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea140] >[558980.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea140] width 1280 pitch 5120 (/4 1280) >[558980.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b0c10] >[558980.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b0c10] width 1280 pitch 5120 (/4 1280) >[558980.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257bdc0] >[558980.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257bdc0] width 1280 pitch 5120 (/4 1280) >[558980.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a4cb0] >[558980.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a4cb0] width 1280 pitch 5120 (/4 1280) >[559015.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257bdc0] >[559015.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257bdc0] width 1280 pitch 5120 (/4 1280) >[559015.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x257bdc0] >[559015.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x257bdc0] width 1280 pitch 5120 (/4 1280) >[559036.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c5240] >[559036.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c5240] width 1280 pitch 5120 (/4 1280) >[559036.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3090] >[559036.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3090] width 1280 pitch 5120 (/4 1280) >[559036.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36552b0] >[559036.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36552b0] width 1280 pitch 5120 (/4 1280) >[559036.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371c990] >[559036.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371c990] width 1280 pitch 5120 (/4 1280) >[559151.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5ac0] >[559151.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5ac0] width 1280 pitch 5120 (/4 1280) >[559156.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb730] >[559156.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb730] width 1280 pitch 5120 (/4 1280) >[559156.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9e40] >[559156.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9e40] width 1280 pitch 5120 (/4 1280) >[559156.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3423170] >[559156.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3423170] width 1280 pitch 5120 (/4 1280) >[559156.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cb130] >[559156.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cb130] width 1280 pitch 5120 (/4 1280) >[559454.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127200] >[559454.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127200] width 1280 pitch 5120 (/4 1280) >[559454.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54a70] >[559454.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54a70] width 1280 pitch 5120 (/4 1280) >[559454.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361efb0] >[559454.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361efb0] width 1280 pitch 5120 (/4 1280) >[559454.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54a70] >[559454.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54a70] width 1280 pitch 5120 (/4 1280) >[559464.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a840] >[559464.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a840] width 1280 pitch 5120 (/4 1280) >[559464.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127200] >[559464.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127200] width 1280 pitch 5120 (/4 1280) >[559464.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04490] >[559464.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04490] width 1280 pitch 5120 (/4 1280) >[559464.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3a840] >[559464.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3a840] width 1280 pitch 5120 (/4 1280) >[559498.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3308030] >[559498.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3308030] width 1280 pitch 5120 (/4 1280) >[559498.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127200] >[559498.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127200] width 1280 pitch 5120 (/4 1280) >[559498.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abca70] >[559498.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abca70] width 1280 pitch 5120 (/4 1280) >[559498.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb200] >[559498.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb200] width 1280 pitch 5120 (/4 1280) >[559527.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f3d0] >[559527.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f3d0] width 1280 pitch 5120 (/4 1280) >[559527.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb200] >[559527.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb200] width 1280 pitch 5120 (/4 1280) >[559527.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127200] >[559527.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127200] width 1280 pitch 5120 (/4 1280) >[559527.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f3d0] >[559527.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f3d0] width 1280 pitch 5120 (/4 1280) >[559536.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3127200] >[559536.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3127200] width 1280 pitch 5120 (/4 1280) >[559536.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ad370] >[559536.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ad370] width 1280 pitch 5120 (/4 1280) >[559566.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f290] >[559566.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f290] width 1280 pitch 5120 (/4 1280) >[559566.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ce430] >[559567.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ce430] width 1280 pitch 5120 (/4 1280) >[559589.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b980] >[559589.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b980] width 1280 pitch 5120 (/4 1280) >[559589.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b980] >[559589.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b980] width 1280 pitch 5120 (/4 1280) >[559589.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c8b10] >[559589.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c8b10] width 1280 pitch 5120 (/4 1280) >[559589.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbb060] >[559589.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbb060] width 1280 pitch 5120 (/4 1280) >[559591.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359b530] >[559591.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359b530] width 1280 pitch 5120 (/4 1280) >[559591.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559591.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559591.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559591.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559591.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbc60] >[559591.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbc60] width 1280 pitch 5120 (/4 1280) >[559595.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559595.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559595.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559595.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559596.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559596.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559596.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559596.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559596.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[559596.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[559596.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559596.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559667.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33314e0] >[559667.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33314e0] width 1280 pitch 5120 (/4 1280) >[559671.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d7b0] >[559671.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d7b0] width 1280 pitch 5120 (/4 1280) >[559671.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d8f40] >[559671.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d8f40] width 1280 pitch 5120 (/4 1280) >[559677.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630d80] >[559677.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630d80] width 1280 pitch 5120 (/4 1280) >[559677.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400130] >[559677.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400130] width 1280 pitch 5120 (/4 1280) >[559677.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34ef0] >[559677.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34ef0] width 1280 pitch 5120 (/4 1280) >[559677.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3400130] >[559677.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3400130] width 1280 pitch 5120 (/4 1280) >[559710.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364c880] >[559710.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364c880] width 1280 pitch 5120 (/4 1280) >[559710.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559710.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559710.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364c880] >[559711.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364c880] width 1280 pitch 5120 (/4 1280) >[559711.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559711.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559711.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559711.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559712.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364c880] >[559712.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364c880] width 1280 pitch 5120 (/4 1280) >[559712.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[559712.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[559712.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364c880] >[559712.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364c880] width 1280 pitch 5120 (/4 1280) >[559712.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a08a0] >[559712.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a08a0] width 1280 pitch 5120 (/4 1280) >[559713.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d7b0] >[559713.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d7b0] width 1280 pitch 5120 (/4 1280) >[559713.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a08a0] >[559713.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a08a0] width 1280 pitch 5120 (/4 1280) >[559713.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d7b0] >[559713.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d7b0] width 1280 pitch 5120 (/4 1280) >[559752.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b510] >[559752.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b510] width 1280 pitch 5120 (/4 1280) >[560039.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3330f30] >[560039.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3330f30] width 1280 pitch 5120 (/4 1280) >[560040.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ecaf0] >[560040.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ecaf0] width 1280 pitch 5120 (/4 1280) >[560040.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f290] >[560040.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f290] width 1280 pitch 5120 (/4 1280) >[560040.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c24b30] >[560040.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c24b30] width 1280 pitch 5120 (/4 1280) >[560040.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f290] >[560040.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f290] width 1280 pitch 5120 (/4 1280) >[561377.686] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[561377.686] (II) RADEON(0): Using hsync ranges from config file >[561377.686] (II) RADEON(0): Using vrefresh ranges from config file >[561377.686] (II) RADEON(0): Printing DDC gathered Modelines: >[561377.686] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[561377.686] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[561377.686] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[561377.686] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[561377.686] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[561377.686] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[561377.686] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[561377.686] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[561377.686] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[561377.686] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[561467.553] (II) RADEON(0): RADEONSaveScreen(2) >[561467.553] (II) RADEON(0): RADEONSaveScreen(0) >[594900.824] (II) RADEON(0): RADEONSaveScreen(1) >[594901.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa4400] >[594901.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa4400] width 1280 pitch 5120 (/4 1280) >[594903.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b390] >[594903.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b390] width 1280 pitch 5120 (/4 1280) >[595169.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c27ec0] >[595169.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c27ec0] width 1280 pitch 5120 (/4 1280) >[595170.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b390] >[595170.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b390] width 1280 pitch 5120 (/4 1280) >[595170.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e6e80] >[595170.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e6e80] width 1280 pitch 5120 (/4 1280) >[595170.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368b390] >[595170.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368b390] width 1280 pitch 5120 (/4 1280) >[595170.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8e40] >[595170.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8e40] width 1280 pitch 5120 (/4 1280) >[595171.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8e40] >[595171.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8e40] width 1280 pitch 5120 (/4 1280) >[595171.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3316c70] >[595171.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3316c70] width 1280 pitch 5120 (/4 1280) >[595171.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e8ba0] >[595171.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e8ba0] width 1280 pitch 5120 (/4 1280) >[595171.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[595171.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[595171.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[595171.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[595172.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33315d0] >[595172.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33315d0] width 1280 pitch 5120 (/4 1280) >[595172.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[595172.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[595354.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33863d0] >[595354.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33863d0] width 1280 pitch 5120 (/4 1280) >[595354.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8e40] >[595354.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8e40] width 1280 pitch 5120 (/4 1280) >[595354.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70c90] >[595354.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70c90] width 1280 pitch 5120 (/4 1280) >[595354.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a8e40] >[595354.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a8e40] width 1280 pitch 5120 (/4 1280) >[595764.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x313d3f0] >[595764.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x313d3f0] width 1280 pitch 5120 (/4 1280) >[595764.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70cf0] >[595764.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70cf0] width 1280 pitch 5120 (/4 1280) >[595780.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3389320] >[595780.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3389320] width 1280 pitch 5120 (/4 1280) >[595780.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37341c0] >[595780.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37341c0] width 1280 pitch 5120 (/4 1280) >[595780.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c269d0] >[595780.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c269d0] width 1280 pitch 5120 (/4 1280) >[595780.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37341c0] >[595780.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37341c0] width 1280 pitch 5120 (/4 1280) >[595981.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b7cf0] >[595981.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b7cf0] width 1280 pitch 5120 (/4 1280) >[595981.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bab730] >[595981.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bab730] width 1280 pitch 5120 (/4 1280) >[596088.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338dda0] >[596088.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338dda0] width 1280 pitch 5120 (/4 1280) >[596088.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bab730] >[596088.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bab730] width 1280 pitch 5120 (/4 1280) >[596088.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34973c0] >[596088.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34973c0] width 1280 pitch 5120 (/4 1280) >[596088.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bab730] >[596088.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bab730] width 1280 pitch 5120 (/4 1280) >[596089.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[596089.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[596089.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb430] >[596089.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb430] width 1280 pitch 5120 (/4 1280) >[596089.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b650] >[596089.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b650] width 1280 pitch 5120 (/4 1280) >[596089.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb430] >[596090.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb430] width 1280 pitch 5120 (/4 1280) >[596092.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb430] >[596092.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb430] width 1280 pitch 5120 (/4 1280) >[596092.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b650] >[596092.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b650] width 1280 pitch 5120 (/4 1280) >[596092.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cba0c0] >[596092.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cba0c0] width 1280 pitch 5120 (/4 1280) >[596092.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362b650] >[596092.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362b650] width 1280 pitch 5120 (/4 1280) >[596098.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bab730] >[596098.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bab730] width 1280 pitch 5120 (/4 1280) >[596098.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da350] >[596098.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da350] width 1280 pitch 5120 (/4 1280) >[596703.682] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[596703.682] (II) RADEON(0): Using hsync ranges from config file >[596703.682] (II) RADEON(0): Using vrefresh ranges from config file >[596703.682] (II) RADEON(0): Printing DDC gathered Modelines: >[596703.682] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[596703.682] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[596703.682] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[596703.683] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[596703.683] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[596703.683] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[596703.683] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[596703.683] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[596703.683] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[596703.683] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[596793.538] (II) RADEON(0): RADEONSaveScreen(2) >[596793.538] (II) RADEON(0): RADEONSaveScreen(0) >[600409.558] (II) RADEON(0): RADEONSaveScreen(1) >[600409.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3628500] >[600409.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3628500] width 1280 pitch 5120 (/4 1280) >[600418.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba45b0] >[600418.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba45b0] width 1280 pitch 5120 (/4 1280) >[600419.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ee00] >[600419.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ee00] width 1280 pitch 5120 (/4 1280) >[600419.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ee00] >[600420.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ee00] width 1280 pitch 5120 (/4 1280) >[600420.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e12b0] >[600420.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e12b0] width 1280 pitch 5120 (/4 1280) >[600420.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ee00] >[600420.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ee00] width 1280 pitch 5120 (/4 1280) >[600465.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336efb0] >[600465.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336efb0] width 1280 pitch 5120 (/4 1280) >[600465.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb430] >[600465.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb430] width 1280 pitch 5120 (/4 1280) >[600465.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336f150] >[600465.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336f150] width 1280 pitch 5120 (/4 1280) >[600465.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d5010] >[600465.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d5010] width 1280 pitch 5120 (/4 1280) >[600473.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335b980] >[600473.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335b980] width 1280 pitch 5120 (/4 1280) >[600473.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb200] >[600473.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb200] width 1280 pitch 5120 (/4 1280) >[600507.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600507.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600507.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600507.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600507.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600507.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600507.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600507.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600531.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600531.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600531.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600531.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600531.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600531.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600531.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600531.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600532.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600532.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600532.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600532.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600532.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600532.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600532.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600532.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600532.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600532.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600533.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600533.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600533.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600533.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600533.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600533.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600533.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600533.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600534.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600534.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600534.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b98b50] >[600534.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b98b50] width 1280 pitch 5120 (/4 1280) >[600534.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600534.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600534.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b98b50] >[600534.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b98b50] width 1280 pitch 5120 (/4 1280) >[600543.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600543.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600544.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600544.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600546.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600546.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600546.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600546.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600546.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600546.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600557.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600557.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600557.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600557.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600557.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08fc0] >[600557.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08fc0] width 1280 pitch 5120 (/4 1280) >[600557.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600557.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600559.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600560.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600560.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600560.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600560.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600560.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600560.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600560.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600567.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600567.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600567.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600567.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600567.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08fd0] >[600567.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08fd0] width 1280 pitch 5120 (/4 1280) >[600567.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600567.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600568.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600568.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600568.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600568.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600568.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600568.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600568.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600568.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600626.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600626.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600626.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600626.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600626.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67710] >[600627.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67710] width 1280 pitch 5120 (/4 1280) >[600627.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600627.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600632.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eeb50] >[600632.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eeb50] width 1280 pitch 5120 (/4 1280) >[600632.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600632.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600632.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362c330] >[600632.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362c330] width 1280 pitch 5120 (/4 1280) >[600632.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600632.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600632.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362c330] >[600632.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362c330] width 1280 pitch 5120 (/4 1280) >[600636.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600636.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600636.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362c330] >[600636.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362c330] width 1280 pitch 5120 (/4 1280) >[600636.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[600636.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[600636.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a06c0] >[600636.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a06c0] width 1280 pitch 5120 (/4 1280) >[600650.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363d770] >[600650.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363d770] width 1280 pitch 5120 (/4 1280) >[600650.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c66410] >[600650.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c66410] width 1280 pitch 5120 (/4 1280) >[600652.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[600652.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[600652.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c66410] >[600652.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c66410] width 1280 pitch 5120 (/4 1280) >[600656.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c95780] >[600656.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c95780] width 1280 pitch 5120 (/4 1280) >[600694.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cac860] >[600694.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cac860] width 1280 pitch 5120 (/4 1280) >[600694.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370caf0] >[600694.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370caf0] width 1280 pitch 5120 (/4 1280) >[600695.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[600696.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[600696.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c6a90] >[600696.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c6a90] width 1280 pitch 5120 (/4 1280) >[600696.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f54c0] >[600696.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f54c0] width 1280 pitch 5120 (/4 1280) >[600696.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c6a90] >[600696.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c6a90] width 1280 pitch 5120 (/4 1280) >[600696.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9600] >[600696.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9600] width 1280 pitch 5120 (/4 1280) >[600696.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[600696.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[600731.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[600731.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[600731.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23970] >[600732.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23970] width 1280 pitch 5120 (/4 1280) >[600732.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6c80] >[600732.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6c80] width 1280 pitch 5120 (/4 1280) >[600732.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[600732.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[600733.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[600733.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[600733.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[600733.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[600733.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d660] >[600733.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d660] width 1280 pitch 5120 (/4 1280) >[600733.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[600733.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[600733.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709770] >[600733.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709770] width 1280 pitch 5120 (/4 1280) >[600733.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36db9a0] >[600733.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36db9a0] width 1280 pitch 5120 (/4 1280) >[600778.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3599c90] >[600778.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3599c90] width 1280 pitch 5120 (/4 1280) >[600778.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bd660] >[600778.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bd660] width 1280 pitch 5120 (/4 1280) >[600778.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594b0] >[600778.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594b0] width 1280 pitch 5120 (/4 1280) >[600778.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32469a0] >[600778.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32469a0] width 1280 pitch 5120 (/4 1280) >[600778.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361f2e0] >[600778.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361f2e0] width 1280 pitch 5120 (/4 1280) >[600778.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3599c90] >[600778.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3599c90] width 1280 pitch 5120 (/4 1280) >[600778.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3615c70] >[600778.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3615c70] width 1280 pitch 5120 (/4 1280) >[600778.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d150] >[600778.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d150] width 1280 pitch 5120 (/4 1280) >[600778.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d150] >[600778.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d150] width 1280 pitch 5120 (/4 1280) >[600778.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3615c70] >[600778.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3615c70] width 1280 pitch 5120 (/4 1280) >[600778.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d150] >[600778.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d150] width 1280 pitch 5120 (/4 1280) >[600779.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3615c70] >[600779.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3615c70] width 1280 pitch 5120 (/4 1280) >[600779.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2c420] >[600779.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2c420] width 1280 pitch 5120 (/4 1280) >[600779.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362aa90] >[600779.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362aa90] width 1280 pitch 5120 (/4 1280) >[600779.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b4c0] >[600779.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b4c0] width 1280 pitch 5120 (/4 1280) >[600779.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3324630] >[600779.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3324630] width 1280 pitch 5120 (/4 1280) >[600779.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b4c0] >[600779.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b4c0] width 1280 pitch 5120 (/4 1280) >[600779.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3324630] >[600779.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3324630] width 1280 pitch 5120 (/4 1280) >[600779.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b4ad0] >[600779.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b4ad0] width 1280 pitch 5120 (/4 1280) >[600779.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfd60] >[600779.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfd60] width 1280 pitch 5120 (/4 1280) >[600779.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b4a70] >[600779.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b4a70] width 1280 pitch 5120 (/4 1280) >[600779.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e4da0] >[600780.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e4da0] width 1280 pitch 5120 (/4 1280) >[600780.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b4a70] >[600780.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b4a70] width 1280 pitch 5120 (/4 1280) >[600780.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c78770] >[600780.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c78770] width 1280 pitch 5120 (/4 1280) >[600780.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c787d0] >[600780.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c787d0] width 1280 pitch 5120 (/4 1280) >[600780.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c78770] >[600780.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c78770] width 1280 pitch 5120 (/4 1280) >[600780.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c787d0] >[600780.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c787d0] width 1280 pitch 5120 (/4 1280) >[601460.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3609990] >[601460.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3609990] width 1280 pitch 5120 (/4 1280) >[601527.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33bc420] >[601527.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33bc420] width 1280 pitch 5120 (/4 1280) >[601533.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96640] >[601533.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96640] width 1280 pitch 5120 (/4 1280) >[601533.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302eb0] >[601533.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302eb0] width 1280 pitch 5120 (/4 1280) >[601533.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96640] >[601533.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96640] width 1280 pitch 5120 (/4 1280) >[601533.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302eb0] >[601533.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302eb0] width 1280 pitch 5120 (/4 1280) >[601537.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[601537.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[601537.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3718e00] >[601538.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3718e00] width 1280 pitch 5120 (/4 1280) >[601538.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3710250] >[601538.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3710250] width 1280 pitch 5120 (/4 1280) >[601538.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601538.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601538.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3710250] >[601538.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3710250] width 1280 pitch 5120 (/4 1280) >[601548.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601548.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601548.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601548.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601548.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601548.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601548.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601548.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601548.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a7ca0] >[601548.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a7ca0] width 1280 pitch 5120 (/4 1280) >[601548.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601548.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601548.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3710250] >[601548.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3710250] width 1280 pitch 5120 (/4 1280) >[601548.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[601548.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[601548.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601548.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601549.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601549.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601549.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601549.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601549.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601549.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601551.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601551.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601554.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601554.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601554.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601554.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601554.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c90940] >[601554.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c90940] width 1280 pitch 5120 (/4 1280) >[601554.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c908e0] >[601554.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c908e0] width 1280 pitch 5120 (/4 1280) >[601554.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c909d0] >[601554.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c909d0] width 1280 pitch 5120 (/4 1280) >[601554.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c908e0] >[601554.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c908e0] width 1280 pitch 5120 (/4 1280) >[601554.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361da40] >[601554.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361da40] width 1280 pitch 5120 (/4 1280) >[601554.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331d030] >[601554.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331d030] width 1280 pitch 5120 (/4 1280) >[601554.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a1d00] >[601554.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a1d00] width 1280 pitch 5120 (/4 1280) >[601554.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341d80] >[601554.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341d80] width 1280 pitch 5120 (/4 1280) >[601554.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0510] >[601554.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0510] width 1280 pitch 5120 (/4 1280) >[601560.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6d80] >[601560.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6d80] width 1280 pitch 5120 (/4 1280) >[601561.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363f380] >[601561.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363f380] width 1280 pitch 5120 (/4 1280) >[601561.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf690] >[601561.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf690] width 1280 pitch 5120 (/4 1280) >[601561.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598b50] >[601561.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598b50] width 1280 pitch 5120 (/4 1280) >[601561.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c330] >[601561.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c330] width 1280 pitch 5120 (/4 1280) >[601561.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c330] >[601561.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c330] width 1280 pitch 5120 (/4 1280) >[601561.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601561.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601561.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375c330] >[601561.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375c330] width 1280 pitch 5120 (/4 1280) >[601561.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601561.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601565.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6be0] >[601565.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6be0] width 1280 pitch 5120 (/4 1280) >[601565.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601565.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601565.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601565.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601565.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601565.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601565.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baf960] >[601565.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baf960] width 1280 pitch 5120 (/4 1280) >[601565.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b6e20] >[601565.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b6e20] width 1280 pitch 5120 (/4 1280) >[601565.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3330b90] >[601565.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3330b90] width 1280 pitch 5120 (/4 1280) >[601566.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601566.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601566.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601566.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601566.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601566.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3334f30] >[601566.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3334f30] width 1280 pitch 5120 (/4 1280) >[601566.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[601566.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[601567.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a860] >[601567.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a860] width 1280 pitch 5120 (/4 1280) >[601567.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601567.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[601567.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[601567.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d680] >[601567.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d680] width 1280 pitch 5120 (/4 1280) >[601568.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76760] >[601568.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76760] width 1280 pitch 5120 (/4 1280) >[601568.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a4c30] >[601568.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a4c30] width 1280 pitch 5120 (/4 1280) >[601581.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601581.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601581.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8c0] >[601581.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8c0] width 1280 pitch 5120 (/4 1280) >[601581.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601581.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601591.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c48940] >[601591.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c48940] width 1280 pitch 5120 (/4 1280) >[601591.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45832a0] >[601591.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45832a0] width 1280 pitch 5120 (/4 1280) >[601591.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d130] >[601591.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d130] width 1280 pitch 5120 (/4 1280) >[601591.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[601591.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[601603.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc1e0] >[601603.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc1e0] width 1280 pitch 5120 (/4 1280) >[601622.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[601623.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[601623.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601623.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[601623.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348e470] >[601623.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348e470] width 1280 pitch 5120 (/4 1280) >[601623.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[601623.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[601624.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601624.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[601624.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302010] >[601624.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302010] width 1280 pitch 5120 (/4 1280) >[601624.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[601624.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[601626.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601626.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[601626.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[601626.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[601626.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601626.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[601626.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601626.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[601626.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[601626.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[601627.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369f410] >[601627.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369f410] width 1280 pitch 5120 (/4 1280) >[602028.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b5b30] >[602028.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b5b30] width 1280 pitch 5120 (/4 1280) >[602031.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[602031.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[602031.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b5b30] >[602031.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b5b30] width 1280 pitch 5120 (/4 1280) >[602031.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602031.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602031.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b5b30] >[602031.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b5b30] width 1280 pitch 5120 (/4 1280) >[602066.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602066.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602066.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602066.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602066.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[602066.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[602069.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[602069.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[602069.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f20b0] >[602069.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f20b0] width 1280 pitch 5120 (/4 1280) >[602073.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345baa0] >[602073.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345baa0] width 1280 pitch 5120 (/4 1280) >[602073.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365e0b0] >[602073.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365e0b0] width 1280 pitch 5120 (/4 1280) >[602073.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602073.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602090.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[602090.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[602090.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602090.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602090.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302010] >[602090.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302010] width 1280 pitch 5120 (/4 1280) >[602090.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602090.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602091.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[602091.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[602091.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602091.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602091.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[602091.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[602091.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602091.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602091.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36447e0] >[602091.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36447e0] width 1280 pitch 5120 (/4 1280) >[602091.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358ea10] >[602091.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358ea10] width 1280 pitch 5120 (/4 1280) >[602096.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dc240] >[602096.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dc240] width 1280 pitch 5120 (/4 1280) >[602096.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd930] >[602096.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd930] width 1280 pitch 5120 (/4 1280) >[602096.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602096.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602105.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602105.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602105.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c38e0] >[602105.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c38e0] width 1280 pitch 5120 (/4 1280) >[602105.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ee60] >[602105.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ee60] width 1280 pitch 5120 (/4 1280) >[602115.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602115.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602115.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f33d0] >[602115.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f33d0] width 1280 pitch 5120 (/4 1280) >[602115.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602115.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602123.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f33d0] >[602123.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f33d0] width 1280 pitch 5120 (/4 1280) >[602124.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602124.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602124.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f33d0] >[602124.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f33d0] width 1280 pitch 5120 (/4 1280) >[602124.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[602124.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[602124.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6c80] >[602124.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6c80] width 1280 pitch 5120 (/4 1280) >[602124.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[602124.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[602158.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602158.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602158.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9a10] >[602158.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9a10] width 1280 pitch 5120 (/4 1280) >[602158.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[602158.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[602158.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602158.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602160.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[602160.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[602160.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602160.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602160.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[602161.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[602176.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6960] >[602176.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6960] width 1280 pitch 5120 (/4 1280) >[602176.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[602176.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[602179.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d6d0] >[602179.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d6d0] width 1280 pitch 5120 (/4 1280) >[602179.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32544c0] >[602179.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32544c0] width 1280 pitch 5120 (/4 1280) >[602179.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602179.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602182.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5120] >[602182.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5120] width 1280 pitch 5120 (/4 1280) >[602182.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfa860] >[602182.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfa860] width 1280 pitch 5120 (/4 1280) >[602183.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[602183.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[602183.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfa860] >[602183.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfa860] width 1280 pitch 5120 (/4 1280) >[602183.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602183.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602184.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d650] >[602184.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d650] width 1280 pitch 5120 (/4 1280) >[602184.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602184.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602184.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[602184.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[602184.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[602184.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[602216.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23970] >[602216.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23970] width 1280 pitch 5120 (/4 1280) >[602216.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602216.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602216.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[602216.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[602216.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602216.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602219.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d270] >[602219.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d270] width 1280 pitch 5120 (/4 1280) >[602219.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602219.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602219.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333a2e0] >[602219.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333a2e0] width 1280 pitch 5120 (/4 1280) >[602219.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602219.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602249.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[602249.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[602249.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598370] >[602249.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598370] width 1280 pitch 5120 (/4 1280) >[602249.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602249.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602250.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b987a0] >[602250.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b987a0] width 1280 pitch 5120 (/4 1280) >[602252.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5120] >[602252.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5120] width 1280 pitch 5120 (/4 1280) >[602252.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602252.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602258.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602258.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602258.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcd930] >[602258.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcd930] width 1280 pitch 5120 (/4 1280) >[602263.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3729040] >[602263.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3729040] width 1280 pitch 5120 (/4 1280) >[602263.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602263.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602263.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c9550] >[602263.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c9550] width 1280 pitch 5120 (/4 1280) >[602263.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602263.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602263.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c9550] >[602263.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c9550] width 1280 pitch 5120 (/4 1280) >[602263.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602263.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602263.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c9550] >[602263.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c9550] width 1280 pitch 5120 (/4 1280) >[602263.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602263.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602263.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c9550] >[602263.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c9550] width 1280 pitch 5120 (/4 1280) >[602263.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602263.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602330.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[602330.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[602330.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333a2e0] >[602330.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333a2e0] width 1280 pitch 5120 (/4 1280) >[602332.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c493e0] >[602332.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c493e0] width 1280 pitch 5120 (/4 1280) >[602332.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602332.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602332.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602332.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602332.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[602332.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[602332.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3417380] >[602332.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3417380] width 1280 pitch 5120 (/4 1280) >[602332.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[602333.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[602334.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602334.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602334.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d270] >[602334.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d270] width 1280 pitch 5120 (/4 1280) >[602335.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c973a0] >[602335.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c973a0] width 1280 pitch 5120 (/4 1280) >[602420.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c783a0] >[602420.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c783a0] width 1280 pitch 5120 (/4 1280) >[602585.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[602585.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[602588.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457e7f0] >[602588.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457e7f0] width 1280 pitch 5120 (/4 1280) >[602610.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3339190] >[602610.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3339190] width 1280 pitch 5120 (/4 1280) >[602611.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333a2e0] >[602611.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333a2e0] width 1280 pitch 5120 (/4 1280) >[602611.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[602611.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[602611.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfa860] >[602611.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfa860] width 1280 pitch 5120 (/4 1280) >[602611.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[602611.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[602612.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6c80] >[602612.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6c80] width 1280 pitch 5120 (/4 1280) >[602612.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[602612.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[602616.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602616.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602616.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602616.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602616.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602616.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602616.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[602616.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[602674.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b5b30] >[602674.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b5b30] width 1280 pitch 5120 (/4 1280) >[602674.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c783a0] >[602674.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c783a0] width 1280 pitch 5120 (/4 1280) >[602674.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602674.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602674.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c783a0] >[602674.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c783a0] width 1280 pitch 5120 (/4 1280) >[602735.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8d30] >[602735.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8d30] width 1280 pitch 5120 (/4 1280) >[602735.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[602736.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[602736.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5120] >[602736.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5120] width 1280 pitch 5120 (/4 1280) >[602736.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b5120] >[602736.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b5120] width 1280 pitch 5120 (/4 1280) >[602736.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c973a0] >[602736.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c973a0] width 1280 pitch 5120 (/4 1280) >[602736.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[602737.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[602737.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457e7f0] >[602737.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457e7f0] width 1280 pitch 5120 (/4 1280) >[602737.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c973a0] >[602737.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c973a0] width 1280 pitch 5120 (/4 1280) >[602737.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[602737.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[602737.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[602737.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[602856.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6c80] >[602856.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6c80] width 1280 pitch 5120 (/4 1280) >[602857.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602857.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602857.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3727820] >[602857.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3727820] width 1280 pitch 5120 (/4 1280) >[602857.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4dab0] >[602857.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4dab0] width 1280 pitch 5120 (/4 1280) >[602858.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f44b0] >[602858.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f44b0] width 1280 pitch 5120 (/4 1280) >[602858.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e78b0] >[602858.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e78b0] width 1280 pitch 5120 (/4 1280) >[602858.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0b80] >[602858.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0b80] width 1280 pitch 5120 (/4 1280) >[602858.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424e90] >[602858.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424e90] width 1280 pitch 5120 (/4 1280) >[602858.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300190] >[602858.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300190] width 1280 pitch 5120 (/4 1280) >[602858.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602858.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602878.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f380] >[602878.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f380] width 1280 pitch 5120 (/4 1280) >[602878.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[602878.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[602878.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[602878.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[602878.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602878.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602878.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[602878.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[602878.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602878.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602878.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[602878.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[602878.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602879.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602879.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[602879.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[602879.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dd8a0] >[602879.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dd8a0] width 1280 pitch 5120 (/4 1280) >[602879.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3598370] >[602879.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3598370] width 1280 pitch 5120 (/4 1280) >[602879.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[602879.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[602880.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c783a0] >[602880.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c783a0] width 1280 pitch 5120 (/4 1280) >[602880.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33991d0] >[602880.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33991d0] width 1280 pitch 5120 (/4 1280) >[602884.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457e7f0] >[602884.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457e7f0] width 1280 pitch 5120 (/4 1280) >[602884.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602884.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602884.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a5ff0] >[602884.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a5ff0] width 1280 pitch 5120 (/4 1280) >[602884.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da7b0] >[602884.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da7b0] width 1280 pitch 5120 (/4 1280) >[602884.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c43940] >[602884.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c43940] width 1280 pitch 5120 (/4 1280) >[602884.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[602884.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[602884.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35abe80] >[602884.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35abe80] width 1280 pitch 5120 (/4 1280) >[602884.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a5ff0] >[602884.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a5ff0] width 1280 pitch 5120 (/4 1280) >[602885.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3485890] >[602885.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3485890] width 1280 pitch 5120 (/4 1280) >[602885.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335f2a0] >[602885.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335f2a0] width 1280 pitch 5120 (/4 1280) >[602908.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d8160] >[602908.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d8160] width 1280 pitch 5120 (/4 1280) >[602909.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357c3b0] >[602909.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357c3b0] width 1280 pitch 5120 (/4 1280) >[602909.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32306b0] >[602909.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32306b0] width 1280 pitch 5120 (/4 1280) >[602909.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8d0f0] >[602909.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8d0f0] width 1280 pitch 5120 (/4 1280) >[602927.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99680] >[602927.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99680] width 1280 pitch 5120 (/4 1280) >[602952.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1ad0] >[602952.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1ad0] width 1280 pitch 5120 (/4 1280) >[602953.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1ad0] >[602953.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1ad0] width 1280 pitch 5120 (/4 1280) >[602953.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b25800] >[602953.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b25800] width 1280 pitch 5120 (/4 1280) >[602954.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717070] >[602954.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717070] width 1280 pitch 5120 (/4 1280) >[602974.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab09b0] >[602974.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab09b0] width 1280 pitch 5120 (/4 1280) >[602976.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32306b0] >[602976.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32306b0] width 1280 pitch 5120 (/4 1280) >[602976.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357aff0] >[602976.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357aff0] width 1280 pitch 5120 (/4 1280) >[602976.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32306b0] >[602976.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32306b0] width 1280 pitch 5120 (/4 1280) >[603016.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d4b10] >[603016.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d4b10] width 1280 pitch 5120 (/4 1280) >[603019.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cfb80] >[603019.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cfb80] width 1280 pitch 5120 (/4 1280) >[603019.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33415e0] >[603019.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33415e0] width 1280 pitch 5120 (/4 1280) >[603019.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3626dc0] >[603019.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3626dc0] width 1280 pitch 5120 (/4 1280) >[603019.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33415e0] >[603019.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33415e0] width 1280 pitch 5120 (/4 1280) >[603052.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b6010] >[603052.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b6010] width 1280 pitch 5120 (/4 1280) >[603056.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99740] >[603056.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99740] width 1280 pitch 5120 (/4 1280) >[603056.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33415e0] >[603056.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33415e0] width 1280 pitch 5120 (/4 1280) >[603056.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99740] >[603056.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99740] width 1280 pitch 5120 (/4 1280) >[603056.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99740] >[603056.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99740] width 1280 pitch 5120 (/4 1280) >[603120.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05b70] >[603120.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05b70] width 1280 pitch 5120 (/4 1280) >[603123.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603123.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603128.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ebe20] >[603128.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ebe20] width 1280 pitch 5120 (/4 1280) >[603128.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368fd90] >[603128.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368fd90] width 1280 pitch 5120 (/4 1280) >[603128.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[603128.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[603128.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ea0e0] >[603128.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ea0e0] width 1280 pitch 5120 (/4 1280) >[603129.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[603129.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[603129.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318f80] >[603129.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318f80] width 1280 pitch 5120 (/4 1280) >[603129.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585ca0] >[603129.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585ca0] width 1280 pitch 5120 (/4 1280) >[603129.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9400] >[603129.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9400] width 1280 pitch 5120 (/4 1280) >[603129.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6c80] >[603129.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6c80] width 1280 pitch 5120 (/4 1280) >[603135.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0590] >[603135.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0590] width 1280 pitch 5120 (/4 1280) >[603137.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a75c0] >[603137.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a75c0] width 1280 pitch 5120 (/4 1280) >[603137.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e880] >[603137.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e880] width 1280 pitch 5120 (/4 1280) >[603137.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6960] >[603137.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6960] width 1280 pitch 5120 (/4 1280) >[603137.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331e0a0] >[603137.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331e0a0] width 1280 pitch 5120 (/4 1280) >[603137.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[603137.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[603140.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d130] >[603140.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d130] width 1280 pitch 5120 (/4 1280) >[603145.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4580480] >[603145.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4580480] width 1280 pitch 5120 (/4 1280) >[603145.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a0fa0] >[603145.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a0fa0] width 1280 pitch 5120 (/4 1280) >[603146.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a0fa0] >[603146.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a0fa0] width 1280 pitch 5120 (/4 1280) >[603146.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d130] >[603146.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d130] width 1280 pitch 5120 (/4 1280) >[603146.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e6960] >[603146.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e6960] width 1280 pitch 5120 (/4 1280) >[603146.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d130] >[603146.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d130] width 1280 pitch 5120 (/4 1280) >[603147.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d45e0] >[603147.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d45e0] width 1280 pitch 5120 (/4 1280) >[603147.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23970] >[603147.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23970] width 1280 pitch 5120 (/4 1280) >[603147.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cd8c0] >[603148.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cd8c0] width 1280 pitch 5120 (/4 1280) >[603360.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366ca00] >[603360.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366ca00] width 1280 pitch 5120 (/4 1280) >[603364.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355780] >[603364.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355780] width 1280 pitch 5120 (/4 1280) >[603364.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d810] >[603364.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d810] width 1280 pitch 5120 (/4 1280) >[603364.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603365.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603365.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d810] >[603365.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d810] width 1280 pitch 5120 (/4 1280) >[603391.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c2cc0] >[603391.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c2cc0] width 1280 pitch 5120 (/4 1280) >[603391.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d810] >[603391.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d810] width 1280 pitch 5120 (/4 1280) >[603391.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31362d0] >[603391.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31362d0] width 1280 pitch 5120 (/4 1280) >[603391.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323d810] >[603391.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323d810] width 1280 pitch 5120 (/4 1280) >[603400.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35cf0] >[603400.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35cf0] width 1280 pitch 5120 (/4 1280) >[603400.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[603400.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[603400.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeaf0] >[603400.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeaf0] width 1280 pitch 5120 (/4 1280) >[603515.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414d30] >[603515.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414d30] width 1280 pitch 5120 (/4 1280) >[603516.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603516.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603516.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a0c80] >[603516.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a0c80] width 1280 pitch 5120 (/4 1280) >[603516.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ec930] >[603516.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ec930] width 1280 pitch 5120 (/4 1280) >[603525.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603525.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603525.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603525.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603525.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abbf20] >[603525.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abbf20] width 1280 pitch 5120 (/4 1280) >[603525.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfe10] >[603525.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfe10] width 1280 pitch 5120 (/4 1280) >[603539.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be28c0] >[603539.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be28c0] width 1280 pitch 5120 (/4 1280) >[603542.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34735c0] >[603542.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34735c0] width 1280 pitch 5120 (/4 1280) >[603542.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fdb0] >[603542.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fdb0] width 1280 pitch 5120 (/4 1280) >[603542.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414d30] >[603542.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414d30] width 1280 pitch 5120 (/4 1280) >[603542.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fdb0] >[603542.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fdb0] width 1280 pitch 5120 (/4 1280) >[603726.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbc420] >[603726.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbc420] width 1280 pitch 5120 (/4 1280) >[603738.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375a570] >[603738.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375a570] width 1280 pitch 5120 (/4 1280) >[603739.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324afa0] >[603739.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324afa0] width 1280 pitch 5120 (/4 1280) >[603739.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3318e50] >[603739.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3318e50] width 1280 pitch 5120 (/4 1280) >[603739.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324afa0] >[603739.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324afa0] width 1280 pitch 5120 (/4 1280) >[603805.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c35cf0] >[603806.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c35cf0] width 1280 pitch 5120 (/4 1280) >[603833.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d150] >[603833.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d150] width 1280 pitch 5120 (/4 1280) >[603833.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341dae0] >[603833.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341dae0] width 1280 pitch 5120 (/4 1280) >[603833.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315d150] >[603833.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315d150] width 1280 pitch 5120 (/4 1280) >[603833.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341dae0] >[603833.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341dae0] width 1280 pitch 5120 (/4 1280) >[603833.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cea00] >[603833.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cea00] width 1280 pitch 5120 (/4 1280) >[603856.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bb110] >[603856.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bb110] width 1280 pitch 5120 (/4 1280) >[604474.293] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[604474.294] (II) RADEON(0): Using hsync ranges from config file >[604474.294] (II) RADEON(0): Using vrefresh ranges from config file >[604474.294] (II) RADEON(0): Printing DDC gathered Modelines: >[604474.294] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[604474.294] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[604474.294] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[604474.294] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[604474.294] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[604474.294] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[604474.294] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[604474.294] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[604474.294] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[604474.294] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[604564.555] (II) RADEON(0): RADEONSaveScreen(2) >[604564.555] (II) RADEON(0): RADEONSaveScreen(0) >[606374.909] (II) RADEON(0): RADEONSaveScreen(1) >[607072.543] (II) RADEON(0): RADEONSaveScreen(2) >[607072.543] (II) RADEON(0): RADEONSaveScreen(0) >[609009.644] (II) RADEON(0): RADEONSaveScreen(1) >[609009.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3727820] >[609009.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3727820] width 1280 pitch 5120 (/4 1280) >[610733.544] (II) RADEON(0): RADEONSaveScreen(2) >[610733.545] (II) RADEON(0): RADEONSaveScreen(0) >[643034.420] (II) RADEON(0): RADEONSaveScreen(1) >[643037.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3727820] >[643037.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3727820] width 1280 pitch 5120 (/4 1280) >[643040.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3727820] >[643040.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3727820] width 1280 pitch 5120 (/4 1280) >[643040.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99590] >[643040.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99590] width 1280 pitch 5120 (/4 1280) >[643041.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace990] >[643041.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace990] width 1280 pitch 5120 (/4 1280) >[643041.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643041.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3195090] >[643041.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3195090] width 1280 pitch 5120 (/4 1280) >[643041.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[643041.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[643135.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a0500] >[643135.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a0500] width 1280 pitch 5120 (/4 1280) >[643135.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3125090] >[643135.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3125090] width 1280 pitch 5120 (/4 1280) >[643135.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37226a0] >[643135.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37226a0] width 1280 pitch 5120 (/4 1280) >[643135.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3125090] >[643135.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3125090] width 1280 pitch 5120 (/4 1280) >[643537.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e98f0] >[643537.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e98f0] width 1280 pitch 5120 (/4 1280) >[645092.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370b310] >[645092.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370b310] width 1280 pitch 5120 (/4 1280) >[645104.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dbf0] >[645104.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dbf0] width 1280 pitch 5120 (/4 1280) >[645117.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59090] >[645117.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59090] width 1280 pitch 5120 (/4 1280) >[645117.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aeb270] >[645117.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aeb270] width 1280 pitch 5120 (/4 1280) >[645117.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59090] >[645117.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59090] width 1280 pitch 5120 (/4 1280) >[645117.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be1330] >[645117.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be1330] width 1280 pitch 5120 (/4 1280) >[645117.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ca250] >[645117.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ca250] width 1280 pitch 5120 (/4 1280) >[645117.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be1330] >[645117.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be1330] width 1280 pitch 5120 (/4 1280) >[645117.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0640] >[645117.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0640] width 1280 pitch 5120 (/4 1280) >[645117.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c0640] >[645117.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c0640] width 1280 pitch 5120 (/4 1280) >[645117.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ca250] >[645117.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ca250] width 1280 pitch 5120 (/4 1280) >[645117.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a2e80] >[645117.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a2e80] width 1280 pitch 5120 (/4 1280) >[645117.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645117.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645118.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645118.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645118.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645118.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645118.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645118.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645118.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645118.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645118.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645119.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645119.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645119.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645119.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645119.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645119.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645119.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645119.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645119.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645119.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645119.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645119.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645119.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645119.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ee7e0] >[645119.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ee7e0] width 1280 pitch 5120 (/4 1280) >[645119.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c23890] >[645119.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c23890] width 1280 pitch 5120 (/4 1280) >[645648.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca7590] >[645648.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca7590] width 1280 pitch 5120 (/4 1280) >[645649.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3725650] >[645649.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3725650] width 1280 pitch 5120 (/4 1280) >[645649.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e390] >[645649.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e390] width 1280 pitch 5120 (/4 1280) >[645649.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e1ab0] >[645649.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e1ab0] width 1280 pitch 5120 (/4 1280) >[646956.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca7590] >[646956.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca7590] width 1280 pitch 5120 (/4 1280) >[647193.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3570f00] >[647193.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3570f00] width 1280 pitch 5120 (/4 1280) >[647193.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[647193.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[647195.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[647195.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[647195.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ec20] >[647195.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ec20] width 1280 pitch 5120 (/4 1280) >[647195.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32626d0] >[647195.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32626d0] width 1280 pitch 5120 (/4 1280) >[647195.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[647195.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[647195.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[647195.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[647195.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e3c30] >[647195.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e3c30] width 1280 pitch 5120 (/4 1280) >[647195.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eeb50] >[647195.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eeb50] width 1280 pitch 5120 (/4 1280) >[647195.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3570f00] >[647195.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3570f00] width 1280 pitch 5120 (/4 1280) >[647195.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6f70] >[647195.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6f70] width 1280 pitch 5120 (/4 1280) >[647195.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[647195.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[647198.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[647198.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[647198.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[647198.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[647198.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[647198.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[647200.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37253c0] >[647200.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37253c0] width 1280 pitch 5120 (/4 1280) >[647202.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ca60] >[647202.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ca60] width 1280 pitch 5120 (/4 1280) >[647202.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca87d0] >[647202.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca87d0] width 1280 pitch 5120 (/4 1280) >[647202.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458abe0] >[647202.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458abe0] width 1280 pitch 5120 (/4 1280) >[647202.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x458abe0] >[647202.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x458abe0] width 1280 pitch 5120 (/4 1280) >[647202.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722f90] >[647202.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722f90] width 1280 pitch 5120 (/4 1280) >[647202.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3722e70] >[647202.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3722e70] width 1280 pitch 5120 (/4 1280) >[647204.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8af60] >[647204.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8af60] width 1280 pitch 5120 (/4 1280) >[647204.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367c40] >[647204.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367c40] width 1280 pitch 5120 (/4 1280) >[647204.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333af60] >[647204.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333af60] width 1280 pitch 5120 (/4 1280) >[647216.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6f70] >[647216.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6f70] width 1280 pitch 5120 (/4 1280) >[647216.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6f70] >[647216.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6f70] width 1280 pitch 5120 (/4 1280) >[647216.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c30110] >[647216.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c30110] width 1280 pitch 5120 (/4 1280) >[647216.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3476a40] >[647216.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3476a40] width 1280 pitch 5120 (/4 1280) >[647224.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8770] >[647224.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8770] width 1280 pitch 5120 (/4 1280) >[648542.806] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[648542.807] (II) RADEON(0): Using hsync ranges from config file >[648542.807] (II) RADEON(0): Using vrefresh ranges from config file >[648542.807] (II) RADEON(0): Printing DDC gathered Modelines: >[648542.807] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[648542.807] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[648542.807] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[648542.807] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[648542.807] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[648542.807] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[648542.807] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[648542.807] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[648542.807] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[648542.807] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[648632.537] (II) RADEON(0): RADEONSaveScreen(2) >[648632.537] (II) RADEON(0): RADEONSaveScreen(0) >[649355.010] (II) RADEON(0): RADEONSaveScreen(1) >[650045.535] (II) RADEON(0): RADEONSaveScreen(2) >[650045.535] (II) RADEON(0): RADEONSaveScreen(0) >[650897.519] (II) RADEON(0): RADEONSaveScreen(1) >[650897.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba2bc0] >[650897.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba2bc0] width 1280 pitch 5120 (/4 1280) >[650902.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580180] >[650902.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580180] width 1280 pitch 5120 (/4 1280) >[650907.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3718700] >[650907.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3718700] width 1280 pitch 5120 (/4 1280) >[650908.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eff20] >[650908.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eff20] width 1280 pitch 5120 (/4 1280) >[650908.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9750] >[650908.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9750] width 1280 pitch 5120 (/4 1280) >[650908.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eff20] >[650908.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eff20] width 1280 pitch 5120 (/4 1280) >[650909.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dbd20] >[650909.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dbd20] width 1280 pitch 5120 (/4 1280) >[650909.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b81f0] >[650909.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b81f0] width 1280 pitch 5120 (/4 1280) >[650909.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b81f0] >[650909.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b81f0] width 1280 pitch 5120 (/4 1280) >[650909.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[650909.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[650922.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b81f0] >[650922.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b81f0] width 1280 pitch 5120 (/4 1280) >[650924.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[650924.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[650924.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326f40] >[650924.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326f40] width 1280 pitch 5120 (/4 1280) >[650924.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[650924.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[650925.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326f40] >[650925.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326f40] width 1280 pitch 5120 (/4 1280) >[650925.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[650925.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[651035.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d100] >[651035.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d100] width 1280 pitch 5120 (/4 1280) >[651035.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414d30] >[651035.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414d30] width 1280 pitch 5120 (/4 1280) >[651035.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ef10] >[651035.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ef10] width 1280 pitch 5120 (/4 1280) >[651035.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3718700] >[651035.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3718700] width 1280 pitch 5120 (/4 1280) >[651198.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfa170] >[651198.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfa170] width 1280 pitch 5120 (/4 1280) >[651199.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x325ed70] >[651199.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x325ed70] width 1280 pitch 5120 (/4 1280) >[651200.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3660520] >[651200.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3660520] width 1280 pitch 5120 (/4 1280) >[651200.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[651200.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[651200.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[651200.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[651260.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619850] >[651260.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619850] width 1280 pitch 5120 (/4 1280) >[651260.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594e0] >[651260.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594e0] width 1280 pitch 5120 (/4 1280) >[651260.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fdb0] >[651260.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fdb0] width 1280 pitch 5120 (/4 1280) >[651261.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594e0] >[651261.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594e0] width 1280 pitch 5120 (/4 1280) >[651261.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[651261.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[651261.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[651261.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[651261.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619850] >[651261.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619850] width 1280 pitch 5120 (/4 1280) >[651261.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeaf0] >[651261.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeaf0] width 1280 pitch 5120 (/4 1280) >[651262.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[651262.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[651262.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c12bc0] >[651262.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c12bc0] width 1280 pitch 5120 (/4 1280) >[651262.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d52b0] >[651262.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d52b0] width 1280 pitch 5120 (/4 1280) >[651262.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359db70] >[651262.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359db70] width 1280 pitch 5120 (/4 1280) >[652821.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3440080] >[652821.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3440080] width 1280 pitch 5120 (/4 1280) >[652826.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x371dcb0] >[652826.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x371dcb0] width 1280 pitch 5120 (/4 1280) >[652826.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388fc0] >[652826.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388fc0] width 1280 pitch 5120 (/4 1280) >[652826.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb830] >[652826.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb830] width 1280 pitch 5120 (/4 1280) >[652826.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7e3a0] >[652826.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7e3a0] width 1280 pitch 5120 (/4 1280) >[653371.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3612ad0] >[653371.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3612ad0] width 1280 pitch 5120 (/4 1280) >[653372.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338aa60] >[653372.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338aa60] width 1280 pitch 5120 (/4 1280) >[653373.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341eda0] >[653373.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341eda0] width 1280 pitch 5120 (/4 1280) >[653373.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[653373.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[653373.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341eda0] >[653373.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341eda0] width 1280 pitch 5120 (/4 1280) >[653785.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363ebd0] >[653785.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363ebd0] width 1280 pitch 5120 (/4 1280) >[653785.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414d30] >[653785.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414d30] width 1280 pitch 5120 (/4 1280) >[653785.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363ebd0] >[653785.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363ebd0] width 1280 pitch 5120 (/4 1280) >[653785.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414d30] >[653785.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414d30] width 1280 pitch 5120 (/4 1280) >[654525.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3e70] >[654525.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3e70] width 1280 pitch 5120 (/4 1280) >[655320.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655320.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655320.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d7d90] >[655320.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d7d90] width 1280 pitch 5120 (/4 1280) >[655320.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655320.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655320.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655320.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655320.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655320.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655320.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f71f0] >[655320.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f71f0] width 1280 pitch 5120 (/4 1280) >[655321.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655321.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655321.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655321.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655321.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655321.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655321.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655321.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655322.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655322.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655322.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655322.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655322.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655322.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655322.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655322.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655322.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0310] >[655322.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0310] width 1280 pitch 5120 (/4 1280) >[655322.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655322.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655325.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f71f0] >[655325.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f71f0] width 1280 pitch 5120 (/4 1280) >[655325.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475eb0] >[655325.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475eb0] width 1280 pitch 5120 (/4 1280) >[655325.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364e390] >[655325.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364e390] width 1280 pitch 5120 (/4 1280) >[655325.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3612880] >[655325.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3612880] width 1280 pitch 5120 (/4 1280) >[655325.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x459fe80] >[655325.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x459fe80] width 1280 pitch 5120 (/4 1280) >[655325.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3475eb0] >[655325.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3475eb0] width 1280 pitch 5120 (/4 1280) >[655325.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3620a10] >[655325.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3620a10] width 1280 pitch 5120 (/4 1280) >[655325.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d99f0] >[655325.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d99f0] width 1280 pitch 5120 (/4 1280) >[655326.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3510] >[655326.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3510] width 1280 pitch 5120 (/4 1280) >[655326.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655326.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655327.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3510] >[655327.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3510] width 1280 pitch 5120 (/4 1280) >[655327.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655327.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655327.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d99f0] >[655327.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d99f0] width 1280 pitch 5120 (/4 1280) >[655328.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1d20] >[655328.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1d20] width 1280 pitch 5120 (/4 1280) >[655328.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04c30] >[655328.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04c30] width 1280 pitch 5120 (/4 1280) >[655328.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691970] >[655328.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691970] width 1280 pitch 5120 (/4 1280) >[655328.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04c30] >[655328.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04c30] width 1280 pitch 5120 (/4 1280) >[655328.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691970] >[655328.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691970] width 1280 pitch 5120 (/4 1280) >[655328.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04c30] >[655328.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04c30] width 1280 pitch 5120 (/4 1280) >[655328.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691970] >[655328.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691970] width 1280 pitch 5120 (/4 1280) >[655328.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c04c30] >[655328.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c04c30] width 1280 pitch 5120 (/4 1280) >[655334.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[655334.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[655541.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[655541.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[655541.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330a9a0] >[655541.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330a9a0] width 1280 pitch 5120 (/4 1280) >[655541.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36326d0] >[655541.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36326d0] width 1280 pitch 5120 (/4 1280) >[655541.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330a9a0] >[655541.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330a9a0] width 1280 pitch 5120 (/4 1280) >[655542.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[655542.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[655543.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[655543.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[655543.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abd5f0] >[655543.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abd5f0] width 1280 pitch 5120 (/4 1280) >[655543.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1e40] >[655543.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1e40] width 1280 pitch 5120 (/4 1280) >[656707.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359bf00] >[656707.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359bf00] width 1280 pitch 5120 (/4 1280) >[656834.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35791a0] >[656834.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35791a0] width 1280 pitch 5120 (/4 1280) >[656882.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eb530] >[656882.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eb530] width 1280 pitch 5120 (/4 1280) >[656882.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adb5d0] >[656882.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adb5d0] width 1280 pitch 5120 (/4 1280) >[656883.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ae10] >[656883.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ae10] width 1280 pitch 5120 (/4 1280) >[656883.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29890] >[656883.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29890] width 1280 pitch 5120 (/4 1280) >[656883.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bca820] >[656883.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bca820] width 1280 pitch 5120 (/4 1280) >[656883.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29890] >[656883.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29890] width 1280 pitch 5120 (/4 1280) >[656998.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[656998.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[656998.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ae10] >[656998.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ae10] width 1280 pitch 5120 (/4 1280) >[656998.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35852e0] >[656998.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35852e0] width 1280 pitch 5120 (/4 1280) >[656998.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3414360] >[656998.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3414360] width 1280 pitch 5120 (/4 1280) >[656999.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34142e0] >[656999.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34142e0] width 1280 pitch 5120 (/4 1280) >[656999.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349ed40] >[656999.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349ed40] width 1280 pitch 5120 (/4 1280) >[657000.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34142e0] >[657000.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34142e0] width 1280 pitch 5120 (/4 1280) >[657001.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253b40] >[657001.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253b40] width 1280 pitch 5120 (/4 1280) >[657001.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[657001.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[657001.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253b40] >[657001.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253b40] width 1280 pitch 5120 (/4 1280) >[657014.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[657014.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[657021.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[657021.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[657021.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9aa0] >[657021.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9aa0] width 1280 pitch 5120 (/4 1280) >[657023.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[657023.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[657023.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[657023.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[657023.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[657023.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[657023.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[657023.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[657039.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[657039.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[657039.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[657039.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[657042.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d100] >[657042.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d100] width 1280 pitch 5120 (/4 1280) >[657042.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657042.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657042.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fcd20] >[657042.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fcd20] width 1280 pitch 5120 (/4 1280) >[657042.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657042.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657049.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9470] >[657049.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9470] width 1280 pitch 5120 (/4 1280) >[657050.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeaf0] >[657050.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeaf0] width 1280 pitch 5120 (/4 1280) >[657050.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[657050.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[657050.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[657050.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[657050.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c29ee0] >[657050.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c29ee0] width 1280 pitch 5120 (/4 1280) >[657050.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fcd20] >[657050.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fcd20] width 1280 pitch 5120 (/4 1280) >[657056.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ae10] >[657056.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ae10] width 1280 pitch 5120 (/4 1280) >[657056.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9470] >[657056.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9470] width 1280 pitch 5120 (/4 1280) >[657061.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[657061.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[657061.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330a9a0] >[657061.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330a9a0] width 1280 pitch 5120 (/4 1280) >[657061.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd060] >[657061.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd060] width 1280 pitch 5120 (/4 1280) >[657061.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0bbb0] >[657061.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0bbb0] width 1280 pitch 5120 (/4 1280) >[657107.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[657107.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[657107.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[657107.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[657110.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657110.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657110.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657110.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657110.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657110.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657110.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657110.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657150.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346a7f0] >[657150.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346a7f0] width 1280 pitch 5120 (/4 1280) >[657150.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657150.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657150.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366a740] >[657150.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366a740] width 1280 pitch 5120 (/4 1280) >[657150.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657150.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657170.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc310] >[657170.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc310] width 1280 pitch 5120 (/4 1280) >[657170.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[657170.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[657170.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fcd80] >[657170.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fcd80] width 1280 pitch 5120 (/4 1280) >[657170.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[657170.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[657193.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc310] >[657193.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc310] width 1280 pitch 5120 (/4 1280) >[657193.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adb2f0] >[657193.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adb2f0] width 1280 pitch 5120 (/4 1280) >[657193.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[657193.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[657193.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9aa0] >[657193.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9aa0] width 1280 pitch 5120 (/4 1280) >[657197.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[657197.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[657197.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[657197.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[657198.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88450] >[657198.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88450] width 1280 pitch 5120 (/4 1280) >[657198.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8470] >[657198.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8470] width 1280 pitch 5120 (/4 1280) >[657213.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bafcd0] >[657213.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bafcd0] width 1280 pitch 5120 (/4 1280) >[657213.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[657213.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[657215.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[657215.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[657215.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8070] >[657215.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8070] width 1280 pitch 5120 (/4 1280) >[657215.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaf750] >[657215.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaf750] width 1280 pitch 5120 (/4 1280) >[657215.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238df0] >[657215.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238df0] width 1280 pitch 5120 (/4 1280) >[657223.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ff70] >[657223.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ff70] width 1280 pitch 5120 (/4 1280) >[657223.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358e570] >[657223.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358e570] width 1280 pitch 5120 (/4 1280) >[657225.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c3fb0] >[657225.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c3fb0] width 1280 pitch 5120 (/4 1280) >[657225.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657225.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657225.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3244950] >[657225.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3244950] width 1280 pitch 5120 (/4 1280) >[657225.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657225.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657229.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374d100] >[657229.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374d100] width 1280 pitch 5120 (/4 1280) >[657229.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b9aa0] >[657229.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b9aa0] width 1280 pitch 5120 (/4 1280) >[657232.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657232.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657233.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adb2f0] >[657233.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adb2f0] width 1280 pitch 5120 (/4 1280) >[657233.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346a7f0] >[657233.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346a7f0] width 1280 pitch 5120 (/4 1280) >[657233.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[657233.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[657301.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eb3b0] >[657301.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eb3b0] width 1280 pitch 5120 (/4 1280) >[657301.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bafcd0] >[657301.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bafcd0] width 1280 pitch 5120 (/4 1280) >[657307.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[657307.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[657307.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e78b0] >[657307.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e78b0] width 1280 pitch 5120 (/4 1280) >[657307.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ea0d0] >[657307.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ea0d0] width 1280 pitch 5120 (/4 1280) >[657307.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[657307.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[657335.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c9da0] >[657335.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c9da0] width 1280 pitch 5120 (/4 1280) >[657335.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657335.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657351.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[657351.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[657351.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeaf0] >[657351.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeaf0] width 1280 pitch 5120 (/4 1280) >[657351.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3301550] >[657351.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3301550] width 1280 pitch 5120 (/4 1280) >[657351.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3714f80] >[657351.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3714f80] width 1280 pitch 5120 (/4 1280) >[657381.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[657381.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[657381.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[657381.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[657396.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adb390] >[657396.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adb390] width 1280 pitch 5120 (/4 1280) >[657396.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f72a0] >[657396.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f72a0] width 1280 pitch 5120 (/4 1280) >[657396.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca0f10] >[657396.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca0f10] width 1280 pitch 5120 (/4 1280) >[657396.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362dad0] >[657396.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362dad0] width 1280 pitch 5120 (/4 1280) >[657398.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338aa60] >[657398.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338aa60] width 1280 pitch 5120 (/4 1280) >[657398.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331ff70] >[657398.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331ff70] width 1280 pitch 5120 (/4 1280) >[657403.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333ae10] >[657404.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333ae10] width 1280 pitch 5120 (/4 1280) >[657404.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338db40] >[657404.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338db40] width 1280 pitch 5120 (/4 1280) >[657404.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36218b0] >[657404.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36218b0] width 1280 pitch 5120 (/4 1280) >[657404.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d7c40] >[657404.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d7c40] width 1280 pitch 5120 (/4 1280) >[657509.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230fd0] >[657509.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230fd0] width 1280 pitch 5120 (/4 1280) >[657510.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230fd0] >[657510.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230fd0] width 1280 pitch 5120 (/4 1280) >[657510.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366a960] >[657510.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366a960] width 1280 pitch 5120 (/4 1280) >[657510.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeaf0] >[657510.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeaf0] width 1280 pitch 5120 (/4 1280) >[657510.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[657510.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[657513.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[657513.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[657514.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691790] >[657514.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691790] width 1280 pitch 5120 (/4 1280) >[657514.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691730] >[657514.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691730] width 1280 pitch 5120 (/4 1280) >[657514.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3691790] >[657514.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3691790] width 1280 pitch 5120 (/4 1280) >[659017.263] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[659017.263] (II) RADEON(0): Using hsync ranges from config file >[659017.263] (II) RADEON(0): Using vrefresh ranges from config file >[659017.263] (II) RADEON(0): Printing DDC gathered Modelines: >[659017.263] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[659017.263] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[659017.263] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[659017.263] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[659017.263] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[659017.263] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[659017.263] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[659017.263] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[659017.263] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[659017.263] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[659107.535] (II) RADEON(0): RADEONSaveScreen(2) >[659107.535] (II) RADEON(0): RADEONSaveScreen(0) >[660481.051] (II) RADEON(0): RADEONSaveScreen(1) >[660612.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd280] >[660612.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd280] width 1280 pitch 5120 (/4 1280) >[661171.536] (II) RADEON(0): RADEONSaveScreen(2) >[661171.536] (II) RADEON(0): RADEONSaveScreen(0) >[667964.208] (II) RADEON(0): RADEONSaveScreen(1) >[667976.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb010] >[667976.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb010] width 1280 pitch 5120 (/4 1280) >[668579.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b2c50] >[668579.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b2c50] width 1280 pitch 5120 (/4 1280) >[668590.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b2c50] >[668590.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b2c50] width 1280 pitch 5120 (/4 1280) >[668590.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b84f0] >[668590.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b84f0] width 1280 pitch 5120 (/4 1280) >[668590.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860b0] >[668590.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860b0] width 1280 pitch 5120 (/4 1280) >[668591.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45860b0] >[668591.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45860b0] width 1280 pitch 5120 (/4 1280) >[668614.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[668614.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[668615.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a7ed0] >[668615.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a7ed0] width 1280 pitch 5120 (/4 1280) >[668615.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a54a0] >[668615.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a54a0] width 1280 pitch 5120 (/4 1280) >[668615.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a7ed0] >[668615.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a7ed0] width 1280 pitch 5120 (/4 1280) >[668616.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a7e30] >[668616.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a7e30] width 1280 pitch 5120 (/4 1280) >[668617.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c075b0] >[668617.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c075b0] width 1280 pitch 5120 (/4 1280) >[668617.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336e210] >[668617.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336e210] width 1280 pitch 5120 (/4 1280) >[668617.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336e210] >[668617.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336e210] width 1280 pitch 5120 (/4 1280) >[668621.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37253c0] >[668621.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37253c0] width 1280 pitch 5120 (/4 1280) >[668621.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[668621.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[668621.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[668621.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[668621.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[668621.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[668621.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[668621.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[668621.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[668621.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[668621.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32beac0] >[668621.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32beac0] width 1280 pitch 5120 (/4 1280) >[668626.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eeb50] >[668626.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eeb50] width 1280 pitch 5120 (/4 1280) >[668626.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[668626.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[668626.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c7f30] >[668626.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c7f30] width 1280 pitch 5120 (/4 1280) >[668626.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8cf0] >[668626.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8cf0] width 1280 pitch 5120 (/4 1280) >[669589.735] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[669589.735] (II) RADEON(0): Using hsync ranges from config file >[669589.735] (II) RADEON(0): Using vrefresh ranges from config file >[669589.735] (II) RADEON(0): Printing DDC gathered Modelines: >[669589.735] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[669589.735] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[669589.735] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[669589.735] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[669589.735] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[669589.735] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[669589.736] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[669589.736] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[669589.736] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[669589.736] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[669679.554] (II) RADEON(0): RADEONSaveScreen(2) >[669679.555] (II) RADEON(0): RADEONSaveScreen(0) >[674003.746] (II) RADEON(0): RADEONSaveScreen(1) >[674003.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356dcb0] >[674003.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356dcb0] width 1280 pitch 5120 (/4 1280) >[674693.558] (II) RADEON(0): RADEONSaveScreen(2) >[674693.558] (II) RADEON(0): RADEONSaveScreen(0) >[677094.817] (II) RADEON(0): RADEONSaveScreen(1) >[677097.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356da90] >[677097.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356da90] width 1280 pitch 5120 (/4 1280) >[677099.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356da90] >[677099.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356da90] width 1280 pitch 5120 (/4 1280) >[677100.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356da90] >[677100.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356da90] width 1280 pitch 5120 (/4 1280) >[677100.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45827c0] >[677100.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45827c0] width 1280 pitch 5120 (/4 1280) >[677100.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582870] >[677100.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582870] width 1280 pitch 5120 (/4 1280) >[677108.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9350] >[677108.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9350] width 1280 pitch 5120 (/4 1280) >[677109.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[677109.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[677109.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[677109.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[677110.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba66f0] >[677110.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba66f0] width 1280 pitch 5120 (/4 1280) >[677329.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34988a0] >[677329.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34988a0] width 1280 pitch 5120 (/4 1280) >[677336.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3628400] >[677336.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3628400] width 1280 pitch 5120 (/4 1280) >[677742.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9470] >[677742.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9470] width 1280 pitch 5120 (/4 1280) >[677743.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c27440] >[677743.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c27440] width 1280 pitch 5120 (/4 1280) >[677743.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[677743.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[677743.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c27440] >[677743.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c27440] width 1280 pitch 5120 (/4 1280) >[677753.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606450] >[677753.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606450] width 1280 pitch 5120 (/4 1280) >[677753.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409fd0] >[677753.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409fd0] width 1280 pitch 5120 (/4 1280) >[677753.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3222140] >[677753.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3222140] width 1280 pitch 5120 (/4 1280) >[677753.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be6860] >[677753.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be6860] width 1280 pitch 5120 (/4 1280) >[677795.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36548a0] >[677795.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36548a0] width 1280 pitch 5120 (/4 1280) >[677795.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[677795.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[677796.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[677796.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[677796.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364d290] >[677796.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364d290] width 1280 pitch 5120 (/4 1280) >[677796.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[677796.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[677797.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[677797.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[677797.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9470] >[677797.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9470] width 1280 pitch 5120 (/4 1280) >[677797.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6380] >[677797.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6380] width 1280 pitch 5120 (/4 1280) >[677809.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d9470] >[677809.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d9470] width 1280 pitch 5120 (/4 1280) >[678059.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370eaf0] >[678059.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370eaf0] width 1280 pitch 5120 (/4 1280) >[678059.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3396ca0] >[678059.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3396ca0] width 1280 pitch 5120 (/4 1280) >[678083.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[678083.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[678083.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370eaf0] >[678083.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370eaf0] width 1280 pitch 5120 (/4 1280) >[678083.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e4cb0] >[678083.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e4cb0] width 1280 pitch 5120 (/4 1280) >[678083.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370eaf0] >[678083.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370eaf0] width 1280 pitch 5120 (/4 1280) >[678137.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d4de0] >[678137.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d4de0] width 1280 pitch 5120 (/4 1280) >[678137.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[678137.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[678137.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[678137.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[678137.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54310] >[678137.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54310] width 1280 pitch 5120 (/4 1280) >[678139.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fbd60] >[678139.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fbd60] width 1280 pitch 5120 (/4 1280) >[678139.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54310] >[678139.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54310] width 1280 pitch 5120 (/4 1280) >[678139.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32626d0] >[678139.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32626d0] width 1280 pitch 5120 (/4 1280) >[678139.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54310] >[678139.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54310] width 1280 pitch 5120 (/4 1280) >[678139.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34988a0] >[678139.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34988a0] width 1280 pitch 5120 (/4 1280) >[678140.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e970] >[678140.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e970] width 1280 pitch 5120 (/4 1280) >[678140.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[678140.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[678140.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3326f40] >[678140.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3326f40] width 1280 pitch 5120 (/4 1280) >[678142.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338aa60] >[678142.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338aa60] width 1280 pitch 5120 (/4 1280) >[678142.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[678142.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[678142.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3393710] >[678142.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3393710] width 1280 pitch 5120 (/4 1280) >[678142.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[678142.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[678144.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d0e70] >[678144.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d0e70] width 1280 pitch 5120 (/4 1280) >[678144.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[678144.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[678144.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[678144.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[678144.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb47e0] >[678144.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb47e0] width 1280 pitch 5120 (/4 1280) >[678209.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364d290] >[678209.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364d290] width 1280 pitch 5120 (/4 1280) >[678209.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253b40] >[678209.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253b40] width 1280 pitch 5120 (/4 1280) >[678209.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5910] >[678209.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5910] width 1280 pitch 5120 (/4 1280) >[678209.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253b40] >[678209.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253b40] width 1280 pitch 5120 (/4 1280) >[678303.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5910] >[678303.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5910] width 1280 pitch 5120 (/4 1280) >[678303.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5910] >[678303.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5910] width 1280 pitch 5120 (/4 1280) >[678303.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[678303.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[678303.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5910] >[678303.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5910] width 1280 pitch 5120 (/4 1280) >[679005.451] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[679005.451] (II) RADEON(0): Using hsync ranges from config file >[679005.451] (II) RADEON(0): Using vrefresh ranges from config file >[679005.451] (II) RADEON(0): Printing DDC gathered Modelines: >[679005.451] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[679005.451] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[679005.451] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[679005.451] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[679005.451] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[679005.451] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[679005.451] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[679005.451] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[679005.451] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[679005.451] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[679095.536] (II) RADEON(0): RADEONSaveScreen(2) >[679095.536] (II) RADEON(0): RADEONSaveScreen(0) >[679984.450] (II) RADEON(0): RADEONSaveScreen(1) >[679987.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341050] >[679987.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341050] width 1280 pitch 5120 (/4 1280) >[680052.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590e60] >[680052.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590e60] width 1280 pitch 5120 (/4 1280) >[680052.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[680052.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[680052.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f6a0] >[680052.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f6a0] width 1280 pitch 5120 (/4 1280) >[680052.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[680052.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[680056.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4bb0] >[680056.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4bb0] width 1280 pitch 5120 (/4 1280) >[680056.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32626d0] >[680056.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32626d0] width 1280 pitch 5120 (/4 1280) >[680056.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364d290] >[680056.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364d290] width 1280 pitch 5120 (/4 1280) >[680056.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4bb0] >[680056.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4bb0] width 1280 pitch 5120 (/4 1280) >[680067.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32626d0] >[680067.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32626d0] width 1280 pitch 5120 (/4 1280) >[680067.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae7530] >[680067.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae7530] width 1280 pitch 5120 (/4 1280) >[680067.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3324e40] >[680067.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3324e40] width 1280 pitch 5120 (/4 1280) >[680067.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae7530] >[680067.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae7530] width 1280 pitch 5120 (/4 1280) >[680671.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4070] >[680671.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4070] width 1280 pitch 5120 (/4 1280) >[680671.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d42d0] >[680671.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d42d0] width 1280 pitch 5120 (/4 1280) >[680672.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4070] >[680672.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4070] width 1280 pitch 5120 (/4 1280) >[680672.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d42d0] >[680672.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d42d0] width 1280 pitch 5120 (/4 1280) >[680672.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[680672.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[680672.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[680672.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[680675.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba930] >[680675.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba930] width 1280 pitch 5120 (/4 1280) >[680675.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[680675.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[680675.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363cb0] >[680675.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363cb0] width 1280 pitch 5120 (/4 1280) >[680675.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[680675.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[680736.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca87d0] >[680736.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca87d0] width 1280 pitch 5120 (/4 1280) >[680736.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b570] >[680736.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b570] width 1280 pitch 5120 (/4 1280) >[680750.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9f310] >[680750.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9f310] width 1280 pitch 5120 (/4 1280) >[680751.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9f310] >[680751.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9f310] width 1280 pitch 5120 (/4 1280) >[680751.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab7f0] >[680751.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab7f0] width 1280 pitch 5120 (/4 1280) >[681351.272] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[681351.273] (II) RADEON(0): Using hsync ranges from config file >[681351.273] (II) RADEON(0): Using vrefresh ranges from config file >[681351.273] (II) RADEON(0): Printing DDC gathered Modelines: >[681351.273] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[681351.273] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[681351.273] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[681351.273] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[681351.273] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[681351.273] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[681351.273] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[681351.273] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[681351.273] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[681351.273] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[681441.536] (II) RADEON(0): RADEONSaveScreen(2) >[681441.536] (II) RADEON(0): RADEONSaveScreen(0) >[685604.450] (II) RADEON(0): RADEONSaveScreen(1) >[685604.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373e790] >[685604.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373e790] width 1280 pitch 5120 (/4 1280) >[685607.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[685607.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[685609.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325760] >[685609.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325760] width 1280 pitch 5120 (/4 1280) >[685609.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8080] >[685609.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8080] width 1280 pitch 5120 (/4 1280) >[685609.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325760] >[685609.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325760] width 1280 pitch 5120 (/4 1280) >[685609.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3333ae0] >[685609.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3333ae0] width 1280 pitch 5120 (/4 1280) >[685609.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685609.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685609.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[685609.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[685609.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685609.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685609.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[685609.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[685609.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685609.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685609.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[685610.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[685610.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685610.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685610.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[685610.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[685610.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685610.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685610.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[685610.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[685610.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685610.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685610.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325760] >[685610.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325760] width 1280 pitch 5120 (/4 1280) >[685610.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685610.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[685610.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325760] >[685610.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325760] width 1280 pitch 5120 (/4 1280) >[685610.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[685610.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[686654.822] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[686654.822] (II) RADEON(0): Using hsync ranges from config file >[686654.822] (II) RADEON(0): Using vrefresh ranges from config file >[686654.822] (II) RADEON(0): Printing DDC gathered Modelines: >[686654.822] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[686654.822] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[686654.822] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[686654.822] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[686654.822] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[686654.822] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[686654.822] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[686654.822] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[686654.822] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[686654.822] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[686745.550] (II) RADEON(0): RADEONSaveScreen(2) >[686745.550] (II) RADEON(0): RADEONSaveScreen(0) >[687791.506] (II) RADEON(0): RADEONSaveScreen(1) >[687866.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3413660] >[687866.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3413660] width 1280 pitch 5120 (/4 1280) >[687870.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3413660] >[687870.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3413660] width 1280 pitch 5120 (/4 1280) >[687870.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683990] >[687870.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683990] width 1280 pitch 5120 (/4 1280) >[687870.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b9f20] >[687870.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b9f20] width 1280 pitch 5120 (/4 1280) >[687870.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683990] >[687870.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683990] width 1280 pitch 5120 (/4 1280) >[687871.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb32b0] >[687871.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb32b0] width 1280 pitch 5120 (/4 1280) >[687871.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[687871.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[687871.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3413660] >[687871.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3413660] width 1280 pitch 5120 (/4 1280) >[687871.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[687871.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[687872.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3396ca0] >[687873.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3396ca0] width 1280 pitch 5120 (/4 1280) >[687873.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366a610] >[687873.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366a610] width 1280 pitch 5120 (/4 1280) >[687873.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3396ca0] >[687873.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3396ca0] width 1280 pitch 5120 (/4 1280) >[687971.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab010] >[687971.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab010] width 1280 pitch 5120 (/4 1280) >[687979.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b570] >[687979.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b570] width 1280 pitch 5120 (/4 1280) >[687990.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a41f0] >[687990.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a41f0] width 1280 pitch 5120 (/4 1280) >[687990.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd760] >[687990.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd760] width 1280 pitch 5120 (/4 1280) >[687992.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5f90] >[687992.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5f90] width 1280 pitch 5120 (/4 1280) >[687992.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3308c50] >[687992.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3308c50] width 1280 pitch 5120 (/4 1280) >[688000.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45965a0] >[688000.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45965a0] width 1280 pitch 5120 (/4 1280) >[688000.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45965a0] >[688000.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45965a0] width 1280 pitch 5120 (/4 1280) >[688002.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649ab0] >[688002.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649ab0] width 1280 pitch 5120 (/4 1280) >[688002.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3388aa0] >[688002.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3388aa0] width 1280 pitch 5120 (/4 1280) >[688008.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469610] >[688008.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469610] width 1280 pitch 5120 (/4 1280) >[688008.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3331c90] >[688008.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3331c90] width 1280 pitch 5120 (/4 1280) >[688009.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d7ad0] >[688009.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d7ad0] width 1280 pitch 5120 (/4 1280) >[688022.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f680] >[688022.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f680] width 1280 pitch 5120 (/4 1280) >[688022.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc230] >[688022.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc230] width 1280 pitch 5120 (/4 1280) >[688049.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3367a30] >[688049.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3367a30] width 1280 pitch 5120 (/4 1280) >[688049.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3677a20] >[688049.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3677a20] width 1280 pitch 5120 (/4 1280) >[688054.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f680] >[688054.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f680] width 1280 pitch 5120 (/4 1280) >[688056.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3645620] >[688056.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3645620] width 1280 pitch 5120 (/4 1280) >[688056.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c08640] >[688056.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c08640] width 1280 pitch 5120 (/4 1280) >[688060.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb99a0] >[688060.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb99a0] width 1280 pitch 5120 (/4 1280) >[688061.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ac80] >[688061.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ac80] width 1280 pitch 5120 (/4 1280) >[688062.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f680] >[688062.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f680] width 1280 pitch 5120 (/4 1280) >[688062.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33889e0] >[688062.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33889e0] width 1280 pitch 5120 (/4 1280) >[688062.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3734e50] >[688062.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3734e50] width 1280 pitch 5120 (/4 1280) >[688073.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3707630] >[688073.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3707630] width 1280 pitch 5120 (/4 1280) >[688076.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469610] >[688076.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469610] width 1280 pitch 5120 (/4 1280) >[688076.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e2a00] >[688076.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e2a00] width 1280 pitch 5120 (/4 1280) >[688084.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335e4e0] >[688084.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335e4e0] width 1280 pitch 5120 (/4 1280) >[688084.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db6d0] >[688084.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db6d0] width 1280 pitch 5120 (/4 1280) >[688086.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ab230] >[688086.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ab230] width 1280 pitch 5120 (/4 1280) >[688086.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f98d0] >[688086.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f98d0] width 1280 pitch 5120 (/4 1280) >[688091.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374aa90] >[688091.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374aa90] width 1280 pitch 5120 (/4 1280) >[688091.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3755150] >[688091.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3755150] width 1280 pitch 5120 (/4 1280) >[688099.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34cb190] >[688099.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34cb190] width 1280 pitch 5120 (/4 1280) >[688099.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3706c00] >[688099.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3706c00] width 1280 pitch 5120 (/4 1280) >[688099.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae5fe0] >[688099.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae5fe0] width 1280 pitch 5120 (/4 1280) >[688099.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33edc90] >[688099.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33edc90] width 1280 pitch 5120 (/4 1280) >[688106.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b7280] >[688106.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b7280] width 1280 pitch 5120 (/4 1280) >[688121.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e2950] >[688121.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e2950] width 1280 pitch 5120 (/4 1280) >[688121.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36869b0] >[688121.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36869b0] width 1280 pitch 5120 (/4 1280) >[688121.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[688121.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[688121.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36869b0] >[688121.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36869b0] width 1280 pitch 5120 (/4 1280) >[688123.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ba910] >[688123.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ba910] width 1280 pitch 5120 (/4 1280) >[688123.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36869b0] >[688123.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36869b0] width 1280 pitch 5120 (/4 1280) >[688123.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73990] >[688123.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73990] width 1280 pitch 5120 (/4 1280) >[688123.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ba910] >[688123.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ba910] width 1280 pitch 5120 (/4 1280) >[688123.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f680] >[688123.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f680] width 1280 pitch 5120 (/4 1280) >[688123.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ac20] >[688123.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ac20] width 1280 pitch 5120 (/4 1280) >[688125.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362da10] >[688125.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362da10] width 1280 pitch 5120 (/4 1280) >[688125.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0530] >[688125.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0530] width 1280 pitch 5120 (/4 1280) >[688127.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349c990] >[688127.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349c990] width 1280 pitch 5120 (/4 1280) >[688127.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36869b0] >[688127.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36869b0] width 1280 pitch 5120 (/4 1280) >[688128.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362da10] >[688128.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362da10] width 1280 pitch 5120 (/4 1280) >[688129.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362da10] >[688129.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362da10] width 1280 pitch 5120 (/4 1280) >[688131.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688131.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688131.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688131.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688145.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688145.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688145.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688145.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688145.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688145.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688145.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688145.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688145.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688145.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688145.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688145.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688145.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688145.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688145.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688145.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688146.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688146.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688146.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688146.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688146.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688146.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688146.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688146.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688146.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688146.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688146.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688146.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688146.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688146.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688146.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3721930] >[688146.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3721930] width 1280 pitch 5120 (/4 1280) >[688146.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c737c0] >[688146.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c737c0] width 1280 pitch 5120 (/4 1280) >[688147.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3332080] >[688147.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3332080] width 1280 pitch 5120 (/4 1280) >[688147.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd8c0] >[688147.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd8c0] width 1280 pitch 5120 (/4 1280) >[688151.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba510] >[688151.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba510] width 1280 pitch 5120 (/4 1280) >[688156.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ba4d0] >[688156.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ba4d0] width 1280 pitch 5120 (/4 1280) >[688156.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35b9b20] >[688156.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35b9b20] width 1280 pitch 5120 (/4 1280) >[688156.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a5df0] >[688156.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a5df0] width 1280 pitch 5120 (/4 1280) >[688163.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33321e0] >[688163.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33321e0] width 1280 pitch 5120 (/4 1280) >[688163.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8b10] >[688163.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8b10] width 1280 pitch 5120 (/4 1280) >[688163.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36869b0] >[688163.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36869b0] width 1280 pitch 5120 (/4 1280) >[688169.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f0530] >[688169.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f0530] width 1280 pitch 5120 (/4 1280) >[688170.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300a70] >[688170.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300a70] width 1280 pitch 5120 (/4 1280) >[688170.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73ac0] >[688170.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73ac0] width 1280 pitch 5120 (/4 1280) >[688176.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[688176.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[688176.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0ac10] >[688176.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0ac10] width 1280 pitch 5120 (/4 1280) >[688176.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce100] >[688176.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce100] width 1280 pitch 5120 (/4 1280) >[688176.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3396ca0] >[688176.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3396ca0] width 1280 pitch 5120 (/4 1280) >[688685.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5700] >[688685.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5700] width 1280 pitch 5120 (/4 1280) >[688685.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da4a0] >[688685.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da4a0] width 1280 pitch 5120 (/4 1280) >[688685.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5700] >[688685.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5700] width 1280 pitch 5120 (/4 1280) >[688685.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da4a0] >[688685.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da4a0] width 1280 pitch 5120 (/4 1280) >[688687.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679bf0] >[688687.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679bf0] width 1280 pitch 5120 (/4 1280) >[688687.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5700] >[688687.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5700] width 1280 pitch 5120 (/4 1280) >[688687.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32314d0] >[688687.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32314d0] width 1280 pitch 5120 (/4 1280) >[688687.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5700] >[688687.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5700] width 1280 pitch 5120 (/4 1280) >[688689.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f5870] >[688689.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f5870] width 1280 pitch 5120 (/4 1280) >[688689.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5700] >[688689.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5700] width 1280 pitch 5120 (/4 1280) >[688879.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cb220] >[688879.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cb220] width 1280 pitch 5120 (/4 1280) >[688879.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[688879.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[688879.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457f3f0] >[688879.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457f3f0] width 1280 pitch 5120 (/4 1280) >[688879.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[688879.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[688880.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457f3f0] >[688880.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457f3f0] width 1280 pitch 5120 (/4 1280) >[688880.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[688880.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[688880.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da4a0] >[688880.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da4a0] width 1280 pitch 5120 (/4 1280) >[688880.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[688880.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689146.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a539e0] >[689146.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a539e0] width 1280 pitch 5120 (/4 1280) >[689149.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456e590] >[689149.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456e590] width 1280 pitch 5120 (/4 1280) >[689149.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae9620] >[689149.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae9620] width 1280 pitch 5120 (/4 1280) >[689151.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8020] >[689151.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8020] width 1280 pitch 5120 (/4 1280) >[689151.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff140] >[689151.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff140] width 1280 pitch 5120 (/4 1280) >[689158.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a52980] >[689158.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a52980] width 1280 pitch 5120 (/4 1280) >[689158.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a539e0] >[689158.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a539e0] width 1280 pitch 5120 (/4 1280) >[689161.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd580] >[689161.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd580] width 1280 pitch 5120 (/4 1280) >[689161.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427d20] >[689161.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427d20] width 1280 pitch 5120 (/4 1280) >[689167.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3459eb0] >[689167.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3459eb0] width 1280 pitch 5120 (/4 1280) >[689178.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff140] >[689178.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff140] width 1280 pitch 5120 (/4 1280) >[689178.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff140] >[689179.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff140] width 1280 pitch 5120 (/4 1280) >[689181.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bff140] >[689181.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bff140] width 1280 pitch 5120 (/4 1280) >[689181.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a15d0] >[689181.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a15d0] width 1280 pitch 5120 (/4 1280) >[689183.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf850] >[689183.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf850] width 1280 pitch 5120 (/4 1280) >[689198.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a1630] >[689198.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a1630] width 1280 pitch 5120 (/4 1280) >[689198.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7f30] >[689198.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7f30] width 1280 pitch 5120 (/4 1280) >[689198.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d4070] >[689198.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d4070] width 1280 pitch 5120 (/4 1280) >[689198.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d42d0] >[689198.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d42d0] width 1280 pitch 5120 (/4 1280) >[689203.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32391b0] >[689203.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32391b0] width 1280 pitch 5120 (/4 1280) >[689203.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d42d0] >[689203.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d42d0] width 1280 pitch 5120 (/4 1280) >[689203.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3427d20] >[689203.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3427d20] width 1280 pitch 5120 (/4 1280) >[689203.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469060] >[689204.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469060] width 1280 pitch 5120 (/4 1280) >[689204.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3163ec0] >[689204.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3163ec0] width 1280 pitch 5120 (/4 1280) >[689204.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce990] >[689204.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce990] width 1280 pitch 5120 (/4 1280) >[689210.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb79e0] >[689210.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb79e0] width 1280 pitch 5120 (/4 1280) >[689210.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3459b70] >[689210.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3459b70] width 1280 pitch 5120 (/4 1280) >[689211.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce990] >[689211.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce990] width 1280 pitch 5120 (/4 1280) >[689211.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa5740] >[689211.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa5740] width 1280 pitch 5120 (/4 1280) >[689212.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae9620] >[689212.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae9620] width 1280 pitch 5120 (/4 1280) >[689212.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae9620] >[689212.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae9620] width 1280 pitch 5120 (/4 1280) >[689212.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7f30] >[689212.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7f30] width 1280 pitch 5120 (/4 1280) >[689212.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356cf70] >[689212.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356cf70] width 1280 pitch 5120 (/4 1280) >[689213.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bf50] >[689213.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bf50] width 1280 pitch 5120 (/4 1280) >[689213.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb7f80] >[689213.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb7f80] width 1280 pitch 5120 (/4 1280) >[689213.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3468830] >[689213.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3468830] width 1280 pitch 5120 (/4 1280) >[689214.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb7f80] >[689214.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb7f80] width 1280 pitch 5120 (/4 1280) >[689214.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa5de0] >[689214.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa5de0] width 1280 pitch 5120 (/4 1280) >[689214.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469060] >[689214.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469060] width 1280 pitch 5120 (/4 1280) >[689214.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa5de0] >[689214.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa5de0] width 1280 pitch 5120 (/4 1280) >[689214.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae9620] >[689214.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae9620] width 1280 pitch 5120 (/4 1280) >[689215.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb7f80] >[689215.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb7f80] width 1280 pitch 5120 (/4 1280) >[689215.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469060] >[689215.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469060] width 1280 pitch 5120 (/4 1280) >[689217.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34664e0] >[689217.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34664e0] width 1280 pitch 5120 (/4 1280) >[689225.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469060] >[689225.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469060] width 1280 pitch 5120 (/4 1280) >[689226.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbd880] >[689226.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbd880] width 1280 pitch 5120 (/4 1280) >[689226.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa76a0] >[689226.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa76a0] width 1280 pitch 5120 (/4 1280) >[689226.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3469060] >[689226.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3469060] width 1280 pitch 5120 (/4 1280) >[689226.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cbd880] >[689226.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cbd880] width 1280 pitch 5120 (/4 1280) >[689226.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7f30] >[689226.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7f30] width 1280 pitch 5120 (/4 1280) >[689227.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669b10] >[689227.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669b10] width 1280 pitch 5120 (/4 1280) >[689227.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa76a0] >[689227.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa76a0] width 1280 pitch 5120 (/4 1280) >[689233.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45260] >[689233.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45260] width 1280 pitch 5120 (/4 1280) >[689233.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd7e0] >[689233.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd7e0] width 1280 pitch 5120 (/4 1280) >[689233.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364ff80] >[689233.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364ff80] width 1280 pitch 5120 (/4 1280) >[689276.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eb3b0] >[689277.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eb3b0] width 1280 pitch 5120 (/4 1280) >[689277.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3713130] >[689277.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3713130] width 1280 pitch 5120 (/4 1280) >[689289.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa47a0] >[689289.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa47a0] width 1280 pitch 5120 (/4 1280) >[689289.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341f7f0] >[689289.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341f7f0] width 1280 pitch 5120 (/4 1280) >[689335.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345ebc0] >[689335.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345ebc0] width 1280 pitch 5120 (/4 1280) >[689335.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x366dbe0] >[689335.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x366dbe0] width 1280 pitch 5120 (/4 1280) >[689340.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae71c0] >[689340.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae71c0] width 1280 pitch 5120 (/4 1280) >[689340.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382ed0] >[689340.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382ed0] width 1280 pitch 5120 (/4 1280) >[689340.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae71c0] >[689340.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae71c0] width 1280 pitch 5120 (/4 1280) >[689340.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382ed0] >[689340.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382ed0] width 1280 pitch 5120 (/4 1280) >[689370.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689370.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689370.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689370.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689370.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689370.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689370.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689370.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689384.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fac90] >[689384.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fac90] width 1280 pitch 5120 (/4 1280) >[689384.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689384.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689384.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba82e0] >[689384.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba82e0] width 1280 pitch 5120 (/4 1280) >[689384.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae71c0] >[689384.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae71c0] width 1280 pitch 5120 (/4 1280) >[689388.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eb400] >[689388.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eb400] width 1280 pitch 5120 (/4 1280) >[689388.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bee0] >[689388.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bee0] width 1280 pitch 5120 (/4 1280) >[689399.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bdf00] >[689399.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bdf00] width 1280 pitch 5120 (/4 1280) >[689399.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3337770] >[689399.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3337770] width 1280 pitch 5120 (/4 1280) >[689399.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fac90] >[689399.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fac90] width 1280 pitch 5120 (/4 1280) >[689399.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689399.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689406.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689406.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689406.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689406.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689406.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689406.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689406.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689406.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689414.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324af50] >[689414.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324af50] width 1280 pitch 5120 (/4 1280) >[689414.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3bfb0] >[689414.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3bfb0] width 1280 pitch 5120 (/4 1280) >[689414.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3641980] >[689414.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3641980] width 1280 pitch 5120 (/4 1280) >[689415.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258b10] >[689415.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258b10] width 1280 pitch 5120 (/4 1280) >[689440.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3492b80] >[689440.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3492b80] width 1280 pitch 5120 (/4 1280) >[689442.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4594500] >[689442.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4594500] width 1280 pitch 5120 (/4 1280) >[689442.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368c960] >[689442.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368c960] width 1280 pitch 5120 (/4 1280) >[689442.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124d00] >[689442.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124d00] width 1280 pitch 5120 (/4 1280) >[689442.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124d00] >[689442.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124d00] width 1280 pitch 5120 (/4 1280) >[689443.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124d00] >[689443.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124d00] width 1280 pitch 5120 (/4 1280) >[689443.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689443.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689443.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33524a0] >[689443.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33524a0] width 1280 pitch 5120 (/4 1280) >[689443.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a10f0] >[689443.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a10f0] width 1280 pitch 5120 (/4 1280) >[689467.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f6c40] >[689467.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f6c40] width 1280 pitch 5120 (/4 1280) >[689467.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3456940] >[689467.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3456940] width 1280 pitch 5120 (/4 1280) >[689489.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415900] >[689489.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415900] width 1280 pitch 5120 (/4 1280) >[689489.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b5a0] >[689489.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b5a0] width 1280 pitch 5120 (/4 1280) >[689489.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124d00] >[689489.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124d00] width 1280 pitch 5120 (/4 1280) >[689489.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b5a0] >[689489.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b5a0] width 1280 pitch 5120 (/4 1280) >[689490.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415900] >[689490.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415900] width 1280 pitch 5120 (/4 1280) >[689490.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc660] >[689490.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc660] width 1280 pitch 5120 (/4 1280) >[689490.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aac8c0] >[689490.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aac8c0] width 1280 pitch 5120 (/4 1280) >[689490.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc660] >[689490.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc660] width 1280 pitch 5120 (/4 1280) >[689491.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2c40] >[689491.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2c40] width 1280 pitch 5120 (/4 1280) >[689491.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689260] >[689491.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689260] width 1280 pitch 5120 (/4 1280) >[689492.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341fd60] >[689492.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341fd60] width 1280 pitch 5120 (/4 1280) >[689493.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689493.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689493.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415b40] >[689493.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415b40] width 1280 pitch 5120 (/4 1280) >[689493.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368c960] >[689493.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368c960] width 1280 pitch 5120 (/4 1280) >[689494.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689494.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689494.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a2c40] >[689494.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a2c40] width 1280 pitch 5120 (/4 1280) >[689494.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689494.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689540.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3714f80] >[689540.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3714f80] width 1280 pitch 5120 (/4 1280) >[689540.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689540.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689540.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345ad80] >[689540.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345ad80] width 1280 pitch 5120 (/4 1280) >[689540.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3593250] >[689540.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3593250] width 1280 pitch 5120 (/4 1280) >[689542.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689542.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689542.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689542.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689542.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689620.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689620.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689621.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa5830] >[689621.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa5830] width 1280 pitch 5120 (/4 1280) >[689621.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689621.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689621.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689621.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689621.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359d690] >[689621.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359d690] width 1280 pitch 5120 (/4 1280) >[689625.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa5830] >[689625.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa5830] width 1280 pitch 5120 (/4 1280) >[689625.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aac8c0] >[689625.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aac8c0] width 1280 pitch 5120 (/4 1280) >[689625.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689625.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689625.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382ed0] >[689625.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382ed0] width 1280 pitch 5120 (/4 1280) >[689625.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689625.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689625.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382ed0] >[689625.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382ed0] width 1280 pitch 5120 (/4 1280) >[689625.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689625.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689625.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382ed0] >[689625.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382ed0] width 1280 pitch 5120 (/4 1280) >[689625.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372eab0] >[689625.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372eab0] width 1280 pitch 5120 (/4 1280) >[689625.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3258b10] >[689625.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3258b10] width 1280 pitch 5120 (/4 1280) >[689625.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba82e0] >[689625.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba82e0] width 1280 pitch 5120 (/4 1280) >[689626.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5550] >[689626.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5550] width 1280 pitch 5120 (/4 1280) >[689626.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3714f80] >[689626.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3714f80] width 1280 pitch 5120 (/4 1280) >[689626.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aac8c0] >[689626.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aac8c0] width 1280 pitch 5120 (/4 1280) >[689626.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3714f80] >[689626.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3714f80] width 1280 pitch 5120 (/4 1280) >[689627.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4586ae0] >[689627.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4586ae0] width 1280 pitch 5120 (/4 1280) >[689627.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3372e90] >[689627.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3372e90] width 1280 pitch 5120 (/4 1280) >[689627.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a73d0] >[689627.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a73d0] width 1280 pitch 5120 (/4 1280) >[689627.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3372e90] >[689627.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3372e90] width 1280 pitch 5120 (/4 1280) >[689627.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3372e90] >[689627.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3372e90] width 1280 pitch 5120 (/4 1280) >[689627.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd6e20] >[689627.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd6e20] width 1280 pitch 5120 (/4 1280) >[689627.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befa90] >[689627.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befa90] width 1280 pitch 5120 (/4 1280) >[689627.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3153c30] >[689627.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3153c30] width 1280 pitch 5120 (/4 1280) >[689627.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3153fd0] >[689627.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3153fd0] width 1280 pitch 5120 (/4 1280) >[689627.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befa90] >[689627.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befa90] width 1280 pitch 5120 (/4 1280) >[689649.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a630] >[689649.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a630] width 1280 pitch 5120 (/4 1280) >[689651.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2ae50] >[689651.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2ae50] width 1280 pitch 5120 (/4 1280) >[689651.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a2e0] >[689651.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a2e0] width 1280 pitch 5120 (/4 1280) >[689651.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a4490] >[689651.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a4490] width 1280 pitch 5120 (/4 1280) >[689747.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3665780] >[689747.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3665780] width 1280 pitch 5120 (/4 1280) >[689750.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689750.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689785.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3714f80] >[689785.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3714f80] width 1280 pitch 5120 (/4 1280) >[689793.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bde040] >[689793.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bde040] width 1280 pitch 5120 (/4 1280) >[689793.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689793.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689793.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689793.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689793.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689793.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[689793.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[689793.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3befae0] >[689793.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3befae0] width 1280 pitch 5120 (/4 1280) >[689912.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36da4a0] >[689912.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36da4a0] width 1280 pitch 5120 (/4 1280) >[689912.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251260] >[689912.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251260] width 1280 pitch 5120 (/4 1280) >[689912.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415b40] >[689912.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415b40] width 1280 pitch 5120 (/4 1280) >[689912.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689912.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689914.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54310] >[689914.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54310] width 1280 pitch 5120 (/4 1280) >[689914.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4bb0] >[689914.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4bb0] width 1280 pitch 5120 (/4 1280) >[689915.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a10f0] >[689915.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a10f0] width 1280 pitch 5120 (/4 1280) >[689915.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3124d00] >[689915.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3124d00] width 1280 pitch 5120 (/4 1280) >[689932.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4bb0] >[689932.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4bb0] width 1280 pitch 5120 (/4 1280) >[689932.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409fd0] >[689932.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409fd0] width 1280 pitch 5120 (/4 1280) >[689932.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34159d0] >[689932.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34159d0] width 1280 pitch 5120 (/4 1280) >[689932.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409fd0] >[689932.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409fd0] width 1280 pitch 5120 (/4 1280) >[689951.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9910] >[689951.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9910] width 1280 pitch 5120 (/4 1280) >[689951.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb0fa0] >[689951.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb0fa0] width 1280 pitch 5120 (/4 1280) >[689951.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3253b40] >[689951.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3253b40] width 1280 pitch 5120 (/4 1280) >[689951.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415b40] >[689951.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415b40] width 1280 pitch 5120 (/4 1280) >[690297.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339f000] >[690297.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339f000] width 1280 pitch 5120 (/4 1280) >[690297.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f7020] >[690297.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f7020] width 1280 pitch 5120 (/4 1280) >[690323.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331aa80] >[690323.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331aa80] width 1280 pitch 5120 (/4 1280) >[690475.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3151ff0] >[690476.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3151ff0] width 1280 pitch 5120 (/4 1280) >[690493.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36955b0] >[690493.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36955b0] width 1280 pitch 5120 (/4 1280) >[690493.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2ada0] >[690493.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2ada0] width 1280 pitch 5120 (/4 1280) >[690493.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694030] >[690494.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694030] width 1280 pitch 5120 (/4 1280) >[690518.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409fd0] >[690518.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409fd0] width 1280 pitch 5120 (/4 1280) >[690518.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3409fd0] >[690518.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3409fd0] width 1280 pitch 5120 (/4 1280) >[690520.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694030] >[690520.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694030] width 1280 pitch 5120 (/4 1280) >[690520.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bee000] >[690520.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bee000] width 1280 pitch 5120 (/4 1280) >[690535.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323b4d0] >[690535.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323b4d0] width 1280 pitch 5120 (/4 1280) >[690535.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353d430] >[690535.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353d430] width 1280 pitch 5120 (/4 1280) >[690536.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353d430] >[690536.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353d430] width 1280 pitch 5120 (/4 1280) >[690537.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c15620] >[690537.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c15620] width 1280 pitch 5120 (/4 1280) >[690537.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36955b0] >[690537.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36955b0] width 1280 pitch 5120 (/4 1280) >[690537.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36954e0] >[690537.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36954e0] width 1280 pitch 5120 (/4 1280) >[690537.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f7020] >[690537.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f7020] width 1280 pitch 5120 (/4 1280) >[690537.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4581b50] >[690537.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4581b50] width 1280 pitch 5120 (/4 1280) >[690537.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ec930] >[690537.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ec930] width 1280 pitch 5120 (/4 1280) >[690537.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357e720] >[690537.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357e720] width 1280 pitch 5120 (/4 1280) >[690537.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b760] >[690537.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b760] width 1280 pitch 5120 (/4 1280) >[690537.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f7020] >[690537.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f7020] width 1280 pitch 5120 (/4 1280) >[690554.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x339efa0] >[690554.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x339efa0] width 1280 pitch 5120 (/4 1280) >[690554.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694030] >[690554.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694030] width 1280 pitch 5120 (/4 1280) >[690554.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2cab0] >[690554.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2cab0] width 1280 pitch 5120 (/4 1280) >[690554.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694030] >[690554.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694030] width 1280 pitch 5120 (/4 1280) >[690554.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415900] >[690554.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415900] width 1280 pitch 5120 (/4 1280) >[690584.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2cab0] >[690584.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2cab0] width 1280 pitch 5120 (/4 1280) >[690584.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3355270] >[690584.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3355270] width 1280 pitch 5120 (/4 1280) >[690584.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca9290] >[690584.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca9290] width 1280 pitch 5120 (/4 1280) >[690584.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ec930] >[690584.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ec930] width 1280 pitch 5120 (/4 1280) >[690647.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3664ec0] >[690648.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3664ec0] width 1280 pitch 5120 (/4 1280) >[690648.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3415980] >[690648.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3415980] width 1280 pitch 5120 (/4 1280) >[690658.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fb470] >[690658.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fb470] width 1280 pitch 5120 (/4 1280) >[690658.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456e0f0] >[690658.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456e0f0] width 1280 pitch 5120 (/4 1280) >[690658.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[690658.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[690658.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x456e0f0] >[690658.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x456e0f0] width 1280 pitch 5120 (/4 1280) >[690667.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[690667.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[690667.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d230] >[690667.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d230] width 1280 pitch 5120 (/4 1280) >[690700.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315ea80] >[690700.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315ea80] width 1280 pitch 5120 (/4 1280) >[690700.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2ca90] >[690700.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2ca90] width 1280 pitch 5120 (/4 1280) >[690700.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37535a0] >[690700.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37535a0] width 1280 pitch 5120 (/4 1280) >[690701.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d6760] >[690701.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d6760] width 1280 pitch 5120 (/4 1280) >[690763.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fb470] >[690763.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fb470] width 1280 pitch 5120 (/4 1280) >[690763.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59fa0] >[690763.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59fa0] width 1280 pitch 5120 (/4 1280) >[690763.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf24c0] >[690763.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf24c0] width 1280 pitch 5120 (/4 1280) >[690775.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369b850] >[690775.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369b850] width 1280 pitch 5120 (/4 1280) >[690775.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3243630] >[690775.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3243630] width 1280 pitch 5120 (/4 1280) >[690822.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37198a0] >[690822.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37198a0] width 1280 pitch 5120 (/4 1280) >[690822.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315ea80] >[690822.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315ea80] width 1280 pitch 5120 (/4 1280) >[690841.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[690841.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[690841.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x349d230] >[690841.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x349d230] width 1280 pitch 5120 (/4 1280) >[690841.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[690841.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[690841.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3e10] >[690841.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3e10] width 1280 pitch 5120 (/4 1280) >[690870.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3613e90] >[690871.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3613e90] width 1280 pitch 5120 (/4 1280) >[690871.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32621e0] >[690871.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32621e0] width 1280 pitch 5120 (/4 1280) >[690871.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315ea80] >[690871.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315ea80] width 1280 pitch 5120 (/4 1280) >[690871.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315ea80] >[690871.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315ea80] width 1280 pitch 5120 (/4 1280) >[690871.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa12e0] >[690871.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa12e0] width 1280 pitch 5120 (/4 1280) >[690872.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[690872.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[690872.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32621e0] >[690872.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32621e0] width 1280 pitch 5120 (/4 1280) >[690872.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[690872.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[691758.565] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[691758.565] (II) RADEON(0): Using hsync ranges from config file >[691758.565] (II) RADEON(0): Using vrefresh ranges from config file >[691758.566] (II) RADEON(0): Printing DDC gathered Modelines: >[691758.566] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[691758.566] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[691758.566] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[691758.566] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[691758.566] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[691758.566] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[691758.566] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[691758.566] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[691758.566] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[691758.566] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[691848.553] (II) RADEON(0): RADEONSaveScreen(2) >[691848.553] (II) RADEON(0): RADEONSaveScreen(0) >[697702.201] (II) RADEON(0): RADEONSaveScreen(1) >[697702.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f6f0] >[697702.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f6f0] width 1280 pitch 5120 (/4 1280) >[698722.536] (II) RADEON(0): RADEONSaveScreen(2) >[698722.536] (II) RADEON(0): RADEONSaveScreen(0) >[699097.727] (II) RADEON(0): RADEONSaveScreen(1) >[700282.536] (II) RADEON(0): RADEONSaveScreen(2) >[700282.536] (II) RADEON(0): RADEONSaveScreen(0) >[701862.859] (II) RADEON(0): RADEONSaveScreen(1) >[702592.542] (II) RADEON(0): RADEONSaveScreen(2) >[702592.542] (II) RADEON(0): RADEONSaveScreen(0) >[702928.420] (II) RADEON(0): RADEONSaveScreen(1) >[704216.540] (II) RADEON(0): RADEONSaveScreen(2) >[704216.540] (II) RADEON(0): RADEONSaveScreen(0) >[706080.352] (II) RADEON(0): RADEONSaveScreen(1) >[706782.536] (II) RADEON(0): RADEONSaveScreen(2) >[706782.537] (II) RADEON(0): RADEONSaveScreen(0) >[710096.363] (II) RADEON(0): RADEONSaveScreen(1) >[711267.536] (II) RADEON(0): RADEONSaveScreen(2) >[711267.536] (II) RADEON(0): RADEONSaveScreen(0) >[714725.352] (II) RADEON(0): RADEONSaveScreen(1) >[715415.540] (II) RADEON(0): RADEONSaveScreen(2) >[715415.540] (II) RADEON(0): RADEONSaveScreen(0) >[716954.521] (II) RADEON(0): RADEONSaveScreen(1) >[718756.536] (II) RADEON(0): RADEONSaveScreen(2) >[718756.536] (II) RADEON(0): RADEONSaveScreen(0) >[722980.513] (II) RADEON(0): RADEONSaveScreen(1) >[723824.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3240db0] >[723825.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3240db0] width 1280 pitch 5120 (/4 1280) >[724660.219] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[724660.219] (II) RADEON(0): Using hsync ranges from config file >[724660.219] (II) RADEON(0): Using vrefresh ranges from config file >[724660.219] (II) RADEON(0): Printing DDC gathered Modelines: >[724660.219] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[724660.219] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[724660.219] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[724660.219] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[724660.219] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[724660.219] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[724660.219] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[724660.219] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[724660.219] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[724660.219] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[724750.555] (II) RADEON(0): RADEONSaveScreen(2) >[724750.555] (II) RADEON(0): RADEONSaveScreen(0) >[759777.508] (II) RADEON(0): RADEONSaveScreen(1) >[759777.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3602290] >[759777.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3602290] width 1280 pitch 5120 (/4 1280) >[759781.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba5400] >[759781.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba5400] width 1280 pitch 5120 (/4 1280) >[760375.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3243b90] >[760375.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3243b90] width 1280 pitch 5120 (/4 1280) >[760376.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dbc20] >[760376.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dbc20] width 1280 pitch 5120 (/4 1280) >[760376.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b3c50] >[760376.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b3c50] width 1280 pitch 5120 (/4 1280) >[760376.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[760376.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[760376.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e9d0] >[760376.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e9d0] width 1280 pitch 5120 (/4 1280) >[760376.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[760376.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[760417.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[760417.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[760418.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e9d0] >[760418.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e9d0] width 1280 pitch 5120 (/4 1280) >[760418.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345c8f0] >[760418.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345c8f0] width 1280 pitch 5120 (/4 1280) >[760418.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e9d0] >[760418.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e9d0] width 1280 pitch 5120 (/4 1280) >[760441.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a52a20] >[760441.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a52a20] width 1280 pitch 5120 (/4 1280) >[760441.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfdd0] >[760441.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfdd0] width 1280 pitch 5120 (/4 1280) >[760599.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[760599.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[760599.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ee00] >[760599.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ee00] width 1280 pitch 5120 (/4 1280) >[760600.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[760600.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[760600.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a1a40] >[760600.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a1a40] width 1280 pitch 5120 (/4 1280) >[760600.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493390] >[760600.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493390] width 1280 pitch 5120 (/4 1280) >[760600.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493390] >[760600.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493390] width 1280 pitch 5120 (/4 1280) >[760615.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760615.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760615.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[760615.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[760615.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[760615.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[760615.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[760615.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[760615.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760615.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760615.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760615.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760615.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760615.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760615.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760615.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760616.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760616.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760616.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760616.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760616.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05b90] >[760616.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05b90] width 1280 pitch 5120 (/4 1280) >[760616.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760616.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760617.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[760617.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[760617.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[760617.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[760617.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760617.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760617.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[760617.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[760617.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3424690] >[760617.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3424690] width 1280 pitch 5120 (/4 1280) >[760617.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fb470] >[760617.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fb470] width 1280 pitch 5120 (/4 1280) >[760617.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c05b90] >[760618.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c05b90] width 1280 pitch 5120 (/4 1280) >[760618.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338c170] >[760618.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338c170] width 1280 pitch 5120 (/4 1280) >[760619.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aabe70] >[760619.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aabe70] width 1280 pitch 5120 (/4 1280) >[760619.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b7d0] >[760619.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b7d0] width 1280 pitch 5120 (/4 1280) >[760679.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760679.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760679.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493390] >[760679.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493390] width 1280 pitch 5120 (/4 1280) >[760679.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3630] >[760679.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3630] width 1280 pitch 5120 (/4 1280) >[760679.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493390] >[760679.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493390] width 1280 pitch 5120 (/4 1280) >[761107.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[761107.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[761121.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3329bf0] >[761121.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3329bf0] width 1280 pitch 5120 (/4 1280) >[761121.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36ba800] >[761121.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36ba800] width 1280 pitch 5120 (/4 1280) >[761121.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bf5b0] >[761121.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bf5b0] width 1280 pitch 5120 (/4 1280) >[761121.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[761121.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[761231.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4570cf0] >[761231.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4570cf0] width 1280 pitch 5120 (/4 1280) >[761456.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323fbf0] >[761456.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323fbf0] width 1280 pitch 5120 (/4 1280) >[761456.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761456.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761456.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bafe0] >[761456.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bafe0] width 1280 pitch 5120 (/4 1280) >[761456.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761456.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761459.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34bafe0] >[761459.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34bafe0] width 1280 pitch 5120 (/4 1280) >[761459.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761459.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761459.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0440] >[761459.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0440] width 1280 pitch 5120 (/4 1280) >[761459.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0440] >[761459.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0440] width 1280 pitch 5120 (/4 1280) >[761469.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761469.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761470.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761470.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761470.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[761470.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[761470.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3620] >[761470.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3620] width 1280 pitch 5120 (/4 1280) >[761491.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aea210] >[761491.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aea210] width 1280 pitch 5120 (/4 1280) >[761491.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ee00] >[761491.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ee00] width 1280 pitch 5120 (/4 1280) >[761491.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363b0f0] >[761491.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363b0f0] width 1280 pitch 5120 (/4 1280) >[761491.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ee00] >[761491.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ee00] width 1280 pitch 5120 (/4 1280) >[761547.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aea210] >[761547.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aea210] width 1280 pitch 5120 (/4 1280) >[761548.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6ee00] >[761548.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6ee00] width 1280 pitch 5120 (/4 1280) >[761548.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0440] >[761548.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0440] width 1280 pitch 5120 (/4 1280) >[761548.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[761548.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[761548.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aea210] >[761548.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aea210] width 1280 pitch 5120 (/4 1280) >[761549.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3153760] >[761549.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3153760] width 1280 pitch 5120 (/4 1280) >[761549.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3153760] >[761549.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3153760] width 1280 pitch 5120 (/4 1280) >[761549.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0200] >[761549.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0200] width 1280 pitch 5120 (/4 1280) >[761549.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c34db0] >[761549.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c34db0] width 1280 pitch 5120 (/4 1280) >[761561.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[761561.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[761561.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[761561.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[761561.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[761561.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[761561.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[761561.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[761562.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd530] >[761562.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd530] width 1280 pitch 5120 (/4 1280) >[762068.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b28ca0] >[762068.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b28ca0] width 1280 pitch 5120 (/4 1280) >[762074.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9eb00] >[762074.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9eb00] width 1280 pitch 5120 (/4 1280) >[762074.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b99570] >[762074.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b99570] width 1280 pitch 5120 (/4 1280) >[762074.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3461440] >[762074.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3461440] width 1280 pitch 5120 (/4 1280) >[762074.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34af050] >[762074.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34af050] width 1280 pitch 5120 (/4 1280) >[762115.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36585b0] >[762115.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36585b0] width 1280 pitch 5120 (/4 1280) >[762115.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d7950] >[762115.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d7950] width 1280 pitch 5120 (/4 1280) >[762116.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cce10] >[762116.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cce10] width 1280 pitch 5120 (/4 1280) >[762116.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c15620] >[762116.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c15620] width 1280 pitch 5120 (/4 1280) >[762116.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ccdb0] >[762116.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ccdb0] width 1280 pitch 5120 (/4 1280) >[762116.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[762116.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[762723.925] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[762723.926] (II) RADEON(0): Using hsync ranges from config file >[762723.926] (II) RADEON(0): Using vrefresh ranges from config file >[762723.926] (II) RADEON(0): Printing DDC gathered Modelines: >[762723.926] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[762723.926] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[762723.926] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[762723.926] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[762723.926] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[762723.926] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[762723.926] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[762723.926] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[762723.926] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[762723.926] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[762814.536] (II) RADEON(0): RADEONSaveScreen(2) >[762814.536] (II) RADEON(0): RADEONSaveScreen(0) >[764548.270] (II) RADEON(0): RADEONSaveScreen(1) >[764560.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[764560.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[764563.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[764563.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[764563.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764563.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764563.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36668b0] >[764564.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36668b0] width 1280 pitch 5120 (/4 1280) >[764564.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[764564.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[764564.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[764564.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[764564.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[764564.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[764564.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3477cb0] >[764564.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3477cb0] width 1280 pitch 5120 (/4 1280) >[764564.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[764564.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[764587.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[764587.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[764599.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[764599.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[764600.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[764600.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[764600.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c15620] >[764600.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c15620] width 1280 pitch 5120 (/4 1280) >[764600.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[764600.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[764602.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[764602.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[764602.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf8cc0] >[764602.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf8cc0] width 1280 pitch 5120 (/4 1280) >[764602.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b6970] >[764602.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b6970] width 1280 pitch 5120 (/4 1280) >[764603.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e9d0] >[764603.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e9d0] width 1280 pitch 5120 (/4 1280) >[764795.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b6970] >[764795.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b6970] width 1280 pitch 5120 (/4 1280) >[764798.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35774b0] >[764798.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35774b0] width 1280 pitch 5120 (/4 1280) >[764813.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457d7c0] >[764813.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457d7c0] width 1280 pitch 5120 (/4 1280) >[764828.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af04b0] >[764828.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af04b0] width 1280 pitch 5120 (/4 1280) >[764828.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b9ee0] >[764828.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b9ee0] width 1280 pitch 5120 (/4 1280) >[764828.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658fb0] >[764828.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658fb0] width 1280 pitch 5120 (/4 1280) >[764828.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b9ee0] >[764828.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b9ee0] width 1280 pitch 5120 (/4 1280) >[764828.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658fb0] >[764828.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658fb0] width 1280 pitch 5120 (/4 1280) >[764828.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b9ee0] >[764828.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b9ee0] width 1280 pitch 5120 (/4 1280) >[764828.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658fb0] >[764828.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658fb0] width 1280 pitch 5120 (/4 1280) >[764828.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b9ee0] >[764828.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b9ee0] width 1280 pitch 5120 (/4 1280) >[764828.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658fb0] >[764828.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658fb0] width 1280 pitch 5120 (/4 1280) >[764828.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32de970] >[764828.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32de970] width 1280 pitch 5120 (/4 1280) >[764828.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658fb0] >[764828.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658fb0] width 1280 pitch 5120 (/4 1280) >[764828.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340ef0] >[764828.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340ef0] width 1280 pitch 5120 (/4 1280) >[764828.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af04b0] >[764828.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af04b0] width 1280 pitch 5120 (/4 1280) >[764828.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3694200] >[764828.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3694200] width 1280 pitch 5120 (/4 1280) >[764847.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[764847.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[764855.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4335e70] >[764855.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4335e70] width 1280 pitch 5120 (/4 1280) >[764855.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4335e70] >[764855.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4335e70] width 1280 pitch 5120 (/4 1280) >[764855.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e0e40] >[764855.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e0e40] width 1280 pitch 5120 (/4 1280) >[764855.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a9f1b0] >[764855.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a9f1b0] width 1280 pitch 5120 (/4 1280) >[764857.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a9f1b0] >[764857.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a9f1b0] width 1280 pitch 5120 (/4 1280) >[764857.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af42d0] >[764857.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af42d0] width 1280 pitch 5120 (/4 1280) >[764857.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34fa950] >[764857.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34fa950] width 1280 pitch 5120 (/4 1280) >[764857.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af42d0] >[764857.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af42d0] width 1280 pitch 5120 (/4 1280) >[764858.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e0e40] >[764858.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e0e40] width 1280 pitch 5120 (/4 1280) >[764858.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a9f1b0] >[764858.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a9f1b0] width 1280 pitch 5120 (/4 1280) >[764858.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[764858.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[764858.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd73d0] >[764858.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd73d0] width 1280 pitch 5120 (/4 1280) >[764865.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a9f1b0] >[764865.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a9f1b0] width 1280 pitch 5120 (/4 1280) >[764865.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a529a0] >[764865.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a529a0] width 1280 pitch 5120 (/4 1280) >[764865.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[764865.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[764865.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd73d0] >[764865.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd73d0] width 1280 pitch 5120 (/4 1280) >[764870.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f8760] >[764870.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f8760] width 1280 pitch 5120 (/4 1280) >[764977.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433b0b0] >[764977.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433b0b0] width 1280 pitch 5120 (/4 1280) >[764977.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea470] >[764977.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea470] width 1280 pitch 5120 (/4 1280) >[764977.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3604980] >[764977.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3604980] width 1280 pitch 5120 (/4 1280) >[764977.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32ea470] >[764977.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32ea470] width 1280 pitch 5120 (/4 1280) >[764986.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1890] >[764986.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1890] width 1280 pitch 5120 (/4 1280) >[764986.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45692a0] >[764986.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45692a0] width 1280 pitch 5120 (/4 1280) >[764986.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45692a0] >[764986.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45692a0] width 1280 pitch 5120 (/4 1280) >[764986.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43346f0] >[764986.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43346f0] width 1280 pitch 5120 (/4 1280) >[764990.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1c4c0] >[764990.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1c4c0] width 1280 pitch 5120 (/4 1280) >[764990.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43346f0] >[764990.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43346f0] width 1280 pitch 5120 (/4 1280) >[764990.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[764990.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[764990.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4334530] >[764990.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4334530] width 1280 pitch 5120 (/4 1280) >[765020.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a9f1b0] >[765020.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a9f1b0] width 1280 pitch 5120 (/4 1280) >[765020.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4334530] >[765020.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4334530] width 1280 pitch 5120 (/4 1280) >[765020.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569320] >[765020.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569320] width 1280 pitch 5120 (/4 1280) >[765020.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345900] >[765020.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345900] width 1280 pitch 5120 (/4 1280) >[765045.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331d400] >[765045.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331d400] width 1280 pitch 5120 (/4 1280) >[765045.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345900] >[765045.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345900] width 1280 pitch 5120 (/4 1280) >[765045.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36779c0] >[765045.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36779c0] width 1280 pitch 5120 (/4 1280) >[765045.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580180] >[765045.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580180] width 1280 pitch 5120 (/4 1280) >[765046.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346dc10] >[765046.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346dc10] width 1280 pitch 5120 (/4 1280) >[765046.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374cbc0] >[765046.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374cbc0] width 1280 pitch 5120 (/4 1280) >[765046.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f3aa0] >[765046.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f3aa0] width 1280 pitch 5120 (/4 1280) >[765046.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374cbc0] >[765046.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374cbc0] width 1280 pitch 5120 (/4 1280) >[765130.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36960a0] >[765130.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36960a0] width 1280 pitch 5120 (/4 1280) >[765130.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b236d0] >[765130.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b236d0] width 1280 pitch 5120 (/4 1280) >[765130.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[765130.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[765130.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569320] >[765130.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569320] width 1280 pitch 5120 (/4 1280) >[765151.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335d630] >[765151.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335d630] width 1280 pitch 5120 (/4 1280) >[765152.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3476880] >[765152.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3476880] width 1280 pitch 5120 (/4 1280) >[765152.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36960a0] >[765152.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36960a0] width 1280 pitch 5120 (/4 1280) >[765152.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0ee0] >[765152.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0ee0] width 1280 pitch 5120 (/4 1280) >[765152.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4582660] >[765152.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4582660] width 1280 pitch 5120 (/4 1280) >[765152.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0ee0] >[765153.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0ee0] width 1280 pitch 5120 (/4 1280) >[765174.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b6970] >[765174.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b6970] width 1280 pitch 5120 (/4 1280) >[765174.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251510] >[765174.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251510] width 1280 pitch 5120 (/4 1280) >[765174.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[765174.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[765174.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251510] >[765174.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251510] width 1280 pitch 5120 (/4 1280) >[765181.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af6840] >[765181.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af6840] width 1280 pitch 5120 (/4 1280) >[765189.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[765189.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[765189.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594e0] >[765189.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594e0] width 1280 pitch 5120 (/4 1280) >[765189.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[765189.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[765189.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0ee0] >[765189.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0ee0] width 1280 pitch 5120 (/4 1280) >[765190.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36664a0] >[765190.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36664a0] width 1280 pitch 5120 (/4 1280) >[765190.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36664a0] >[765190.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36664a0] width 1280 pitch 5120 (/4 1280) >[765191.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44e70] >[765191.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44e70] width 1280 pitch 5120 (/4 1280) >[765191.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335d630] >[765191.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335d630] width 1280 pitch 5120 (/4 1280) >[765191.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb24e0] >[765191.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb24e0] width 1280 pitch 5120 (/4 1280) >[765191.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[765191.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[765195.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32df280] >[765195.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32df280] width 1280 pitch 5120 (/4 1280) >[765200.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577850] >[765200.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577850] width 1280 pitch 5120 (/4 1280) >[765200.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x332ce00] >[765200.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x332ce00] width 1280 pitch 5120 (/4 1280) >[765200.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577850] >[765200.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577850] width 1280 pitch 5120 (/4 1280) >[765200.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32de7b0] >[765200.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32de7b0] width 1280 pitch 5120 (/4 1280) >[765200.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3577850] >[765200.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3577850] width 1280 pitch 5120 (/4 1280) >[765201.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1db0] >[765201.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1db0] width 1280 pitch 5120 (/4 1280) >[765201.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c836c0] >[765201.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c836c0] width 1280 pitch 5120 (/4 1280) >[765201.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314ba50] >[765201.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314ba50] width 1280 pitch 5120 (/4 1280) >[765201.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314ba50] >[765201.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314ba50] width 1280 pitch 5120 (/4 1280) >[765201.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c836c0] >[765201.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c836c0] width 1280 pitch 5120 (/4 1280) >[765218.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x314ba50] >[765218.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x314ba50] width 1280 pitch 5120 (/4 1280) >[765218.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x432e260] >[765218.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x432e260] width 1280 pitch 5120 (/4 1280) >[765218.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf94c0] >[765218.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf94c0] width 1280 pitch 5120 (/4 1280) >[765218.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1db0] >[765218.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1db0] width 1280 pitch 5120 (/4 1280) >[765221.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e2ff0] >[765221.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e2ff0] width 1280 pitch 5120 (/4 1280) >[765229.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34d79e0] >[765229.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34d79e0] width 1280 pitch 5120 (/4 1280) >[765240.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c836c0] >[765240.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c836c0] width 1280 pitch 5120 (/4 1280) >[765240.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c4c0] >[765240.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c4c0] width 1280 pitch 5120 (/4 1280) >[765240.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363a2a0] >[765240.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363a2a0] width 1280 pitch 5120 (/4 1280) >[765240.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c4c0] >[765240.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c4c0] width 1280 pitch 5120 (/4 1280) >[765240.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363a2a0] >[765240.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363a2a0] width 1280 pitch 5120 (/4 1280) >[765240.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c4c0] >[765240.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c4c0] width 1280 pitch 5120 (/4 1280) >[765240.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363a2a0] >[765240.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363a2a0] width 1280 pitch 5120 (/4 1280) >[765240.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c4c0] >[765240.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c4c0] width 1280 pitch 5120 (/4 1280) >[765240.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363a2a0] >[765240.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363a2a0] width 1280 pitch 5120 (/4 1280) >[765241.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457c4c0] >[765241.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457c4c0] width 1280 pitch 5120 (/4 1280) >[765241.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b300] >[765241.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b300] width 1280 pitch 5120 (/4 1280) >[765243.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3476880] >[765243.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3476880] width 1280 pitch 5120 (/4 1280) >[765243.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x43454f0] >[765243.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x43454f0] width 1280 pitch 5120 (/4 1280) >[765243.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dfae0] >[765243.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dfae0] width 1280 pitch 5120 (/4 1280) >[765243.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345900] >[765243.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345900] width 1280 pitch 5120 (/4 1280) >[765243.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594e0] >[765244.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594e0] width 1280 pitch 5120 (/4 1280) >[765244.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1db0] >[765244.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1db0] width 1280 pitch 5120 (/4 1280) >[765244.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32e1db0] >[765244.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32e1db0] width 1280 pitch 5120 (/4 1280) >[765244.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709e40] >[765244.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709e40] width 1280 pitch 5120 (/4 1280) >[765251.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3709e40] >[765251.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3709e40] width 1280 pitch 5120 (/4 1280) >[765251.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335d630] >[765251.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335d630] width 1280 pitch 5120 (/4 1280) >[765251.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf94c0] >[765251.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf94c0] width 1280 pitch 5120 (/4 1280) >[765251.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[765251.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[765254.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f9f70] >[765254.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f9f70] width 1280 pitch 5120 (/4 1280) >[765260.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34704a0] >[765260.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34704a0] width 1280 pitch 5120 (/4 1280) >[765263.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36960a0] >[765263.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36960a0] width 1280 pitch 5120 (/4 1280) >[765263.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3569f70] >[765263.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3569f70] width 1280 pitch 5120 (/4 1280) >[765263.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35fc3c0] >[765263.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35fc3c0] width 1280 pitch 5120 (/4 1280) >[765263.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3569f70] >[765263.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3569f70] width 1280 pitch 5120 (/4 1280) >[765264.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36960a0] >[765264.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36960a0] width 1280 pitch 5120 (/4 1280) >[765264.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c15620] >[765264.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c15620] width 1280 pitch 5120 (/4 1280) >[765264.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3363cb0] >[765264.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3363cb0] width 1280 pitch 5120 (/4 1280) >[765264.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3576d30] >[765265.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3576d30] width 1280 pitch 5120 (/4 1280) >[765265.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b2e40] >[765265.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b2e40] width 1280 pitch 5120 (/4 1280) >[765265.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b99790] >[765265.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b99790] width 1280 pitch 5120 (/4 1280) >[765281.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b2e40] >[765281.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b2e40] width 1280 pitch 5120 (/4 1280) >[765281.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aee620] >[765281.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aee620] width 1280 pitch 5120 (/4 1280) >[765281.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580180] >[765281.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580180] width 1280 pitch 5120 (/4 1280) >[765281.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3569f70] >[765281.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3569f70] width 1280 pitch 5120 (/4 1280) >[765299.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dccd0] >[765299.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dccd0] width 1280 pitch 5120 (/4 1280) >[765303.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[765303.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[765303.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bc060] >[765303.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bc060] width 1280 pitch 5120 (/4 1280) >[765303.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335d630] >[765303.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335d630] width 1280 pitch 5120 (/4 1280) >[765333.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33056c0] >[765333.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33056c0] width 1280 pitch 5120 (/4 1280) >[765333.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x457df10] >[765333.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x457df10] width 1280 pitch 5120 (/4 1280) >[765333.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36347e0] >[765333.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36347e0] width 1280 pitch 5120 (/4 1280) >[765334.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[765334.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[765334.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[765334.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[765334.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[765334.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[765337.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b6a90] >[765337.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b6a90] width 1280 pitch 5120 (/4 1280) >[765337.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[765337.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[765337.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[765337.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[765337.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3230c70] >[765337.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3230c70] width 1280 pitch 5120 (/4 1280) >[765338.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[765338.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[765338.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[765338.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[765338.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[765338.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[765338.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a84f0] >[765338.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a84f0] width 1280 pitch 5120 (/4 1280) >[765342.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33594e0] >[765342.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33594e0] width 1280 pitch 5120 (/4 1280) >[765345.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345900] >[765345.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345900] width 1280 pitch 5120 (/4 1280) >[765350.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb24e0] >[765350.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb24e0] width 1280 pitch 5120 (/4 1280) >[765350.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33dc760] >[765350.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33dc760] width 1280 pitch 5120 (/4 1280) >[765350.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x335d630] >[765350.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x335d630] width 1280 pitch 5120 (/4 1280) >[765350.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36211d0] >[765350.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36211d0] width 1280 pitch 5120 (/4 1280) >[765466.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ecc50] >[765466.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ecc50] width 1280 pitch 5120 (/4 1280) >[765485.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3467dd0] >[765485.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3467dd0] width 1280 pitch 5120 (/4 1280) >[765485.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b42c0] >[765485.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b42c0] width 1280 pitch 5120 (/4 1280) >[765485.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b42c0] >[765485.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b42c0] width 1280 pitch 5120 (/4 1280) >[766226.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf5f0] >[766226.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf5f0] width 1280 pitch 5120 (/4 1280) >[766358.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636d00] >[766358.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636d00] width 1280 pitch 5120 (/4 1280) >[766358.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697eb0] >[766358.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697eb0] width 1280 pitch 5120 (/4 1280) >[766358.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e6c00] >[766358.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e6c00] width 1280 pitch 5120 (/4 1280) >[766358.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x433f730] >[766358.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x433f730] width 1280 pitch 5120 (/4 1280) >[766425.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ce70] >[766425.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ce70] width 1280 pitch 5120 (/4 1280) >[766432.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373ce70] >[766432.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373ce70] width 1280 pitch 5120 (/4 1280) >[766432.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32abfd0] >[766432.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32abfd0] width 1280 pitch 5120 (/4 1280) >[766432.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x368deb0] >[766432.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x368deb0] width 1280 pitch 5120 (/4 1280) >[766432.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac6cd0] >[766432.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac6cd0] width 1280 pitch 5120 (/4 1280) >[766432.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e0850] >[766432.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e0850] width 1280 pitch 5120 (/4 1280) >[766432.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[766432.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[766432.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1a30] >[766432.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1a30] width 1280 pitch 5120 (/4 1280) >[766432.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[766432.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[766432.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697eb0] >[766432.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697eb0] width 1280 pitch 5120 (/4 1280) >[766442.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bc620] >[766442.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bc620] width 1280 pitch 5120 (/4 1280) >[766464.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c1c40] >[766464.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c1c40] width 1280 pitch 5120 (/4 1280) >[766464.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[766464.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[766466.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35d85e0] >[766466.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35d85e0] width 1280 pitch 5120 (/4 1280) >[766466.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8030] >[766466.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8030] width 1280 pitch 5120 (/4 1280) >[766466.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[766466.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[766466.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[766466.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[766466.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1a30] >[766466.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1a30] width 1280 pitch 5120 (/4 1280) >[766466.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366c30] >[766466.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366c30] width 1280 pitch 5120 (/4 1280) >[766474.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[766474.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[766476.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34677a0] >[766476.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34677a0] width 1280 pitch 5120 (/4 1280) >[766476.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaa350] >[766476.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaa350] width 1280 pitch 5120 (/4 1280) >[766476.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[766476.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[766477.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baae60] >[766477.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baae60] width 1280 pitch 5120 (/4 1280) >[766477.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaa350] >[766477.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaa350] width 1280 pitch 5120 (/4 1280) >[766477.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baae60] >[766477.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baae60] width 1280 pitch 5120 (/4 1280) >[766477.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3341e90] >[766477.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3341e90] width 1280 pitch 5120 (/4 1280) >[766477.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f0c40] >[766477.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f0c40] width 1280 pitch 5120 (/4 1280) >[766495.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619610] >[766495.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619610] width 1280 pitch 5120 (/4 1280) >[766495.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baae60] >[766495.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baae60] width 1280 pitch 5120 (/4 1280) >[766495.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[766495.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[766495.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365c610] >[766495.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365c610] width 1280 pitch 5120 (/4 1280) >[766496.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af5100] >[766496.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af5100] width 1280 pitch 5120 (/4 1280) >[766496.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4fd80] >[766496.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4fd80] width 1280 pitch 5120 (/4 1280) >[766497.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4fd80] >[766497.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4fd80] width 1280 pitch 5120 (/4 1280) >[766501.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cc430] >[766501.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cc430] width 1280 pitch 5120 (/4 1280) >[766501.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c1a30] >[766501.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c1a30] width 1280 pitch 5120 (/4 1280) >[766501.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36730e0] >[766501.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36730e0] width 1280 pitch 5120 (/4 1280) >[766501.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[766502.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[766521.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3240] >[766521.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3240] width 1280 pitch 5120 (/4 1280) >[766521.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3240] >[766521.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3240] width 1280 pitch 5120 (/4 1280) >[766521.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3366c30] >[766521.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3366c30] width 1280 pitch 5120 (/4 1280) >[766521.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[766521.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[766525.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[766525.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[766525.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e5cd0] >[766525.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e5cd0] width 1280 pitch 5120 (/4 1280) >[766526.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32db720] >[766526.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32db720] width 1280 pitch 5120 (/4 1280) >[766526.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3467b20] >[766526.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3467b20] width 1280 pitch 5120 (/4 1280) >[766526.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[766526.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[766526.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357ce80] >[766526.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357ce80] width 1280 pitch 5120 (/4 1280) >[766527.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3467b20] >[766527.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3467b20] width 1280 pitch 5120 (/4 1280) >[766527.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365c610] >[766527.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365c610] width 1280 pitch 5120 (/4 1280) >[766527.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaa270] >[766527.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaa270] width 1280 pitch 5120 (/4 1280) >[766527.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af45e0] >[766527.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af45e0] width 1280 pitch 5120 (/4 1280) >[766528.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bc620] >[766528.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bc620] width 1280 pitch 5120 (/4 1280) >[766528.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30820] >[766528.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30820] width 1280 pitch 5120 (/4 1280) >[766529.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1390] >[766529.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1390] width 1280 pitch 5120 (/4 1280) >[766529.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8030] >[766529.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8030] width 1280 pitch 5120 (/4 1280) >[766529.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1390] >[766529.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1390] width 1280 pitch 5120 (/4 1280) >[766529.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8030] >[766529.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8030] width 1280 pitch 5120 (/4 1280) >[766631.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315b910] >[766631.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315b910] width 1280 pitch 5120 (/4 1280) >[766632.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e0850] >[766632.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e0850] width 1280 pitch 5120 (/4 1280) >[766632.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33df640] >[766632.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33df640] width 1280 pitch 5120 (/4 1280) >[766632.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e0850] >[766632.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e0850] width 1280 pitch 5120 (/4 1280) >[767251.540] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[767251.540] (II) RADEON(0): Using hsync ranges from config file >[767251.540] (II) RADEON(0): Using vrefresh ranges from config file >[767251.540] (II) RADEON(0): Printing DDC gathered Modelines: >[767251.540] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[767251.540] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[767251.540] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[767251.540] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[767251.540] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[767251.540] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[767251.540] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[767251.540] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[767251.540] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[767251.540] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[767341.536] (II) RADEON(0): RADEONSaveScreen(2) >[767341.536] (II) RADEON(0): RADEONSaveScreen(0) >[774861.328] (II) RADEON(0): RADEONSaveScreen(1) >[774861.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dc9a0] >[774861.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dc9a0] width 1280 pitch 5120 (/4 1280) >[774867.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3652d80] >[774867.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3652d80] width 1280 pitch 5120 (/4 1280) >[774873.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a7e30] >[774873.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a7e30] width 1280 pitch 5120 (/4 1280) >[775151.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c6e20] >[775151.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c6e20] width 1280 pitch 5120 (/4 1280) >[775152.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[775152.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[775152.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ac1d0] >[775152.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ac1d0] width 1280 pitch 5120 (/4 1280) >[775152.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[775152.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[775201.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[775201.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[775242.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfbf00] >[775242.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfbf00] width 1280 pitch 5120 (/4 1280) >[775242.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3920] >[775242.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3920] width 1280 pitch 5120 (/4 1280) >[775242.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ac1d0] >[775242.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ac1d0] width 1280 pitch 5120 (/4 1280) >[775242.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3920] >[775242.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3920] width 1280 pitch 5120 (/4 1280) >[775256.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ffda0] >[775256.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ffda0] width 1280 pitch 5120 (/4 1280) >[775257.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325760] >[775257.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325760] width 1280 pitch 5120 (/4 1280) >[775257.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ffda0] >[775257.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ffda0] width 1280 pitch 5120 (/4 1280) >[775257.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33393f0] >[775257.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33393f0] width 1280 pitch 5120 (/4 1280) >[775273.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0e3c0] >[775273.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0e3c0] width 1280 pitch 5120 (/4 1280) >[775273.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3683990] >[775273.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3683990] width 1280 pitch 5120 (/4 1280) >[775273.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362ce80] >[775273.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362ce80] width 1280 pitch 5120 (/4 1280) >[775273.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c3920] >[775273.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c3920] width 1280 pitch 5120 (/4 1280) >[775275.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348d040] >[775275.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348d040] width 1280 pitch 5120 (/4 1280) >[775276.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d1cf0] >[775276.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d1cf0] width 1280 pitch 5120 (/4 1280) >[775276.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0a000] >[775276.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0a000] width 1280 pitch 5120 (/4 1280) >[775276.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d1cf0] >[775276.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d1cf0] width 1280 pitch 5120 (/4 1280) >[775277.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb830] >[775277.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb830] width 1280 pitch 5120 (/4 1280) >[775277.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238e80] >[775277.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238e80] width 1280 pitch 5120 (/4 1280) >[775277.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[775277.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[775302.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[775302.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[775302.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238e80] >[775302.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238e80] width 1280 pitch 5120 (/4 1280) >[775302.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[775302.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[775302.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238e80] >[775302.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238e80] width 1280 pitch 5120 (/4 1280) >[775314.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[775314.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[775314.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[775314.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[775315.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[775315.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[775315.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775315.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775315.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1260] >[775315.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1260] width 1280 pitch 5120 (/4 1280) >[775315.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775315.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775315.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1260] >[775315.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1260] width 1280 pitch 5120 (/4 1280) >[775315.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775315.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775315.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1260] >[775315.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1260] width 1280 pitch 5120 (/4 1280) >[775315.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775315.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775315.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1260] >[775315.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1260] width 1280 pitch 5120 (/4 1280) >[775315.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775315.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775315.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f1260] >[775315.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f1260] width 1280 pitch 5120 (/4 1280) >[775316.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf57b0] >[775316.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf57b0] width 1280 pitch 5120 (/4 1280) >[775316.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649940] >[775316.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649940] width 1280 pitch 5120 (/4 1280) >[775316.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[775316.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[775316.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346a320] >[775316.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346a320] width 1280 pitch 5120 (/4 1280) >[775316.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[775316.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[775316.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3193bb0] >[775316.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3193bb0] width 1280 pitch 5120 (/4 1280) >[775317.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0dcd0] >[775317.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0dcd0] width 1280 pitch 5120 (/4 1280) >[775317.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331a6f0] >[775317.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331a6f0] width 1280 pitch 5120 (/4 1280) >[775317.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aac8e0] >[775317.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aac8e0] width 1280 pitch 5120 (/4 1280) >[775340.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365a860] >[775340.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365a860] width 1280 pitch 5120 (/4 1280) >[775343.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[775343.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[775343.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331a6f0] >[775343.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331a6f0] width 1280 pitch 5120 (/4 1280) >[775343.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331a6f0] >[775343.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331a6f0] width 1280 pitch 5120 (/4 1280) >[775380.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32dfdf0] >[775380.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32dfdf0] width 1280 pitch 5120 (/4 1280) >[775381.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357c070] >[775381.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357c070] width 1280 pitch 5120 (/4 1280) >[775381.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f500] >[775381.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f500] width 1280 pitch 5120 (/4 1280) >[775382.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[775382.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[775436.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aef5e0] >[775436.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aef5e0] width 1280 pitch 5120 (/4 1280) >[775438.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aef470] >[775438.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aef470] width 1280 pitch 5120 (/4 1280) >[775438.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[775438.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[775438.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3193bb0] >[775438.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3193bb0] width 1280 pitch 5120 (/4 1280) >[775438.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357bd40] >[775438.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357bd40] width 1280 pitch 5120 (/4 1280) >[775439.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3193bb0] >[775439.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3193bb0] width 1280 pitch 5120 (/4 1280) >[775470.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3238e80] >[775470.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3238e80] width 1280 pitch 5120 (/4 1280) >[775470.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[775470.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[775470.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[775470.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[775470.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3244550] >[775470.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3244550] width 1280 pitch 5120 (/4 1280) >[775471.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[775471.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[775493.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[775493.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[775494.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607480] >[775494.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607480] width 1280 pitch 5120 (/4 1280) >[775494.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607480] >[775494.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607480] width 1280 pitch 5120 (/4 1280) >[775494.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[775494.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[775494.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607480] >[775494.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607480] width 1280 pitch 5120 (/4 1280) >[775494.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f500] >[775494.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f500] width 1280 pitch 5120 (/4 1280) >[775495.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36baaa0] >[775495.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36baaa0] width 1280 pitch 5120 (/4 1280) >[775495.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[775495.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[775495.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[775495.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[776097.351] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[776097.351] (II) RADEON(0): Using hsync ranges from config file >[776097.351] (II) RADEON(0): Using vrefresh ranges from config file >[776097.351] (II) RADEON(0): Printing DDC gathered Modelines: >[776097.351] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[776097.351] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[776097.351] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[776097.351] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[776097.351] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[776097.351] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[776097.351] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[776097.351] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[776097.351] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[776097.351] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[776187.555] (II) RADEON(0): RADEONSaveScreen(2) >[776187.555] (II) RADEON(0): RADEONSaveScreen(0) >[812707.497] (II) RADEON(0): RADEONSaveScreen(1) >[812707.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812707.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812711.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812711.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812711.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812711.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812711.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812711.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812711.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812711.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812711.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812712.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812712.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812712.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812712.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812712.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812712.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812712.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812712.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812712.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812713.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[812713.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[812713.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624700] >[812713.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624700] width 1280 pitch 5120 (/4 1280) >[812713.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[812713.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[812713.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624700] >[812713.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624700] width 1280 pitch 5120 (/4 1280) >[812713.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[812713.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[812713.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624700] >[812713.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624700] width 1280 pitch 5120 (/4 1280) >[812713.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[812713.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[812713.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3624700] >[812713.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3624700] width 1280 pitch 5120 (/4 1280) >[812713.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ade170] >[812713.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ade170] width 1280 pitch 5120 (/4 1280) >[812714.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812714.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812714.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812714.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812714.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812714.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812714.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812714.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812714.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x372c640] >[812714.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x372c640] width 1280 pitch 5120 (/4 1280) >[812714.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812714.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812714.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b760] >[812714.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b760] width 1280 pitch 5120 (/4 1280) >[812714.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812714.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812714.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b760] >[812714.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b760] width 1280 pitch 5120 (/4 1280) >[812714.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812714.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812714.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b760] >[812714.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b760] width 1280 pitch 5120 (/4 1280) >[812714.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3329410] >[812714.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3329410] width 1280 pitch 5120 (/4 1280) >[812714.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2b760] >[812714.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2b760] width 1280 pitch 5120 (/4 1280) >[812714.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3329410] >[812714.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3329410] width 1280 pitch 5120 (/4 1280) >[812719.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812719.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812719.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812719.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812719.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812719.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812719.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812719.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812719.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812719.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812719.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812719.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812719.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812719.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812719.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812719.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812719.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812719.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812719.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812719.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812720.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812720.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812720.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812720.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812720.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812720.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812720.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812720.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812720.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812720.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812720.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812720.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812720.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812720.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812720.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812720.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812721.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812721.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812721.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812721.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812721.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812721.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812721.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812721.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812721.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812721.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812721.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812721.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812721.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812721.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812722.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812722.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812722.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e51c0] >[812722.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e51c0] width 1280 pitch 5120 (/4 1280) >[812722.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812722.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812724.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812724.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812724.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812724.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812724.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812724.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812724.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812724.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812724.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812724.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812724.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812724.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812724.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812724.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812730.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812730.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812730.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8f70] >[812730.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8f70] width 1280 pitch 5120 (/4 1280) >[812730.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812730.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812730.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ca30] >[812730.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ca30] width 1280 pitch 5120 (/4 1280) >[812730.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba170] >[812730.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba170] width 1280 pitch 5120 (/4 1280) >[812730.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8d10] >[812730.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8d10] width 1280 pitch 5120 (/4 1280) >[812730.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812730.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812730.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812730.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812730.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a9eb0] >[812730.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a9eb0] width 1280 pitch 5120 (/4 1280) >[812730.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812730.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812730.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812730.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812730.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812730.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812730.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812730.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812730.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ca30] >[812730.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ca30] width 1280 pitch 5120 (/4 1280) >[812731.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8f70] >[812731.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8f70] width 1280 pitch 5120 (/4 1280) >[812731.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1030] >[812731.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1030] width 1280 pitch 5120 (/4 1280) >[812731.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812731.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812731.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812731.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812731.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812731.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812731.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4000] >[812731.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4000] width 1280 pitch 5120 (/4 1280) >[812731.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812731.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812731.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8f70] >[812731.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8f70] width 1280 pitch 5120 (/4 1280) >[812731.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812731.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812731.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1030] >[812731.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1030] width 1280 pitch 5120 (/4 1280) >[812731.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812731.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812731.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812731.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812731.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812731.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812731.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[812731.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[812731.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812731.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812731.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812731.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812732.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812732.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812732.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812732.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812732.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812732.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812732.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba170] >[812732.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba170] width 1280 pitch 5120 (/4 1280) >[812732.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a1030] >[812732.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a1030] width 1280 pitch 5120 (/4 1280) >[812732.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812732.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812732.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4000] >[812732.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4000] width 1280 pitch 5120 (/4 1280) >[812732.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x357d1f0] >[812733.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x357d1f0] width 1280 pitch 5120 (/4 1280) >[812733.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4000] >[812733.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4000] width 1280 pitch 5120 (/4 1280) >[812733.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812733.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812733.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812733.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812733.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812733.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812733.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812733.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812733.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812733.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812733.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812733.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812733.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ba60] >[812733.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ba60] width 1280 pitch 5120 (/4 1280) >[812733.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x361ba60] >[812734.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x361ba60] width 1280 pitch 5120 (/4 1280) >[812734.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812734.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812734.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[812734.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[812734.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812734.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812734.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ca30] >[812734.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ca30] width 1280 pitch 5120 (/4 1280) >[812734.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812734.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812734.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba170] >[812734.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba170] width 1280 pitch 5120 (/4 1280) >[812734.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbde0] >[812734.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbde0] width 1280 pitch 5120 (/4 1280) >[812734.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbde0] >[812734.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbde0] width 1280 pitch 5120 (/4 1280) >[812734.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbde0] >[812734.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbde0] width 1280 pitch 5120 (/4 1280) >[812734.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbde0] >[812734.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbde0] width 1280 pitch 5120 (/4 1280) >[812734.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c76150] >[812734.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c76150] width 1280 pitch 5120 (/4 1280) >[812734.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812734.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812734.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812734.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812734.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812734.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812734.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8f70] >[812734.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8f70] width 1280 pitch 5120 (/4 1280) >[812734.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ca30] >[812734.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ca30] width 1280 pitch 5120 (/4 1280) >[812734.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ba170] >[812734.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ba170] width 1280 pitch 5120 (/4 1280) >[812734.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a9eb0] >[812734.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a9eb0] width 1280 pitch 5120 (/4 1280) >[812734.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353dd60] >[812734.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353dd60] width 1280 pitch 5120 (/4 1280) >[812734.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[812734.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[812734.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812734.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812735.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a9eb0] >[812735.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a9eb0] width 1280 pitch 5120 (/4 1280) >[812735.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356ca30] >[812735.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356ca30] width 1280 pitch 5120 (/4 1280) >[812735.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b90b0] >[812735.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b90b0] width 1280 pitch 5120 (/4 1280) >[812737.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3636c70] >[812737.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3636c70] width 1280 pitch 5120 (/4 1280) >[812737.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812737.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812737.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812737.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812738.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812738.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812738.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[812738.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[812738.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812738.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812738.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[812738.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[812738.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812738.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812738.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[812738.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[812738.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812738.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812738.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[812738.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[812738.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33de8a0] >[812739.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33de8a0] width 1280 pitch 5120 (/4 1280) >[812739.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf290] >[812739.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf290] width 1280 pitch 5120 (/4 1280) >[812741.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[812741.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[812741.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251260] >[812741.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251260] width 1280 pitch 5120 (/4 1280) >[812741.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa1e30] >[812741.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa1e30] width 1280 pitch 5120 (/4 1280) >[812741.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251260] >[812741.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251260] width 1280 pitch 5120 (/4 1280) >[813030.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x353de30] >[813030.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x353de30] width 1280 pitch 5120 (/4 1280) >[813030.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[813030.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[813030.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251260] >[813030.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251260] width 1280 pitch 5120 (/4 1280) >[813031.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[813031.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[813031.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3251260] >[813031.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3251260] width 1280 pitch 5120 (/4 1280) >[813031.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[813031.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[813031.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4020] >[813031.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4020] width 1280 pitch 5120 (/4 1280) >[813042.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f9d10] >[813042.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f9d10] width 1280 pitch 5120 (/4 1280) >[813042.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31d3640] >[813042.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31d3640] width 1280 pitch 5120 (/4 1280) >[813042.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649400] >[813042.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649400] width 1280 pitch 5120 (/4 1280) >[813043.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f9d10] >[813043.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f9d10] width 1280 pitch 5120 (/4 1280) >[813057.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a6070] >[813057.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a6070] width 1280 pitch 5120 (/4 1280) >[813146.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315c4b0] >[813146.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315c4b0] width 1280 pitch 5120 (/4 1280) >[813146.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e2d10] >[813146.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e2d10] width 1280 pitch 5120 (/4 1280) >[813146.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315c4b0] >[813146.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315c4b0] width 1280 pitch 5120 (/4 1280) >[813146.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e2d10] >[813146.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e2d10] width 1280 pitch 5120 (/4 1280) >[813898.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369e3b0] >[813898.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369e3b0] width 1280 pitch 5120 (/4 1280) >[813991.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[813991.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[813991.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[813991.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[813991.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619850] >[813991.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619850] width 1280 pitch 5120 (/4 1280) >[813991.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[813991.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[814032.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3fc0] >[814032.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3fc0] width 1280 pitch 5120 (/4 1280) >[814037.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8d50] >[814037.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8d50] width 1280 pitch 5120 (/4 1280) >[814037.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[814037.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[814037.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8d50] >[814037.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8d50] width 1280 pitch 5120 (/4 1280) >[814037.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814037.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814038.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814038.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814039.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[814039.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[814039.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3fc0] >[814039.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3fc0] width 1280 pitch 5120 (/4 1280) >[814039.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[814039.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[814124.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814124.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814125.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3474990] >[814125.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3474990] width 1280 pitch 5120 (/4 1280) >[814125.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32be320] >[814125.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32be320] width 1280 pitch 5120 (/4 1280) >[814125.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c8d10] >[814125.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c8d10] width 1280 pitch 5120 (/4 1280) >[814126.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369e3b0] >[814127.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369e3b0] width 1280 pitch 5120 (/4 1280) >[814127.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814127.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814127.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814127.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814127.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814127.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814153.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b5360] >[814153.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b5360] width 1280 pitch 5120 (/4 1280) >[814153.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814153.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814153.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3607480] >[814153.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3607480] width 1280 pitch 5120 (/4 1280) >[814153.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a8920] >[814153.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a8920] width 1280 pitch 5120 (/4 1280) >[814154.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3244550] >[814154.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3244550] width 1280 pitch 5120 (/4 1280) >[814226.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814226.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814226.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c38870] >[814226.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c38870] width 1280 pitch 5120 (/4 1280) >[814226.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814226.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814228.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[814228.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[814228.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814228.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814228.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab120] >[814228.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab120] width 1280 pitch 5120 (/4 1280) >[814228.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x356f500] >[814228.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x356f500] width 1280 pitch 5120 (/4 1280) >[814228.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aef470] >[814229.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aef470] width 1280 pitch 5120 (/4 1280) >[814229.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[814229.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[814237.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9c640] >[814237.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9c640] width 1280 pitch 5120 (/4 1280) >[814237.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aef470] >[814237.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aef470] width 1280 pitch 5120 (/4 1280) >[814237.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34740a0] >[814237.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34740a0] width 1280 pitch 5120 (/4 1280) >[814237.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3fc0] >[814237.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3fc0] width 1280 pitch 5120 (/4 1280) >[814417.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37511c0] >[814417.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37511c0] width 1280 pitch 5120 (/4 1280) >[814419.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3471390] >[814419.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3471390] width 1280 pitch 5120 (/4 1280) >[814423.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e9e40] >[814423.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e9e40] width 1280 pitch 5120 (/4 1280) >[814423.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a4b50] >[814423.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a4b50] width 1280 pitch 5120 (/4 1280) >[814423.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e9e40] >[814423.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e9e40] width 1280 pitch 5120 (/4 1280) >[814424.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a4b50] >[814424.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a4b50] width 1280 pitch 5120 (/4 1280) >[814481.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e0b40] >[814481.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e0b40] width 1280 pitch 5120 (/4 1280) >[814481.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[814481.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[814481.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d8f60] >[814482.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d8f60] width 1280 pitch 5120 (/4 1280) >[814482.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c0e0e0] >[814482.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c0e0e0] width 1280 pitch 5120 (/4 1280) >[814719.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4578ef0] >[814719.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4578ef0] width 1280 pitch 5120 (/4 1280) >[814719.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3468a90] >[814719.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3468a90] width 1280 pitch 5120 (/4 1280) >[814720.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331d910] >[814720.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331d910] width 1280 pitch 5120 (/4 1280) >[814720.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a210] >[814720.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a210] width 1280 pitch 5120 (/4 1280) >[814720.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331d910] >[814720.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331d910] width 1280 pitch 5120 (/4 1280) >[814734.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a210] >[814734.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a210] width 1280 pitch 5120 (/4 1280) >[814734.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[814734.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[814734.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3468a90] >[814734.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3468a90] width 1280 pitch 5120 (/4 1280) >[814734.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8dd00] >[814734.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8dd00] width 1280 pitch 5120 (/4 1280) >[814824.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3619120] >[814824.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3619120] width 1280 pitch 5120 (/4 1280) >[814824.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36456f0] >[814824.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36456f0] width 1280 pitch 5120 (/4 1280) >[814825.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36469d0] >[814825.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36469d0] width 1280 pitch 5120 (/4 1280) >[814825.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36456f0] >[814825.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36456f0] width 1280 pitch 5120 (/4 1280) >[814825.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d4b60] >[814825.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d4b60] width 1280 pitch 5120 (/4 1280) >[814825.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36456f0] >[814826.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36456f0] width 1280 pitch 5120 (/4 1280) >[814830.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4586e40] >[814830.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4586e40] width 1280 pitch 5120 (/4 1280) >[814830.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45ab400] >[814830.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45ab400] width 1280 pitch 5120 (/4 1280) >[814831.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf1660] >[814831.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf1660] width 1280 pitch 5120 (/4 1280) >[814831.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36456f0] >[814831.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36456f0] width 1280 pitch 5120 (/4 1280) >[814831.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3153bd0] >[814831.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3153bd0] width 1280 pitch 5120 (/4 1280) >[814831.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36456f0] >[814831.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36456f0] width 1280 pitch 5120 (/4 1280) >[815469.046] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[815469.046] (II) RADEON(0): Using hsync ranges from config file >[815469.046] (II) RADEON(0): Using vrefresh ranges from config file >[815469.046] (II) RADEON(0): Printing DDC gathered Modelines: >[815469.046] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[815469.046] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[815469.046] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[815469.046] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[815469.046] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[815469.046] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[815469.046] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[815469.046] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[815469.046] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[815469.046] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[815559.555] (II) RADEON(0): RADEONSaveScreen(2) >[815559.555] (II) RADEON(0): RADEONSaveScreen(0) >[818633.217] (II) RADEON(0): RADEONSaveScreen(1) >[818633.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34aa930] >[818633.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34aa930] width 1280 pitch 5120 (/4 1280) >[818636.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36baaa0] >[818636.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36baaa0] width 1280 pitch 5120 (/4 1280) >[818835.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd36e0] >[818835.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd36e0] width 1280 pitch 5120 (/4 1280) >[818835.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aed470] >[818835.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aed470] width 1280 pitch 5120 (/4 1280) >[818835.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bc430] >[818835.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bc430] width 1280 pitch 5120 (/4 1280) >[818835.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35966b0] >[818835.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35966b0] width 1280 pitch 5120 (/4 1280) >[818836.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a210] >[818836.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a210] width 1280 pitch 5120 (/4 1280) >[818836.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[818836.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[818836.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x323a210] >[818836.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x323a210] width 1280 pitch 5120 (/4 1280) >[818837.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[818837.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[818859.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36baaa0] >[818859.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36baaa0] width 1280 pitch 5120 (/4 1280) >[818859.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fc10] >[818859.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fc10] width 1280 pitch 5120 (/4 1280) >[818859.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97a20] >[818859.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97a20] width 1280 pitch 5120 (/4 1280) >[818859.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fc10] >[818859.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fc10] width 1280 pitch 5120 (/4 1280) >[818863.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362d4c0] >[818863.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362d4c0] width 1280 pitch 5120 (/4 1280) >[818863.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34688c0] >[818863.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34688c0] width 1280 pitch 5120 (/4 1280) >[819523.585] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[819523.585] (II) RADEON(0): Using hsync ranges from config file >[819523.585] (II) RADEON(0): Using vrefresh ranges from config file >[819523.585] (II) RADEON(0): Printing DDC gathered Modelines: >[819523.585] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[819523.585] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[819523.585] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[819523.585] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[819523.585] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[819523.585] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[819523.585] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[819523.585] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[819523.585] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[819523.585] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[819613.536] (II) RADEON(0): RADEONSaveScreen(2) >[819613.536] (II) RADEON(0): RADEONSaveScreen(0) >[820127.159] (II) RADEON(0): RADEONSaveScreen(1) >[820130.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649b40] >[820130.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649b40] width 1280 pitch 5120 (/4 1280) >[820135.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc230] >[820135.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc230] width 1280 pitch 5120 (/4 1280) >[820135.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c98c0] >[820135.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c98c0] width 1280 pitch 5120 (/4 1280) >[820135.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33db2a0] >[820135.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33db2a0] width 1280 pitch 5120 (/4 1280) >[820135.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45692d0] >[820135.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45692d0] width 1280 pitch 5120 (/4 1280) >[820407.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36c98c0] >[820407.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36c98c0] width 1280 pitch 5120 (/4 1280) >[820408.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[820408.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[820408.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3679fa0] >[820408.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3679fa0] width 1280 pitch 5120 (/4 1280) >[820408.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae9910] >[820408.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae9910] width 1280 pitch 5120 (/4 1280) >[820593.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[820593.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[820594.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[820594.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[820594.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fc10] >[820594.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fc10] width 1280 pitch 5120 (/4 1280) >[820594.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd300] >[820594.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd300] width 1280 pitch 5120 (/4 1280) >[821277.240] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[821277.240] (II) RADEON(0): Using hsync ranges from config file >[821277.240] (II) RADEON(0): Using vrefresh ranges from config file >[821277.240] (II) RADEON(0): Printing DDC gathered Modelines: >[821277.240] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[821277.240] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[821277.240] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[821277.240] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[821277.240] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[821277.240] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[821277.240] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[821277.240] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[821277.240] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[821277.240] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[821367.544] (II) RADEON(0): RADEONSaveScreen(2) >[821367.544] (II) RADEON(0): RADEONSaveScreen(0) >[823091.235] (II) RADEON(0): RADEONSaveScreen(1) >[823099.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823099.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823101.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823101.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823101.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823101.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823101.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823101.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823101.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823101.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823101.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823101.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823101.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823101.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658ff0] >[823101.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658ff0] width 1280 pitch 5120 (/4 1280) >[823101.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823101.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823101.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823102.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fb0b0] >[823102.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fb0b0] width 1280 pitch 5120 (/4 1280) >[823102.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[823102.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[823104.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36241c0] >[823104.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36241c0] width 1280 pitch 5120 (/4 1280) >[823122.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4595c60] >[823122.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4595c60] width 1280 pitch 5120 (/4 1280) >[823973.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259650] >[823973.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259650] width 1280 pitch 5120 (/4 1280) >[823984.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3704980] >[823984.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3704980] width 1280 pitch 5120 (/4 1280) >[823984.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3259650] >[823984.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3259650] width 1280 pitch 5120 (/4 1280) >[823984.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3237570] >[823985.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3237570] width 1280 pitch 5120 (/4 1280) >[823985.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e1bf0] >[823985.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e1bf0] width 1280 pitch 5120 (/4 1280) >[824866.788] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[824866.789] (II) RADEON(0): Using hsync ranges from config file >[824866.789] (II) RADEON(0): Using vrefresh ranges from config file >[824866.789] (II) RADEON(0): Printing DDC gathered Modelines: >[824866.789] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[824866.789] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[824866.789] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[824866.789] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[824866.789] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[824866.789] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[824866.789] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[824866.789] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[824866.789] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[824866.789] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[824953.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45a6900] >[824953.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45a6900] width 1280 pitch 5120 (/4 1280) >[826721.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c534a0] >[826721.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c534a0] width 1280 pitch 5120 (/4 1280) >[829481.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e4f30] >[829481.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e4f30] width 1280 pitch 5120 (/4 1280) >[829482.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99cc0] >[829482.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99cc0] width 1280 pitch 5120 (/4 1280) >[829482.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99cc0] >[829482.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99cc0] width 1280 pitch 5120 (/4 1280) >[829482.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aec690] >[829482.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aec690] width 1280 pitch 5120 (/4 1280) >[829483.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[829483.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[829483.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[829483.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[829483.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1510] >[829483.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1510] width 1280 pitch 5120 (/4 1280) >[829483.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc6aa0] >[829483.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc6aa0] width 1280 pitch 5120 (/4 1280) >[829491.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33d7650] >[829491.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33d7650] width 1280 pitch 5120 (/4 1280) >[829611.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ca900] >[829611.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ca900] width 1280 pitch 5120 (/4 1280) >[829734.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cd690] >[829734.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cd690] width 1280 pitch 5120 (/4 1280) >[829777.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b5d50] >[829777.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b5d50] width 1280 pitch 5120 (/4 1280) >[829784.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345440] >[829784.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345440] width 1280 pitch 5120 (/4 1280) >[829785.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af24c0] >[829785.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af24c0] width 1280 pitch 5120 (/4 1280) >[829785.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b7110] >[829785.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b7110] width 1280 pitch 5120 (/4 1280) >[829785.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b7110] >[829785.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b7110] width 1280 pitch 5120 (/4 1280) >[829786.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b28400] >[829786.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b28400] width 1280 pitch 5120 (/4 1280) >[829786.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829786.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829786.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829786.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829786.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829786.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829786.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829786.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829786.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829786.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829786.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829786.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829786.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829787.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829787.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829787.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829787.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829787.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829787.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[829787.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[829787.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829787.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829788.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bad10] >[829788.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bad10] width 1280 pitch 5120 (/4 1280) >[829788.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35be800] >[829788.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35be800] width 1280 pitch 5120 (/4 1280) >[829788.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4343b40] >[829788.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4343b40] width 1280 pitch 5120 (/4 1280) >[829788.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bad10] >[829788.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bad10] width 1280 pitch 5120 (/4 1280) >[829790.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35bfc20] >[829790.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35bfc20] width 1280 pitch 5120 (/4 1280) >[829791.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f49d0] >[829791.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f49d0] width 1280 pitch 5120 (/4 1280) >[829791.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4a55c90] >[829791.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4a55c90] width 1280 pitch 5120 (/4 1280) >[829791.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f49d0] >[829791.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f49d0] width 1280 pitch 5120 (/4 1280) >[829997.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31ce390] >[829997.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31ce390] width 1280 pitch 5120 (/4 1280) >[829997.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x342acd0] >[829997.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x342acd0] width 1280 pitch 5120 (/4 1280) >[829997.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3493e10] >[829997.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3493e10] width 1280 pitch 5120 (/4 1280) >[829997.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3399d60] >[829997.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3399d60] width 1280 pitch 5120 (/4 1280) >[830002.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348eab0] >[830002.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348eab0] width 1280 pitch 5120 (/4 1280) >[830002.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367f390] >[830002.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367f390] width 1280 pitch 5120 (/4 1280) >[830002.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367f390] >[830002.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367f390] width 1280 pitch 5120 (/4 1280) >[830002.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d3d50] >[830002.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d3d50] width 1280 pitch 5120 (/4 1280) >[830319.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348eab0] >[830319.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348eab0] width 1280 pitch 5120 (/4 1280) >[830321.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348eab0] >[830322.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348eab0] width 1280 pitch 5120 (/4 1280) >[830328.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36483c0] >[830328.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36483c0] width 1280 pitch 5120 (/4 1280) >[830328.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eae50] >[830328.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eae50] width 1280 pitch 5120 (/4 1280) >[830328.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3157bb0] >[830328.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3157bb0] width 1280 pitch 5120 (/4 1280) >[830328.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367f390] >[830328.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367f390] width 1280 pitch 5120 (/4 1280) >[830330.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0300] >[830330.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0300] width 1280 pitch 5120 (/4 1280) >[830336.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3406390] >[830336.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3406390] width 1280 pitch 5120 (/4 1280) >[830336.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3382760] >[830336.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3382760] width 1280 pitch 5120 (/4 1280) >[830336.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c0300] >[830336.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c0300] width 1280 pitch 5120 (/4 1280) >[830336.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x367f390] >[830336.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x367f390] width 1280 pitch 5120 (/4 1280) >[830345.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eae50] >[830345.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eae50] width 1280 pitch 5120 (/4 1280) >[830360.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eae50] >[830360.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eae50] width 1280 pitch 5120 (/4 1280) >[830377.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdc290] >[830377.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdc290] width 1280 pitch 5120 (/4 1280) >[830377.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4593d80] >[830377.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4593d80] width 1280 pitch 5120 (/4 1280) >[830377.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdc290] >[830377.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdc290] width 1280 pitch 5120 (/4 1280) >[830377.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c32760] >[830377.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c32760] width 1280 pitch 5120 (/4 1280) >[830377.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cb5cf0] >[830377.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cb5cf0] width 1280 pitch 5120 (/4 1280) >[830377.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3337040] >[830377.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3337040] width 1280 pitch 5120 (/4 1280) >[830377.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3337040] >[830377.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3337040] width 1280 pitch 5120 (/4 1280) >[830377.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830377.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830377.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3499f80] >[830377.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3499f80] width 1280 pitch 5120 (/4 1280) >[830377.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830377.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f59f0] >[830378.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f59f0] width 1280 pitch 5120 (/4 1280) >[830378.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f59f0] >[830378.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f59f0] width 1280 pitch 5120 (/4 1280) >[830378.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f59f0] >[830378.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f59f0] width 1280 pitch 5120 (/4 1280) >[830378.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340f60] >[830378.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340f60] width 1280 pitch 5120 (/4 1280) >[830378.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f59f0] >[830378.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f59f0] width 1280 pitch 5120 (/4 1280) >[830378.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340f60] >[830378.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340f60] width 1280 pitch 5120 (/4 1280) >[830378.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340f60] >[830378.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340f60] width 1280 pitch 5120 (/4 1280) >[830378.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830378.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4340f60] >[830378.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4340f60] width 1280 pitch 5120 (/4 1280) >[830378.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fdb20] >[830378.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fdb20] width 1280 pitch 5120 (/4 1280) >[830393.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c2000] >[830393.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c2000] width 1280 pitch 5120 (/4 1280) >[830407.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3756670] >[830407.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3756670] width 1280 pitch 5120 (/4 1280) >[830407.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e57b0] >[830407.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e57b0] width 1280 pitch 5120 (/4 1280) >[830407.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b930] >[830407.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b930] width 1280 pitch 5120 (/4 1280) >[830407.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x336a1d0] >[830407.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x336a1d0] width 1280 pitch 5120 (/4 1280) >[830407.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3300890] >[830407.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3300890] width 1280 pitch 5120 (/4 1280) >[830407.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3756670] >[830407.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3756670] width 1280 pitch 5120 (/4 1280) >[830407.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c18c90] >[830407.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c18c90] width 1280 pitch 5120 (/4 1280) >[830407.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b930] >[830407.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b930] width 1280 pitch 5120 (/4 1280) >[830407.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c18c90] >[830407.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c18c90] width 1280 pitch 5120 (/4 1280) >[830407.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338b930] >[830407.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338b930] width 1280 pitch 5120 (/4 1280) >[830408.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f0f0] >[830408.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f0f0] width 1280 pitch 5120 (/4 1280) >[830408.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334f5e0] >[830408.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334f5e0] width 1280 pitch 5120 (/4 1280) >[830436.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5f60] >[830436.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5f60] width 1280 pitch 5120 (/4 1280) >[830437.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3613e90] >[830437.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3613e90] width 1280 pitch 5120 (/4 1280) >[830437.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2b320] >[830437.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2b320] width 1280 pitch 5120 (/4 1280) >[830437.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3613e90] >[830437.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3613e90] width 1280 pitch 5120 (/4 1280) >[830440.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c18cd0] >[830440.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c18cd0] width 1280 pitch 5120 (/4 1280) >[830444.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37566b0] >[830444.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37566b0] width 1280 pitch 5120 (/4 1280) >[830444.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5b30] >[830444.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5b30] width 1280 pitch 5120 (/4 1280) >[830444.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37566b0] >[830444.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37566b0] width 1280 pitch 5120 (/4 1280) >[830444.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c5b30] >[830444.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c5b30] width 1280 pitch 5120 (/4 1280) >[830448.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3613e90] >[830448.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3613e90] width 1280 pitch 5120 (/4 1280) >[830454.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59090] >[830454.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59090] width 1280 pitch 5120 (/4 1280) >[830454.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3613e90] >[830454.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3613e90] width 1280 pitch 5120 (/4 1280) >[830454.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d220] >[830454.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d220] width 1280 pitch 5120 (/4 1280) >[830458.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309a30] >[830458.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309a30] width 1280 pitch 5120 (/4 1280) >[830464.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f04a0] >[830464.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f04a0] width 1280 pitch 5120 (/4 1280) >[830464.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3260850] >[830464.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3260850] width 1280 pitch 5120 (/4 1280) >[830465.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c39bc0] >[830465.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c39bc0] width 1280 pitch 5120 (/4 1280) >[830465.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x359a0e0] >[830465.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x359a0e0] width 1280 pitch 5120 (/4 1280) >[830466.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e3c30] >[830466.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e3c30] width 1280 pitch 5120 (/4 1280) >[830466.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c09fa0] >[830466.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c09fa0] width 1280 pitch 5120 (/4 1280) >[830466.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c09fa0] >[830466.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c09fa0] width 1280 pitch 5120 (/4 1280) >[830469.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8c0] >[830469.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8c0] width 1280 pitch 5120 (/4 1280) >[830469.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e3c30] >[830469.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e3c30] width 1280 pitch 5120 (/4 1280) >[830512.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830512.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830512.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338de90] >[830512.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338de90] width 1280 pitch 5120 (/4 1280) >[830512.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d9f0] >[830512.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d9f0] width 1280 pitch 5120 (/4 1280) >[830512.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfa00] >[830512.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfa00] width 1280 pitch 5120 (/4 1280) >[830556.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830556.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830556.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfa00] >[830556.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfa00] width 1280 pitch 5120 (/4 1280) >[830556.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfa00] >[830556.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfa00] width 1280 pitch 5120 (/4 1280) >[830556.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830556.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830570.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d40] >[830570.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d40] width 1280 pitch 5120 (/4 1280) >[830570.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345ace0] >[830570.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345ace0] width 1280 pitch 5120 (/4 1280) >[830570.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d9f0] >[830570.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d9f0] width 1280 pitch 5120 (/4 1280) >[830570.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d40] >[830570.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d40] width 1280 pitch 5120 (/4 1280) >[830571.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be15f0] >[830571.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be15f0] width 1280 pitch 5120 (/4 1280) >[830571.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35eb080] >[830571.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35eb080] width 1280 pitch 5120 (/4 1280) >[830575.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0cc0] >[830575.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0cc0] width 1280 pitch 5120 (/4 1280) >[830575.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2bc5f60] >[830575.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2bc5f60] width 1280 pitch 5120 (/4 1280) >[830599.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830599.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830599.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3352d40] >[830599.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3352d40] width 1280 pitch 5120 (/4 1280) >[830599.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830599.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830599.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aca450] >[830599.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aca450] width 1280 pitch 5120 (/4 1280) >[830605.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3370ee0] >[830605.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3370ee0] width 1280 pitch 5120 (/4 1280) >[830605.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf9f0] >[830605.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf9f0] width 1280 pitch 5120 (/4 1280) >[830617.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfe440] >[830617.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfe440] width 1280 pitch 5120 (/4 1280) >[830617.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d9f0] >[830617.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d9f0] width 1280 pitch 5120 (/4 1280) >[830617.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a5180] >[830617.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a5180] width 1280 pitch 5120 (/4 1280) >[830617.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b0cc0] >[830617.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b0cc0] width 1280 pitch 5120 (/4 1280) >[830619.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x375d9f0] >[830619.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x375d9f0] width 1280 pitch 5120 (/4 1280) >[830619.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfa00] >[830619.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfa00] width 1280 pitch 5120 (/4 1280) >[830619.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30610] >[830619.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30610] width 1280 pitch 5120 (/4 1280) >[830619.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf7c0] >[830619.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf7c0] width 1280 pitch 5120 (/4 1280) >[830620.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c59090] >[830620.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c59090] width 1280 pitch 5120 (/4 1280) >[830620.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31cf7c0] >[830620.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31cf7c0] width 1280 pitch 5120 (/4 1280) >[830622.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35f04a0] >[830622.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35f04a0] width 1280 pitch 5120 (/4 1280) >[830622.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338de90] >[830622.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338de90] width 1280 pitch 5120 (/4 1280) >[830622.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfe440] >[830622.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfe440] width 1280 pitch 5120 (/4 1280) >[830622.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x338de90] >[830622.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x338de90] width 1280 pitch 5120 (/4 1280) >[830637.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ede00] >[830637.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ede00] width 1280 pitch 5120 (/4 1280) >[830637.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362f150] >[830637.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362f150] width 1280 pitch 5120 (/4 1280) >[830637.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309a30] >[830637.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309a30] width 1280 pitch 5120 (/4 1280) >[830637.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362f150] >[830637.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362f150] width 1280 pitch 5120 (/4 1280) >[830638.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35ede00] >[830638.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35ede00] width 1280 pitch 5120 (/4 1280) >[830643.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a92c0] >[830643.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a92c0] width 1280 pitch 5120 (/4 1280) >[830643.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9fc80] >[830643.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9fc80] width 1280 pitch 5120 (/4 1280) >[830643.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36a92c0] >[830643.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36a92c0] width 1280 pitch 5120 (/4 1280) >[830643.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346df70] >[830643.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346df70] width 1280 pitch 5120 (/4 1280) >[830644.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d1300] >[830644.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d1300] width 1280 pitch 5120 (/4 1280) >[830654.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4c30] >[830654.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4c30] width 1280 pitch 5120 (/4 1280) >[830669.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3473b00] >[830669.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3473b00] width 1280 pitch 5120 (/4 1280) >[830685.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585ca0] >[830685.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585ca0] width 1280 pitch 5120 (/4 1280) >[830685.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a96b0] >[830685.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a96b0] width 1280 pitch 5120 (/4 1280) >[830685.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[830685.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[830685.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[830685.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[830685.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99590] >[830685.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99590] width 1280 pitch 5120 (/4 1280) >[830685.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99590] >[830685.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99590] width 1280 pitch 5120 (/4 1280) >[830685.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4595ae0] >[830686.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4595ae0] width 1280 pitch 5120 (/4 1280) >[830686.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33328c0] >[830686.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33328c0] width 1280 pitch 5120 (/4 1280) >[830687.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606240] >[830687.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606240] width 1280 pitch 5120 (/4 1280) >[830687.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4595ae0] >[830687.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4595ae0] width 1280 pitch 5120 (/4 1280) >[830687.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3606240] >[830687.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3606240] width 1280 pitch 5120 (/4 1280) >[830687.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4595ae0] >[830687.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4595ae0] width 1280 pitch 5120 (/4 1280) >[830687.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf6de0] >[830687.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf6de0] width 1280 pitch 5120 (/4 1280) >[830687.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365c940] >[830687.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365c940] width 1280 pitch 5120 (/4 1280) >[830687.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669a70] >[830687.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669a70] width 1280 pitch 5120 (/4 1280) >[830687.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3692ac0] >[830687.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3692ac0] width 1280 pitch 5120 (/4 1280) >[830687.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34278e0] >[830687.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34278e0] width 1280 pitch 5120 (/4 1280) >[830687.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a7e30] >[830687.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a7e30] width 1280 pitch 5120 (/4 1280) >[830687.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669a70] >[830687.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669a70] width 1280 pitch 5120 (/4 1280) >[830687.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a7e30] >[830687.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a7e30] width 1280 pitch 5120 (/4 1280) >[830687.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669a70] >[830687.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669a70] width 1280 pitch 5120 (/4 1280) >[830718.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231410] >[830718.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231410] width 1280 pitch 5120 (/4 1280) >[830742.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3231410] >[830742.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3231410] width 1280 pitch 5120 (/4 1280) >[830742.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad94b0] >[830742.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad94b0] width 1280 pitch 5120 (/4 1280) >[830742.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3717ed0] >[830742.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3717ed0] width 1280 pitch 5120 (/4 1280) >[830742.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad94b0] >[830742.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad94b0] width 1280 pitch 5120 (/4 1280) >[830742.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab2590] >[830742.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab2590] width 1280 pitch 5120 (/4 1280) >[830742.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369bc40] >[830742.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369bc40] width 1280 pitch 5120 (/4 1280) >[830742.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab2590] >[830742.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab2590] width 1280 pitch 5120 (/4 1280) >[830742.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x31a36b0] >[830742.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x31a36b0] width 1280 pitch 5120 (/4 1280) >[830742.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab2590] >[830742.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab2590] width 1280 pitch 5120 (/4 1280) >[830742.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36bfed0] >[830742.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36bfed0] width 1280 pitch 5120 (/4 1280) >[830742.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab2590] >[830742.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab2590] width 1280 pitch 5120 (/4 1280) >[830761.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35aeb80] >[830761.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35aeb80] width 1280 pitch 5120 (/4 1280) >[830832.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21260] >[830832.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21260] width 1280 pitch 5120 (/4 1280) >[830832.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b7f0] >[830832.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b7f0] width 1280 pitch 5120 (/4 1280) >[830832.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2cc20] >[830832.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2cc20] width 1280 pitch 5120 (/4 1280) >[830832.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365b7f0] >[830832.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365b7f0] width 1280 pitch 5120 (/4 1280) >[830832.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2cc20] >[830832.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2cc20] width 1280 pitch 5120 (/4 1280) >[830832.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34e95f0] >[830832.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34e95f0] width 1280 pitch 5120 (/4 1280) >[830832.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689d90] >[830832.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689d90] width 1280 pitch 5120 (/4 1280) >[830832.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348deb0] >[830832.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348deb0] width 1280 pitch 5120 (/4 1280) >[830832.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689d90] >[830832.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689d90] width 1280 pitch 5120 (/4 1280) >[830832.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1510] >[830832.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1510] width 1280 pitch 5120 (/4 1280) >[830832.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3689d90] >[830832.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3689d90] width 1280 pitch 5120 (/4 1280) >[830836.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348deb0] >[830836.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348deb0] width 1280 pitch 5120 (/4 1280) >[830836.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1510] >[830837.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1510] width 1280 pitch 5120 (/4 1280) >[830837.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21260] >[830837.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21260] width 1280 pitch 5120 (/4 1280) >[830837.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e1510] >[830837.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e1510] width 1280 pitch 5120 (/4 1280) >[830848.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21260] >[830848.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21260] width 1280 pitch 5120 (/4 1280) >[830848.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348deb0] >[830848.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348deb0] width 1280 pitch 5120 (/4 1280) >[830848.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36eca40] >[830848.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36eca40] width 1280 pitch 5120 (/4 1280) >[830848.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x348deb0] >[830848.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x348deb0] width 1280 pitch 5120 (/4 1280) >[830851.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bf4050] >[830851.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bf4050] width 1280 pitch 5120 (/4 1280) >[830853.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac6130] >[830853.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac6130] width 1280 pitch 5120 (/4 1280) >[830853.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3583b50] >[830854.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3583b50] width 1280 pitch 5120 (/4 1280) >[830854.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36885a0] >[830854.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36885a0] width 1280 pitch 5120 (/4 1280) >[830854.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba70e0] >[830854.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba70e0] width 1280 pitch 5120 (/4 1280) >[830855.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d2e60] >[830855.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d2e60] width 1280 pitch 5120 (/4 1280) >[830864.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ccd10] >[830864.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ccd10] width 1280 pitch 5120 (/4 1280) >[830878.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c542b0] >[830878.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c542b0] width 1280 pitch 5120 (/4 1280) >[830895.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369dec0] >[830895.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369dec0] width 1280 pitch 5120 (/4 1280) >[830895.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dbd40] >[830895.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dbd40] width 1280 pitch 5120 (/4 1280) >[830895.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a96b0] >[830895.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a96b0] width 1280 pitch 5120 (/4 1280) >[830895.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33200e0] >[830895.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33200e0] width 1280 pitch 5120 (/4 1280) >[830895.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34a96b0] >[830895.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34a96b0] width 1280 pitch 5120 (/4 1280) >[830895.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33eebe0] >[830895.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33eebe0] width 1280 pitch 5120 (/4 1280) >[830895.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4585ca0] >[830895.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4585ca0] width 1280 pitch 5120 (/4 1280) >[830895.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362ab10] >[830895.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362ab10] width 1280 pitch 5120 (/4 1280) >[830895.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24040] >[830895.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24040] width 1280 pitch 5120 (/4 1280) >[830896.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830896.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d93f0] >[830896.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d93f0] width 1280 pitch 5120 (/4 1280) >[830896.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341d830] >[830896.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341d830] width 1280 pitch 5120 (/4 1280) >[830921.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33f82b0] >[830921.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33f82b0] width 1280 pitch 5120 (/4 1280) >[830930.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3af55b0] >[830930.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3af55b0] width 1280 pitch 5120 (/4 1280) >[830930.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3370] >[830930.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3370] width 1280 pitch 5120 (/4 1280) >[830930.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cba670] >[830930.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cba670] width 1280 pitch 5120 (/4 1280) >[830930.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3370] >[830930.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3370] width 1280 pitch 5120 (/4 1280) >[830931.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345690] >[830931.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345690] width 1280 pitch 5120 (/4 1280) >[830931.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cba670] >[830931.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cba670] width 1280 pitch 5120 (/4 1280) >[830931.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325490] >[830931.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325490] width 1280 pitch 5120 (/4 1280) >[830931.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4345690] >[830931.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4345690] width 1280 pitch 5120 (/4 1280) >[830932.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3408c30] >[830932.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3408c30] width 1280 pitch 5120 (/4 1280) >[830932.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32b50c0] >[830932.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32b50c0] width 1280 pitch 5120 (/4 1280) >[830952.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e5710] >[830952.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e5710] width 1280 pitch 5120 (/4 1280) >[830953.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x370d3b0] >[830953.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x370d3b0] width 1280 pitch 5120 (/4 1280) >[830954.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c866b0] >[830954.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c866b0] width 1280 pitch 5120 (/4 1280) >[830954.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35979a0] >[830954.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35979a0] width 1280 pitch 5120 (/4 1280) >[830955.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35979a0] >[830955.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35979a0] width 1280 pitch 5120 (/4 1280) >[830955.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3309d00] >[830955.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3309d00] width 1280 pitch 5120 (/4 1280) >[830955.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x343fad0] >[830955.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x343fad0] width 1280 pitch 5120 (/4 1280) >[830968.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x331cae0] >[830968.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x331cae0] width 1280 pitch 5120 (/4 1280) >[830968.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3674a40] >[830969.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3674a40] width 1280 pitch 5120 (/4 1280) >[830970.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20bf0] >[830970.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20bf0] width 1280 pitch 5120 (/4 1280) >[830971.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3643770] >[830971.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3643770] width 1280 pitch 5120 (/4 1280) >[830971.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[830971.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[830973.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beea90] >[830973.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beea90] width 1280 pitch 5120 (/4 1280) >[830973.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cadb0] >[830973.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cadb0] width 1280 pitch 5120 (/4 1280) >[830974.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135e90] >[830974.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135e90] width 1280 pitch 5120 (/4 1280) >[830974.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acc610] >[830974.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acc610] width 1280 pitch 5120 (/4 1280) >[830974.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33870d0] >[830974.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33870d0] width 1280 pitch 5120 (/4 1280) >[831001.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3421820] >[831002.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3421820] width 1280 pitch 5120 (/4 1280) >[831002.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3594070] >[831002.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3594070] width 1280 pitch 5120 (/4 1280) >[831002.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32d25f0] >[831002.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32d25f0] width 1280 pitch 5120 (/4 1280) >[831002.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3594070] >[831002.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3594070] width 1280 pitch 5120 (/4 1280) >[831003.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[831003.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[831003.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3325490] >[831003.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3325490] width 1280 pitch 5120 (/4 1280) >[831004.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c534f0] >[831004.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c534f0] width 1280 pitch 5120 (/4 1280) >[831004.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c092a0] >[831004.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c092a0] width 1280 pitch 5120 (/4 1280) >[831004.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[831004.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[831004.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c092a0] >[831004.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c092a0] width 1280 pitch 5120 (/4 1280) >[831004.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[831004.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[831004.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c092a0] >[831004.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c092a0] width 1280 pitch 5120 (/4 1280) >[831004.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[831004.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[831004.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c092a0] >[831004.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c092a0] width 1280 pitch 5120 (/4 1280) >[831004.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x330eb50] >[831004.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x330eb50] width 1280 pitch 5120 (/4 1280) >[831004.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c092a0] >[831004.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c092a0] width 1280 pitch 5120 (/4 1280) >[831004.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33c9bf0] >[831004.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33c9bf0] width 1280 pitch 5120 (/4 1280) >[831004.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f03c0] >[831004.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f03c0] width 1280 pitch 5120 (/4 1280) >[831004.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x373cef0] >[831004.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x373cef0] width 1280 pitch 5120 (/4 1280) >[831004.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9bd0] >[831004.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9bd0] width 1280 pitch 5120 (/4 1280) >[831005.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x333d970] >[831005.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x333d970] width 1280 pitch 5120 (/4 1280) >[831006.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3732e00] >[831006.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3732e00] width 1280 pitch 5120 (/4 1280) >[831006.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3674a40] >[831006.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3674a40] width 1280 pitch 5120 (/4 1280) >[831006.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad3370] >[831006.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad3370] width 1280 pitch 5120 (/4 1280) >[831006.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3674a40] >[831006.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3674a40] width 1280 pitch 5120 (/4 1280) >[831049.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3674a40] >[831049.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3674a40] width 1280 pitch 5120 (/4 1280) >[831049.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab3d90] >[831049.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab3d90] width 1280 pitch 5120 (/4 1280) >[831049.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4be0] >[831049.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4be0] width 1280 pitch 5120 (/4 1280) >[831049.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35caca0] >[831049.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35caca0] width 1280 pitch 5120 (/4 1280) >[831058.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de020] >[831058.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de020] width 1280 pitch 5120 (/4 1280) >[831061.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b76b0] >[831061.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b76b0] width 1280 pitch 5120 (/4 1280) >[831061.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9adb0] >[831061.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9adb0] width 1280 pitch 5120 (/4 1280) >[831062.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34b76b0] >[831062.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34b76b0] width 1280 pitch 5120 (/4 1280) >[831062.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c140] >[831062.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c140] width 1280 pitch 5120 (/4 1280) >[831070.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35c8c90] >[831070.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35c8c90] width 1280 pitch 5120 (/4 1280) >[831078.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4591d20] >[831078.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4591d20] width 1280 pitch 5120 (/4 1280) >[831095.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8940] >[831095.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8940] width 1280 pitch 5120 (/4 1280) >[831095.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363e390] >[831095.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363e390] width 1280 pitch 5120 (/4 1280) >[831095.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37142f0] >[831095.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37142f0] width 1280 pitch 5120 (/4 1280) >[831095.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3585ae0] >[831095.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3585ae0] width 1280 pitch 5120 (/4 1280) >[831095.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x345d3a0] >[831095.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x345d3a0] width 1280 pitch 5120 (/4 1280) >[831095.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc5590] >[831095.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc5590] width 1280 pitch 5120 (/4 1280) >[831095.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33ea7b0] >[831095.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33ea7b0] width 1280 pitch 5120 (/4 1280) >[831095.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x346deb0] >[831095.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x346deb0] width 1280 pitch 5120 (/4 1280) >[831095.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ab8800] >[831095.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ab8800] width 1280 pitch 5120 (/4 1280) >[831096.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831096.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0480] >[831096.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0480] width 1280 pitch 5120 (/4 1280) >[831096.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3402180] >[831096.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3402180] width 1280 pitch 5120 (/4 1280) >[831135.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3566490] >[831135.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3566490] width 1280 pitch 5120 (/4 1280) >[831173.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9350] >[831173.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9350] width 1280 pitch 5120 (/4 1280) >[831173.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b34e80] >[831173.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b34e80] width 1280 pitch 5120 (/4 1280) >[831173.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9a10] >[831173.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9a10] width 1280 pitch 5120 (/4 1280) >[831173.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33b1000] >[831173.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33b1000] width 1280 pitch 5120 (/4 1280) >[831177.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3255bf0] >[831177.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3255bf0] width 1280 pitch 5120 (/4 1280) >[831177.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aad240] >[831177.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aad240] width 1280 pitch 5120 (/4 1280) >[831177.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358dea0] >[831177.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358dea0] width 1280 pitch 5120 (/4 1280) >[831177.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aad240] >[831177.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aad240] width 1280 pitch 5120 (/4 1280) >[831296.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35827b0] >[831296.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35827b0] width 1280 pitch 5120 (/4 1280) >[831296.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4583be0] >[831296.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4583be0] width 1280 pitch 5120 (/4 1280) >[831296.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36867e0] >[831296.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36867e0] width 1280 pitch 5120 (/4 1280) >[831296.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334c110] >[831296.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334c110] width 1280 pitch 5120 (/4 1280) >[831303.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2db0] >[831303.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2db0] width 1280 pitch 5120 (/4 1280) >[831312.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2e50] >[831312.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2e50] width 1280 pitch 5120 (/4 1280) >[831312.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adeb50] >[831312.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adeb50] width 1280 pitch 5120 (/4 1280) >[831312.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2e50] >[831312.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2e50] width 1280 pitch 5120 (/4 1280) >[831576.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f2e50] >[831577.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f2e50] width 1280 pitch 5120 (/4 1280) >[831577.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e20b0] >[831577.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e20b0] width 1280 pitch 5120 (/4 1280) >[831577.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c956d0] >[831577.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c956d0] width 1280 pitch 5120 (/4 1280) >[831577.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1580] >[831577.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1580] width 1280 pitch 5120 (/4 1280) >[831583.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfdb90] >[831583.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfdb90] width 1280 pitch 5120 (/4 1280) >[831588.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bfdb90] >[831588.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bfdb90] width 1280 pitch 5120 (/4 1280) >[831588.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cf520] >[831588.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cf520] width 1280 pitch 5120 (/4 1280) >[831588.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aa9350] >[831588.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aa9350] width 1280 pitch 5120 (/4 1280) >[831588.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9a10] >[831588.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9a10] width 1280 pitch 5120 (/4 1280) >[831601.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cd180] >[831601.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cd180] width 1280 pitch 5120 (/4 1280) >[831606.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33fe6e0] >[831606.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33fe6e0] width 1280 pitch 5120 (/4 1280) >[831606.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9a10] >[831606.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9a10] width 1280 pitch 5120 (/4 1280) >[831606.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x358de80] >[831606.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x358de80] width 1280 pitch 5120 (/4 1280) >[831607.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9a10] >[831607.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9a10] width 1280 pitch 5120 (/4 1280) >[831642.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4e30] >[831642.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4e30] width 1280 pitch 5120 (/4 1280) >[831643.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0040] >[831643.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0040] width 1280 pitch 5120 (/4 1280) >[831643.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3695990] >[831643.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3695990] width 1280 pitch 5120 (/4 1280) >[831643.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adeb50] >[831643.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adeb50] width 1280 pitch 5120 (/4 1280) >[831643.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaecd0] >[831643.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaecd0] width 1280 pitch 5120 (/4 1280) >[831895.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334c110] >[831895.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334c110] width 1280 pitch 5120 (/4 1280) >[831896.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3740] >[831896.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3740] width 1280 pitch 5120 (/4 1280) >[831896.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x334c110] >[831896.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x334c110] width 1280 pitch 5120 (/4 1280) >[831896.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32f3740] >[831896.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32f3740] width 1280 pitch 5120 (/4 1280) >[831901.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34c0040] >[831901.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34c0040] width 1280 pitch 5120 (/4 1280) >[831904.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33e29f0] >[831904.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33e29f0] width 1280 pitch 5120 (/4 1280) >[831904.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32326c0] >[831904.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32326c0] width 1280 pitch 5120 (/4 1280) >[831931.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73520] >[831931.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73520] width 1280 pitch 5120 (/4 1280) >[831931.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374af00] >[831931.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374af00] width 1280 pitch 5120 (/4 1280) >[831931.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73520] >[831931.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73520] width 1280 pitch 5120 (/4 1280) >[831931.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374af00] >[831931.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374af00] width 1280 pitch 5120 (/4 1280) >[832064.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4569720] >[832064.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4569720] width 1280 pitch 5120 (/4 1280) >[832079.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fd70] >[832079.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fd70] width 1280 pitch 5120 (/4 1280) >[832079.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fb90] >[832079.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fb90] width 1280 pitch 5120 (/4 1280) >[832079.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x45696c0] >[832079.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x45696c0] width 1280 pitch 5120 (/4 1280) >[832079.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd6c90] >[832079.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd6c90] width 1280 pitch 5120 (/4 1280) >[832108.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x324fb90] >[832108.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x324fb90] width 1280 pitch 5120 (/4 1280) >[832109.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaed90] >[832109.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaed90] width 1280 pitch 5120 (/4 1280) >[832109.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4e30] >[832109.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4e30] width 1280 pitch 5120 (/4 1280) >[832109.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaed90] >[832109.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaed90] width 1280 pitch 5120 (/4 1280) >[832122.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adeb50] >[832123.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adeb50] width 1280 pitch 5120 (/4 1280) >[832123.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cf600] >[832123.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cf600] width 1280 pitch 5120 (/4 1280) >[832123.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341bc70] >[832123.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341bc70] width 1280 pitch 5120 (/4 1280) >[832123.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cf600] >[832123.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cf600] width 1280 pitch 5120 (/4 1280) >[832155.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32c4e30] >[832155.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32c4e30] width 1280 pitch 5120 (/4 1280) >[832155.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1580] >[832155.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1580] width 1280 pitch 5120 (/4 1280) >[832184.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1580] >[832184.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1580] width 1280 pitch 5120 (/4 1280) >[832184.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aaecd0] >[832184.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4aaecd0] width 1280 pitch 5120 (/4 1280) >[832184.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362fcc0] >[832184.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362fcc0] width 1280 pitch 5120 (/4 1280) >[832184.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37277a0] >[832185.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37277a0] width 1280 pitch 5120 (/4 1280) >[832197.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302ab0] >[832197.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302ab0] width 1280 pitch 5120 (/4 1280) >[832197.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302ab0] >[832197.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302ab0] width 1280 pitch 5120 (/4 1280) >[832197.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b34e80] >[832197.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b34e80] width 1280 pitch 5120 (/4 1280) >[832197.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3302ab0] >[832197.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3302ab0] width 1280 pitch 5120 (/4 1280) >[832225.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adeb50] >[832225.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adeb50] width 1280 pitch 5120 (/4 1280) >[832226.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b34e80] >[832226.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b34e80] width 1280 pitch 5120 (/4 1280) >[832226.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362fcc0] >[832226.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362fcc0] width 1280 pitch 5120 (/4 1280) >[832226.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x341bc70] >[832226.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x341bc70] width 1280 pitch 5120 (/4 1280) >[832265.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3135f00] >[832265.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3135f00] width 1280 pitch 5120 (/4 1280) >[832334.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832334.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832334.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832334.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832334.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832334.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832334.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832335.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832335.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b560] >[832335.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b560] width 1280 pitch 5120 (/4 1280) >[832335.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832335.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832335.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832335.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832335.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832335.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832335.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832335.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832335.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832335.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832336.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832336.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832336.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832336.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832337.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832337.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832337.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832337.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832337.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x374ad30] >[832337.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x374ad30] width 1280 pitch 5120 (/4 1280) >[832337.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b560] >[832337.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b560] width 1280 pitch 5120 (/4 1280) >[832337.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0760] >[832337.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0760] width 1280 pitch 5120 (/4 1280) >[832337.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b560] >[832337.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b560] width 1280 pitch 5120 (/4 1280) >[832337.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35a0760] >[832337.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35a0760] width 1280 pitch 5120 (/4 1280) >[832337.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b560] >[832337.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b560] width 1280 pitch 5120 (/4 1280) >[832337.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac94a0] >[832337.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac94a0] width 1280 pitch 5120 (/4 1280) >[832337.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b560] >[832337.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b560] width 1280 pitch 5120 (/4 1280) >[832337.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac94a0] >[832337.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac94a0] width 1280 pitch 5120 (/4 1280) >[832337.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832337.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832337.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36566d0] >[832337.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36566d0] width 1280 pitch 5120 (/4 1280) >[832337.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832337.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832337.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580110] >[832338.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580110] width 1280 pitch 5120 (/4 1280) >[832338.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832338.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832338.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580110] >[832338.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580110] width 1280 pitch 5120 (/4 1280) >[832338.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832338.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832338.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36566d0] >[832338.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36566d0] width 1280 pitch 5120 (/4 1280) >[832338.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832338.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832338.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36566d0] >[832338.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36566d0] width 1280 pitch 5120 (/4 1280) >[832338.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832338.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832338.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36566d0] >[832338.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36566d0] width 1280 pitch 5120 (/4 1280) >[832338.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832338.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832338.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36566d0] >[832338.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36566d0] width 1280 pitch 5120 (/4 1280) >[832338.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3580110] >[832338.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3580110] width 1280 pitch 5120 (/4 1280) >[832339.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf00] >[832339.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf00] width 1280 pitch 5120 (/4 1280) >[832339.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf00] >[832339.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf00] width 1280 pitch 5120 (/4 1280) >[832339.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365ae90] >[832339.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365ae90] width 1280 pitch 5120 (/4 1280) >[832339.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf00] >[832339.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf00] width 1280 pitch 5120 (/4 1280) >[832339.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365ae90] >[832339.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365ae90] width 1280 pitch 5120 (/4 1280) >[832339.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf00] >[832339.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf00] width 1280 pitch 5120 (/4 1280) >[832339.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365ae90] >[832339.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365ae90] width 1280 pitch 5120 (/4 1280) >[832339.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365ae90] >[832339.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365ae90] width 1280 pitch 5120 (/4 1280) >[832339.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x365ae90] >[832339.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x365ae90] width 1280 pitch 5120 (/4 1280) >[832339.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db20] >[832339.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db20] width 1280 pitch 5120 (/4 1280) >[832342.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x315c3f0] >[832342.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x315c3f0] width 1280 pitch 5120 (/4 1280) >[832342.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3248140] >[832342.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3248140] width 1280 pitch 5120 (/4 1280) >[832342.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3591e20] >[832342.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3591e20] width 1280 pitch 5120 (/4 1280) >[832342.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3622370] >[832342.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3622370] width 1280 pitch 5120 (/4 1280) >[832343.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb08c0] >[832343.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb08c0] width 1280 pitch 5120 (/4 1280) >[832378.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33567e0] >[832378.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33567e0] width 1280 pitch 5120 (/4 1280) >[832378.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c09420] >[832378.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c09420] width 1280 pitch 5120 (/4 1280) >[832378.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c09420] >[832378.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c09420] width 1280 pitch 5120 (/4 1280) >[832378.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cfae0] >[832378.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cfae0] width 1280 pitch 5120 (/4 1280) >[832381.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60050] >[832381.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60050] width 1280 pitch 5120 (/4 1280) >[832382.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140c60] >[832382.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140c60] width 1280 pitch 5120 (/4 1280) >[832382.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34719e0] >[832382.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34719e0] width 1280 pitch 5120 (/4 1280) >[832382.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x32cc1a0] >[832382.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x32cc1a0] width 1280 pitch 5120 (/4 1280) >[832382.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3260310] >[832382.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3260310] width 1280 pitch 5120 (/4 1280) >[832411.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33a6ca0] >[832411.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33a6ca0] width 1280 pitch 5120 (/4 1280) >[832411.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832411.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832411.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cfae0] >[832411.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cfae0] width 1280 pitch 5120 (/4 1280) >[832411.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34719e0] >[832411.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34719e0] width 1280 pitch 5120 (/4 1280) >[832413.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832414.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x33cfae0] >[832414.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x33cfae0] width 1280 pitch 5120 (/4 1280) >[832414.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832414.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832414.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf60] >[832414.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf60] width 1280 pitch 5120 (/4 1280) >[832414.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832414.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf60] >[832414.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf60] width 1280 pitch 5120 (/4 1280) >[832414.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832414.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf60] >[832414.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf60] width 1280 pitch 5120 (/4 1280) >[832414.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832414.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf60] >[832414.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf60] width 1280 pitch 5120 (/4 1280) >[832414.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832414.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf60] >[832414.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf60] width 1280 pitch 5120 (/4 1280) >[832414.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4abae80] >[832414.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4abae80] width 1280 pitch 5120 (/4 1280) >[832416.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832416.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832416.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3140c60] >[832416.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3140c60] width 1280 pitch 5120 (/4 1280) >[832416.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36f1580] >[832416.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36f1580] width 1280 pitch 5120 (/4 1280) >[832417.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35cf600] >[832417.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35cf600] width 1280 pitch 5120 (/4 1280) >[832417.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cb90] >[832417.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cb90] width 1280 pitch 5120 (/4 1280) >[832417.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6a810] >[832417.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6a810] width 1280 pitch 5120 (/4 1280) >[832417.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3260ec0] >[832417.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3260ec0] width 1280 pitch 5120 (/4 1280) >[832417.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3633570] >[832417.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3633570] width 1280 pitch 5120 (/4 1280) >[833019.547] (II) RADEON(0): EDID vendor "DEL", prod id 16421 >[833019.547] (II) RADEON(0): Using hsync ranges from config file >[833019.547] (II) RADEON(0): Using vrefresh ranges from config file >[833019.547] (II) RADEON(0): Printing DDC gathered Modelines: >[833019.547] (II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz eP) >[833019.547] (II) RADEON(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) >[833019.547] (II) RADEON(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) >[833019.547] (II) RADEON(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) >[833019.547] (II) RADEON(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) >[833019.547] (II) RADEON(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) >[833019.547] (II) RADEON(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) >[833019.547] (II) RADEON(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) >[833019.547] (II) RADEON(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) >[833019.547] (II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) >[833109.536] (II) RADEON(0): RADEONSaveScreen(2) >[833109.536] (II) RADEON(0): RADEONSaveScreen(0) >[849804.979] (II) RADEON(0): RADEONSaveScreen(1) >[849805.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4aecb20] >[849811.209] [mi] EQ overflowing. Additional events will be discarded until existing events are processed. >[849811.209] >[849811.210] Backtrace: >[849811.369] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[849811.369] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x55155b] >[849811.369] 2: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[849811.369] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fab556e8000+0x60e4) [0x7fab556ee0e4] >[849811.369] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[849811.369] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[849811.369] 6: /lib64/libpthread.so.0 (0x7fab579d8000+0xefe0) [0x7fab579e6fe0] >[849811.369] 7: /lib64/libc.so.6 (ioctl+0x7) [0x7fab57202307] >[849811.369] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x7fab5622b658] >[849811.369] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x7fab5622d8cc] >[849811.370] 10: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2009) [0x7fab558fa009] >[849811.370] 11: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2234) [0x7fab558fa234] >[849811.370] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fab55b08000+0xacb4a) [0x7fab55bb4b4a] >[849811.370] 13: /usr/lib64/xorg/modules/libexa.so (0x7fab550c8000+0xafaf) [0x7fab550d2faf] >[849811.370] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543] >[849811.370] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20] >[849811.370] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8] >[849811.370] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[849811.370] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[849811.370] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fab57139735] >[849811.370] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[849811.370] >[849811.370] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack. >[849811.370] [mi] mieq is *NOT* the cause. It is a victim. >[849811.770] [mi] EQ overflow continuing. 100 events have been dropped. >[849811.770] >[849811.770] Backtrace: >[849811.770] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[849811.770] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[849811.770] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fab556e8000+0x60e4) [0x7fab556ee0e4] >[849811.770] 3: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[849811.770] 4: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[849811.770] 5: /lib64/libpthread.so.0 (0x7fab579d8000+0xefe0) [0x7fab579e6fe0] >[849811.770] 6: /lib64/libc.so.6 (ioctl+0x7) [0x7fab57202307] >[849811.770] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x7fab5622b658] >[849811.770] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x7fab5622d8cc] >[849811.770] 9: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2009) [0x7fab558fa009] >[849811.771] 10: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2234) [0x7fab558fa234] >[849811.771] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fab55b08000+0xacb4a) [0x7fab55bb4b4a] >[849811.771] 12: /usr/lib64/xorg/modules/libexa.so (0x7fab550c8000+0xafaf) [0x7fab550d2faf] >[849811.771] 13: /usr/bin/Xorg (0x400000+0x160543) [0x560543] >[849811.771] 14: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20] >[849811.771] 15: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8] >[849811.771] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[849811.771] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[849811.771] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fab57139735] >[849811.771] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[849811.771] >[849812.594] [mi] EQ overflow continuing. 200 events have been dropped. >[849812.594] >[849812.594] Backtrace: >[849812.594] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[849812.594] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[849812.594] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fab556e8000+0x60e4) [0x7fab556ee0e4] >[849812.594] 3: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[849812.594] 4: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[849812.594] 5: /lib64/libpthread.so.0 (0x7fab579d8000+0xefe0) [0x7fab579e6fe0] >[849812.595] 6: /lib64/libc.so.6 (ioctl+0x7) [0x7fab57202307] >[849812.595] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x7fab5622b658] >[849812.595] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x7fab5622d8cc] >[849812.595] 9: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2009) [0x7fab558fa009] >[849812.595] 10: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2234) [0x7fab558fa234] >[849812.595] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fab55b08000+0xacb4a) [0x7fab55bb4b4a] >[849812.595] 12: /usr/lib64/xorg/modules/libexa.so (0x7fab550c8000+0xafaf) [0x7fab550d2faf] >[849812.595] 13: /usr/bin/Xorg (0x400000+0x160543) [0x560543] >[849812.595] 14: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20] >[849812.595] 15: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8] >[849812.595] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[849812.595] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[849812.595] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fab57139735] >[849812.595] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[849812.595] >[849813.026] [mi] EQ overflow continuing. 300 events have been dropped. >[849813.026] >[849813.026] Backtrace: >[849813.026] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[849813.026] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[849813.026] 2: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fab556e8000+0x60e4) [0x7fab556ee0e4] >[849813.026] 3: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[849813.026] 4: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[849813.026] 5: /lib64/libpthread.so.0 (0x7fab579d8000+0xefe0) [0x7fab579e6fe0] >[849813.026] 6: /lib64/libc.so.6 (ioctl+0x7) [0x7fab57202307] >[849813.026] 7: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x7fab5622b658] >[849813.026] 8: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x7fab5622d8cc] >[849813.026] 9: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2009) [0x7fab558fa009] >[849813.026] 10: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2234) [0x7fab558fa234] >[849813.026] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fab55b08000+0xacb4a) [0x7fab55bb4b4a] >[849813.026] 12: /usr/lib64/xorg/modules/libexa.so (0x7fab550c8000+0xafaf) [0x7fab550d2faf] >[849813.026] 13: /usr/bin/Xorg (0x400000+0x160543) [0x560543] >[849813.026] 14: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20] >[849813.026] 15: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8] >[849813.026] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[849813.026] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[849813.026] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fab57139735] >[849813.026] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[849813.026] >[849814.023] [mi] EQ overflow continuing. 400 events have been dropped. >[849814.023] >[849814.023] Backtrace: >[849814.023] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326] >[849814.023] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22] >[849814.023] 2: /usr/bin/Xorg (xf86PostKeyboardEvent+0x4b) [0x49091b] >[849814.023] 3: /usr/lib64/xorg/modules/input/evdev_drv.so (0x7fab556e8000+0x611f) [0x7fab556ee11f] >[849814.023] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817] >[849814.023] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00] >[849814.023] 6: /lib64/libpthread.so.0 (0x7fab579d8000+0xefe0) [0x7fab579e6fe0] >[849814.023] 7: /lib64/libc.so.6 (ioctl+0x7) [0x7fab57202307] >[849814.023] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x7fab5622b658] >[849814.023] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x7fab5622d8cc] >[849814.023] 10: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2009) [0x7fab558fa009] >[849814.024] 11: /lib64/libdrm_radeon.so.1 (0x7fab558f8000+0x2234) [0x7fab558fa234] >[849814.024] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7fab55b08000+0xacb4a) [0x7fab55bb4b4a] >[849814.024] 13: /usr/lib64/xorg/modules/libexa.so (0x7fab550c8000+0xafaf) [0x7fab550d2faf] >[849814.024] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543] >[849814.024] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20] >[849814.024] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8] >[849814.024] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a] >[849814.024] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475] >[849814.024] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fab57139735] >[849814.024] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d] >[849814.024]
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