Attachment 669858 Details for Bug 890653 – File: Xorg.0.log

File: Xorg.0.log

Xorg.0.log (text/plain), 7.60 MB, created by Václav Jansa on 2012-12-28 13:55:56 UTC

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Creator: Václav Jansa

Created: 2012-12-28 13:55:56 UTC

Size: 7.60 MB

patch

obsolete

>[    40.806] 
>X.Org X Server 1.12.4
>Release Date: 2012-08-27
>[    40.806] X Protocol Version 11, Revision 0
>[    40.806] Build Operating System:  2.6.32-279.9.1.el6.x86_64 
>[    40.806] Current Operating System: Linux mozart.ntkcz.cz 3.6.10-2.fc17.x86_64 #1 SMP Tue Dec 11 18:07:34 UTC 2012 x86_64
>[    40.807] Kernel command line: BOOT_IMAGE=/vmlinuz-3.6.10-2.fc17.x86_64 root=/dev/mapper/vg_mozart-root ro rd.md=0 rd.dm=0 rd.lvm.lv=vg_mozart/root KEYTABLE=us quiet SYSFONT=latarcyrheb-sun16 rhgb rd.luks=0 rd.lvm.lv=vg_mozart/swap LANG=en_US.UTF-8
>[    40.807] Build Date: 28 November 2012  05:10:39PM
>[    40.807] Build ID: xorg-x11-server 1.12.4-1.fc17 
>[    40.807] Current version of pixman: 0.24.4
>[    40.807] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    40.807] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    40.807] (==) Log file: "/var/log/Xorg.0.log", Time: Tue Dec 18 21:07:49 2012
>[    40.826] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    40.827] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
>[    40.827] (==) No Layout section.  Using the first Screen section.
>[    40.827] (==) No screen section available. Using defaults.
>[    40.827] (**) |-->Screen "Default Screen Section" (0)
>[    40.827] (**) |   |-->Monitor "<default monitor>"
>[    40.827] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    40.827] (==) Automatically adding devices
>[    40.827] (==) Automatically enabling devices
>[    40.827] (==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>[    40.827] (==) ModulePath set to "/usr/lib64/xorg/modules"
>[    40.827] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    40.827] (II) Loader magic: 0x7c6ac0
>[    40.827] (II) Module ABI versions:
>[    40.827] 	X.Org ANSI C Emulation: 0.4
>[    40.827] 	X.Org Video Driver: 12.1
>[    40.827] 	X.Org XInput driver : 16.0
>[    40.827] 	X.Org Server Extension : 6.0
>[    40.828] (--) PCI:*(0:1:0:0) 1002:6760:103c:161e rev 0, Mem @ 0xc0000000/268435456, 0xd4400000/131072, I/O @ 0x00004000/256, BIOS @ 0x????????/131072
>[    40.828] (II) LoadModule: "extmod"
>[    40.866] (II) Loading /usr/lib64/xorg/modules/extensions/libextmod.so
>[    40.867] (II) Module extmod: vendor="X.Org Foundation"
>[    40.867] 	compiled for 1.12.4, module version = 1.0.0
>[    40.867] 	Module class: X.Org Server Extension
>[    40.867] 	ABI class: X.Org Server Extension, version 6.0
>[    40.867] (II) Loading extension SELinux
>[    40.867] (II) Loading extension MIT-SCREEN-SAVER
>[    40.867] (II) Loading extension XFree86-VidModeExtension
>[    40.867] (II) Loading extension XFree86-DGA
>[    40.867] (II) Loading extension DPMS
>[    40.867] (II) Loading extension XVideo
>[    40.867] (II) Loading extension XVideo-MotionCompensation
>[    40.867] (II) Loading extension X-Resource
>[    40.867] (II) LoadModule: "dbe"
>[    40.867] (II) Loading /usr/lib64/xorg/modules/extensions/libdbe.so
>[    40.867] (II) Module dbe: vendor="X.Org Foundation"
>[    40.867] 	compiled for 1.12.4, module version = 1.0.0
>[    40.867] 	Module class: X.Org Server Extension
>[    40.867] 	ABI class: X.Org Server Extension, version 6.0
>[    40.867] (II) Loading extension DOUBLE-BUFFER
>[    40.867] (II) LoadModule: "glx"
>[    40.867] (II) Loading /usr/lib64/xorg/modules/extensions/libglx.so
>[    40.867] (II) Module glx: vendor="X.Org Foundation"
>[    40.867] 	compiled for 1.12.4, module version = 1.0.0
>[    40.867] 	ABI class: X.Org Server Extension, version 6.0
>[    40.867] (==) AIGLX enabled
>[    40.867] (II) Loading extension GLX
>[    40.867] (II) LoadModule: "record"
>[    40.867] (II) Loading /usr/lib64/xorg/modules/extensions/librecord.so
>[    40.867] (II) Module record: vendor="X.Org Foundation"
>[    40.867] 	compiled for 1.12.4, module version = 1.13.0
>[    40.867] 	Module class: X.Org Server Extension
>[    40.867] 	ABI class: X.Org Server Extension, version 6.0
>[    40.867] (II) Loading extension RECORD
>[    40.867] (II) LoadModule: "dri"
>[    40.868] (II) Loading /usr/lib64/xorg/modules/extensions/libdri.so
>[    40.868] (II) Module dri: vendor="X.Org Foundation"
>[    40.868] 	compiled for 1.12.4, module version = 1.0.0
>[    40.868] 	ABI class: X.Org Server Extension, version 6.0
>[    40.868] (II) Loading extension XFree86-DRI
>[    40.868] (II) LoadModule: "dri2"
>[    40.868] (II) Loading /usr/lib64/xorg/modules/extensions/libdri2.so
>[    40.868] (II) Module dri2: vendor="X.Org Foundation"
>[    40.868] 	compiled for 1.12.4, module version = 1.2.0
>[    40.868] 	ABI class: X.Org Server Extension, version 6.0
>[    40.868] (II) Loading extension DRI2
>[    40.868] (==) Matched ati as autoconfigured driver 0
>[    40.868] (==) Matched vesa as autoconfigured driver 1
>[    40.868] (==) Matched modesetting as autoconfigured driver 2
>[    40.868] (==) Matched fbdev as autoconfigured driver 3
>[    40.868] (==) Assigned the driver to the xf86ConfigLayout
>[    40.868] (II) LoadModule: "ati"
>[    40.868] (II) Loading /usr/lib64/xorg/modules/drivers/ati_drv.so
>[    40.868] (II) Module ati: vendor="X.Org Foundation"
>[    40.868] 	compiled for 1.12.0, module version = 6.14.99
>[    40.868] 	Module class: X.Org Video Driver
>[    40.868] 	ABI class: X.Org Video Driver, version 12.0
>[    40.868] (II) LoadModule: "radeon"
>[    40.868] (II) Loading /usr/lib64/xorg/modules/drivers/radeon_drv.so
>[    40.868] (II) Module radeon: vendor="X.Org Foundation"
>[    40.868] 	compiled for 1.12.0, module version = 6.14.99
>[    40.868] 	Module class: X.Org Video Driver
>[    40.868] 	ABI class: X.Org Video Driver, version 12.0
>[    40.868] (II) LoadModule: "vesa"
>[    40.868] (II) Loading /usr/lib64/xorg/modules/drivers/vesa_drv.so
>[    40.868] (II) Module vesa: vendor="X.Org Foundation"
>[    40.868] 	compiled for 1.12.0, module version = 2.3.1
>[    40.868] 	Module class: X.Org Video Driver
>[    40.868] 	ABI class: X.Org Video Driver, version 12.0
>[    40.868] (II) LoadModule: "modesetting"
>[    40.869] (II) Loading /usr/lib64/xorg/modules/drivers/modesetting_drv.so
>[    40.869] (II) Module modesetting: vendor="X.Org Foundation"
>[    40.869] 	compiled for 1.12.2, module version = 0.4.0
>[    40.869] 	Module class: X.Org Video Driver
>[    40.869] 	ABI class: X.Org Video Driver, version 12.0
>[    40.869] (II) LoadModule: "fbdev"
>[    40.869] (II) Loading /usr/lib64/xorg/modules/drivers/fbdev_drv.so
>[    40.869] (II) Module fbdev: vendor="X.Org Foundation"
>[    40.869] 	compiled for 1.11.99.901, module version = 0.4.2
>[    40.869] 	ABI class: X.Org Video Driver, version 12.0
>[    40.869] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI FireMV 2400 PCI,
>	ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP),
>	ATI Radeon 9600TX NF (AGP), ATI FireGL X1 NG (AGP),
>	ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP),
>	ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, SUMO, SUMO, SUMO2, SUMO2, SUMO2, SUMO2,
>	SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, SUMO, ATI Radeon HD 4200,
>	ATI Radeon 4100, ATI Mobility Radeon HD 4200,
>	ATI Mobility Radeon 4100, ATI Radeon HD 4290, ATI Radeon HD 4250,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, PALM, PALM, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900 Series, AMD Radeon HD 6900 Series, CAYMAN, CAYMAN,
>	CAYMAN, AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series,
>	BARTS, BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, ARUBA, ARUBA, ARUBA,
>	ARUBA, ARUBA, ARUBA, ARUBA
>[    40.871] (II) VESA: driver for VESA chipsets: vesa
>[    40.871] (II) modesetting: Driver for Modesetting Kernel Drivers: kms
>[    40.871] (II) FBDEV: driver for framebuffer: fbdev
>[    40.871] (++) using VT number 1
>
>[    40.872] (II) [KMS] Kernel modesetting enabled.
>[    40.872] (WW) Falling back to old probe method for vesa
>[    40.872] (WW) Falling back to old probe method for modesetting
>[    40.872] (WW) Falling back to old probe method for fbdev
>[    40.872] (II) Loading sub module "fbdevhw"
>[    40.872] (II) LoadModule: "fbdevhw"
>[    40.872] (II) Loading /usr/lib64/xorg/modules/libfbdevhw.so
>[    40.872] (II) Module fbdevhw: vendor="X.Org Foundation"
>[    40.872] 	compiled for 1.12.4, module version = 0.0.2
>[    40.872] 	ABI class: X.Org Video Driver, version 12.1
>[    40.872] (II) RADEON(0): RADEONPreInit_KMS
>[    40.872] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    40.872] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    40.872] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    40.872] (==) RADEON(0): Default visual is TrueColor
>[    40.872] (==) RADEON(0): RGB weight 888
>[    40.872] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    40.872] (--) RADEON(0): Chipset: "CAICOS" (ChipID = 0x6760)
>[    40.872] (II) RADEON(0): PCIE card detected
>[    40.872] drmOpenDevice: node name is /dev/dri/card0
>[    40.872] drmOpenDevice: open result is 8, (OK)
>[    40.872] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    40.872] drmOpenDevice: node name is /dev/dri/card0
>[    40.872] drmOpenDevice: open result is 8, (OK)
>[    40.872] drmOpenByBusid: drmOpenMinor returns 8
>[    40.872] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    40.872] (II) Loading sub module "exa"
>[    40.872] (II) LoadModule: "exa"
>[    40.872] (II) Loading /usr/lib64/xorg/modules/libexa.so
>[    40.872] (II) Module exa: vendor="X.Org Foundation"
>[    40.872] 	compiled for 1.12.4, module version = 2.5.0
>[    40.872] 	ABI class: X.Org Video Driver, version 12.1
>[    40.872] (II) RADEON(0): KMS Color Tiling: enabled
>[    40.872] (II) RADEON(0): KMS Pageflipping: enabled
>[    40.872] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    40.872] (II) RADEON(0): Output LVDS has no monitor section
>[    40.878] (II) RADEON(0): Output DisplayPort-0 has no monitor section
>[    40.884] (II) RADEON(0): Output DisplayPort-1 has no monitor section
>[    40.892] (II) RADEON(0): Output DisplayPort-2 has no monitor section
>[    40.922] (II) RADEON(0): Output VGA-0 has no monitor section
>[    40.922] (II) RADEON(0): EDID for output LVDS
>[    40.922] (II) RADEON(0): Manufacturer: AUO  Model: 223e  Serial#: 0
>[    40.922] (II) RADEON(0): Year: 2010  Week: 34
>[    40.922] (II) RADEON(0): EDID Version: 1.3
>[    40.922] (II) RADEON(0): Digital Display Input
>[    40.922] (II) RADEON(0): Max Image Size [cm]: horiz.: 31  vert.: 17
>[    40.922] (II) RADEON(0): Gamma: 2.20
>[    40.922] (II) RADEON(0): No DPMS capabilities specified
>[    40.922] (II) RADEON(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
>[    40.922] (II) RADEON(0): First detailed timing is preferred mode
>[    40.922] (II) RADEON(0): redX: 0.610 redY: 0.350   greenX: 0.320 greenY: 0.560
>[    40.922] (II) RADEON(0): blueX: 0.150 blueY: 0.130   whiteX: 0.313 whiteY: 0.329
>[    40.922] (II) RADEON(0): Manufacturer's mask: 0
>[    40.922] (II) RADEON(0): Supported detailed timing:
>[    40.922] (II) RADEON(0): clock: 107.8 MHz   Image Size:  309 x 174 mm
>[    40.922] (II) RADEON(0): h_active: 1600  h_sync: 1664  h_sync_end 1706 h_blank_end 1970 h_border: 0
>[    40.922] (II) RADEON(0): v_active: 900  v_sync: 903  v_sync_end 906 v_blanking: 912 v_border: 0
>[    40.922] (II) RADEON(0): Supported detailed timing:
>[    40.922] (II) RADEON(0): clock: 71.9 MHz   Image Size:  309 x 174 mm
>[    40.922] (II) RADEON(0): h_active: 1600  h_sync: 1664  h_sync_end 1706 h_blank_end 1970 h_border: 0
>[    40.922] (II) RADEON(0): v_active: 900  v_sync: 903  v_sync_end 906 v_blanking: 912 v_border: 0
>[    40.922] (II) RADEON(0): Unknown vendor-specific block 2
>[    40.922] (II) RADEON(0): EDID (in hex):
>[    40.922] (II) RADEON(0): 	00ffffffffffff0006af3e2200000000
>[    40.922] (II) RADEON(0): 	22140103801f11780a61959c59528f26
>[    40.922] (II) RADEON(0): 	21505400000001010101010101010101
>[    40.922] (II) RADEON(0): 	0101010101011c2a407261840c30402a
>[    40.922] (II) RADEON(0): 	330035ae10000018131c407261840c30
>[    40.922] (II) RADEON(0): 	402a330035ae10000018000000000000
>[    40.922] (II) RADEON(0): 	00000000000000000000000000000002
>[    40.922] (II) RADEON(0): 	000b48f50a3c64140e1a68202020005b
>[    40.922] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[    40.922] (II) RADEON(0): Printing DDC gathered Modelines:
>[    40.922] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    40.922] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    40.922] (II) RADEON(0): Printing probed modes for output LVDS
>[    40.922] (II) RADEON(0): Modeline "1600x900"x60.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    40.922] (II) RADEON(0): Modeline "1600x900"x40.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    40.922] (II) RADEON(0): Modeline "1440x900"x59.9  106.50  1440 1528 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz)
>[    40.922] (II) RADEON(0): Modeline "1280x854"x59.9   89.25  1280 1352 1480 1680  854 857 867 887 -hsync +vsync (53.1 kHz)
>[    40.922] (II) RADEON(0): Modeline "1280x800"x59.8   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz)
>[    40.922] (II) RADEON(0): Modeline "1280x720"x59.9   74.50  1280 1344 1472 1664  720 723 728 748 -hsync +vsync (44.8 kHz)
>[    40.922] (II) RADEON(0): Modeline "1152x768"x59.8   71.75  1152 1216 1328 1504  768 771 781 798 -hsync +vsync (47.7 kHz)
>[    40.923] (II) RADEON(0): Modeline "1024x768"x120.1  133.47  1024 1100 1212 1400  768 768 770 794 doublescan -hsync +vsync (95.3 kHz d)
>[    40.923] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz d)
>[    40.923] (II) RADEON(0): Modeline "1024x768"x59.9   63.50  1024 1072 1176 1328  768 771 775 798 -hsync +vsync (47.8 kHz)
>[    40.923] (II) RADEON(0): Modeline "960x720"x120.0  117.00  960 1024 1128 1300  720 720 722 750 doublescan -hsync +vsync (90.0 kHz d)
>[    40.923] (II) RADEON(0): Modeline "928x696"x120.1  109.15  928 976 1088 1264  696 696 698 719 doublescan -hsync +vsync (86.4 kHz d)
>[    40.923] (II) RADEON(0): Modeline "896x672"x120.0  102.40  896 960 1060 1224  672 672 674 697 doublescan -hsync +vsync (83.7 kHz d)
>[    40.923] (II) RADEON(0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
>[    40.923] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
>[    40.923] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    40.923] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
>[    40.923] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    40.923] (II) RADEON(0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
>[    40.923] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    40.923] (II) RADEON(0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
>[    40.923] (II) RADEON(0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
>[    40.923] (II) RADEON(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
>[    40.923] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    40.923] (II) RADEON(0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
>[    40.923] (II) RADEON(0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
>[    40.923] (II) RADEON(0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
>[    40.923] (II) RADEON(0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
>[    40.929] (II) RADEON(0): EDID for output DisplayPort-0
>[    40.935] (II) RADEON(0): EDID for output DisplayPort-1
>[    40.943] (II) RADEON(0): EDID for output DisplayPort-2
>[    40.973] (II) RADEON(0): EDID for output VGA-0
>[    40.973] (II) RADEON(0): Manufacturer: SAM  Model: 577  Serial#: 1162228274
>[    40.973] (II) RADEON(0): Year: 2009  Week: 11
>[    40.973] (II) RADEON(0): EDID Version: 1.3
>[    40.973] (II) RADEON(0): Analog Display Input,  Input Voltage Level: 0.700/0.300 V
>[    40.973] (II) RADEON(0): Sync:  Separate  Composite  SyncOnGreen
>[    40.973] (II) RADEON(0): Max Image Size [cm]: horiz.: 48  vert.: 27
>[    40.973] (II) RADEON(0): Gamma: 2.20
>[    40.973] (II) RADEON(0): DPMS capabilities: Off; RGB/Color Display
>[    40.973] (II) RADEON(0): First detailed timing is preferred mode
>[    40.973] (II) RADEON(0): GTF timings supported
>[    40.973] (II) RADEON(0): redX: 0.648 redY: 0.339   greenX: 0.282 greenY: 0.603
>[    40.973] (II) RADEON(0): blueX: 0.143 blueY: 0.070   whiteX: 0.312 whiteY: 0.329
>[    40.973] (II) RADEON(0): Supported established timings:
>[    40.973] (II) RADEON(0): 720x400@70Hz
>[    40.973] (II) RADEON(0): 640x480@60Hz
>[    40.973] (II) RADEON(0): 640x480@67Hz
>[    40.973] (II) RADEON(0): 640x480@72Hz
>[    40.973] (II) RADEON(0): 640x480@75Hz
>[    40.973] (II) RADEON(0): 800x600@56Hz
>[    40.973] (II) RADEON(0): 800x600@60Hz
>[    40.973] (II) RADEON(0): 800x600@72Hz
>[    40.973] (II) RADEON(0): 800x600@75Hz
>[    40.973] (II) RADEON(0): 832x624@75Hz
>[    40.973] (II) RADEON(0): 1024x768@60Hz
>[    40.973] (II) RADEON(0): 1024x768@70Hz
>[    40.973] (II) RADEON(0): 1024x768@75Hz
>[    40.973] (II) RADEON(0): 1280x1024@75Hz
>[    40.973] (II) RADEON(0): 1152x864@75Hz
>[    40.973] (II) RADEON(0): Manufacturer's mask: 0
>[    40.973] (II) RADEON(0): Supported standard timings:
>[    40.973] (II) RADEON(0): #0: hsize: 1152  vsize 864  refresh: 75  vid: 20337
>[    40.973] (II) RADEON(0): #1: hsize: 1280  vsize 800  refresh: 60  vid: 129
>[    40.973] (II) RADEON(0): #2: hsize: 1280  vsize 960  refresh: 60  vid: 16513
>[    40.973] (II) RADEON(0): #3: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
>[    40.973] (II) RADEON(0): #4: hsize: 1440  vsize 900  refresh: 60  vid: 149
>[    40.973] (II) RADEON(0): #5: hsize: 1600  vsize 1200  refresh: 60  vid: 16553
>[    40.973] (II) RADEON(0): #6: hsize: 1680  vsize 1050  refresh: 60  vid: 179
>[    40.973] (II) RADEON(0): Supported detailed timing:
>[    40.973] (II) RADEON(0): clock: 148.5 MHz   Image Size:  476 x 268 mm
>[    40.973] (II) RADEON(0): h_active: 1920  h_sync: 2008  h_sync_end 2052 h_blank_end 2200 h_border: 0
>[    40.973] (II) RADEON(0): v_active: 1080  v_sync: 1084  v_sync_end 1089 v_blanking: 1125 v_border: 0
>[    40.973] (II) RADEON(0): Ranges: V min: 56 V max: 75 Hz, H min: 30 H max: 81 kHz, PixClock max 175 MHz
>[    40.973] (II) RADEON(0): Monitor name: SyncMaster
>[    40.973] (II) RADEON(0): Serial No: H1AK500000
>[    40.973] (II) RADEON(0): EDID (in hex):
>[    40.973] (II) RADEON(0): 	00ffffffffffff004c2d770532324645
>[    40.973] (II) RADEON(0): 	0b1301030e301b782b3581a656489a24
>[    40.973] (II) RADEON(0): 	125054bfef80714f8100814081809500
>[    40.973] (II) RADEON(0): 	a940b3000101023a801871382d40582c
>[    40.973] (II) RADEON(0): 	4500dc0c1100001e000000fd00384b1e
>[    40.973] (II) RADEON(0): 	5111000a202020202020000000fc0053
>[    40.973] (II) RADEON(0): 	796e634d61737465720a2020000000ff
>[    40.973] (II) RADEON(0): 	004831414b3530303030300a202000dc
>[    40.973] (II) RADEON(0): Printing probed modes for output VGA-0
>[    40.973] (II) RADEON(0): Modeline "1920x1080"x60.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    40.973] (II) RADEON(0): Modeline "1600x1200"x60.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1680x1050"x60.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1680x945"x60.0  131.48  1680 1784 1960 2240  945 946 949 978 -hsync +vsync (58.7 kHz)
>[    40.973] (II) RADEON(0): Modeline "1400x1050"x60.0  121.75  1400 1488 1632 1864  1050 1053 1057 1089 -hsync +vsync (65.3 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1600x900"x60.0  118.96  1600 1696 1864 2128  900 901 904 932 -hsync +vsync (55.9 kHz)
>[    40.973] (II) RADEON(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1440x900"x75.0  136.75  1440 1536 1688 1936  900 903 909 942 -hsync +vsync (70.6 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1440x900"x59.9  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1366x768"x60.0   85.89  1366 1439 1583 1800  768 769 772 795 -hsync +vsync (47.7 kHz)
>[    40.973] (II) RADEON(0): Modeline "1360x768"x60.0   85.50  1360 1424 1536 1792  768 771 777 795 +hsync +vsync (47.7 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x800"x74.9  106.50  1280 1360 1488 1696  800 803 809 838 -hsync +vsync (62.8 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x800"x59.8   83.50  1280 1352 1480 1680  800 803 809 831 +hsync -vsync (49.7 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x768"x74.9  102.25  1280 1360 1488 1696  768 771 778 805 +hsync -vsync (60.3 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1280x768"x59.9   79.50  1280 1344 1472 1664  768 771 778 798 -hsync +vsync (47.8 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1024x768"x75.1   78.80  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.1 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    40.973] (II) RADEON(0): Modeline "1024x576"x60.0   46.97  1024 1064 1168 1312  576 577 580 597 -hsync +vsync (35.8 kHz)
>[    40.973] (II) RADEON(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    40.973] (II) RADEON(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    40.973] (II) RADEON(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    40.973] (II) RADEON(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    40.973] (II) RADEON(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    40.973] (II) RADEON(0): Modeline "848x480"x60.0   33.75  848 864 976 1088  480 486 494 517 +hsync +vsync (31.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz e)
>[    40.973] (II) RADEON(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    40.973] (II) RADEON(0): Modeline "640x480"x66.7   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    40.973] (II) RADEON(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    40.973] (II) RADEON(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    40.973] (II) RADEON(0): Output LVDS connected
>[    40.973] (II) RADEON(0): Output DisplayPort-0 disconnected
>[    40.973] (II) RADEON(0): Output DisplayPort-1 disconnected
>[    40.973] (II) RADEON(0): Output DisplayPort-2 disconnected
>[    40.973] (II) RADEON(0): Output VGA-0 connected
>[    40.973] (II) RADEON(0): Using spanning desktop for initial modes
>[    40.973] (II) RADEON(0): Output LVDS using initial mode 1600x900 +0+0
>[    40.973] (II) RADEON(0): Output VGA-0 using initial mode 1920x1080 +1600+0
>[    40.973] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    40.973] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:40000000 visible:f7d7000
>[    40.973] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    40.973] (**) RADEON(0): Display dimensions: (310, 170) mm
>[    40.973] (**) RADEON(0): DPI set to (288, 161)
>[    40.973] (II) Loading sub module "fb"
>[    40.973] (II) LoadModule: "fb"
>[    40.974] (II) Loading /usr/lib64/xorg/modules/libfb.so
>[    40.974] (II) Module fb: vendor="X.Org Foundation"
>[    40.974] 	compiled for 1.12.4, module version = 1.0.0
>[    40.974] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    40.974] (II) Loading sub module "ramdac"
>[    40.974] (II) LoadModule: "ramdac"
>[    40.974] (II) Module "ramdac" already built-in
>[    40.974] (II) UnloadModule: "vesa"
>[    40.974] (II) Unloading vesa
>[    40.974] (II) UnloadModule: "modesetting"
>[    40.974] (II) Unloading modesetting
>[    40.974] (II) UnloadModule: "fbdev"
>[    40.974] (II) Unloading fbdev
>[    40.974] (II) UnloadSubModule: "fbdevhw"
>[    40.974] (II) Unloading fbdevhw
>[    40.974] (--) Depth 24 pixmap format is 32 bpp
>[    40.975] (II) RADEON(0): [DRI2] Setup complete
>[    40.975] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    40.975] (II) RADEON(0): [DRI2]   VDPAU driver: r600
>[    40.975] (II) RADEON(0): Front buffer size: 14852K
>[    40.975] (II) RADEON(0): VRAM usage limit set to 215042K
>[    40.975] (II) RADEON(0): Initializing backing store
>[    40.975] (==) RADEON(0): Backing store disabled
>[    40.975] (II) RADEON(0): Direct rendering enabled
>[    40.975] (II) RADEON(0): Initializing Acceleration
>[    40.975] (II) RADEON(0): Setting EXA maxPitchBytes
>[    40.975] (II) EXA(0): Driver allocated offscreen pixmaps
>[    40.975] (II) EXA(0): Driver registered support for the following operations:
>[    40.975] (II)         Solid
>[    40.975] (II)         Copy
>[    40.975] (II)         Composite (RENDER acceleration)
>[    40.975] (II)         UploadToScreen
>[    40.975] (II)         DownloadFromScreen
>[    40.975] (II) RADEON(0): Acceleration enabled
>[    40.975] (II) RADEON(0): Initializing DPMS
>[    40.975] (==) RADEON(0): DPMS enabled
>[    40.975] (II) RADEON(0): Initializing Cursor
>[    40.975] (==) RADEON(0): Silken mouse enabled
>[    40.975] (II) RADEON(0): Initializing Xv
>[    40.975] (II) RADEON(0): Set up textured video
>[    40.975] (II) RADEON(0): [XvMC] Associated with Radeon Textured Video.
>[    40.975] (II) RADEON(0): [XvMC] Extension initialized.
>[    40.975] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    40.976] (II) RADEON(0): Initializing kms color map
>[    40.976] (II) RADEON(0): RADEONScreenInit finished
>[    40.976] (--) RandR disabled
>[    40.976] (II) Initializing built-in extension Generic Event Extension
>[    40.976] (II) Initializing built-in extension SHAPE
>[    40.976] (II) Initializing built-in extension MIT-SHM
>[    40.976] (II) Initializing built-in extension XInputExtension
>[    40.976] (II) Initializing built-in extension XTEST
>[    40.976] (II) Initializing built-in extension BIG-REQUESTS
>[    40.976] (II) Initializing built-in extension SYNC
>[    40.976] (II) Initializing built-in extension XKEYBOARD
>[    40.976] (II) Initializing built-in extension XC-MISC
>[    40.976] (II) Initializing built-in extension XINERAMA
>[    40.976] (II) Initializing built-in extension XFIXES
>[    40.976] (II) Initializing built-in extension RENDER
>[    40.976] (II) Initializing built-in extension RANDR
>[    40.976] (II) Initializing built-in extension COMPOSITE
>[    40.976] (II) Initializing built-in extension DAMAGE
>[    40.977] (II) SELinux: Disabled by boolean
>[    42.557] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    42.557] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    42.557] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    42.557] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    42.557] (II) AIGLX: Loaded and initialized r600
>[    42.557] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    42.562] (II) RADEON(0): Setting screen physical size to 931 x 285
>[    42.630] (II) XKB: Reusing cached keymap
>[    42.631] (II) config/udev: Adding input device Power Button (/dev/input/event2)
>[    42.631] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    42.631] (**) Power Button: Applying InputClass "system-setup-keyboard"
>[    42.631] (II) LoadModule: "evdev"
>[    42.631] (II) Loading /usr/lib64/xorg/modules/input/evdev_drv.so
>[    42.632] (II) Module evdev: vendor="X.Org Foundation"
>[    42.632] 	compiled for 1.12.0, module version = 2.7.0
>[    42.632] 	Module class: X.Org XInput Driver
>[    42.632] 	ABI class: X.Org XInput driver, version 16.0
>[    42.632] (II) Using input driver 'evdev' for 'Power Button'
>[    42.632] 	Option "XkbRules" "evdev"
>[    42.632] 	Option "XkbModel" "pc105+inet"
>[    42.632] 	Option "XkbLayout" "us"
>[    42.632] 	Option "_source" "server/udev"
>[    42.632] 	Option "name" "Power Button"
>[    42.632] 	Option "path" "/dev/input/event2"
>[    42.632] 	Option "device" "/dev/input/event2"
>[    42.632] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    42.632] 	Option "driver" "evdev"
>[    42.632] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.632] (**) Power Button: always reports core events
>[    42.632] (**) evdev: Power Button: Device: "/dev/input/event2"
>[    42.632] (--) evdev: Power Button: Vendor 0 Product 0x1
>[    42.632] (--) evdev: Power Button: Found keys
>[    42.632] (II) evdev: Power Button: Configuring as keyboard
>[    42.632] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input2/event2"
>[    42.632] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
>[    42.632] (**) Option "xkb_rules" "evdev"
>[    42.632] (**) Option "xkb_model" "pc105+inet"
>[    42.632] (**) Option "xkb_layout" "us"
>[    42.632] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.653] (II) config/udev: Adding input device Video Bus (/dev/input/event9)
>[    42.653] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    42.653] (**) Video Bus: Applying InputClass "system-setup-keyboard"
>[    42.653] (II) Using input driver 'evdev' for 'Video Bus'
>[    42.653] 	Option "XkbRules" "evdev"
>[    42.653] 	Option "XkbModel" "pc105+inet"
>[    42.653] 	Option "XkbLayout" "us"
>[    42.653] 	Option "_source" "server/udev"
>[    42.653] 	Option "name" "Video Bus"
>[    42.653] 	Option "path" "/dev/input/event9"
>[    42.653] 	Option "device" "/dev/input/event9"
>[    42.653] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input9/event9"
>[    42.653] 	Option "driver" "evdev"
>[    42.653] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.653] (**) Video Bus: always reports core events
>[    42.653] (**) evdev: Video Bus: Device: "/dev/input/event9"
>[    42.653] (--) evdev: Video Bus: Vendor 0 Product 0x6
>[    42.653] (--) evdev: Video Bus: Found keys
>[    42.653] (II) evdev: Video Bus: Configuring as keyboard
>[    42.653] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input9/event9"
>[    42.653] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD, id 7)
>[    42.653] (**) Option "xkb_rules" "evdev"
>[    42.653] (**) Option "xkb_model" "pc105+inet"
>[    42.653] (**) Option "xkb_layout" "us"
>[    42.653] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.653] (II) XKB: Reusing cached keymap
>[    42.654] (II) config/udev: Adding input device Lid Switch (/dev/input/event1)
>[    42.654] (II) No input driver specified, ignoring this device.
>[    42.654] (II) This device may have been added with another device file.
>[    42.654] (II) config/udev: Adding input device Sleep Button (/dev/input/event0)
>[    42.654] (**) Sleep Button: Applying InputClass "evdev keyboard catchall"
>[    42.654] (**) Sleep Button: Applying InputClass "system-setup-keyboard"
>[    42.654] (II) Using input driver 'evdev' for 'Sleep Button'
>[    42.654] 	Option "XkbRules" "evdev"
>[    42.654] 	Option "XkbModel" "pc105+inet"
>[    42.654] 	Option "XkbLayout" "us"
>[    42.654] 	Option "_source" "server/udev"
>[    42.654] 	Option "name" "Sleep Button"
>[    42.654] 	Option "path" "/dev/input/event0"
>[    42.654] 	Option "device" "/dev/input/event0"
>[    42.654] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    42.654] 	Option "driver" "evdev"
>[    42.654] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.654] (**) Sleep Button: always reports core events
>[    42.654] (**) evdev: Sleep Button: Device: "/dev/input/event0"
>[    42.654] (--) evdev: Sleep Button: Vendor 0 Product 0x3
>[    42.654] (--) evdev: Sleep Button: Found keys
>[    42.654] (II) evdev: Sleep Button: Configuring as keyboard
>[    42.654] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input0/event0"
>[    42.654] (II) XINPUT: Adding extended input device "Sleep Button" (type: KEYBOARD, id 8)
>[    42.654] (**) Option "xkb_rules" "evdev"
>[    42.654] (**) Option "xkb_model" "pc105+inet"
>[    42.654] (**) Option "xkb_layout" "us"
>[    42.654] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.654] (II) XKB: Reusing cached keymap
>[    42.655] (II) config/udev: Adding input device HD-Audio Generic HDMI/DP,pcm=3 (/dev/input/event16)
>[    42.655] (II) No input driver specified, ignoring this device.
>[    42.655] (II) This device may have been added with another device file.
>[    42.655] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event6)
>[    42.655] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[    42.655] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[    42.655] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[    42.655] 	Option "XkbRules" "evdev"
>[    42.655] 	Option "XkbModel" "pc105+inet"
>[    42.655] 	Option "XkbLayout" "us"
>[    42.655] 	Option "_source" "server/udev"
>[    42.655] 	Option "name" "USB USB Keykoard"
>[    42.655] 	Option "path" "/dev/input/event6"
>[    42.655] 	Option "device" "/dev/input/event6"
>[    42.655] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input6/event6"
>[    42.655] 	Option "driver" "evdev"
>[    42.655] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.655] (**) USB USB Keykoard: always reports core events
>[    42.655] (**) evdev: USB USB Keykoard: Device: "/dev/input/event6"
>[    42.655] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[    42.655] (--) evdev: USB USB Keykoard: Found keys
>[    42.655] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[    42.655] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input6/event6"
>[    42.655] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 9)
>[    42.655] (**) Option "xkb_rules" "evdev"
>[    42.655] (**) Option "xkb_model" "pc105+inet"
>[    42.655] (**) Option "xkb_layout" "us"
>[    42.655] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.655] (II) XKB: Reusing cached keymap
>[    42.656] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event7)
>[    42.656] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[    42.656] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[    42.656] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[    42.656] 	Option "XkbRules" "evdev"
>[    42.656] 	Option "XkbModel" "pc105+inet"
>[    42.656] 	Option "XkbLayout" "us"
>[    42.656] 	Option "_source" "server/udev"
>[    42.656] 	Option "name" "USB USB Keykoard"
>[    42.656] 	Option "path" "/dev/input/event7"
>[    42.656] 	Option "device" "/dev/input/event7"
>[    42.656] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input7/event7"
>[    42.656] 	Option "driver" "evdev"
>[    42.656] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.656] (**) USB USB Keykoard: always reports core events
>[    42.656] (**) evdev: USB USB Keykoard: Device: "/dev/input/event7"
>[    42.656] (--) evdev: USB USB Keykoard: absolute axis 0x20 [572..0]
>[    42.656] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[    42.656] (--) evdev: USB USB Keykoard: Found 1 mouse buttons
>[    42.656] (--) evdev: USB USB Keykoard: Found scroll wheel(s)
>[    42.656] (--) evdev: USB USB Keykoard: Found relative axes
>[    42.656] (II) evdev: USB USB Keykoard: Forcing relative x/y axes to exist.
>[    42.656] (--) evdev: USB USB Keykoard: Found absolute axes
>[    42.656] (II) evdev: USB USB Keykoard: Forcing absolute x/y axes to exist.
>[    42.656] (--) evdev: USB USB Keykoard: Found keys
>[    42.656] (II) evdev: USB USB Keykoard: Configuring as mouse
>[    42.656] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[    42.656] (II) evdev: USB USB Keykoard: Adding scrollwheel support
>[    42.656] (**) evdev: USB USB Keykoard: YAxisMapping: buttons 4 and 5
>[    42.656] (**) evdev: USB USB Keykoard: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    42.656] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input7/event7"
>[    42.656] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 10)
>[    42.656] (**) Option "xkb_rules" "evdev"
>[    42.656] (**) Option "xkb_model" "pc105+inet"
>[    42.656] (**) Option "xkb_layout" "us"
>[    42.656] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.656] (II) XKB: Reusing cached keymap
>[    42.656] (II) evdev: USB USB Keykoard: initialized for relative axes.
>[    42.656] (WW) evdev: USB USB Keykoard: ignoring absolute axes.
>[    42.656] (**) USB USB Keykoard: (accel) keeping acceleration scheme 1
>[    42.656] (**) USB USB Keykoard: (accel) acceleration profile 0
>[    42.656] (**) USB USB Keykoard: (accel) acceleration factor: 2.000
>[    42.656] (**) USB USB Keykoard: (accel) acceleration threshold: 4
>[    42.657] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event8)
>[    42.657] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[    42.657] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[    42.657] 	Option "XkbRules" "evdev"
>[    42.657] 	Option "XkbModel" "evdev"
>[    42.657] 	Option "XkbLayout" "us"
>[    42.657] 	Option "_source" "server/udev"
>[    42.657] 	Option "name" "Logitech USB Optical Mouse"
>[    42.657] 	Option "path" "/dev/input/event8"
>[    42.657] 	Option "device" "/dev/input/event8"
>[    42.657] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input8/event8"
>[    42.657] 	Option "driver" "evdev"
>[    42.657] (**) Logitech USB Optical Mouse: always reports core events
>[    42.657] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event8"
>[    42.657] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[    42.657] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[    42.657] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[    42.657] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[    42.657] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[    42.657] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[    42.657] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[    42.657] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[    42.657] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    42.657] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input8/event8"
>[    42.657] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 11)
>[    42.657] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[    42.657] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[    42.657] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[    42.657] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[    42.657] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[    42.657] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse2)
>[    42.657] (II) No input driver specified, ignoring this device.
>[    42.657] (II) This device may have been added with another device file.
>[    42.657] (II) config/udev: Adding input device HDA Intel PCH Line (/dev/input/event12)
>[    42.657] (II) No input driver specified, ignoring this device.
>[    42.657] (II) This device may have been added with another device file.
>[    42.658] (II) config/udev: Adding input device HDA Intel PCH Mic (/dev/input/event13)
>[    42.658] (II) No input driver specified, ignoring this device.
>[    42.658] (II) This device may have been added with another device file.
>[    42.658] (II) config/udev: Adding input device HDA Intel PCH Headphone (/dev/input/event14)
>[    42.658] (II) No input driver specified, ignoring this device.
>[    42.658] (II) This device may have been added with another device file.
>[    42.658] (II) config/udev: Adding input device HDA Intel PCH Dock Line Out (/dev/input/event15)
>[    42.658] (II) No input driver specified, ignoring this device.
>[    42.658] (II) This device may have been added with another device file.
>[    42.658] (II) config/udev: Adding input device HP HD Webcam [Fixed] (/dev/input/event17)
>[    42.658] (**) HP HD Webcam [Fixed]: Applying InputClass "evdev keyboard catchall"
>[    42.658] (**) HP HD Webcam [Fixed]: Applying InputClass "system-setup-keyboard"
>[    42.658] (II) Using input driver 'evdev' for 'HP HD Webcam [Fixed]'
>[    42.658] 	Option "XkbRules" "evdev"
>[    42.658] 	Option "XkbModel" "pc105+inet"
>[    42.658] 	Option "XkbLayout" "us"
>[    42.658] 	Option "_source" "server/udev"
>[    42.658] 	Option "name" "HP HD Webcam [Fixed]"
>[    42.658] 	Option "path" "/dev/input/event17"
>[    42.658] 	Option "device" "/dev/input/event17"
>[    42.658] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.4/2-1.4:1.0/input/input17/event17"
>[    42.658] 	Option "driver" "evdev"
>[    42.658] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.658] (**) HP HD Webcam [Fixed]: always reports core events
>[    42.658] (**) evdev: HP HD Webcam [Fixed]: Device: "/dev/input/event17"
>[    42.658] (--) evdev: HP HD Webcam [Fixed]: Vendor 0x461 Product 0x4dce
>[    42.658] (--) evdev: HP HD Webcam [Fixed]: Found keys
>[    42.658] (II) evdev: HP HD Webcam [Fixed]: Configuring as keyboard
>[    42.658] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.4/2-1.4:1.0/input/input17/event17"
>[    42.658] (II) XINPUT: Adding extended input device "HP HD Webcam [Fixed]" (type: KEYBOARD, id 12)
>[    42.658] (**) Option "xkb_rules" "evdev"
>[    42.658] (**) Option "xkb_model" "pc105+inet"
>[    42.658] (**) Option "xkb_layout" "us"
>[    42.658] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.658] (II) XKB: Reusing cached keymap
>[    42.659] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event3)
>[    42.659] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    42.659] (**) AT Translated Set 2 keyboard: Applying InputClass "system-setup-keyboard"
>[    42.659] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    42.659] 	Option "XkbRules" "evdev"
>[    42.659] 	Option "XkbModel" "pc105+inet"
>[    42.659] 	Option "XkbLayout" "us"
>[    42.659] 	Option "_source" "server/udev"
>[    42.659] 	Option "name" "AT Translated Set 2 keyboard"
>[    42.659] 	Option "path" "/dev/input/event3"
>[    42.659] 	Option "device" "/dev/input/event3"
>[    42.659] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    42.659] 	Option "driver" "evdev"
>[    42.659] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.659] (**) AT Translated Set 2 keyboard: always reports core events
>[    42.659] (**) evdev: AT Translated Set 2 keyboard: Device: "/dev/input/event3"
>[    42.659] (--) evdev: AT Translated Set 2 keyboard: Vendor 0x1 Product 0x1
>[    42.659] (--) evdev: AT Translated Set 2 keyboard: Found keys
>[    42.659] (II) evdev: AT Translated Set 2 keyboard: Configuring as keyboard
>[    42.659] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input3/event3"
>[    42.659] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD, id 13)
>[    42.659] (**) Option "xkb_rules" "evdev"
>[    42.659] (**) Option "xkb_model" "pc105+inet"
>[    42.659] (**) Option "xkb_layout" "us"
>[    42.659] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.659] (II) XKB: Reusing cached keymap
>[    42.659] (II) config/udev: Adding input device PS/2 Generic Mouse (/dev/input/event4)
>[    42.659] (**) PS/2 Generic Mouse: Applying InputClass "evdev pointer catchall"
>[    42.659] (II) Using input driver 'evdev' for 'PS/2 Generic Mouse'
>[    42.659] 	Option "XkbRules" "evdev"
>[    42.659] 	Option "XkbModel" "evdev"
>[    42.659] 	Option "XkbLayout" "us"
>[    42.659] 	Option "_source" "server/udev"
>[    42.659] 	Option "name" "PS/2 Generic Mouse"
>[    42.659] 	Option "path" "/dev/input/event4"
>[    42.659] 	Option "device" "/dev/input/event4"
>[    42.659] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input4/event4"
>[    42.659] 	Option "driver" "evdev"
>[    42.659] (**) PS/2 Generic Mouse: always reports core events
>[    42.659] (**) evdev: PS/2 Generic Mouse: Device: "/dev/input/event4"
>[    42.659] (--) evdev: PS/2 Generic Mouse: Vendor 0x2 Product 0x1
>[    42.659] (--) evdev: PS/2 Generic Mouse: Found 3 mouse buttons
>[    42.659] (--) evdev: PS/2 Generic Mouse: Found relative axes
>[    42.659] (--) evdev: PS/2 Generic Mouse: Found x and y relative axes
>[    42.659] (II) evdev: PS/2 Generic Mouse: Configuring as mouse
>[    42.659] (**) evdev: PS/2 Generic Mouse: YAxisMapping: buttons 4 and 5
>[    42.659] (**) evdev: PS/2 Generic Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    42.659] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input4/event4"
>[    42.659] (II) XINPUT: Adding extended input device "PS/2 Generic Mouse" (type: MOUSE, id 14)
>[    42.659] (II) evdev: PS/2 Generic Mouse: initialized for relative axes.
>[    42.659] (**) PS/2 Generic Mouse: (accel) keeping acceleration scheme 1
>[    42.659] (**) PS/2 Generic Mouse: (accel) acceleration profile 0
>[    42.659] (**) PS/2 Generic Mouse: (accel) acceleration factor: 2.000
>[    42.659] (**) PS/2 Generic Mouse: (accel) acceleration threshold: 4
>[    42.659] (II) config/udev: Adding input device PS/2 Generic Mouse (/dev/input/mouse0)
>[    42.659] (II) No input driver specified, ignoring this device.
>[    42.660] (II) This device may have been added with another device file.
>[    42.660] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event5)
>[    42.660] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    42.660] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    42.660] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "Default clickpad buttons"
>[    42.660] (II) LoadModule: "synaptics"
>[    42.660] (II) Loading /usr/lib64/xorg/modules/input/synaptics_drv.so
>[    42.660] (II) Module synaptics: vendor="X.Org Foundation"
>[    42.660] 	compiled for 1.12.3, module version = 1.6.2
>[    42.660] 	Module class: X.Org XInput Driver
>[    42.660] 	ABI class: X.Org XInput driver, version 16.0
>[    42.660] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    42.660] 	Option "_source" "server/udev"
>[    42.660] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    42.660] 	Option "path" "/dev/input/event5"
>[    42.660] 	Option "device" "/dev/input/event5"
>[    42.660] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input5/event5"
>[    42.660] 	Option "driver" "synaptics"
>[    42.660] 	Option "SoftButtonAreas" "50% 0 82% 0 0 0 0 0"
>[    42.660] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    42.660] (**) Option "Device" "/dev/input/event5"
>[    42.691] (**) Option "Device" "/dev/input/event5"
>[    42.691] port opened successfully
>[    42.691] (II) synaptics: SynPS/2 Synaptics TouchPad: ignoring touch events for semi-multitouch device
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5728
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4916
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: buttons: left right double triple
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: Vendor 0x2 Product 0x7
>[    42.691] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    42.691] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    42.710] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio4/input/input5/event5"
>[    42.710] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD, id 15)
>[    42.710] (**) synaptics: SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    42.710] (**) synaptics: SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    42.710] (**) synaptics: SynPS/2 Synaptics TouchPad: AccelFactor is now 0.036
>[    42.710] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    42.710] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    42.710] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    42.710] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    42.710] (**) Option "Device" "/dev/input/event5"
>[    42.711] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[    42.711] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse1)
>[    42.711] (II) No input driver specified, ignoring this device.
>[    42.711] (II) This device may have been added with another device file.
>[    42.712] (II) config/udev: Adding input device ST LIS3LV02DL Accelerometer (/dev/input/event11)
>[    42.712] (II) No input driver specified, ignoring this device.
>[    42.712] (II) This device may have been added with another device file.
>[    42.713] (II) config/udev: Adding input device HP WMI hotkeys (/dev/input/event10)
>[    42.713] (**) HP WMI hotkeys: Applying InputClass "evdev keyboard catchall"
>[    42.713] (**) HP WMI hotkeys: Applying InputClass "system-setup-keyboard"
>[    42.713] (II) Using input driver 'evdev' for 'HP WMI hotkeys'
>[    42.713] 	Option "XkbRules" "evdev"
>[    42.713] 	Option "XkbModel" "pc105+inet"
>[    42.713] 	Option "XkbLayout" "us"
>[    42.713] 	Option "_source" "server/udev"
>[    42.713] 	Option "name" "HP WMI hotkeys"
>[    42.713] 	Option "path" "/dev/input/event10"
>[    42.713] 	Option "device" "/dev/input/event10"
>[    42.713] 	Option "config_info" "udev:/sys/devices/virtual/input/input10/event10"
>[    42.713] 	Option "driver" "evdev"
>[    42.713] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[    42.713] (**) HP WMI hotkeys: always reports core events
>[    42.713] (**) evdev: HP WMI hotkeys: Device: "/dev/input/event10"
>[    42.713] (--) evdev: HP WMI hotkeys: Vendor 0 Product 0
>[    42.713] (--) evdev: HP WMI hotkeys: Found keys
>[    42.713] (II) evdev: HP WMI hotkeys: Configuring as keyboard
>[    42.713] (**) Option "config_info" "udev:/sys/devices/virtual/input/input10/event10"
>[    42.713] (II) XINPUT: Adding extended input device "HP WMI hotkeys" (type: KEYBOARD, id 16)
>[    42.713] (**) Option "xkb_rules" "evdev"
>[    42.714] (**) Option "xkb_model" "pc105+inet"
>[    42.714] (**) Option "xkb_layout" "us"
>[    42.714] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[    42.714] (II) XKB: Reusing cached keymap
>[    42.719] (II) RADEON(0): RADEONSaveScreen(2)
>[    42.722] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[    42.722] (II) RADEON(0): Printing DDC gathered Modelines:
>[    42.722] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    42.722] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    45.005] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[    45.006] (II) RADEON(0): Printing DDC gathered Modelines:
>[    45.006] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    45.006] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    47.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efba0]
>[    47.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efba0] width 3520 pitch 14080 (/4 3520)
>[    47.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efb40]
>[    47.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efb40] width 3520 pitch 14080 (/4 3520)
>[    47.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efba0]
>[    47.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efba0] width 3520 pitch 14080 (/4 3520)
>[    47.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efb40]
>[    47.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efb40] width 3520 pitch 14080 (/4 3520)
>[    47.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efd30]
>[    47.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efd30] width 3520 pitch 14080 (/4 3520)
>[    47.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efb40]
>[    47.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efb40] width 3520 pitch 14080 (/4 3520)
>[    47.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efd30]
>[    47.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efd30] width 3520 pitch 14080 (/4 3520)
>[    47.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efb40]
>[    47.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efb40] width 3520 pitch 14080 (/4 3520)
>[    47.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efd30]
>[    47.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efd30] width 3520 pitch 14080 (/4 3520)
>[    47.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efb40]
>[    47.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efb40] width 3520 pitch 14080 (/4 3520)
>[    47.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    47.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    47.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    47.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    47.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    48.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    48.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    48.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    48.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    48.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    48.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    48.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    48.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    48.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    48.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    48.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    48.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    48.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b10]
>[    48.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b10] width 3520 pitch 14080 (/4 3520)
>[    48.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    48.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    52.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1b70]
>[    52.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1b70] width 3520 pitch 14080 (/4 3520)
>[    60.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efba0]
>[    60.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efba0] width 3520 pitch 14080 (/4 3520)
>[    74.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    74.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    74.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    74.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    74.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    75.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    75.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    75.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    75.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    76.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    76.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    76.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f63e0]
>[    76.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f63e0] width 3520 pitch 14080 (/4 3520)
>[    76.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f1340]
>[    76.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f1340] width 3520 pitch 14080 (/4 3520)
>[    77.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f90]
>[    77.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f90] width 3520 pitch 14080 (/4 3520)
>[    78.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f30]
>[    78.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f30] width 3520 pitch 14080 (/4 3520)
>[    79.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f90]
>[    79.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f90] width 3520 pitch 14080 (/4 3520)
>[    79.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f30]
>[    79.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f30] width 3520 pitch 14080 (/4 3520)
>[    79.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f90]
>[    79.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f90] width 3520 pitch 14080 (/4 3520)
>[    79.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f30]
>[    79.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f30] width 3520 pitch 14080 (/4 3520)
>[    80.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f5f90]
>[    80.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f5f90] width 3520 pitch 14080 (/4 3520)
>[    83.273] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[    83.273] (II) RADEON(0): Printing DDC gathered Modelines:
>[    83.273] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    83.273] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    83.476] (II) RADEON(0): Allocate new frame buffer 1920x1080 stride 1920
>[    83.478] (II) RADEON(0): VRAM usage limit set to 221119K
>[    84.905] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[    84.905] (II) RADEON(0): Printing DDC gathered Modelines:
>[    84.905] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[    84.905] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[    85.729] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[    85.729] (II) RADEON(0): Using hsync ranges from config file
>[    85.729] (II) RADEON(0): Using vrefresh ranges from config file
>[    85.729] (II) RADEON(0): Printing DDC gathered Modelines:
>[    85.729] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[    85.729] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[    85.729] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[    85.729] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[    85.729] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[    85.729] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[    85.729] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[    85.729] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[    85.729] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[    85.729] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[    85.729] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[   117.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3858c50]
>[   117.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3858c50] width 1920 pitch 7680 (/4 1920)
>[   117.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[   117.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1920 pitch 7680 (/4 1920)
>[   117.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3858c50]
>[   117.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3858c50] width 1920 pitch 7680 (/4 1920)
>[   117.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[   117.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1920 pitch 7680 (/4 1920)
>[   117.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ee30]
>[   117.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ee30] width 1920 pitch 7680 (/4 1920)
>[   117.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0010]
>[   117.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0010] width 1920 pitch 7680 (/4 1920)
>[   117.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ff20]
>[   117.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ff20] width 1920 pitch 7680 (/4 1920)
>[   118.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ffc0]
>[   118.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ffc0] width 1920 pitch 7680 (/4 1920)
>[   118.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   118.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389ff20]
>[   118.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389ff20] width 1920 pitch 7680 (/4 1920)
>[   118.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a0180]
>[   118.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a0180] width 1920 pitch 7680 (/4 1920)
>[   119.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   119.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389b110]
>[   122.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389b110] width 1920 pitch 7680 (/4 1920)
>[   122.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   122.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24db1a0]
>[   122.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24db1a0] width 1920 pitch 7680 (/4 1920)
>[   122.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38883f0]
>[   122.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38883f0] width 1920 pitch 7680 (/4 1920)
>[   123.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a37b0]
>[   123.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a37b0] width 1920 pitch 7680 (/4 1920)
>[   123.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c14f0]
>[   123.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c14f0] width 1920 pitch 7680 (/4 1920)
>[   128.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979ad0]
>[   128.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979ad0] width 1920 pitch 7680 (/4 1920)
>[   131.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a40740]
>[   131.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a40740] width 1920 pitch 7680 (/4 1920)
>[   131.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5cb30]
>[   131.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5cb30] width 1920 pitch 7680 (/4 1920)
>[   134.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45d90]
>[   134.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45d90] width 1920 pitch 7680 (/4 1920)
>[   137.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a59440]
>[   137.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a59440] width 1920 pitch 7680 (/4 1920)
>[   446.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cc280]
>[   446.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cc280] width 1920 pitch 7680 (/4 1920)
>[   447.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8b40]
>[   447.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8b40] width 1920 pitch 7680 (/4 1920)
>[   454.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1b70]
>[   454.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1b70] width 1920 pitch 7680 (/4 1920)
>[   454.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   454.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   454.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   454.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   454.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   454.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   454.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   454.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   459.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   459.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   459.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   459.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   459.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   459.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   459.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   459.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   459.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   459.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   459.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   459.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   459.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   459.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   459.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   459.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   460.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   460.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   460.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   460.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   460.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   460.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   460.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   460.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   460.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   460.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   460.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   460.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   460.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   460.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   460.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   460.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   461.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   461.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   463.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   463.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   466.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   466.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   467.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   467.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   467.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38474b0]
>[   467.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38474b0] width 1920 pitch 7680 (/4 1920)
>[   469.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   469.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   469.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   469.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   469.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   470.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   470.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   470.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   470.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   470.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   470.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   470.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   470.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   470.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   470.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   470.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   470.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   470.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   470.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   470.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   470.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   470.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   470.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   472.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3efa0]
>[   472.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3efa0] width 1920 pitch 7680 (/4 1920)
>[   473.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cbfe0]
>[   473.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cbfe0] width 1920 pitch 7680 (/4 1920)
>[   473.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8da0]
>[   473.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8da0] width 1920 pitch 7680 (/4 1920)
>[   473.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3983350]
>[   473.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3983350] width 1920 pitch 7680 (/4 1920)
>[   473.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8e00]
>[   473.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8e00] width 1920 pitch 7680 (/4 1920)
>[   473.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a535c0]
>[   473.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a535c0] width 1920 pitch 7680 (/4 1920)
>[   473.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3983350]
>[   473.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3983350] width 1920 pitch 7680 (/4 1920)
>[   473.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a535c0]
>[   473.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a535c0] width 1920 pitch 7680 (/4 1920)
>[   473.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3983350]
>[   473.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3983350] width 1920 pitch 7680 (/4 1920)
>[   473.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a535c0]
>[   474.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a535c0] width 1920 pitch 7680 (/4 1920)
>[   474.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ef2c0]
>[   474.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ef2c0] width 1920 pitch 7680 (/4 1920)
>[   474.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a535c0]
>[   474.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a535c0] width 1920 pitch 7680 (/4 1920)
>[   474.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ef2c0]
>[   474.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ef2c0] width 1920 pitch 7680 (/4 1920)
>[   474.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396b710]
>[   474.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396b710] width 1920 pitch 7680 (/4 1920)
>[   474.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[   474.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[   481.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9f890]
>[   481.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9f890] width 1920 pitch 7680 (/4 1920)
>[   481.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   481.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   481.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   481.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   481.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   481.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   481.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   481.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   481.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   481.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   481.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   481.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   481.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   481.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   481.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   481.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   481.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   482.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   482.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   482.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   482.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   483.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   483.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   483.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   483.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f580]
>[   483.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f580] width 1920 pitch 7680 (/4 1920)
>[   483.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9f890]
>[   483.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9f890] width 1920 pitch 7680 (/4 1920)
>[   483.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   483.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c9900]
>[   483.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c9900] width 1920 pitch 7680 (/4 1920)
>[   483.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a571b0]
>[   483.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a571b0] width 1920 pitch 7680 (/4 1920)
>[   484.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a48210]
>[   484.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a48210] width 1920 pitch 7680 (/4 1920)
>[   484.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   484.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481b0]
>[   484.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481b0] width 1920 pitch 7680 (/4 1920)
>[   484.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   484.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   496.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   496.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   496.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   496.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   496.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   496.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   496.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   496.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   496.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   496.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   496.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   496.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   497.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   497.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   497.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   497.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   498.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   498.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   498.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   498.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   500.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   500.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   500.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   500.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   500.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   500.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   500.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   500.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   501.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   501.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   501.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   501.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   502.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   502.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   502.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   502.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   503.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   503.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   503.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   503.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   504.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   504.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   504.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   504.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   504.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6be0]
>[   504.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6be0] width 1920 pitch 7680 (/4 1920)
>[   504.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   504.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   504.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   504.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   504.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   508.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ca760]
>[   508.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ca760] width 1920 pitch 7680 (/4 1920)
>[   508.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   508.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   508.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff4ca0]
>[   508.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff4ca0] width 1920 pitch 7680 (/4 1920)
>[   508.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   508.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   508.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   508.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   508.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   508.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   508.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a481a0]
>[   508.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a481a0] width 1920 pitch 7680 (/4 1920)
>[   508.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   508.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   508.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0360]
>[   508.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0360] width 1920 pitch 7680 (/4 1920)
>[   508.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9e350]
>[   508.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9e350] width 1920 pitch 7680 (/4 1920)
>[   509.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f91e0]
>[   509.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f91e0] width 1920 pitch 7680 (/4 1920)
>[   509.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9beb0]
>[   509.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9beb0] width 1920 pitch 7680 (/4 1920)
>[   509.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f91e0]
>[   509.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f91e0] width 1920 pitch 7680 (/4 1920)
>[   604.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c20]
>[   604.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c20] width 1920 pitch 7680 (/4 1920)
>[   604.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   604.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   604.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c20]
>[   604.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c20] width 1920 pitch 7680 (/4 1920)
>[   604.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   604.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   604.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c20]
>[   604.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c20] width 1920 pitch 7680 (/4 1920)
>[   604.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   604.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   604.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c20]
>[   604.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c20] width 1920 pitch 7680 (/4 1920)
>[   604.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   604.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   604.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7a30]
>[   604.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7a30] width 1920 pitch 7680 (/4 1920)
>[   604.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7ba0]
>[   604.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7ba0] width 1920 pitch 7680 (/4 1920)
>[   604.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7a30]
>[   604.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7a30] width 1920 pitch 7680 (/4 1920)
>[   604.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7ba0]
>[   604.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7ba0] width 1920 pitch 7680 (/4 1920)
>[   604.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7a30]
>[   604.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7a30] width 1920 pitch 7680 (/4 1920)
>[   607.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   607.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   607.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   607.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   607.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   607.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   607.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   607.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6610]
>[   607.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6610] width 1920 pitch 7680 (/4 1920)
>[   607.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6af0]
>[   607.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6af0] width 1920 pitch 7680 (/4 1920)
>[   608.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   608.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   608.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   608.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   608.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   608.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   608.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   608.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   608.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   608.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   608.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   608.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   608.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   609.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   609.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   609.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   609.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   609.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   609.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   609.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   609.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   609.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   609.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   609.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   609.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f60]
>[   609.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f60] width 1920 pitch 7680 (/4 1920)
>[   609.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a32090]
>[   609.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a32090] width 1920 pitch 7680 (/4 1920)
>[   617.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c70]
>[   617.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c70] width 1920 pitch 7680 (/4 1920)
>[   617.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c70]
>[   617.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c70] width 1920 pitch 7680 (/4 1920)
>[   617.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c70]
>[   617.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c70] width 1920 pitch 7680 (/4 1920)
>[   617.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7c70]
>[   617.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7c70] width 1920 pitch 7680 (/4 1920)
>[   617.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   617.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   617.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   617.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   617.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7d60]
>[   617.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7d60] width 1920 pitch 7680 (/4 1920)
>[   617.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7dc0]
>[   617.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7dc0] width 1920 pitch 7680 (/4 1920)
>[   619.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   619.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[   619.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[   619.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   619.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[   619.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[   619.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   619.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[   619.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[   619.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   619.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[   619.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[   619.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   619.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[   619.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[   619.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f3980]
>[   619.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f3980] width 1920 pitch 7680 (/4 1920)
>[   620.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   620.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   620.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   620.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   620.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   621.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   621.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   621.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   621.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   622.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   622.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   622.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   622.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   622.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   623.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   623.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   623.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   623.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   624.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   624.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   624.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e90c0]
>[   624.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e90c0] width 1920 pitch 7680 (/4 1920)
>[   626.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   626.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   626.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc150]
>[   626.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc150] width 1920 pitch 7680 (/4 1920)
>[   626.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   626.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   626.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc150]
>[   626.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc150] width 1920 pitch 7680 (/4 1920)
>[   626.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   626.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   626.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc150]
>[   627.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc150] width 1920 pitch 7680 (/4 1920)
>[   627.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   627.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   627.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc150]
>[   627.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc150] width 1920 pitch 7680 (/4 1920)
>[   627.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   627.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   627.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc150]
>[   627.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc150] width 1920 pitch 7680 (/4 1920)
>[   627.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a22900]
>[   627.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a22900] width 1920 pitch 7680 (/4 1920)
>[   628.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a28680]
>[   628.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a28680] width 1920 pitch 7680 (/4 1920)
>[   628.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a287e0]
>[   628.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a287e0] width 1920 pitch 7680 (/4 1920)
>[   628.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a28680]
>[   628.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a28680] width 1920 pitch 7680 (/4 1920)
>[   629.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5f00]
>[   629.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5f00] width 1920 pitch 7680 (/4 1920)
>[   629.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f6ef0]
>[   629.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f6ef0] width 1920 pitch 7680 (/4 1920)
>[   629.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a287e0]
>[   629.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a287e0] width 1920 pitch 7680 (/4 1920)
>[   629.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9a2e0]
>[   629.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9a2e0] width 1920 pitch 7680 (/4 1920)
>[   629.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a28680]
>[   629.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a28680] width 1920 pitch 7680 (/4 1920)
>[   629.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8910]
>[   629.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8910] width 1920 pitch 7680 (/4 1920)
>[   629.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8910]
>[   629.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8910] width 1920 pitch 7680 (/4 1920)
>[   631.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9560]
>[   631.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9560] width 1920 pitch 7680 (/4 1920)
>[   631.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5720]
>[   631.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5720] width 1920 pitch 7680 (/4 1920)
>[   631.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5540]
>[   631.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5540] width 1920 pitch 7680 (/4 1920)
>[   631.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5720]
>[   631.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5720] width 1920 pitch 7680 (/4 1920)
>[   631.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5540]
>[   631.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5540] width 1920 pitch 7680 (/4 1920)
>[   631.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5720]
>[   631.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5720] width 1920 pitch 7680 (/4 1920)
>[   631.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5540]
>[   631.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5540] width 1920 pitch 7680 (/4 1920)
>[   631.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5720]
>[   631.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5720] width 1920 pitch 7680 (/4 1920)
>[   631.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5540]
>[   631.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5540] width 1920 pitch 7680 (/4 1920)
>[   631.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5720]
>[   631.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5720] width 1920 pitch 7680 (/4 1920)
>[   632.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   632.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   633.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   633.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   633.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   633.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   633.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   633.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   633.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   633.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   633.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   633.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   633.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   633.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   634.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   634.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   634.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c5a0]
>[   634.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c5a0] width 1920 pitch 7680 (/4 1920)
>[   634.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21fd0]
>[   634.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21fd0] width 1920 pitch 7680 (/4 1920)
>[   636.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7930]
>[   636.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7930] width 1920 pitch 7680 (/4 1920)
>[   636.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f79c0]
>[   636.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f79c0] width 1920 pitch 7680 (/4 1920)
>[   636.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f79c0]
>[   636.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f79c0] width 1920 pitch 7680 (/4 1920)
>[   636.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f79c0]
>[   636.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f79c0] width 1920 pitch 7680 (/4 1920)
>[   636.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f79c0]
>[   636.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f79c0] width 1920 pitch 7680 (/4 1920)
>[   636.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   636.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7ad0]
>[   636.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7ad0] width 1920 pitch 7680 (/4 1920)
>[   636.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f78d0]
>[   636.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f78d0] width 1920 pitch 7680 (/4 1920)
>[   637.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21a20]
>[   637.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21a20] width 1920 pitch 7680 (/4 1920)
>[   637.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[   637.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[   637.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0eca0]
>[   637.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0eca0] width 1920 pitch 7680 (/4 1920)
>[   638.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d8a0]
>[   638.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d8a0] width 1920 pitch 7680 (/4 1920)
>[   638.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fce60]
>[   638.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fce60] width 1920 pitch 7680 (/4 1920)
>[   638.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d8a0]
>[   638.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d8a0] width 1920 pitch 7680 (/4 1920)
>[   638.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fce60]
>[   638.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fce60] width 1920 pitch 7680 (/4 1920)
>[   638.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d8a0]
>[   638.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d8a0] width 1920 pitch 7680 (/4 1920)
>[   638.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fce60]
>[   638.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fce60] width 1920 pitch 7680 (/4 1920)
>[   638.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d8a0]
>[   638.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d8a0] width 1920 pitch 7680 (/4 1920)
>[   638.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fce60]
>[   638.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fce60] width 1920 pitch 7680 (/4 1920)
>[   638.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d8a0]
>[   638.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d8a0] width 1920 pitch 7680 (/4 1920)
>[   638.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fce60]
>[   638.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fce60] width 1920 pitch 7680 (/4 1920)
>[   698.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392f4f0]
>[   698.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392f4f0] width 1920 pitch 7680 (/4 1920)
>[   699.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03b50]
>[   699.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03b50] width 1920 pitch 7680 (/4 1920)
>[   699.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dad0c0]
>[   699.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dad0c0] width 1920 pitch 7680 (/4 1920)
>[   699.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dabd90]
>[   699.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dabd90] width 1920 pitch 7680 (/4 1920)
>[   711.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10470]
>[   711.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10470] width 1920 pitch 7680 (/4 1920)
>[   711.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fbca0]
>[   711.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fbca0] width 1920 pitch 7680 (/4 1920)
>[   711.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0fca0]
>[   711.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0fca0] width 1920 pitch 7680 (/4 1920)
>[   711.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   711.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   711.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8970]
>[   711.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8970] width 1920 pitch 7680 (/4 1920)
>[   739.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392ec00]
>[   739.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392ec00] width 1920 pitch 7680 (/4 1920)
>[   750.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07020]
>[   750.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07020] width 1920 pitch 7680 (/4 1920)
>[   750.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   750.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   750.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393fc20]
>[   750.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393fc20] width 1920 pitch 7680 (/4 1920)
>[   750.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   750.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   750.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   750.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   750.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   750.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   750.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   750.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   750.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   750.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   750.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   750.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   750.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   750.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   750.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   750.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   750.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   751.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   751.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   751.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   751.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a10090]
>[   751.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a10090] width 1920 pitch 7680 (/4 1920)
>[   751.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dafcd0]
>[   751.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dafcd0] width 1920 pitch 7680 (/4 1920)
>[   769.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8fc0]
>[   769.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8fc0] width 1920 pitch 7680 (/4 1920)
>[   819.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39244c0]
>[   819.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39244c0] width 1920 pitch 7680 (/4 1920)
>[   821.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a12db0]
>[   821.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a12db0] width 1920 pitch 7680 (/4 1920)
>[   848.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4090]
>[   848.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4090] width 1920 pitch 7680 (/4 1920)
>[   937.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3daf720]
>[   937.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3daf720] width 1920 pitch 7680 (/4 1920)
>[   939.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9d570]
>[   939.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9d570] width 1920 pitch 7680 (/4 1920)
>[   940.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[   940.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[   940.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   940.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   940.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[   940.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[   940.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   940.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   940.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[   940.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[   940.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   940.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   940.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[   940.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[   940.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   940.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   940.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbadd0]
>[   940.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbadd0] width 1920 pitch 7680 (/4 1920)
>[   940.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966cd0]
>[   940.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966cd0] width 1920 pitch 7680 (/4 1920)
>[   940.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3daa590]
>[   940.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3daa590] width 1920 pitch 7680 (/4 1920)
>[   940.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966cd0]
>[   940.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966cd0] width 1920 pitch 7680 (/4 1920)
>[   940.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3daa590]
>[   940.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3daa590] width 1920 pitch 7680 (/4 1920)
>[   941.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   941.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   945.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   945.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394cb20]
>[   945.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394cb20] width 1920 pitch 7680 (/4 1920)
>[   945.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39671a0]
>[   945.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39671a0] width 1920 pitch 7680 (/4 1920)
>[   946.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39668c0]
>[   946.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39668c0] width 1920 pitch 7680 (/4 1920)
>[   946.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   946.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   946.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   946.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   946.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   946.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966d70]
>[   946.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966d70] width 1920 pitch 7680 (/4 1920)
>[   946.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1e80]
>[   946.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1e80] width 1920 pitch 7680 (/4 1920)
>[   957.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dae130]
>[   957.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dae130] width 1920 pitch 7680 (/4 1920)
>[   986.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393acb0]
>[   986.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393acb0] width 1920 pitch 7680 (/4 1920)
>[   987.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393acb0]
>[   987.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393acb0] width 1920 pitch 7680 (/4 1920)
>[  1006.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1ee0]
>[  1006.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1ee0] width 1920 pitch 7680 (/4 1920)
>[  1006.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39407e0]
>[  1006.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39407e0] width 1920 pitch 7680 (/4 1920)
>[  1006.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1ee0]
>[  1006.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1ee0] width 1920 pitch 7680 (/4 1920)
>[  1006.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39407e0]
>[  1006.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39407e0] width 1920 pitch 7680 (/4 1920)
>[  1006.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1ee0]
>[  1006.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1ee0] width 1920 pitch 7680 (/4 1920)
>[  1006.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39407e0]
>[  1006.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39407e0] width 1920 pitch 7680 (/4 1920)
>[  1006.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de1ee0]
>[  1006.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de1ee0] width 1920 pitch 7680 (/4 1920)
>[  1006.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1006.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1006.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1007.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1007.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1007.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1007.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1007.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1007.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1007.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1007.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1007.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1013.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1013.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1013.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1013.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1013.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1013.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1013.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1013.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1013.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1013.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1013.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1013.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1013.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1013.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1013.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07990]
>[  1014.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07990] width 1920 pitch 7680 (/4 1920)
>[  1014.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd58a0]
>[  1014.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd58a0] width 1920 pitch 7680 (/4 1920)
>[  1014.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd58a0]
>[  1014.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd58a0] width 1920 pitch 7680 (/4 1920)
>[  1014.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd58a0]
>[  1014.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd58a0] width 1920 pitch 7680 (/4 1920)
>[  1014.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07990]
>[  1014.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07990] width 1920 pitch 7680 (/4 1920)
>[  1014.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07990]
>[  1014.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07990] width 1920 pitch 7680 (/4 1920)
>[  1014.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07990]
>[  1014.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07990] width 1920 pitch 7680 (/4 1920)
>[  1014.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd58a0]
>[  1014.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd58a0] width 1920 pitch 7680 (/4 1920)
>[  1014.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1014.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1014.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4200]
>[  1014.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4200] width 1920 pitch 7680 (/4 1920)
>[  1014.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1014.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1014.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c8c480]
>[  1014.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c8c480] width 1920 pitch 7680 (/4 1920)
>[  1014.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3966c50]
>[  1014.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3966c50] width 1920 pitch 7680 (/4 1920)
>[  1014.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4200]
>[  1014.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4200] width 1920 pitch 7680 (/4 1920)
>[  1014.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1014.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1014.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4200]
>[  1014.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4200] width 1920 pitch 7680 (/4 1920)
>[  1014.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1014.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1014.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4200]
>[  1014.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4200] width 1920 pitch 7680 (/4 1920)
>[  1014.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1014.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1015.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397eb60]
>[  1015.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397eb60] width 1920 pitch 7680 (/4 1920)
>[  1041.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dadf80]
>[  1041.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dadf80] width 1920 pitch 7680 (/4 1920)
>[  1041.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b0d0]
>[  1041.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b0d0] width 1920 pitch 7680 (/4 1920)
>[  1043.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbae50]
>[  1043.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbae50] width 1920 pitch 7680 (/4 1920)
>[  1043.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a99e0]
>[  1043.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a99e0] width 1920 pitch 7680 (/4 1920)
>[  1043.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9560]
>[  1043.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9560] width 1920 pitch 7680 (/4 1920)
>[  1043.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbdd40]
>[  1043.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbdd40] width 1920 pitch 7680 (/4 1920)
>[  1043.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[  1043.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[  1043.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9560]
>[  1043.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9560] width 1920 pitch 7680 (/4 1920)
>[  1043.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[  1043.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[  1043.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9560]
>[  1043.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9560] width 1920 pitch 7680 (/4 1920)
>[  1043.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3949660]
>[  1043.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3949660] width 1920 pitch 7680 (/4 1920)
>[  1043.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9560]
>[  1043.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9560] width 1920 pitch 7680 (/4 1920)
>[  1047.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939110]
>[  1047.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939110] width 1920 pitch 7680 (/4 1920)
>[  1048.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb6c0]
>[  1048.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb6c0] width 1920 pitch 7680 (/4 1920)
>[  1048.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab1f0]
>[  1048.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab1f0] width 1920 pitch 7680 (/4 1920)
>[  1048.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd86a0]
>[  1048.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd86a0] width 1920 pitch 7680 (/4 1920)
>[  1049.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40af2a0]
>[  1049.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40af2a0] width 1920 pitch 7680 (/4 1920)
>[  1110.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b4ea0]
>[  1110.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b4ea0] width 1920 pitch 7680 (/4 1920)
>[  1112.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de0f60]
>[  1112.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de0f60] width 1920 pitch 7680 (/4 1920)
>[  1125.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b5170]
>[  1125.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b5170] width 1920 pitch 7680 (/4 1920)
>[  1125.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929a70]
>[  1125.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929a70] width 1920 pitch 7680 (/4 1920)
>[  1125.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbe870]
>[  1125.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbe870] width 1920 pitch 7680 (/4 1920)
>[  1125.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9dee0]
>[  1125.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9dee0] width 1920 pitch 7680 (/4 1920)
>[  1126.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbcb70]
>[  1126.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbcb70] width 1920 pitch 7680 (/4 1920)
>[  1262.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fe540]
>[  1262.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fe540] width 1920 pitch 7680 (/4 1920)
>[  1265.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1265.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40febe0]
>[  1265.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40febe0] width 1920 pitch 7680 (/4 1920)
>[  1265.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2300]
>[  1265.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2300] width 1920 pitch 7680 (/4 1920)
>[  1265.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1265.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1265.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1265.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1265.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4a10]
>[  1265.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4a10] width 1920 pitch 7680 (/4 1920)
>[  1265.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db1360]
>[  1265.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db1360] width 1920 pitch 7680 (/4 1920)
>[  1272.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d70]
>[  1272.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d70] width 1920 pitch 7680 (/4 1920)
>[  1272.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3938900]
>[  1272.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3938900] width 1920 pitch 7680 (/4 1920)
>[  1272.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c85950]
>[  1272.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c85950] width 1920 pitch 7680 (/4 1920)
>[  1272.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c85730]
>[  1272.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c85730] width 1920 pitch 7680 (/4 1920)
>[  1282.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4070]
>[  1282.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4070] width 1920 pitch 7680 (/4 1920)
>[  1311.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3860b00]
>[  1311.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3860b00] width 1920 pitch 7680 (/4 1920)
>[  1689.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd4b80]
>[  1689.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd4b80] width 1920 pitch 7680 (/4 1920)
>[  1693.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf0e0]
>[  1693.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf0e0] width 1920 pitch 7680 (/4 1920)
>[  1693.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec720]
>[  1693.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec720] width 1920 pitch 7680 (/4 1920)
>[  1693.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2450]
>[  1693.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2450] width 1920 pitch 7680 (/4 1920)
>[  1693.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39402a0]
>[  1693.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39402a0] width 1920 pitch 7680 (/4 1920)
>[  1693.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9fc40]
>[  1693.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9fc40] width 1920 pitch 7680 (/4 1920)
>[  1693.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1693.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1693.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0d70]
>[  1693.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0d70] width 1920 pitch 7680 (/4 1920)
>[  1693.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1693.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1693.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0d70]
>[  1693.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0d70] width 1920 pitch 7680 (/4 1920)
>[  1693.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1693.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1693.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0d70]
>[  1693.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0d70] width 1920 pitch 7680 (/4 1920)
>[  1693.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1693.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1693.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0d70]
>[  1693.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0d70] width 1920 pitch 7680 (/4 1920)
>[  1693.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393da40]
>[  1693.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393da40] width 1920 pitch 7680 (/4 1920)
>[  1726.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5d0]
>[  1726.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5d0] width 1920 pitch 7680 (/4 1920)
>[  1727.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3938900]
>[  1727.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3938900] width 1920 pitch 7680 (/4 1920)
>[  1727.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2280]
>[  1727.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2280] width 1920 pitch 7680 (/4 1920)
>[  1727.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a97a0]
>[  1727.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a97a0] width 1920 pitch 7680 (/4 1920)
>[  1746.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c11b0]
>[  1746.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c11b0] width 1920 pitch 7680 (/4 1920)
>[  2030.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2030.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2030.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2030.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2030.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2030.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2030.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2030.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2030.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2030.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2030.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2030.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2030.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2030.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2030.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2030.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2030.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2030.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2031.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2031.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2031.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2031.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2032.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2032.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2032.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2032.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2033.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2033.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2033.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2033.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2033.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2033.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2033.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2033.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2033.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2033.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2033.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2033.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2033.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2033.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2033.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c0640]
>[  2033.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c0640] width 1920 pitch 7680 (/4 1920)
>[  2033.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda600]
>[  2033.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda600] width 1920 pitch 7680 (/4 1920)
>[  2037.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2037.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2037.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2037.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2037.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2037.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2037.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2037.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2037.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2037.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2037.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2037.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2051.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2051.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2051.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2051.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2051.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2051.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2051.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2051.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2051.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2051.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2051.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2051.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2051.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2051.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2051.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2052.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2052.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2052.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2052.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2052.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2052.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2052.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2052.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2052.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2052.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2052.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2053.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2053.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2053.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2053.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2053.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2053.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2053.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2053.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2054.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2054.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2054.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2054.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2055.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2055.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2055.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2055.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2058.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2058.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2058.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2058.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2058.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2058.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2058.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2058.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2058.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2058.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2058.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2058.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2058.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2058.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2058.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2058.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2058.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2058.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2058.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2058.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2058.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2058.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2058.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2059.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2059.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2059.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2059.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2059.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2059.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2059.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2059.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2059.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2059.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2059.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2059.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2059.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2059.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2059.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2060.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2060.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2060.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2060.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2060.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2060.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2060.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2060.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2060.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2060.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2060.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2060.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2060.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2060.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2060.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2060.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2060.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2060.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2060.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2060.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2060.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2060.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2060.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2060.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2060.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2061.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2061.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2061.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2061.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2061.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2061.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2061.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2061.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2061.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2061.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2061.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2061.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2061.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2061.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2061.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd8b0]
>[  2061.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd8b0] width 1920 pitch 7680 (/4 1920)
>[  2061.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391bac0]
>[  2061.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391bac0] width 1920 pitch 7680 (/4 1920)
>[  2061.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e340]
>[  2061.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e340] width 1920 pitch 7680 (/4 1920)
>[  2061.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1680]
>[  2061.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1680] width 1920 pitch 7680 (/4 1920)
>[  2061.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd8b0]
>[  2061.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd8b0] width 1920 pitch 7680 (/4 1920)
>[  2061.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391bac0]
>[  2061.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391bac0] width 1920 pitch 7680 (/4 1920)
>[  2062.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e340]
>[  2062.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e340] width 1920 pitch 7680 (/4 1920)
>[  2062.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1680]
>[  2062.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1680] width 1920 pitch 7680 (/4 1920)
>[  2062.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd8b0]
>[  2062.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd8b0] width 1920 pitch 7680 (/4 1920)
>[  2062.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391bac0]
>[  2062.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391bac0] width 1920 pitch 7680 (/4 1920)
>[  2062.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391e340]
>[  2062.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391e340] width 1920 pitch 7680 (/4 1920)
>[  2063.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2063.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2063.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2063.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2063.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2063.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2063.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2063.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2063.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2063.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2063.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2063.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2063.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2063.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2063.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2063.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2063.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2063.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2063.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2063.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2063.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2063.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2063.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2063.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2064.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2064.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2064.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2064.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2064.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2064.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2064.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2064.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2064.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2064.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2064.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2064.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2064.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2064.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2064.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2064.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2065.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2065.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2065.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2065.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2065.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2065.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2065.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2065.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2065.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2065.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2065.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2065.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2065.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2065.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2065.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2065.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2065.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2065.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2065.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2065.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2067.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2067.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2067.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2067.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2067.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2067.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2067.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2067.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2067.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2067.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2067.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2067.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2067.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2067.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2067.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2067.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2067.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2067.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2067.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2067.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2067.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2067.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2067.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2067.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2068.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2068.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2068.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2068.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2068.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2068.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2068.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2068.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2068.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2068.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2068.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2068.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2068.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2068.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2068.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2068.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2068.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2068.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2068.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2068.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2068.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2068.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2068.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2068.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2068.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2068.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2068.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2068.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2068.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2068.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2068.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2068.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2068.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2068.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2068.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2068.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2068.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2068.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2068.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2068.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2068.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2068.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2068.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2068.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2068.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7e10]
>[  2068.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7e10] width 1920 pitch 7680 (/4 1920)
>[  2068.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2068.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2068.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2068.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2069.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2069.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2069.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5b90]
>[  2069.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5b90] width 1920 pitch 7680 (/4 1920)
>[  2069.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2069.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2069.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2069.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2069.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2069.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2069.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2069.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2069.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2069.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2069.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2069.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2069.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a89d0]
>[  2069.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a89d0] width 1920 pitch 7680 (/4 1920)
>[  2070.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2070.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2070.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2070.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2070.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2070.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2070.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2070.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2070.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2070.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2070.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbbe80]
>[  2070.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbbe80] width 1920 pitch 7680 (/4 1920)
>[  2070.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd8780]
>[  2070.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd8780] width 1920 pitch 7680 (/4 1920)
>[  2070.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5ac0]
>[  2070.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5ac0] width 1920 pitch 7680 (/4 1920)
>[  2070.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2070.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2070.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2070.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2070.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2070.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2070.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2070.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2070.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2070.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2070.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2070.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2070.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2070.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2070.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2070.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2070.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3963970]
>[  2071.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3963970] width 1920 pitch 7680 (/4 1920)
>[  2071.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2071.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2071.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39639b0]
>[  2071.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39639b0] width 1920 pitch 7680 (/4 1920)
>[  2071.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca5390]
>[  2071.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca5390] width 1920 pitch 7680 (/4 1920)
>[  2071.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2071.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2071.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd88b0]
>[  2071.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd88b0] width 1920 pitch 7680 (/4 1920)
>[  2071.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391ef20]
>[  2071.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391ef20] width 1920 pitch 7680 (/4 1920)
>[  2071.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b8660]
>[  2071.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b8660] width 1920 pitch 7680 (/4 1920)
>[  2071.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de48d0]
>[  2071.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de48d0] width 1920 pitch 7680 (/4 1920)
>[  2071.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2071.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2071.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939120]
>[  2071.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939120] width 1920 pitch 7680 (/4 1920)
>[  2071.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2071.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2071.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d4b0]
>[  2071.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d4b0] width 1920 pitch 7680 (/4 1920)
>[  2071.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939040]
>[  2071.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939040] width 1920 pitch 7680 (/4 1920)
>[  2071.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2071.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2071.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939300]
>[  2071.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939300] width 1920 pitch 7680 (/4 1920)
>[  2071.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d4b0]
>[  2071.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d4b0] width 1920 pitch 7680 (/4 1920)
>[  2071.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939330]
>[  2071.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939330] width 1920 pitch 7680 (/4 1920)
>[  2071.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939330]
>[  2071.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939330] width 1920 pitch 7680 (/4 1920)
>[  2071.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939330]
>[  2071.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939330] width 1920 pitch 7680 (/4 1920)
>[  2071.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d4b0]
>[  2071.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d4b0] width 1920 pitch 7680 (/4 1920)
>[  2071.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391d4b0]
>[  2071.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391d4b0] width 1920 pitch 7680 (/4 1920)
>[  2071.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2072.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2072.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2072.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2072.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4274e40]
>[  2072.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4274e40] width 1920 pitch 7680 (/4 1920)
>[  2072.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39624b0]
>[  2072.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39624b0] width 1920 pitch 7680 (/4 1920)
>[  2072.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39624b0]
>[  2072.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39624b0] width 1920 pitch 7680 (/4 1920)
>[  2072.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da0450]
>[  2072.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da0450] width 1920 pitch 7680 (/4 1920)
>[  2072.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39624b0]
>[  2072.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39624b0] width 1920 pitch 7680 (/4 1920)
>[  2072.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4274e40]
>[  2072.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4274e40] width 1920 pitch 7680 (/4 1920)
>[  2072.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4274e40]
>[  2072.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4274e40] width 1920 pitch 7680 (/4 1920)
>[  2072.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39390e0]
>[  2072.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39390e0] width 1920 pitch 7680 (/4 1920)
>[  2074.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdff0]
>[  2074.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdff0] width 1920 pitch 7680 (/4 1920)
>[  2074.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dce8b0]
>[  2074.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dce8b0] width 1920 pitch 7680 (/4 1920)
>[  2074.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3860bd0]
>[  2074.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3860bd0] width 1920 pitch 7680 (/4 1920)
>[  2074.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea40]
>[  2074.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea40] width 1920 pitch 7680 (/4 1920)
>[  2074.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2074.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2074.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dceac0]
>[  2074.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dceac0] width 1920 pitch 7680 (/4 1920)
>[  2074.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dceb70]
>[  2074.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dceb70] width 1920 pitch 7680 (/4 1920)
>[  2074.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3860bd0]
>[  2075.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3860bd0] width 1920 pitch 7680 (/4 1920)
>[  2075.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dceb70]
>[  2075.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dceb70] width 1920 pitch 7680 (/4 1920)
>[  2075.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dceb70]
>[  2075.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dceb70] width 1920 pitch 7680 (/4 1920)
>[  2075.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea20]
>[  2075.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea20] width 1920 pitch 7680 (/4 1920)
>[  2075.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea20]
>[  2075.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea20] width 1920 pitch 7680 (/4 1920)
>[  2075.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea20]
>[  2075.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea20] width 1920 pitch 7680 (/4 1920)
>[  2075.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcea20]
>[  2075.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcea20] width 1920 pitch 7680 (/4 1920)
>[  2075.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcfc40]
>[  2075.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcfc40] width 1920 pitch 7680 (/4 1920)
>[  2075.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcfbc0]
>[  2075.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcfbc0] width 1920 pitch 7680 (/4 1920)
>[  2075.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcfbc0]
>[  2075.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcfbc0] width 1920 pitch 7680 (/4 1920)
>[  2075.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2075.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2075.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf9f0]
>[  2075.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf9f0] width 1920 pitch 7680 (/4 1920)
>[  2075.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf950]
>[  2075.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf950] width 1920 pitch 7680 (/4 1920)
>[  2075.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf950]
>[  2075.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf950] width 1920 pitch 7680 (/4 1920)
>[  2075.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8d50]
>[  2075.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8d50] width 1920 pitch 7680 (/4 1920)
>[  2075.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcf920]
>[  2075.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcf920] width 1920 pitch 7680 (/4 1920)
>[  2075.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8d50]
>[  2075.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8d50] width 1920 pitch 7680 (/4 1920)
>[  2075.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de5f90]
>[  2075.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de5f90] width 1920 pitch 7680 (/4 1920)
>[  2075.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f794a0]
>[  2075.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f794a0] width 1920 pitch 7680 (/4 1920)
>[  2075.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2075.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2075.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f794a0]
>[  2075.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f794a0] width 1920 pitch 7680 (/4 1920)
>[  2075.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2075.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2075.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8d50]
>[  2075.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8d50] width 1920 pitch 7680 (/4 1920)
>[  2075.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcde70]
>[  2075.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcde70] width 1920 pitch 7680 (/4 1920)
>[  2076.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426fc50]
>[  2076.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426fc50] width 1920 pitch 7680 (/4 1920)
>[  2099.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc78b0]
>[  2099.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc78b0] width 1920 pitch 7680 (/4 1920)
>[  2099.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc36f0]
>[  2099.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc36f0] width 1920 pitch 7680 (/4 1920)
>[  2099.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcb7f0]
>[  2099.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcb7f0] width 1920 pitch 7680 (/4 1920)
>[  2099.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2099.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2099.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2099.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394e240]
>[  2099.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394e240] width 1920 pitch 7680 (/4 1920)
>[  2105.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2105.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2105.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2105.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2105.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2106.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2106.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2106.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2106.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1670]
>[  2106.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1670] width 1920 pitch 7680 (/4 1920)
>[  2106.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d920]
>[  2106.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d920] width 1920 pitch 7680 (/4 1920)
>[  2106.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1700]
>[  2106.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1700] width 1920 pitch 7680 (/4 1920)
>[  2106.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a5fe0]
>[  2106.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a5fe0] width 1920 pitch 7680 (/4 1920)
>[  2106.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1700]
>[  2106.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1700] width 1920 pitch 7680 (/4 1920)
>[  2106.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ccf70]
>[  2107.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ccf70] width 1920 pitch 7680 (/4 1920)
>[  2107.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd87c0]
>[  2107.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd87c0] width 1920 pitch 7680 (/4 1920)
>[  2107.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd8750]
>[  2107.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd8750] width 1920 pitch 7680 (/4 1920)
>[  2107.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8730]
>[  2107.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8730] width 1920 pitch 7680 (/4 1920)
>[  2107.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fda70]
>[  2107.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fda70] width 1920 pitch 7680 (/4 1920)
>[  2107.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc7ca0]
>[  2107.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc7ca0] width 1920 pitch 7680 (/4 1920)
>[  2107.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda780]
>[  2107.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda780] width 1920 pitch 7680 (/4 1920)
>[  2107.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c8730]
>[  2107.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c8730] width 1920 pitch 7680 (/4 1920)
>[  2107.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[  2107.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[  2107.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fda70]
>[  2107.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fda70] width 1920 pitch 7680 (/4 1920)
>[  2107.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b2d0]
>[  2107.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b2d0] width 1920 pitch 7680 (/4 1920)
>[  2107.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b2d0]
>[  2107.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b2d0] width 1920 pitch 7680 (/4 1920)
>[  2107.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd87a0]
>[  2107.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd87a0] width 1920 pitch 7680 (/4 1920)
>[  2107.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fda70]
>[  2107.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fda70] width 1920 pitch 7680 (/4 1920)
>[  2107.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fda70]
>[  2107.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fda70] width 1920 pitch 7680 (/4 1920)
>[  2107.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2107.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd87a0]
>[  2107.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd87a0] width 1920 pitch 7680 (/4 1920)
>[  2107.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c4500]
>[  2107.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c4500] width 1920 pitch 7680 (/4 1920)
>[  2112.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da5c0]
>[  2112.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da5c0] width 1920 pitch 7680 (/4 1920)
>[  2112.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da400]
>[  2112.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da400] width 1920 pitch 7680 (/4 1920)
>[  2112.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2112.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2112.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da710]
>[  2112.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da710] width 1920 pitch 7680 (/4 1920)
>[  2112.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2112.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2112.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da710]
>[  2112.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da710] width 1920 pitch 7680 (/4 1920)
>[  2112.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2112.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2112.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da4d0]
>[  2113.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da4d0] width 1920 pitch 7680 (/4 1920)
>[  2113.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2113.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2113.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da4d0]
>[  2113.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da4d0] width 1920 pitch 7680 (/4 1920)
>[  2113.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2113.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2113.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da4d0]
>[  2113.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da4d0] width 1920 pitch 7680 (/4 1920)
>[  2113.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2113.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2113.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da4d0]
>[  2113.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da4d0] width 1920 pitch 7680 (/4 1920)
>[  2113.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da710]
>[  2113.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da710] width 1920 pitch 7680 (/4 1920)
>[  2113.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2113.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2113.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da710]
>[  2113.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da710] width 1920 pitch 7680 (/4 1920)
>[  2113.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da640]
>[  2113.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da640] width 1920 pitch 7680 (/4 1920)
>[  2113.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40da640]
>[  2113.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40da640] width 1920 pitch 7680 (/4 1920)
>[  2198.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2198.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2198.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2198.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2199.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2199.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2199.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7520]
>[  2199.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7520] width 1920 pitch 7680 (/4 1920)
>[  2200.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2200.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2200.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2200.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2200.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2200.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2200.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2200.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2200.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2200.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2200.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2200.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2200.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2200.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2200.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2200.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2200.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddbaf0]
>[  2200.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddbaf0] width 1920 pitch 7680 (/4 1920)
>[  2200.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2200.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2202.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2202.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2202.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b5d0]
>[  2202.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b5d0] width 1920 pitch 7680 (/4 1920)
>[  2203.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2203.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2204.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2204.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2204.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2204.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2204.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2204.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2204.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2204.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275d20]
>[  2204.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275d20] width 1920 pitch 7680 (/4 1920)
>[  2207.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2207.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2207.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2207.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2207.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a88e0]
>[  2207.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a88e0] width 1920 pitch 7680 (/4 1920)
>[  2207.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2207.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2207.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b5d0]
>[  2207.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b5d0] width 1920 pitch 7680 (/4 1920)
>[  2207.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2207.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2207.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a88e0]
>[  2207.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a88e0] width 1920 pitch 7680 (/4 1920)
>[  2207.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2207.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2207.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2207.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2207.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a88e0]
>[  2207.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a88e0] width 1920 pitch 7680 (/4 1920)
>[  2207.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b5d0]
>[  2207.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b5d0] width 1920 pitch 7680 (/4 1920)
>[  2207.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2207.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2208.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2208.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2208.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b5d0]
>[  2208.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b5d0] width 1920 pitch 7680 (/4 1920)
>[  2208.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2208.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2208.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a88e0]
>[  2208.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a88e0] width 1920 pitch 7680 (/4 1920)
>[  2208.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db90e0]
>[  2208.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db90e0] width 1920 pitch 7680 (/4 1920)
>[  2208.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a88e0]
>[  2208.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a88e0] width 1920 pitch 7680 (/4 1920)
>[  2208.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2208.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2208.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2208.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2208.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2208.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2209.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275c40]
>[  2209.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275c40] width 1920 pitch 7680 (/4 1920)
>[  2214.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816640]
>[  2214.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816640] width 1920 pitch 7680 (/4 1920)
>[  2214.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2214.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2214.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816380]
>[  2214.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816380] width 1920 pitch 7680 (/4 1920)
>[  2214.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816640]
>[  2214.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816640] width 1920 pitch 7680 (/4 1920)
>[  2214.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816380]
>[  2214.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816380] width 1920 pitch 7680 (/4 1920)
>[  2214.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2214.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2214.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816380]
>[  2214.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816380] width 1920 pitch 7680 (/4 1920)
>[  2214.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816640]
>[  2214.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816640] width 1920 pitch 7680 (/4 1920)
>[  2214.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816380]
>[  2214.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816380] width 1920 pitch 7680 (/4 1920)
>[  2214.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2214.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2214.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2817e20]
>[  2214.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2817e20] width 1920 pitch 7680 (/4 1920)
>[  2214.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2214.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2215.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395a2e0]
>[  2215.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395a2e0] width 1920 pitch 7680 (/4 1920)
>[  2215.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daea0]
>[  2215.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daea0] width 1920 pitch 7680 (/4 1920)
>[  2215.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2215.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2215.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[  2215.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[  2215.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957780]
>[  2215.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957780] width 1920 pitch 7680 (/4 1920)
>[  2215.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcc60]
>[  2215.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcc60] width 1920 pitch 7680 (/4 1920)
>[  2215.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2215.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2215.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daea0]
>[  2215.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daea0] width 1920 pitch 7680 (/4 1920)
>[  2215.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395a2e0]
>[  2216.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395a2e0] width 1920 pitch 7680 (/4 1920)
>[  2216.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816440]
>[  2216.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816440] width 1920 pitch 7680 (/4 1920)
>[  2216.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[  2216.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[  2216.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[  2216.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[  2216.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe1e0]
>[  2216.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe1e0] width 1920 pitch 7680 (/4 1920)
>[  2216.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb6560]
>[  2216.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb6560] width 1920 pitch 7680 (/4 1920)
>[  2216.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec25b0]
>[  2216.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec25b0] width 1920 pitch 7680 (/4 1920)
>[  2217.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec70c0]
>[  2217.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec70c0] width 1920 pitch 7680 (/4 1920)
>[  2217.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec8100]
>[  2217.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec8100] width 1920 pitch 7680 (/4 1920)
>[  2218.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148ae0]
>[  2218.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148ae0] width 1920 pitch 7680 (/4 1920)
>[  2218.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148ab0]
>[  2218.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148ab0] width 1920 pitch 7680 (/4 1920)
>[  2218.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2218.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2218.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2218.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2218.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b54b0]
>[  2218.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b54b0] width 1920 pitch 7680 (/4 1920)
>[  2218.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2218.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2218.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2218.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2218.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2218.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2218.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2218.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b54b0]
>[  2218.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b54b0] width 1920 pitch 7680 (/4 1920)
>[  2218.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2218.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2218.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2218.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2218.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489a0]
>[  2218.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489a0] width 1920 pitch 7680 (/4 1920)
>[  2219.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b5460]
>[  2219.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b5460] width 1920 pitch 7680 (/4 1920)
>[  2219.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3965490]
>[  2220.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3965490] width 1920 pitch 7680 (/4 1920)
>[  2220.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2220.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2220.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2220.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2221.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed7f70]
>[  2221.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed7f70] width 1920 pitch 7680 (/4 1920)
>[  2221.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2221.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2221.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e49ac0]
>[  2221.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e49ac0] width 1920 pitch 7680 (/4 1920)
>[  2221.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148850]
>[  2221.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148850] width 1920 pitch 7680 (/4 1920)
>[  2221.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4d80]
>[  2221.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4d80] width 1920 pitch 7680 (/4 1920)
>[  2221.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffdf0]
>[  2221.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffdf0] width 1920 pitch 7680 (/4 1920)
>[  2221.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de4f30]
>[  2221.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de4f30] width 1920 pitch 7680 (/4 1920)
>[  2225.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2225.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2226.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2226.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2226.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2226.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2226.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39634f0]
>[  2226.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39634f0] width 1920 pitch 7680 (/4 1920)
>[  2226.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2226.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2226.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2226.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2226.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2226.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2226.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2226.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2226.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39634f0]
>[  2226.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39634f0] width 1920 pitch 7680 (/4 1920)
>[  2227.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2227.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2227.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39634f0]
>[  2227.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39634f0] width 1920 pitch 7680 (/4 1920)
>[  2227.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2227.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2228.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2228.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2228.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2228.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[  2228.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[  2228.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[  2228.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[  2228.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2228.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2228.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[  2228.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[  2228.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc9570]
>[  2228.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc9570] width 1920 pitch 7680 (/4 1920)
>[  2228.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2228.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2228.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[  2228.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[  2228.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc9570]
>[  2228.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc9570] width 1920 pitch 7680 (/4 1920)
>[  2228.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[  2228.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[  2228.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[  2228.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[  2228.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[  2228.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[  2231.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2231.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2233.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2233.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2233.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2233.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2233.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2233.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2233.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2233.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2233.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2233.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2233.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2233.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2233.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2233.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2233.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2233.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2233.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2233.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2233.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2233.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2233.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2233.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2233.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2233.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2233.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2233.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2233.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2233.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2233.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2234.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2234.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2234.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2234.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2234.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2234.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2234.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2234.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2234.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2234.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2234.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2234.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2234.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2235.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2235.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2235.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2235.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2235.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2235.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2235.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2235.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2241.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2241.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2241.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2241.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2241.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2241.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2241.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2241.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2241.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2241.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2241.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2241.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2241.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2241.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2241.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2241.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2241.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2241.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2242.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc47e0]
>[  2242.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc47e0] width 1920 pitch 7680 (/4 1920)
>[  2242.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2242.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2242.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc8d40]
>[  2242.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc8d40] width 1920 pitch 7680 (/4 1920)
>[  2242.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2242.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2243.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2243.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2243.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2243.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2243.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2243.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2243.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2244.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2244.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2244.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2244.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2244.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2244.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2244.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2244.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2244.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2244.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2244.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2244.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2244.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2244.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2244.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f770]
>[  2244.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f770] width 1920 pitch 7680 (/4 1920)
>[  2244.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2244.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2244.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c84b0]
>[  2244.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c84b0] width 1920 pitch 7680 (/4 1920)
>[  2248.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3954c10]
>[  2248.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3954c10] width 1920 pitch 7680 (/4 1920)
>[  2248.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2248.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2292.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2292.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2292.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2292.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2292.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2292.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2292.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2292.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2292.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2292.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2292.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2292.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2292.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2292.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2292.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2292.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2293.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2293.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2293.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2293.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2293.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2293.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2293.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2293.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2293.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2293.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2294.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2294.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2294.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2294.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2294.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2294.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2294.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2294.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2294.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2294.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2294.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2294.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2294.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2294.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2294.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2294.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2294.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2294.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2294.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2294.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2296.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2296.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2296.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2296.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2296.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2296.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2296.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2296.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2297.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2297.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2297.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2297.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2297.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2297.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2297.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2297.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2297.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2297.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2297.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[  2297.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[  2297.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2297.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2297.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2297.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2297.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4a50]
>[  2297.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4a50] width 1920 pitch 7680 (/4 1920)
>[  2297.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[  2297.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[  2308.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4520]
>[  2308.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4520] width 1920 pitch 7680 (/4 1920)
>[  2308.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbf600]
>[  2308.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbf600] width 1920 pitch 7680 (/4 1920)
>[  2309.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbf600]
>[  2309.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbf600] width 1920 pitch 7680 (/4 1920)
>[  2309.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426e3e0]
>[  2309.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426e3e0] width 1920 pitch 7680 (/4 1920)
>[  2309.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0d2b0]
>[  2309.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0d2b0] width 1920 pitch 7680 (/4 1920)
>[  2309.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0d2b0]
>[  2309.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0d2b0] width 1920 pitch 7680 (/4 1920)
>[  2309.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0d2b0]
>[  2309.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0d2b0] width 1920 pitch 7680 (/4 1920)
>[  2309.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0cae0]
>[  2309.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0cae0] width 1920 pitch 7680 (/4 1920)
>[  2309.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbf600]
>[  2309.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbf600] width 1920 pitch 7680 (/4 1920)
>[  2309.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0cae0]
>[  2309.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0cae0] width 1920 pitch 7680 (/4 1920)
>[  2309.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0d2b0]
>[  2309.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0d2b0] width 1920 pitch 7680 (/4 1920)
>[  2309.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39631c0]
>[  2310.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39631c0] width 1920 pitch 7680 (/4 1920)
>[  2310.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2310.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[  2310.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[  2310.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[  2310.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[  2799.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[  2799.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[  2799.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c977a0]
>[  2799.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c977a0] width 1920 pitch 7680 (/4 1920)
>[  2800.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eed470]
>[  2800.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eed470] width 1920 pitch 7680 (/4 1920)
>[  2800.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e68750]
>[  2800.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e68750] width 1920 pitch 7680 (/4 1920)
>[  2863.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fe20]
>[  2863.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fe20] width 1920 pitch 7680 (/4 1920)
>[  2863.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fe20]
>[  2863.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fe20] width 1920 pitch 7680 (/4 1920)
>[  2863.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fe20]
>[  2863.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fe20] width 1920 pitch 7680 (/4 1920)
>[  2863.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[  2863.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[  2863.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[  2863.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[  2863.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[  2863.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[  2863.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[  2863.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[  2863.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[  2863.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[  2868.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2868.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2868.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2868.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2868.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2868.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2868.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2868.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2868.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2868.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2868.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2868.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2868.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2868.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2868.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2868.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2868.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2869.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2869.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2869.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2869.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2869.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2869.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2869.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7bd0]
>[  2869.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7bd0] width 1920 pitch 7680 (/4 1920)
>[  2869.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94480]
>[  2869.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94480] width 1920 pitch 7680 (/4 1920)
>[  2869.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7bd0]
>[  2869.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7bd0] width 1920 pitch 7680 (/4 1920)
>[  2869.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94480]
>[  2869.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94480] width 1920 pitch 7680 (/4 1920)
>[  2869.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b7bd0]
>[  2869.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b7bd0] width 1920 pitch 7680 (/4 1920)
>[  2869.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94480]
>[  2869.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94480] width 1920 pitch 7680 (/4 1920)
>[  2869.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060490]
>[  2869.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060490] width 1920 pitch 7680 (/4 1920)
>[  2870.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[  2870.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[  2870.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2870.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2870.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2908.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055340]
>[  2908.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055340] width 1920 pitch 7680 (/4 1920)
>[  2908.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084e10]
>[  2908.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084e10] width 1920 pitch 7680 (/4 1920)
>[  2913.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2913.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2913.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2913.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2913.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2913.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2913.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2913.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2913.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2913.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2913.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2914.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2914.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2914.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2914.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2914.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2914.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2914.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2914.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2914.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2914.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e30]
>[  2914.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e30] width 1920 pitch 7680 (/4 1920)
>[  2915.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2915.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2915.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5086350]
>[  2915.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5086350] width 1920 pitch 7680 (/4 1920)
>[  2915.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2915.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5086350]
>[  2915.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5086350] width 1920 pitch 7680 (/4 1920)
>[  2915.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2915.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5086350]
>[  2915.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5086350] width 1920 pitch 7680 (/4 1920)
>[  2915.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2915.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5086350]
>[  2915.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5086350] width 1920 pitch 7680 (/4 1920)
>[  2915.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077050]
>[  2915.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077050] width 1920 pitch 7680 (/4 1920)
>[  2994.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5118580]
>[  2994.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5118580] width 1920 pitch 7680 (/4 1920)
>[  3189.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3189.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3189.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061510]
>[  3189.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061510] width 1920 pitch 7680 (/4 1920)
>[  3189.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3189.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958140]
>[  3190.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958140] width 1920 pitch 7680 (/4 1920)
>[  3190.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3190.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3190.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3190.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3190.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3190.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3190.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3191.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3191.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3191.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3191.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3192.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3192.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3192.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085740]
>[  3192.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085740] width 1920 pitch 7680 (/4 1920)
>[  3208.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3208.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3208.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3208.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3209.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3209.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3209.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3209.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3209.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3209.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3209.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf9c0]
>[  3209.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf9c0] width 1920 pitch 7680 (/4 1920)
>[  3209.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3209.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3209.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3209.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3209.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3209.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3209.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3209.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3209.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3209.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3209.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3209.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3209.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3209.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3209.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3209.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3209.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3209.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3209.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3209.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3209.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3209.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf9c0]
>[  3209.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf9c0] width 1920 pitch 7680 (/4 1920)
>[  3209.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3209.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3209.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3209.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3209.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3209.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3209.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3209.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3209.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3209.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3209.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3209.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3209.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3209.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3209.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3209.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3209.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3209.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3209.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3209.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3209.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3209.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3210.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3210.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3210.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf9c0]
>[  3210.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf9c0] width 1920 pitch 7680 (/4 1920)
>[  3210.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3210.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3210.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3210.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3210.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3210.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3210.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3210.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3210.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3210.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3210.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3210.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3210.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3210.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3210.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3210.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3210.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3210.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3210.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3210.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3210.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3210.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3210.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf9c0]
>[  3210.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf9c0] width 1920 pitch 7680 (/4 1920)
>[  3210.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[  3210.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[  3210.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3210.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3210.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3210.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3210.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3210.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3210.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42730d0]
>[  3210.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42730d0] width 1920 pitch 7680 (/4 1920)
>[  3210.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3210.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3210.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3210.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3210.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50abcc0]
>[  3210.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50abcc0] width 1920 pitch 7680 (/4 1920)
>[  3210.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3210.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3210.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3210.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3213.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3213.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3213.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5134d60]
>[  3213.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5134d60] width 1920 pitch 7680 (/4 1920)
>[  3213.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fd90]
>[  3213.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fd90] width 1920 pitch 7680 (/4 1920)
>[  3213.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ef80]
>[  3213.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ef80] width 1920 pitch 7680 (/4 1920)
>[  3214.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[  3214.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[  3214.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[  3214.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[  3215.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51022c0]
>[  3215.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51022c0] width 1920 pitch 7680 (/4 1920)
>[  3215.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[  3215.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[  3215.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51022c0]
>[  3215.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51022c0] width 1920 pitch 7680 (/4 1920)
>[  3215.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3215.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3215.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3215.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3215.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51022c0]
>[  3215.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51022c0] width 1920 pitch 7680 (/4 1920)
>[  3215.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3215.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3215.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[  3215.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[  3215.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3215.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3215.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[  3215.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[  3215.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[  3215.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[  3215.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[  3215.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[  3215.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[  3215.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[  3215.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bc90]
>[  3215.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bc90] width 1920 pitch 7680 (/4 1920)
>[  3215.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a700]
>[  3215.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a700] width 1920 pitch 7680 (/4 1920)
>[  3215.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3215.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3216.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3216.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3216.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3216.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3216.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2c0]
>[  3216.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2c0] width 1920 pitch 7680 (/4 1920)
>[  3216.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3216.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3216.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2c0]
>[  3216.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2c0] width 1920 pitch 7680 (/4 1920)
>[  3216.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2c0]
>[  3216.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2c0] width 1920 pitch 7680 (/4 1920)
>[  3216.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3216.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3216.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2c0]
>[  3216.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2c0] width 1920 pitch 7680 (/4 1920)
>[  3216.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3216.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3216.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3216.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3217.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3217.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3217.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e2c0]
>[  3217.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e2c0] width 1920 pitch 7680 (/4 1920)
>[  3217.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3217.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3217.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3217.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3217.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3217.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3217.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[  3217.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1920 pitch 7680 (/4 1920)
>[  3217.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[  3217.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[  3217.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3217.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3217.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a660]
>[  3217.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a660] width 1920 pitch 7680 (/4 1920)
>[  3217.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87360]
>[  3217.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87360] width 1920 pitch 7680 (/4 1920)
>[  3217.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3217.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3488.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030cf0]
>[  3488.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030cf0] width 1920 pitch 7680 (/4 1920)
>[  3488.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50da370]
>[  3488.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50da370] width 1920 pitch 7680 (/4 1920)
>[  3488.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281bb50]
>[  3488.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281bb50] width 1920 pitch 7680 (/4 1920)
>[  3488.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281bb50]
>[  3488.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281bb50] width 1920 pitch 7680 (/4 1920)
>[  3488.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50da370]
>[  3488.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50da370] width 1920 pitch 7680 (/4 1920)
>[  3488.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd880]
>[  3488.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd880] width 1920 pitch 7680 (/4 1920)
>[  3488.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3488.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3488.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030c60]
>[  3488.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030c60] width 1920 pitch 7680 (/4 1920)
>[  3488.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3488.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3488.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3488.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3488.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030c60]
>[  3488.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030c60] width 1920 pitch 7680 (/4 1920)
>[  3488.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3488.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3488.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030c60]
>[  3488.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030c60] width 1920 pitch 7680 (/4 1920)
>[  3488.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030cf0]
>[  3488.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030cf0] width 1920 pitch 7680 (/4 1920)
>[  3488.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9170]
>[  3488.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9170] width 1920 pitch 7680 (/4 1920)
>[  3490.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8680]
>[  3490.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8680] width 1920 pitch 7680 (/4 1920)
>[  3491.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099e60]
>[  3491.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099e60] width 1920 pitch 7680 (/4 1920)
>[  3491.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3491.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d88c0]
>[  3491.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d88c0] width 1920 pitch 7680 (/4 1920)
>[  3491.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861a20]
>[  3491.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861a20] width 1920 pitch 7680 (/4 1920)
>[  3644.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6550]
>[  3644.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6550] width 1920 pitch 7680 (/4 1920)
>[  3644.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c22b0]
>[  3644.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c22b0] width 1920 pitch 7680 (/4 1920)
>[  3644.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bfe90]
>[  3644.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bfe90] width 1920 pitch 7680 (/4 1920)
>[  3644.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3310]
>[  3644.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3310] width 1920 pitch 7680 (/4 1920)
>[  3644.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c22b0]
>[  3644.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c22b0] width 1920 pitch 7680 (/4 1920)
>[  3644.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bfe90]
>[  3644.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bfe90] width 1920 pitch 7680 (/4 1920)
>[  3644.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bfe90]
>[  3644.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bfe90] width 1920 pitch 7680 (/4 1920)
>[  3644.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3310]
>[  3644.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3310] width 1920 pitch 7680 (/4 1920)
>[  3644.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3310]
>[  3644.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3310] width 1920 pitch 7680 (/4 1920)
>[  3644.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c22b0]
>[  3644.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c22b0] width 1920 pitch 7680 (/4 1920)
>[  3644.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c22b0]
>[  3644.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c22b0] width 1920 pitch 7680 (/4 1920)
>[  3644.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bfe90]
>[  3644.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bfe90] width 1920 pitch 7680 (/4 1920)
>[  3644.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bfe90]
>[  3644.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bfe90] width 1920 pitch 7680 (/4 1920)
>[  3644.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3310]
>[  3644.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3310] width 1920 pitch 7680 (/4 1920)
>[  3670.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5f50]
>[  3670.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5f50] width 1920 pitch 7680 (/4 1920)
>[  3670.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeda40]
>[  3670.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeda40] width 1920 pitch 7680 (/4 1920)
>[  3670.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b6a0]
>[  3670.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b6a0] width 1920 pitch 7680 (/4 1920)
>[  3670.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a000]
>[  3670.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a000] width 1920 pitch 7680 (/4 1920)
>[  3670.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87360]
>[  3670.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87360] width 1920 pitch 7680 (/4 1920)
>[  3670.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110350]
>[  3670.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110350] width 1920 pitch 7680 (/4 1920)
>[  3670.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3670.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3670.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3670.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129d30]
>[  3670.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129d30] width 1920 pitch 7680 (/4 1920)
>[  3695.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509a240]
>[  3695.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509a240] width 1920 pitch 7680 (/4 1920)
>[  3695.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509a690]
>[  3695.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509a690] width 1920 pitch 7680 (/4 1920)
>[  3695.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c08a0]
>[  3695.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c08a0] width 1920 pitch 7680 (/4 1920)
>[  3695.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1a50]
>[  3695.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1a50] width 1920 pitch 7680 (/4 1920)
>[  3695.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510e940]
>[  3695.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510e940] width 1920 pitch 7680 (/4 1920)
>[  3853.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3853.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3853.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3853.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3853.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3853.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3853.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3853.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3853.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3854.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3854.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3854.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3854.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3854.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3854.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3854.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3854.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3854.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3854.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3854.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3854.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3854.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3854.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3854.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3854.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3854.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3854.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3854.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3854.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3854.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e56b0]
>[  3854.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e56b0] width 1920 pitch 7680 (/4 1920)
>[  3854.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3854.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3854.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116550]
>[  3854.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116550] width 1920 pitch 7680 (/4 1920)
>[  3854.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3854.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[  3854.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[  3854.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087a00]
>[  3854.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087a00] width 1920 pitch 7680 (/4 1920)
>[  3854.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[  3854.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[  3854.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f369a0]
>[  3854.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f369a0] width 1920 pitch 7680 (/4 1920)
>[  3854.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fde70]
>[  3854.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fde70] width 1920 pitch 7680 (/4 1920)
>[  3854.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e56b0]
>[  3854.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e56b0] width 1920 pitch 7680 (/4 1920)
>[  3854.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3854.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3854.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3854.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3854.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[  3854.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[  3855.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3855.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3855.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3855.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3855.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3855.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3855.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3855.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3855.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e963a0]
>[  3855.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e963a0] width 1920 pitch 7680 (/4 1920)
>[  3855.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e963a0]
>[  3855.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e963a0] width 1920 pitch 7680 (/4 1920)
>[  3855.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3855.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3855.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e963a0]
>[  3855.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e963a0] width 1920 pitch 7680 (/4 1920)
>[  3855.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3855.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3856.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e963a0]
>[  3856.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e963a0] width 1920 pitch 7680 (/4 1920)
>[  3856.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[  3856.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[  3856.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3856.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3856.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3856.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3856.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3856.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3856.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3856.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3856.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3856.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3856.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3856.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3856.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3856.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3856.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3856.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3856.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3856.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3856.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3856.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3857.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3857.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3857.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3857.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3857.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3857.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3857.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3857.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3857.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3857.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3857.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3857.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3857.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3857.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3858.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3858.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3858.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f186e0]
>[  3858.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f186e0] width 1920 pitch 7680 (/4 1920)
>[  3858.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111aa0]
>[  3858.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111aa0] width 1920 pitch 7680 (/4 1920)
>[  3858.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edc9b0]
>[  3858.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edc9b0] width 1920 pitch 7680 (/4 1920)
>[  3866.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3866.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3866.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3866.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3866.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3866.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3866.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3866.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3866.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3866.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3866.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3866.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3866.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3866.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3866.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3866.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3866.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3866.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3867.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3867.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3867.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3867.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3867.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[  3867.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[  3867.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[  3867.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[  3868.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3868.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3868.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3868.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3868.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3868.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3868.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3868.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3868.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3868.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3868.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3868.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3868.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3868.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3868.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3868.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3868.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3868.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3868.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3868.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3869.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3869.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3869.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3869.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3869.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3869.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3869.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3869.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3870.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3870.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3870.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3870.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3870.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3870.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3870.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3870.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  3870.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d8b0]
>[  3870.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d8b0] width 1920 pitch 7680 (/4 1920)
>[  3870.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[  3870.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[  4111.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[  4111.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[  4111.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[  4111.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[  4689.998] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[  4689.998] (II) RADEON(0): Using hsync ranges from config file
>[  4689.998] (II) RADEON(0): Using vrefresh ranges from config file
>[  4689.998] (II) RADEON(0): Printing DDC gathered Modelines:
>[  4689.998] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[  4689.998] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[  4689.998] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[  4689.999] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[  4690.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb5a40]
>[  4690.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb5a40] width 1920 pitch 7680 (/4 1920)
>[  4690.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2829010]
>[  4690.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2829010] width 1920 pitch 7680 (/4 1920)
>[  4690.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2829010]
>[  4690.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2829010] width 1920 pitch 7680 (/4 1920)
>[  4690.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2829010]
>[  4690.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2829010] width 1920 pitch 7680 (/4 1920)
>[  4690.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2829040]
>[  4690.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2829040] width 1920 pitch 7680 (/4 1920)
>[  4690.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2866770]
>[  4690.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2866770] width 1920 pitch 7680 (/4 1920)
>[  4690.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4690.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4690.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4690.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4690.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4690.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4690.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4690.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c8c0]
>[  4691.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c8c0] width 1920 pitch 7680 (/4 1920)
>[  4691.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4691.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7060]
>[  4691.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7060] width 1920 pitch 7680 (/4 1920)
>[  4779.746] (II) RADEON(0): RADEONSaveScreen(2)
>[  4779.746] (II) RADEON(0): RADEONSaveScreen(0)
>[  5202.451] (II) RADEON(0): RADEONSaveScreen(1)
>[  5722.884] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[  5722.884] (II) RADEON(0): Using hsync ranges from config file
>[  5722.884] (II) RADEON(0): Using vrefresh ranges from config file
>[  5722.884] (II) RADEON(0): Printing DDC gathered Modelines:
>[  5722.884] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[  5722.884] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[  5722.884] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[  5812.743] (II) RADEON(0): RADEONSaveScreen(2)
>[  5812.743] (II) RADEON(0): RADEONSaveScreen(0)
>[ 40154.889] (II) RADEON(0): RADEONSaveScreen(1)
>[ 40167.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4043e70]
>[ 40167.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4043e70] width 1920 pitch 7680 (/4 1920)
>[ 40169.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4043e70]
>[ 40169.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4043e70] width 1920 pitch 7680 (/4 1920)
>[ 40169.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40169.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40169.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40169.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40169.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6af10]
>[ 40169.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6af10] width 1920 pitch 7680 (/4 1920)
>[ 40169.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40169.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40169.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40169.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40169.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6aec0]
>[ 40169.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6aec0] width 1920 pitch 7680 (/4 1920)
>[ 40169.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40169.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40169.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40169.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40169.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4043e70]
>[ 40170.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4043e70] width 1920 pitch 7680 (/4 1920)
>[ 40170.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40170.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40170.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40170.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40170.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40170.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40170.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957100]
>[ 40170.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957100] width 1920 pitch 7680 (/4 1920)
>[ 40170.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40170.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40170.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40170.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40170.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40170.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40171.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40171.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40172.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40172.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40172.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40172.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40172.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40172.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40172.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6ab50]
>[ 40172.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6ab50] width 1920 pitch 7680 (/4 1920)
>[ 40172.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40172.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40172.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40172.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40172.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40172.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40172.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40172.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40172.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40172.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40173.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40173.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40173.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40173.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40173.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40173.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40173.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40173.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40173.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40173.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40173.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40173.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40173.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40173.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40173.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40173.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40173.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40173.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40173.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40173.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40173.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40173.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40173.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40173.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40173.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40173.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40173.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40173.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40173.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40173.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40173.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40173.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40173.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40173.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40174.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40174.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40174.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40174.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40174.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40174.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40174.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40175.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40175.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40175.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40175.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40175.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40175.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40175.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40175.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40175.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40175.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40175.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40175.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40175.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40175.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40175.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40175.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40175.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40175.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40175.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40175.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40175.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40175.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40175.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40175.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40175.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40175.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40176.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40176.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40176.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40176.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40176.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40176.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40176.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40176.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40176.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40176.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40176.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40176.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40176.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40176.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40176.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40176.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40176.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40176.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40176.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40176.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40176.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40176.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40176.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40176.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40176.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40176.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40176.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40176.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40176.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40176.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40176.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40176.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40176.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40176.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40176.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40176.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40176.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40176.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40176.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40176.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40176.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40176.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40176.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40177.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40177.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40177.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40177.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40177.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40177.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40177.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40177.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40177.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40177.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40177.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40177.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40177.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40177.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40177.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40177.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40177.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40177.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40178.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40178.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40178.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40178.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40178.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40178.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40178.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40178.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40178.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40178.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40178.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40178.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40178.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40178.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40178.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40178.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40178.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40178.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40178.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40178.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40179.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40179.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40179.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 40179.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 40179.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40179.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40179.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40179.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40179.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40179.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40179.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40179.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40179.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40179.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40179.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40179.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40179.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40179.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40179.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287eec0]
>[ 40179.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287eec0] width 1920 pitch 7680 (/4 1920)
>[ 40179.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ebb0]
>[ 40179.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ebb0] width 1920 pitch 7680 (/4 1920)
>[ 40179.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 40179.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 40179.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40179.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40179.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40179.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40179.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40179.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40179.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40179.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40179.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40180.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40180.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40180.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40180.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8ca0]
>[ 40180.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8ca0] width 1920 pitch 7680 (/4 1920)
>[ 40180.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511cc90]
>[ 40180.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511cc90] width 1920 pitch 7680 (/4 1920)
>[ 40180.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40180.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40184.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40184.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40184.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40184.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40184.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 40184.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 40184.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40184.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40184.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 40184.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 40184.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40184.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40184.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 40184.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 40184.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40184.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40184.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 40184.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 40184.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 40184.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 40184.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 40184.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 40184.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 40184.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 40184.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b090]
>[ 40184.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b090] width 1920 pitch 7680 (/4 1920)
>[ 40528.616] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 40528.616] (II) RADEON(0): Using hsync ranges from config file
>[ 40528.616] (II) RADEON(0): Using vrefresh ranges from config file
>[ 40528.616] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 40528.616] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 40528.616] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 40528.616] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 40528.617] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 40618.750] (II) RADEON(0): RADEONSaveScreen(2)
>[ 40618.750] (II) RADEON(0): RADEONSaveScreen(0)
>[ 41211.482] (II) RADEON(0): RADEONSaveScreen(1)
>[ 41243.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 41243.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 41243.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 41243.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 41244.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41244.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41244.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d040]
>[ 41244.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d040] width 1920 pitch 7680 (/4 1920)
>[ 41244.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1dfd0]
>[ 41244.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1dfd0] width 1920 pitch 7680 (/4 1920)
>[ 41244.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef630]
>[ 41244.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef630] width 1920 pitch 7680 (/4 1920)
>[ 41244.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef630]
>[ 41245.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef630] width 1920 pitch 7680 (/4 1920)
>[ 41245.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41245.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41245.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d040]
>[ 41245.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d040] width 1920 pitch 7680 (/4 1920)
>[ 41245.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41245.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41245.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41245.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41245.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41245.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41245.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41245.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41245.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 41245.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 41245.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41245.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41245.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41245.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41245.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 41246.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 41246.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41246.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41246.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41246.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41246.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca760]
>[ 41246.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca760] width 1920 pitch 7680 (/4 1920)
>[ 41246.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 41246.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 41356.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 41356.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 41356.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41356.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41356.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 41356.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 41356.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 41356.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 41356.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41356.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41356.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 41356.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 41356.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1dfd0]
>[ 41356.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1dfd0] width 1920 pitch 7680 (/4 1920)
>[ 41356.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 41356.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 41356.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d040]
>[ 41356.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d040] width 1920 pitch 7680 (/4 1920)
>[ 41356.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 41356.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 41357.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41357.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41357.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 41357.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 41357.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d040]
>[ 41357.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d040] width 1920 pitch 7680 (/4 1920)
>[ 41357.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41357.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41357.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 41357.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 41358.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41358.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41358.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2832900]
>[ 41358.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2832900] width 1920 pitch 7680 (/4 1920)
>[ 41358.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4870]
>[ 41358.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4870] width 1920 pitch 7680 (/4 1920)
>[ 41358.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 41358.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 41358.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41358.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41358.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 41358.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 41358.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 41358.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 41358.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eba390]
>[ 41358.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eba390] width 1920 pitch 7680 (/4 1920)
>[ 41358.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 41358.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 41359.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 41359.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 41359.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41359.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41359.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 41359.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 41359.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 41359.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 41359.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a488b0]
>[ 41359.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a488b0] width 1920 pitch 7680 (/4 1920)
>[ 41359.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d040]
>[ 41359.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d040] width 1920 pitch 7680 (/4 1920)
>[ 41359.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41359.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41359.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea24e0]
>[ 41359.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea24e0] width 1920 pitch 7680 (/4 1920)
>[ 41359.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 41359.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 41359.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f161d0]
>[ 41359.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f161d0] width 1920 pitch 7680 (/4 1920)
>[ 41359.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4870]
>[ 41359.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4870] width 1920 pitch 7680 (/4 1920)
>[ 41486.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512bef0]
>[ 41486.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512bef0] width 1920 pitch 7680 (/4 1920)
>[ 41486.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41486.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41486.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56c20]
>[ 41486.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56c20] width 1920 pitch 7680 (/4 1920)
>[ 41486.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 41486.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 41486.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511a6a0]
>[ 41486.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511a6a0] width 1920 pitch 7680 (/4 1920)
>[ 41486.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[ 41486.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[ 41486.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512bef0]
>[ 41486.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512bef0] width 1920 pitch 7680 (/4 1920)
>[ 41486.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41486.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41486.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56c20]
>[ 41486.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56c20] width 1920 pitch 7680 (/4 1920)
>[ 41486.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 41486.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 41486.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511a6a0]
>[ 41486.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511a6a0] width 1920 pitch 7680 (/4 1920)
>[ 41486.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[ 41486.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[ 41486.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512bef0]
>[ 41486.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512bef0] width 1920 pitch 7680 (/4 1920)
>[ 41486.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41486.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41486.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56c20]
>[ 41486.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56c20] width 1920 pitch 7680 (/4 1920)
>[ 41486.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 41486.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 41486.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 41486.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 41533.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea90a0]
>[ 41533.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea90a0] width 1920 pitch 7680 (/4 1920)
>[ 41533.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ecf0]
>[ 41533.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ecf0] width 1920 pitch 7680 (/4 1920)
>[ 41533.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea270]
>[ 41533.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea270] width 1920 pitch 7680 (/4 1920)
>[ 41533.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 41533.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 41533.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eabd50]
>[ 41533.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eabd50] width 1920 pitch 7680 (/4 1920)
>[ 41533.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f2880]
>[ 41533.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f2880] width 1920 pitch 7680 (/4 1920)
>[ 41533.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 41533.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 41533.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ecf0]
>[ 41533.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ecf0] width 1920 pitch 7680 (/4 1920)
>[ 41533.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 41533.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 41534.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea90a0]
>[ 41534.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea90a0] width 1920 pitch 7680 (/4 1920)
>[ 41534.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f2880]
>[ 41534.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f2880] width 1920 pitch 7680 (/4 1920)
>[ 41534.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 41534.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 41538.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 41538.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 41539.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea270]
>[ 41539.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea270] width 1920 pitch 7680 (/4 1920)
>[ 41539.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95760]
>[ 41539.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95760] width 1920 pitch 7680 (/4 1920)
>[ 41539.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 41539.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 41539.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eabd50]
>[ 41539.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eabd50] width 1920 pitch 7680 (/4 1920)
>[ 41539.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 41539.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 41539.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f2880]
>[ 41539.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f2880] width 1920 pitch 7680 (/4 1920)
>[ 41539.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea90a0]
>[ 41539.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea90a0] width 1920 pitch 7680 (/4 1920)
>[ 41539.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea270]
>[ 41539.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea270] width 1920 pitch 7680 (/4 1920)
>[ 41539.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ecf0]
>[ 41539.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ecf0] width 1920 pitch 7680 (/4 1920)
>[ 41539.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 41539.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 41539.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f2880]
>[ 41539.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f2880] width 1920 pitch 7680 (/4 1920)
>[ 41569.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41569.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41570.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d63c0]
>[ 41570.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d63c0] width 1920 pitch 7680 (/4 1920)
>[ 41570.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16360]
>[ 41570.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16360] width 1920 pitch 7680 (/4 1920)
>[ 41570.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd620]
>[ 41570.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd620] width 1920 pitch 7680 (/4 1920)
>[ 41570.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41570.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41572.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41572.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41572.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41572.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41572.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41572.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41572.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9c0]
>[ 41572.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9c0] width 1920 pitch 7680 (/4 1920)
>[ 41572.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 41572.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 41572.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41572.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41572.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41572.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41572.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 41572.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 41572.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea6dd0]
>[ 41572.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea6dd0] width 1920 pitch 7680 (/4 1920)
>[ 41572.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f140]
>[ 41572.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f140] width 1920 pitch 7680 (/4 1920)
>[ 41572.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 41572.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 41573.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b150]
>[ 41573.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b150] width 1920 pitch 7680 (/4 1920)
>[ 41573.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41573.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41573.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9e0d0]
>[ 41573.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9e0d0] width 1920 pitch 7680 (/4 1920)
>[ 41573.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41573.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41574.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41574.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41574.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4271330]
>[ 41574.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4271330] width 1920 pitch 7680 (/4 1920)
>[ 41574.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41574.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41574.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41574.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41574.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41574.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41574.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41574.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41574.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41574.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41574.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41574.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41574.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41574.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41574.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41574.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41574.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41574.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41574.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41574.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41575.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41575.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41575.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41575.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41575.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41575.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41575.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41575.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41575.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41575.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41575.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41575.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41575.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41575.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41575.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f870]
>[ 41575.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f870] width 1920 pitch 7680 (/4 1920)
>[ 41575.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41575.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41723.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4266490]
>[ 41723.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4266490] width 1920 pitch 7680 (/4 1920)
>[ 41723.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28277e0]
>[ 41723.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28277e0] width 1920 pitch 7680 (/4 1920)
>[ 41723.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2851580]
>[ 41723.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2851580] width 1920 pitch 7680 (/4 1920)
>[ 41723.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f38c0]
>[ 41723.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f38c0] width 1920 pitch 7680 (/4 1920)
>[ 41723.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70880]
>[ 41723.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70880] width 1920 pitch 7680 (/4 1920)
>[ 41723.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5134f60]
>[ 41723.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5134f60] width 1920 pitch 7680 (/4 1920)
>[ 41723.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ce1b0]
>[ 41723.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ce1b0] width 1920 pitch 7680 (/4 1920)
>[ 41723.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da1b30]
>[ 41723.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da1b30] width 1920 pitch 7680 (/4 1920)
>[ 41723.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51198a0]
>[ 41723.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51198a0] width 1920 pitch 7680 (/4 1920)
>[ 41724.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[ 41724.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[ 41724.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035da0]
>[ 41724.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035da0] width 1920 pitch 7680 (/4 1920)
>[ 41724.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7ea30]
>[ 41724.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7ea30] width 1920 pitch 7680 (/4 1920)
>[ 41724.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28277e0]
>[ 41724.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28277e0] width 1920 pitch 7680 (/4 1920)
>[ 41725.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2851580]
>[ 41725.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2851580] width 1920 pitch 7680 (/4 1920)
>[ 41725.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb66d0]
>[ 41725.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb66d0] width 1920 pitch 7680 (/4 1920)
>[ 41725.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96960]
>[ 41726.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96960] width 1920 pitch 7680 (/4 1920)
>[ 41726.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839140]
>[ 41726.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839140] width 1920 pitch 7680 (/4 1920)
>[ 41726.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[ 41726.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[ 41726.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41726.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41726.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a17780]
>[ 41726.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a17780] width 1920 pitch 7680 (/4 1920)
>[ 41726.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035da0]
>[ 41726.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035da0] width 1920 pitch 7680 (/4 1920)
>[ 41726.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0040]
>[ 41726.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0040] width 1920 pitch 7680 (/4 1920)
>[ 41726.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df520]
>[ 41726.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df520] width 1920 pitch 7680 (/4 1920)
>[ 41726.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51198a0]
>[ 41726.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51198a0] width 1920 pitch 7680 (/4 1920)
>[ 41726.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb66d0]
>[ 41726.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb66d0] width 1920 pitch 7680 (/4 1920)
>[ 41726.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96960]
>[ 41726.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96960] width 1920 pitch 7680 (/4 1920)
>[ 41726.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839140]
>[ 41726.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839140] width 1920 pitch 7680 (/4 1920)
>[ 41726.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bee70]
>[ 41727.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bee70] width 1920 pitch 7680 (/4 1920)
>[ 41727.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3957400]
>[ 41727.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3957400] width 1920 pitch 7680 (/4 1920)
>[ 41727.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a17780]
>[ 41727.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a17780] width 1920 pitch 7680 (/4 1920)
>[ 41727.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035da0]
>[ 41727.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035da0] width 1920 pitch 7680 (/4 1920)
>[ 41727.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a17780]
>[ 41727.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a17780] width 1920 pitch 7680 (/4 1920)
>[ 41727.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff3ff0]
>[ 41727.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff3ff0] width 1920 pitch 7680 (/4 1920)
>[ 41727.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb66d0]
>[ 41727.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb66d0] width 1920 pitch 7680 (/4 1920)
>[ 41727.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839140]
>[ 41727.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839140] width 1920 pitch 7680 (/4 1920)
>[ 41747.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41747.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41747.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41747.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41747.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41751.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41751.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41751.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41751.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41751.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41751.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41751.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41751.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41751.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41751.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41751.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41751.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41751.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41751.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41751.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff42e0]
>[ 41751.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff42e0] width 1920 pitch 7680 (/4 1920)
>[ 41751.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9cc60]
>[ 41751.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9cc60] width 1920 pitch 7680 (/4 1920)
>[ 41751.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41751.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41751.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41751.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41751.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff42e0]
>[ 41752.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff42e0] width 1920 pitch 7680 (/4 1920)
>[ 41752.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41752.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41752.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41752.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41753.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff42e0]
>[ 41753.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff42e0] width 1920 pitch 7680 (/4 1920)
>[ 41753.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41753.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41753.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41753.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41753.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9cc60]
>[ 41753.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9cc60] width 1920 pitch 7680 (/4 1920)
>[ 41753.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41753.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41753.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403cd30]
>[ 41753.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403cd30] width 1920 pitch 7680 (/4 1920)
>[ 41753.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e629a0]
>[ 41753.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e629a0] width 1920 pitch 7680 (/4 1920)
>[ 41753.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff42e0]
>[ 41753.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff42e0] width 1920 pitch 7680 (/4 1920)
>[ 41753.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284cd40]
>[ 41753.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284cd40] width 1920 pitch 7680 (/4 1920)
>[ 41753.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bcb0]
>[ 41753.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bcb0] width 1920 pitch 7680 (/4 1920)
>[ 41753.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41753.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41753.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9cc60]
>[ 41753.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9cc60] width 1920 pitch 7680 (/4 1920)
>[ 41753.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff42e0]
>[ 41753.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff42e0] width 1920 pitch 7680 (/4 1920)
>[ 41753.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403cd30]
>[ 41753.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403cd30] width 1920 pitch 7680 (/4 1920)
>[ 41853.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82210]
>[ 41853.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82210] width 1920 pitch 7680 (/4 1920)
>[ 41853.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41853.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41853.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82210]
>[ 41853.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82210] width 1920 pitch 7680 (/4 1920)
>[ 41853.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41854.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41854.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f793e0]
>[ 41854.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f793e0] width 1920 pitch 7680 (/4 1920)
>[ 41854.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41854.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41854.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f793e0]
>[ 41854.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f793e0] width 1920 pitch 7680 (/4 1920)
>[ 41854.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41854.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41854.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41854.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41854.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41854.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41854.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41854.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41854.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41854.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41855.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc4700]
>[ 41855.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc4700] width 1920 pitch 7680 (/4 1920)
>[ 41855.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41855.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41855.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41855.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41855.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41855.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41855.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41855.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41855.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41856.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41856.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41856.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41856.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41910.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41910.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41910.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41910.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41910.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41910.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41910.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41910.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41910.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41910.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41910.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41911.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41911.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41911.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41911.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41911.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41911.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41911.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41911.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41911.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41911.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41911.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41911.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41911.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41911.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41911.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41911.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41911.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41911.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41911.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41911.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41911.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41911.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41911.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41912.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41912.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41912.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41912.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41912.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41912.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41912.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 41912.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 41912.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 41912.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 41912.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7450]
>[ 41912.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7450] width 1920 pitch 7680 (/4 1920)
>[ 41912.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd620]
>[ 41913.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd620] width 1920 pitch 7680 (/4 1920)
>[ 41913.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41913.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41913.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41913.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41913.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 41913.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 41913.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41913.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41913.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41913.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41913.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41913.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41913.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41913.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41913.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 41913.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 41913.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86bb0]
>[ 41913.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86bb0] width 1920 pitch 7680 (/4 1920)
>[ 41913.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41913.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41913.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8330]
>[ 41913.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8330] width 1920 pitch 7680 (/4 1920)
>[ 41913.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 41913.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 41988.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 41988.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 41988.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41988.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41988.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41988.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41988.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41988.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41988.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86bb0]
>[ 41988.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86bb0] width 1920 pitch 7680 (/4 1920)
>[ 41988.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41988.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41988.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8330]
>[ 41988.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8330] width 1920 pitch 7680 (/4 1920)
>[ 41988.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41988.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41988.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 41988.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 41988.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 41988.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 41988.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9e0d0]
>[ 41988.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9e0d0] width 1920 pitch 7680 (/4 1920)
>[ 41988.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41988.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41988.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41988.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41988.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41988.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41988.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 41988.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 41988.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea6dd0]
>[ 41988.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea6dd0] width 1920 pitch 7680 (/4 1920)
>[ 41988.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41988.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41988.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41988.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41988.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9c0]
>[ 41988.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9c0] width 1920 pitch 7680 (/4 1920)
>[ 41988.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 41988.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 41988.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41988.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41989.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41989.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41989.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41989.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41989.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41989.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41989.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 41989.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 41989.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 41989.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 41989.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9e0d0]
>[ 41989.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9e0d0] width 1920 pitch 7680 (/4 1920)
>[ 41989.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41989.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41989.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41989.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41989.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41989.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41989.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 41989.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 41989.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea6dd0]
>[ 41989.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea6dd0] width 1920 pitch 7680 (/4 1920)
>[ 41989.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41989.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41989.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41989.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41989.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9c0]
>[ 41989.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9c0] width 1920 pitch 7680 (/4 1920)
>[ 41989.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 41989.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 41989.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41989.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41989.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41989.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41989.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41989.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41989.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41989.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41989.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 41989.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 41989.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 41989.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 41989.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9e0d0]
>[ 41989.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9e0d0] width 1920 pitch 7680 (/4 1920)
>[ 41989.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41989.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41989.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41989.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41989.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41989.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41989.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 41989.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 41989.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea6dd0]
>[ 41989.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea6dd0] width 1920 pitch 7680 (/4 1920)
>[ 41989.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41989.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41989.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41989.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41989.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9c0]
>[ 41989.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9c0] width 1920 pitch 7680 (/4 1920)
>[ 41990.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 41990.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 41990.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41990.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41990.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41990.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41990.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e823c0]
>[ 41990.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e823c0] width 1920 pitch 7680 (/4 1920)
>[ 41990.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41990.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41990.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41990.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41991.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41991.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41991.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41991.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb9d0]
>[ 41991.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb9d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb840]
>[ 41991.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb840] width 1920 pitch 7680 (/4 1920)
>[ 41991.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41991.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41991.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f140]
>[ 41991.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f140] width 1920 pitch 7680 (/4 1920)
>[ 41991.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41991.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41991.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f140]
>[ 41991.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f140] width 1920 pitch 7680 (/4 1920)
>[ 41991.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 41991.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 41991.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd620]
>[ 41991.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd620] width 1920 pitch 7680 (/4 1920)
>[ 41991.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41991.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41991.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8330]
>[ 41991.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8330] width 1920 pitch 7680 (/4 1920)
>[ 41991.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 41991.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 41991.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 41991.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 41991.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d7150]
>[ 41991.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d7150] width 1920 pitch 7680 (/4 1920)
>[ 41991.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7450]
>[ 41991.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7450] width 1920 pitch 7680 (/4 1920)
>[ 41991.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 41991.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 41991.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 41991.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 41991.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 41991.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 41991.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41991.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41991.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16360]
>[ 41991.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16360] width 1920 pitch 7680 (/4 1920)
>[ 41991.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41991.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41991.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41991.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41991.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3935050]
>[ 41991.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3935050] width 1920 pitch 7680 (/4 1920)
>[ 41991.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41991.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41991.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41991.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41991.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41991.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41991.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41991.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41992.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd620]
>[ 41992.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd620] width 1920 pitch 7680 (/4 1920)
>[ 41992.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 41992.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 41992.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41992.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41992.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098110]
>[ 41992.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098110] width 1920 pitch 7680 (/4 1920)
>[ 41992.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea2620]
>[ 41992.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea2620] width 1920 pitch 7680 (/4 1920)
>[ 41992.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41992.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41992.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16360]
>[ 41992.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16360] width 1920 pitch 7680 (/4 1920)
>[ 41992.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 41992.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 41992.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 41992.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 41992.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093a60]
>[ 41992.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093a60] width 1920 pitch 7680 (/4 1920)
>[ 41992.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 41992.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 41992.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 41992.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 41993.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e9a0]
>[ 41993.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e9a0] width 1920 pitch 7680 (/4 1920)
>[ 41993.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5b80]
>[ 41993.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5b80] width 1920 pitch 7680 (/4 1920)
>[ 41993.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 41993.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 41993.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 41993.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 41994.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 41994.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 41996.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41996.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41996.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41996.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41996.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41996.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41996.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41996.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41996.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41997.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41997.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41997.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41997.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[ 41997.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[ 41997.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41997.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41997.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41997.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41997.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41997.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41998.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41998.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41998.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41998.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41998.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41998.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41998.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389f530]
>[ 41998.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389f530] width 1920 pitch 7680 (/4 1920)
>[ 41998.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41998.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41998.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fcb60]
>[ 41998.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fcb60] width 1920 pitch 7680 (/4 1920)
>[ 41998.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41998.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 41998.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90df0]
>[ 41998.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90df0] width 1920 pitch 7680 (/4 1920)
>[ 41998.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e2820]
>[ 41998.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e2820] width 1920 pitch 7680 (/4 1920)
>[ 41998.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e8c40]
>[ 41998.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e8c40] width 1920 pitch 7680 (/4 1920)
>[ 42016.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952a30]
>[ 42016.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952a30] width 1920 pitch 7680 (/4 1920)
>[ 42018.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952a30]
>[ 42018.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952a30] width 1920 pitch 7680 (/4 1920)
>[ 42018.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952a30]
>[ 42018.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952a30] width 1920 pitch 7680 (/4 1920)
>[ 42018.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952a30]
>[ 42018.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952a30] width 1920 pitch 7680 (/4 1920)
>[ 42018.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952a30]
>[ 42018.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952a30] width 1920 pitch 7680 (/4 1920)
>[ 42028.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42028.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42028.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42028.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42028.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42029.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42029.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42030.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42030.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42030.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42030.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42031.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42031.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42031.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508b250]
>[ 42031.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508b250] width 1920 pitch 7680 (/4 1920)
>[ 42031.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853200]
>[ 42031.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853200] width 1920 pitch 7680 (/4 1920)
>[ 42042.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e38f0]
>[ 42042.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e38f0] width 1920 pitch 7680 (/4 1920)
>[ 42044.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3860]
>[ 42044.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3860] width 1920 pitch 7680 (/4 1920)
>[ 42044.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106b20]
>[ 42044.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106b20] width 1920 pitch 7680 (/4 1920)
>[ 42044.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106b20]
>[ 42044.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106b20] width 1920 pitch 7680 (/4 1920)
>[ 42044.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6e70]
>[ 42044.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6e70] width 1920 pitch 7680 (/4 1920)
>[ 42044.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080d50]
>[ 42044.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080d50] width 1920 pitch 7680 (/4 1920)
>[ 42044.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15370]
>[ 42044.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15370] width 1920 pitch 7680 (/4 1920)
>[ 42044.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106b20]
>[ 42044.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106b20] width 1920 pitch 7680 (/4 1920)
>[ 42044.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da7fe0]
>[ 42044.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da7fe0] width 1920 pitch 7680 (/4 1920)
>[ 42044.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42044.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42044.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42339.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42339.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42339.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42339.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42339.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42339.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42339.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42339.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42339.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42339.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42339.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42339.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42339.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42339.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42339.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42339.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42339.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42339.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42339.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42339.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42340.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42340.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42340.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42340.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42340.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42340.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42340.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42340.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42340.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42340.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42340.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42340.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42340.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42340.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42340.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42340.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42340.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42340.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42340.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42340.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42340.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42340.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42340.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42340.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42340.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42340.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42341.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42341.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42341.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42341.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42341.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42341.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42341.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42341.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42343.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42343.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42343.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42343.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42343.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42343.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42343.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42343.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42343.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42343.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42344.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ffc0]
>[ 42344.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ffc0] width 1920 pitch 7680 (/4 1920)
>[ 42344.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3010]
>[ 42344.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3010] width 1920 pitch 7680 (/4 1920)
>[ 42344.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fccf0]
>[ 42344.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fccf0] width 1920 pitch 7680 (/4 1920)
>[ 42344.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39374e0]
>[ 42344.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39374e0] width 1920 pitch 7680 (/4 1920)
>[ 42351.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b94e0]
>[ 42351.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b94e0] width 1920 pitch 7680 (/4 1920)
>[ 42352.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835dc0]
>[ 42352.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835dc0] width 1920 pitch 7680 (/4 1920)
>[ 42352.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cdf90]
>[ 42352.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cdf90] width 1920 pitch 7680 (/4 1920)
>[ 42352.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e858b0]
>[ 42352.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e858b0] width 1920 pitch 7680 (/4 1920)
>[ 42352.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cc580]
>[ 42352.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cc580] width 1920 pitch 7680 (/4 1920)
>[ 42354.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6b10]
>[ 42354.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6b10] width 1920 pitch 7680 (/4 1920)
>[ 42354.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42354.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6b10]
>[ 42371.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6b10] width 1920 pitch 7680 (/4 1920)
>[ 42371.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42371.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42371.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42372.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42372.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42372.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42372.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42372.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42372.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42519.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cd270]
>[ 42519.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cd270] width 1920 pitch 7680 (/4 1920)
>[ 42519.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3570]
>[ 42519.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3570] width 1920 pitch 7680 (/4 1920)
>[ 42519.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cd270]
>[ 42519.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cd270] width 1920 pitch 7680 (/4 1920)
>[ 42519.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3570]
>[ 42519.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3570] width 1920 pitch 7680 (/4 1920)
>[ 42519.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275b80]
>[ 42519.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275b80] width 1920 pitch 7680 (/4 1920)
>[ 42521.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da35b0]
>[ 42521.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da35b0] width 1920 pitch 7680 (/4 1920)
>[ 42521.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da3550]
>[ 42521.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da3550] width 1920 pitch 7680 (/4 1920)
>[ 42521.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cc430]
>[ 42521.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cc430] width 1920 pitch 7680 (/4 1920)
>[ 42521.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3680]
>[ 42521.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3680] width 1920 pitch 7680 (/4 1920)
>[ 42521.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cc430]
>[ 42521.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cc430] width 1920 pitch 7680 (/4 1920)
>[ 42521.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3680]
>[ 42521.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3680] width 1920 pitch 7680 (/4 1920)
>[ 42521.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cc430]
>[ 42521.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cc430] width 1920 pitch 7680 (/4 1920)
>[ 42521.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3630]
>[ 42521.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3630] width 1920 pitch 7680 (/4 1920)
>[ 42522.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3630]
>[ 42522.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3630] width 1920 pitch 7680 (/4 1920)
>[ 42522.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da35f0]
>[ 42522.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da35f0] width 1920 pitch 7680 (/4 1920)
>[ 42522.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3630]
>[ 42522.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3630] width 1920 pitch 7680 (/4 1920)
>[ 42522.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42522.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42522.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42522.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42522.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42523.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42523.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42523.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42523.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42523.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42523.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42523.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42523.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42523.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42523.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42523.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42523.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42523.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42523.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42523.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42523.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42523.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42523.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42523.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42523.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42523.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42523.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42523.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42523.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42523.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42523.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42523.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42538.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42538.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42538.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42538.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42538.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42538.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42538.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42538.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42538.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42538.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42538.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef15f0]
>[ 42538.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef15f0] width 1920 pitch 7680 (/4 1920)
>[ 42538.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42538.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42538.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 42538.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 42538.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 42538.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 42538.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 42538.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 42539.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a150]
>[ 42539.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a150] width 1920 pitch 7680 (/4 1920)
>[ 42539.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42539.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42540.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42540.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42540.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42540.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42540.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbb20]
>[ 42540.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbb20] width 1920 pitch 7680 (/4 1920)
>[ 42540.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42540.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42540.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbb20]
>[ 42540.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbb20] width 1920 pitch 7680 (/4 1920)
>[ 42540.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42540.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42540.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbb20]
>[ 42540.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbb20] width 1920 pitch 7680 (/4 1920)
>[ 42541.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42541.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42541.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42541.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42543.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b327f0]
>[ 42543.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b327f0] width 1920 pitch 7680 (/4 1920)
>[ 42544.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b327f0]
>[ 42544.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b327f0] width 1920 pitch 7680 (/4 1920)
>[ 42544.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b327f0]
>[ 42544.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b327f0] width 1920 pitch 7680 (/4 1920)
>[ 42544.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42544.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42544.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee5a60]
>[ 42544.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee5a60] width 1920 pitch 7680 (/4 1920)
>[ 42544.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b327f0]
>[ 42544.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b327f0] width 1920 pitch 7680 (/4 1920)
>[ 42544.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42544.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42544.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee5a60]
>[ 42544.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee5a60] width 1920 pitch 7680 (/4 1920)
>[ 42555.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee5a60]
>[ 42555.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee5a60] width 1920 pitch 7680 (/4 1920)
>[ 42571.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca7f0]
>[ 42571.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca7f0] width 1920 pitch 7680 (/4 1920)
>[ 42576.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca980]
>[ 42576.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca980] width 1920 pitch 7680 (/4 1920)
>[ 42576.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42576.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42576.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca980]
>[ 42576.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca980] width 1920 pitch 7680 (/4 1920)
>[ 42576.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42576.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42576.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca980]
>[ 42576.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca980] width 1920 pitch 7680 (/4 1920)
>[ 42576.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42576.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42576.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42576.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42576.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebab0]
>[ 42576.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebab0] width 1920 pitch 7680 (/4 1920)
>[ 42576.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf11b0]
>[ 42576.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf11b0] width 1920 pitch 7680 (/4 1920)
>[ 42576.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca980]
>[ 42576.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca980] width 1920 pitch 7680 (/4 1920)
>[ 42576.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42576.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42576.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca980]
>[ 42577.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca980] width 1920 pitch 7680 (/4 1920)
>[ 42577.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0030]
>[ 42577.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0030] width 1920 pitch 7680 (/4 1920)
>[ 42619.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebab0]
>[ 42619.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebab0] width 1920 pitch 7680 (/4 1920)
>[ 42619.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ceff60]
>[ 42619.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ceff60] width 1920 pitch 7680 (/4 1920)
>[ 42619.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c57f0]
>[ 42619.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c57f0] width 1920 pitch 7680 (/4 1920)
>[ 42619.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c57f0]
>[ 42619.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c57f0] width 1920 pitch 7680 (/4 1920)
>[ 42619.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c57f0]
>[ 42619.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c57f0] width 1920 pitch 7680 (/4 1920)
>[ 42619.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c57f0]
>[ 42619.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c57f0] width 1920 pitch 7680 (/4 1920)
>[ 42619.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264850]
>[ 42619.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264850] width 1920 pitch 7680 (/4 1920)
>[ 42619.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca3c0]
>[ 42619.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca3c0] width 1920 pitch 7680 (/4 1920)
>[ 42619.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c57f0]
>[ 42619.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c57f0] width 1920 pitch 7680 (/4 1920)
>[ 42626.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf02b0]
>[ 42626.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf02b0] width 1920 pitch 7680 (/4 1920)
>[ 42626.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6100]
>[ 42626.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6100] width 1920 pitch 7680 (/4 1920)
>[ 42626.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264970]
>[ 42626.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264970] width 1920 pitch 7680 (/4 1920)
>[ 42626.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264970]
>[ 42626.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264970] width 1920 pitch 7680 (/4 1920)
>[ 42626.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6100]
>[ 42626.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6100] width 1920 pitch 7680 (/4 1920)
>[ 42626.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec9ee0]
>[ 42626.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec9ee0] width 1920 pitch 7680 (/4 1920)
>[ 42626.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec9ee0]
>[ 42626.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec9ee0] width 1920 pitch 7680 (/4 1920)
>[ 42626.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da3320]
>[ 42626.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da3320] width 1920 pitch 7680 (/4 1920)
>[ 42626.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42626.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bfb0]
>[ 42626.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bfb0] width 1920 pitch 7680 (/4 1920)
>[ 42626.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807d0]
>[ 42626.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807d0] width 1920 pitch 7680 (/4 1920)
>[ 42644.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42644.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42644.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42645.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42645.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42645.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42645.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42645.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42645.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42645.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42645.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42645.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42646.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42646.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42646.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42646.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42646.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42647.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42647.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42647.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42648.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42648.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42648.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42648.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42649.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefea0]
>[ 42649.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefea0] width 1920 pitch 7680 (/4 1920)
>[ 42649.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403b010]
>[ 42649.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403b010] width 1920 pitch 7680 (/4 1920)
>[ 42649.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42649.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42649.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd3e0]
>[ 42649.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd3e0] width 1920 pitch 7680 (/4 1920)
>[ 42649.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42649.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42650.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd230]
>[ 42650.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd230] width 1920 pitch 7680 (/4 1920)
>[ 42650.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42650.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42650.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bd40]
>[ 42650.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bd40] width 1920 pitch 7680 (/4 1920)
>[ 42650.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5f80]
>[ 42650.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5f80] width 1920 pitch 7680 (/4 1920)
>[ 42650.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91f10]
>[ 42650.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91f10] width 1920 pitch 7680 (/4 1920)
>[ 42650.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42650.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42650.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94c40]
>[ 42650.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94c40] width 1920 pitch 7680 (/4 1920)
>[ 42650.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42650.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd5e0]
>[ 42650.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd5e0] width 1920 pitch 7680 (/4 1920)
>[ 42650.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90d10]
>[ 42650.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90d10] width 1920 pitch 7680 (/4 1920)
>[ 42650.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42650.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94ba0]
>[ 42650.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94ba0] width 1920 pitch 7680 (/4 1920)
>[ 42650.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42650.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94ba0]
>[ 42650.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94ba0] width 1920 pitch 7680 (/4 1920)
>[ 42650.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7dc90]
>[ 42650.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7dc90] width 1920 pitch 7680 (/4 1920)
>[ 42655.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873610]
>[ 42655.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873610] width 1920 pitch 7680 (/4 1920)
>[ 42655.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97b90]
>[ 42655.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97b90] width 1920 pitch 7680 (/4 1920)
>[ 42655.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea41c0]
>[ 42655.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea41c0] width 1920 pitch 7680 (/4 1920)
>[ 42655.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2c50]
>[ 42655.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2c50] width 1920 pitch 7680 (/4 1920)
>[ 42655.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3951d50]
>[ 42655.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3951d50] width 1920 pitch 7680 (/4 1920)
>[ 42655.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2c50]
>[ 42655.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2c50] width 1920 pitch 7680 (/4 1920)
>[ 42655.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3951d50]
>[ 42655.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3951d50] width 1920 pitch 7680 (/4 1920)
>[ 42655.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2c50]
>[ 42655.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2c50] width 1920 pitch 7680 (/4 1920)
>[ 42655.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3951d50]
>[ 42655.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3951d50] width 1920 pitch 7680 (/4 1920)
>[ 42655.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97b90]
>[ 42655.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97b90] width 1920 pitch 7680 (/4 1920)
>[ 42655.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2c50]
>[ 42655.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2c50] width 1920 pitch 7680 (/4 1920)
>[ 42655.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952180]
>[ 42655.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952180] width 1920 pitch 7680 (/4 1920)
>[ 42655.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2c50]
>[ 42655.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2c50] width 1920 pitch 7680 (/4 1920)
>[ 42655.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3952180]
>[ 42656.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3952180] width 1920 pitch 7680 (/4 1920)
>[ 42656.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ab40]
>[ 42656.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ab40] width 1920 pitch 7680 (/4 1920)
>[ 42656.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ab40]
>[ 42656.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ab40] width 1920 pitch 7680 (/4 1920)
>[ 42656.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42656.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42656.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953700]
>[ 42657.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953700] width 1920 pitch 7680 (/4 1920)
>[ 42657.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953700]
>[ 42657.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953700] width 1920 pitch 7680 (/4 1920)
>[ 42657.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953700]
>[ 42657.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953700] width 1920 pitch 7680 (/4 1920)
>[ 42657.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953700]
>[ 42657.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953700] width 1920 pitch 7680 (/4 1920)
>[ 42657.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953700]
>[ 42657.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953700] width 1920 pitch 7680 (/4 1920)
>[ 42657.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f939d0]
>[ 42657.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f939d0] width 1920 pitch 7680 (/4 1920)
>[ 42657.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42657.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93110]
>[ 42657.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93110] width 1920 pitch 7680 (/4 1920)
>[ 42657.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39539a0]
>[ 42657.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39539a0] width 1920 pitch 7680 (/4 1920)
>[ 42664.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b2c0]
>[ 42664.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b2c0] width 1920 pitch 7680 (/4 1920)
>[ 42664.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c160]
>[ 42664.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c160] width 1920 pitch 7680 (/4 1920)
>[ 42664.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42664.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42664.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88650]
>[ 42664.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88650] width 1920 pitch 7680 (/4 1920)
>[ 42664.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd5e0]
>[ 42664.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd5e0] width 1920 pitch 7680 (/4 1920)
>[ 42664.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394b2c0]
>[ 42664.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394b2c0] width 1920 pitch 7680 (/4 1920)
>[ 42664.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42664.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42664.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c160]
>[ 42664.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c160] width 1920 pitch 7680 (/4 1920)
>[ 42664.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70670]
>[ 42664.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70670] width 1920 pitch 7680 (/4 1920)
>[ 42664.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd5e0]
>[ 42664.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd5e0] width 1920 pitch 7680 (/4 1920)
>[ 42664.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42664.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42665.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[ 42665.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[ 42677.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfeb00]
>[ 42677.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfeb00] width 1920 pitch 7680 (/4 1920)
>[ 42678.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42678.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42678.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42678.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42678.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42678.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42678.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42679.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42679.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42679.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42679.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42679.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42686.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90280]
>[ 42686.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90280] width 1920 pitch 7680 (/4 1920)
>[ 42686.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42686.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42686.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42686.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42686.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42686.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42686.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f33950]
>[ 42686.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f33950] width 1920 pitch 7680 (/4 1920)
>[ 42686.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42686.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42686.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42686.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42686.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42686.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42686.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42686.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42686.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59020]
>[ 42686.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59020] width 1920 pitch 7680 (/4 1920)
>[ 42686.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5ac0]
>[ 42686.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5ac0] width 1920 pitch 7680 (/4 1920)
>[ 42686.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92680]
>[ 42686.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92680] width 1920 pitch 7680 (/4 1920)
>[ 42690.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3bf0]
>[ 42690.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3bf0] width 1920 pitch 7680 (/4 1920)
>[ 42690.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3bf0]
>[ 42690.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3bf0] width 1920 pitch 7680 (/4 1920)
>[ 42690.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3bf0]
>[ 42690.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3bf0] width 1920 pitch 7680 (/4 1920)
>[ 42690.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42690.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c3bf0]
>[ 42690.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c3bf0] width 1920 pitch 7680 (/4 1920)
>[ 42690.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42690.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42690.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42690.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42695.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80160]
>[ 42695.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80160] width 1920 pitch 7680 (/4 1920)
>[ 42695.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b16b0]
>[ 42695.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b16b0] width 1920 pitch 7680 (/4 1920)
>[ 42695.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 42695.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 42695.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e80]
>[ 42696.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e80] width 1920 pitch 7680 (/4 1920)
>[ 42696.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b8b0]
>[ 42696.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b8b0] width 1920 pitch 7680 (/4 1920)
>[ 42696.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a390]
>[ 42696.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a390] width 1920 pitch 7680 (/4 1920)
>[ 42696.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca9e0]
>[ 42696.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca9e0] width 1920 pitch 7680 (/4 1920)
>[ 42696.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a390]
>[ 42696.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a390] width 1920 pitch 7680 (/4 1920)
>[ 42696.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddb00]
>[ 42696.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddb00] width 1920 pitch 7680 (/4 1920)
>[ 42714.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 42714.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 42714.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879b20]
>[ 42714.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879b20] width 1920 pitch 7680 (/4 1920)
>[ 42714.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 42714.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 42714.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c705a0]
>[ 42714.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c705a0] width 1920 pitch 7680 (/4 1920)
>[ 42714.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 42714.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 42714.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edccb0]
>[ 42714.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edccb0] width 1920 pitch 7680 (/4 1920)
>[ 42746.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 42746.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 42775.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510a140]
>[ 42775.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510a140] width 1920 pitch 7680 (/4 1920)
>[ 42775.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 42775.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 42775.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d40]
>[ 42775.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d40] width 1920 pitch 7680 (/4 1920)
>[ 42775.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42775.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42775.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42776.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42776.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42776.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42776.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42776.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42776.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42776.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dffb0]
>[ 42776.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dffb0] width 1920 pitch 7680 (/4 1920)
>[ 42776.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42776.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42778.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42778.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42778.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd620]
>[ 42778.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd620] width 1920 pitch 7680 (/4 1920)
>[ 42778.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7450]
>[ 42778.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7450] width 1920 pitch 7680 (/4 1920)
>[ 42778.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057810]
>[ 42778.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057810] width 1920 pitch 7680 (/4 1920)
>[ 42778.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fea40]
>[ 42778.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fea40] width 1920 pitch 7680 (/4 1920)
>[ 42778.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8330]
>[ 42779.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8330] width 1920 pitch 7680 (/4 1920)
>[ 42779.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 42779.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 42779.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 42779.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 42779.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 42779.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 42780.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85120]
>[ 42780.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85120] width 1920 pitch 7680 (/4 1920)
>[ 42781.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 42781.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 42782.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8330]
>[ 42782.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8330] width 1920 pitch 7680 (/4 1920)
>[ 42782.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4c4d0]
>[ 42782.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4c4d0] width 1920 pitch 7680 (/4 1920)
>[ 42782.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9c0]
>[ 42782.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9c0] width 1920 pitch 7680 (/4 1920)
>[ 42782.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40306b0]
>[ 42782.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40306b0] width 1920 pitch 7680 (/4 1920)
>[ 42782.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f24120]
>[ 42782.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f24120] width 1920 pitch 7680 (/4 1920)
>[ 42782.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20dd0]
>[ 42782.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20dd0] width 1920 pitch 7680 (/4 1920)
>[ 42782.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098110]
>[ 42782.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098110] width 1920 pitch 7680 (/4 1920)
>[ 42782.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 42782.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 42782.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 42782.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 42782.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b150]
>[ 42782.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b150] width 1920 pitch 7680 (/4 1920)
>[ 42863.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42863.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42863.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 42863.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 42863.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 42863.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 42863.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 42863.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 42863.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 42863.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 42863.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 42863.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 42864.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 42864.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 42864.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42864.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42864.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 42864.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 42864.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42864.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42864.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 42864.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 42864.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42864.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42865.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42865.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42865.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 42865.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 42866.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42866.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42866.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f540]
>[ 42866.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f540] width 1920 pitch 7680 (/4 1920)
>[ 42866.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39607b0]
>[ 42866.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39607b0] width 1920 pitch 7680 (/4 1920)
>[ 42866.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507abb0]
>[ 42866.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507abb0] width 1920 pitch 7680 (/4 1920)
>[ 42866.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42866.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42866.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507abb0]
>[ 42866.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507abb0] width 1920 pitch 7680 (/4 1920)
>[ 42866.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42866.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42866.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507abb0]
>[ 42866.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507abb0] width 1920 pitch 7680 (/4 1920)
>[ 42866.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42866.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42867.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42867.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42867.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b10a0]
>[ 42867.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b10a0] width 1920 pitch 7680 (/4 1920)
>[ 42868.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc61a0]
>[ 42868.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc61a0] width 1920 pitch 7680 (/4 1920)
>[ 42868.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059c30]
>[ 42868.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059c30] width 1920 pitch 7680 (/4 1920)
>[ 42868.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a0a0]
>[ 42868.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a0a0] width 1920 pitch 7680 (/4 1920)
>[ 42868.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a620]
>[ 42868.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a620] width 1920 pitch 7680 (/4 1920)
>[ 42868.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba130]
>[ 42868.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba130] width 1920 pitch 7680 (/4 1920)
>[ 42868.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a0a0]
>[ 42868.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a0a0] width 1920 pitch 7680 (/4 1920)
>[ 42868.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397a0a0]
>[ 42868.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397a0a0] width 1920 pitch 7680 (/4 1920)
>[ 42868.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42868.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42868.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 42868.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 42868.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42868.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42868.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 42868.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 42868.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefd60]
>[ 42868.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefd60] width 1920 pitch 7680 (/4 1920)
>[ 42868.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c706d0]
>[ 42868.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c706d0] width 1920 pitch 7680 (/4 1920)
>[ 42868.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 42869.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 42869.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42869.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42870.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea0a70]
>[ 42870.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea0a70] width 1920 pitch 7680 (/4 1920)
>[ 42870.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42870.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42870.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea0a70]
>[ 42870.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea0a70] width 1920 pitch 7680 (/4 1920)
>[ 42870.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 42870.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 42870.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2c070]
>[ 42870.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2c070] width 1920 pitch 7680 (/4 1920)
>[ 42870.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea0a70]
>[ 42870.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea0a70] width 1920 pitch 7680 (/4 1920)
>[ 42872.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057af0]
>[ 42872.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057af0] width 1920 pitch 7680 (/4 1920)
>[ 42877.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 42877.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 42877.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c60d0]
>[ 42877.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c60d0] width 1920 pitch 7680 (/4 1920)
>[ 42877.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cecf80]
>[ 42877.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cecf80] width 1920 pitch 7680 (/4 1920)
>[ 42877.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1bf0]
>[ 42877.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1bf0] width 1920 pitch 7680 (/4 1920)
>[ 42877.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c60d0]
>[ 42877.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c60d0] width 1920 pitch 7680 (/4 1920)
>[ 42877.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 42877.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 42877.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c60d0]
>[ 42877.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c60d0] width 1920 pitch 7680 (/4 1920)
>[ 42877.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 42877.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 42877.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca6d0]
>[ 42877.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca6d0] width 1920 pitch 7680 (/4 1920)
>[ 42877.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81780]
>[ 42877.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81780] width 1920 pitch 7680 (/4 1920)
>[ 42878.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40579f0]
>[ 42878.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40579f0] width 1920 pitch 7680 (/4 1920)
>[ 42878.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8dfd0]
>[ 42878.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8dfd0] width 1920 pitch 7680 (/4 1920)
>[ 42878.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 42878.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 42878.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb4b0]
>[ 42878.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb4b0] width 1920 pitch 7680 (/4 1920)
>[ 42878.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8dfd0]
>[ 42878.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8dfd0] width 1920 pitch 7680 (/4 1920)
>[ 42878.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030fd0]
>[ 42878.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030fd0] width 1920 pitch 7680 (/4 1920)
>[ 42878.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2870]
>[ 42878.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2870] width 1920 pitch 7680 (/4 1920)
>[ 42878.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2870]
>[ 42878.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2870] width 1920 pitch 7680 (/4 1920)
>[ 42878.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030fd0]
>[ 42878.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030fd0] width 1920 pitch 7680 (/4 1920)
>[ 42883.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[ 42883.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[ 42883.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07820]
>[ 42883.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07820] width 1920 pitch 7680 (/4 1920)
>[ 42883.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07820]
>[ 42883.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07820] width 1920 pitch 7680 (/4 1920)
>[ 42883.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c786a0]
>[ 42883.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c786a0] width 1920 pitch 7680 (/4 1920)
>[ 42883.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c786a0]
>[ 42883.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c786a0] width 1920 pitch 7680 (/4 1920)
>[ 42883.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d7b0]
>[ 42883.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d7b0] width 1920 pitch 7680 (/4 1920)
>[ 42883.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7eb20]
>[ 42883.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7eb20] width 1920 pitch 7680 (/4 1920)
>[ 42883.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbeab0]
>[ 42883.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbeab0] width 1920 pitch 7680 (/4 1920)
>[ 42883.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9d7b0]
>[ 42883.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9d7b0] width 1920 pitch 7680 (/4 1920)
>[ 42883.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f08880]
>[ 42883.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f08880] width 1920 pitch 7680 (/4 1920)
>[ 42883.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbeab0]
>[ 42883.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbeab0] width 1920 pitch 7680 (/4 1920)
>[ 42883.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40255f0]
>[ 42883.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40255f0] width 1920 pitch 7680 (/4 1920)
>[ 42883.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbeab0]
>[ 42883.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbeab0] width 1920 pitch 7680 (/4 1920)
>[ 42883.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40255f0]
>[ 42883.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40255f0] width 1920 pitch 7680 (/4 1920)
>[ 42883.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbeab0]
>[ 42883.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbeab0] width 1920 pitch 7680 (/4 1920)
>[ 42883.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40255f0]
>[ 42883.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40255f0] width 1920 pitch 7680 (/4 1920)
>[ 42883.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbeab0]
>[ 42883.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbeab0] width 1920 pitch 7680 (/4 1920)
>[ 42912.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286dde0]
>[ 42912.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286dde0] width 1920 pitch 7680 (/4 1920)
>[ 42912.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286dde0]
>[ 42912.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286dde0] width 1920 pitch 7680 (/4 1920)
>[ 42912.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f5c0]
>[ 42912.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f5c0] width 1920 pitch 7680 (/4 1920)
>[ 42912.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f5c0]
>[ 42912.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f5c0] width 1920 pitch 7680 (/4 1920)
>[ 42912.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f31c20]
>[ 42912.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f31c20] width 1920 pitch 7680 (/4 1920)
>[ 42912.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f31c20]
>[ 42912.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f31c20] width 1920 pitch 7680 (/4 1920)
>[ 42912.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42912.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42912.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f5c0]
>[ 42912.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f5c0] width 1920 pitch 7680 (/4 1920)
>[ 42912.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc6360]
>[ 42912.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc6360] width 1920 pitch 7680 (/4 1920)
>[ 42912.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f5c0]
>[ 42912.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f5c0] width 1920 pitch 7680 (/4 1920)
>[ 42912.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79e10]
>[ 42912.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79e10] width 1920 pitch 7680 (/4 1920)
>[ 42912.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f5c0]
>[ 42912.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f5c0] width 1920 pitch 7680 (/4 1920)
>[ 42952.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42952.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42952.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42952.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42952.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42952.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42952.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42952.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42952.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42952.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42952.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42952.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42952.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42952.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42952.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42952.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42953.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833f90]
>[ 42953.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833f90] width 1920 pitch 7680 (/4 1920)
>[ 42953.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de910]
>[ 42953.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de910] width 1920 pitch 7680 (/4 1920)
>[ 42981.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42981.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42981.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 42982.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 42982.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 42982.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 42982.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42982.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 42982.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 42982.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42982.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42983.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42983.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42983.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2825f20]
>[ 42983.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2825f20] width 1920 pitch 7680 (/4 1920)
>[ 42983.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 42983.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 42983.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837a70]
>[ 42983.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837a70] width 1920 pitch 7680 (/4 1920)
>[ 42983.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 42983.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 42983.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 42983.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 42983.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 42983.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 42983.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 42983.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 42983.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42983.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42983.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42983.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42983.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397ebc0]
>[ 42983.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397ebc0] width 1920 pitch 7680 (/4 1920)
>[ 42983.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 42983.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 42984.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 42984.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 42984.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42984.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42984.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 42984.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 42984.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 42984.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 42984.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 42984.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 42984.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 42984.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 42984.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 42984.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 42984.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837a70]
>[ 42984.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837a70] width 1920 pitch 7680 (/4 1920)
>[ 42984.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 42984.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 42984.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 42984.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 42988.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42988.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42988.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 42988.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 42988.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 42988.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 42988.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 42988.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 42988.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 42988.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 42988.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42988.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42988.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42988.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42988.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 42988.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 42988.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 42988.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 42988.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 42988.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 42988.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 42988.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 42988.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 42989.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 42989.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 42989.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 42989.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 42989.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 42989.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42989.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42989.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42989.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42989.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42989.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42989.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42989.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42989.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42989.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42989.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42989.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42989.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42989.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42990.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42990.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42990.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42990.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42991.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42991.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42991.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42991.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42991.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42991.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42991.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42991.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42991.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42991.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42991.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42991.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42991.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42991.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 42991.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42992.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42992.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 42992.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 42992.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1ab0]
>[ 42992.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1ab0] width 1920 pitch 7680 (/4 1920)
>[ 42992.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 42992.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43007.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12920]
>[ 43007.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12920] width 1920 pitch 7680 (/4 1920)
>[ 43007.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43007.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43007.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e60980]
>[ 43007.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e60980] width 1920 pitch 7680 (/4 1920)
>[ 43007.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12920]
>[ 43007.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12920] width 1920 pitch 7680 (/4 1920)
>[ 43007.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43007.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43007.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e818f0]
>[ 43007.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e818f0] width 1920 pitch 7680 (/4 1920)
>[ 43007.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e818f0]
>[ 43007.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e818f0] width 1920 pitch 7680 (/4 1920)
>[ 43007.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e818f0]
>[ 43007.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e818f0] width 1920 pitch 7680 (/4 1920)
>[ 43008.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a60]
>[ 43008.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a60] width 1920 pitch 7680 (/4 1920)
>[ 43008.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a60]
>[ 43008.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a60] width 1920 pitch 7680 (/4 1920)
>[ 43008.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e60980]
>[ 43008.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e60980] width 1920 pitch 7680 (/4 1920)
>[ 43008.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e60980]
>[ 43008.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e60980] width 1920 pitch 7680 (/4 1920)
>[ 43008.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e60980]
>[ 43008.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e60980] width 1920 pitch 7680 (/4 1920)
>[ 43009.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea1230]
>[ 43009.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea1230] width 1920 pitch 7680 (/4 1920)
>[ 43009.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43009.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43009.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43009.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43009.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43009.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43009.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43009.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43009.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43009.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43009.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43009.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43009.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43009.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43009.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43009.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43009.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43009.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43009.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43010.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43010.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43010.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43010.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43010.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43010.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43010.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43010.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43010.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43010.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43010.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43010.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43010.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43010.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43010.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43010.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43010.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43010.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1b00]
>[ 43010.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1b00] width 1920 pitch 7680 (/4 1920)
>[ 43029.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43029.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43029.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda7a0]
>[ 43029.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda7a0] width 1920 pitch 7680 (/4 1920)
>[ 43029.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43029.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43029.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43029.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43029.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43029.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43029.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 43029.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 43029.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43029.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43029.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43029.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43029.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a12a70]
>[ 43029.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a12a70] width 1920 pitch 7680 (/4 1920)
>[ 43029.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43029.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43029.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43029.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43030.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43030.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43030.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43030.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43030.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda7a0]
>[ 43030.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda7a0] width 1920 pitch 7680 (/4 1920)
>[ 43030.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 43030.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 43030.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 43030.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 43030.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3bb0]
>[ 43030.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3bb0] width 1920 pitch 7680 (/4 1920)
>[ 43030.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda7a0]
>[ 43030.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda7a0] width 1920 pitch 7680 (/4 1920)
>[ 43030.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f167f0]
>[ 43030.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f167f0] width 1920 pitch 7680 (/4 1920)
>[ 43030.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce3bb0]
>[ 43030.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce3bb0] width 1920 pitch 7680 (/4 1920)
>[ 43031.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda7a0]
>[ 43031.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda7a0] width 1920 pitch 7680 (/4 1920)
>[ 43031.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fda7a0]
>[ 43031.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fda7a0] width 1920 pitch 7680 (/4 1920)
>[ 43033.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fda70]
>[ 43033.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fda70] width 1920 pitch 7680 (/4 1920)
>[ 43034.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048500]
>[ 43034.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048500] width 1920 pitch 7680 (/4 1920)
>[ 43034.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e09f0]
>[ 43034.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e09f0] width 1920 pitch 7680 (/4 1920)
>[ 43034.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8bf00]
>[ 43034.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8bf00] width 1920 pitch 7680 (/4 1920)
>[ 43034.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035390]
>[ 43034.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035390] width 1920 pitch 7680 (/4 1920)
>[ 43034.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8bf00]
>[ 43034.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8bf00] width 1920 pitch 7680 (/4 1920)
>[ 43034.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f90700]
>[ 43034.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f90700] width 1920 pitch 7680 (/4 1920)
>[ 43183.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c9e0]
>[ 43183.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c9e0] width 1920 pitch 7680 (/4 1920)
>[ 43183.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43183.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43183.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43183.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43183.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43183.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43183.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43183.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43183.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92700]
>[ 43184.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92700] width 1920 pitch 7680 (/4 1920)
>[ 43184.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43184.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43184.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92700]
>[ 43184.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92700] width 1920 pitch 7680 (/4 1920)
>[ 43184.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43184.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43184.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43184.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f92700]
>[ 43184.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f92700] width 1920 pitch 7680 (/4 1920)
>[ 43184.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025d60]
>[ 43184.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025d60] width 1920 pitch 7680 (/4 1920)
>[ 43184.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eea0]
>[ 43184.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eea0] width 1920 pitch 7680 (/4 1920)
>[ 43308.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c5b30]
>[ 43308.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c5b30] width 1920 pitch 7680 (/4 1920)
>[ 43308.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43308.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43308.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43308.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43308.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43308.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43308.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43308.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43308.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43308.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43308.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43308.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43308.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43308.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43308.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43308.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43309.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43309.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43309.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43309.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43309.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43309.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43309.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43309.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43309.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43309.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43309.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43309.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43309.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43309.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43309.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43309.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43309.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43309.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43310.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43310.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43311.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 43311.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 43311.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 43311.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 43311.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43311.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43311.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 43311.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 43311.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e5d0]
>[ 43311.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e5d0] width 1920 pitch 7680 (/4 1920)
>[ 43311.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5111bf0]
>[ 43311.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5111bf0] width 1920 pitch 7680 (/4 1920)
>[ 43311.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e5d0]
>[ 43311.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e5d0] width 1920 pitch 7680 (/4 1920)
>[ 43311.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43311.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43311.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb3e90]
>[ 43311.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb3e90] width 1920 pitch 7680 (/4 1920)
>[ 43311.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833e50]
>[ 43311.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833e50] width 1920 pitch 7680 (/4 1920)
>[ 43311.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23bf0]
>[ 43311.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23bf0] width 1920 pitch 7680 (/4 1920)
>[ 43320.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43320.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43320.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43320.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43320.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43320.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43320.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43320.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43320.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43320.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43320.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43320.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43320.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43320.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43320.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43320.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43320.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43320.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43320.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43320.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43320.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43320.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43320.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43320.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43320.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43320.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43320.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43320.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43320.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43320.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43320.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43320.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43320.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43320.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43320.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43320.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43320.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43320.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43320.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43320.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43320.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43320.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43320.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43320.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43320.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43320.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43320.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43320.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43320.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43320.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43320.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43320.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43320.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43320.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43320.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43320.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43320.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43320.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43320.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43320.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43320.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43320.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43320.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43320.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43321.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43321.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43321.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43321.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43321.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43321.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43321.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43321.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43321.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43321.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43321.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43321.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43321.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43321.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43321.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43321.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43321.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43321.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43321.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 43321.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 43321.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43321.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43321.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43321.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43321.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43321.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43321.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43321.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43321.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43321.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43321.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43321.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43321.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43321.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43321.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43321.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43321.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43321.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43321.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43321.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43321.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43321.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43321.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43321.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43321.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43321.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43321.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43321.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43321.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43321.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43321.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43321.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43321.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43321.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43321.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43321.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43321.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43321.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43321.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43321.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43322.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43322.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43322.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43322.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43322.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43322.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43322.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 43322.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 43322.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43322.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43322.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43322.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43322.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43322.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43322.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43322.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43322.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43322.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43322.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43322.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43322.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43322.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43322.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43322.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43322.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43322.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43322.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43322.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43322.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43322.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43322.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43322.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43322.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43322.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43322.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43322.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43322.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43322.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43322.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43322.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43322.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43322.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43322.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43322.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43322.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43322.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43322.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43322.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43322.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43322.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43322.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43322.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43322.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43322.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43322.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 43322.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 43322.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43322.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43322.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43322.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43323.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43323.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43323.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43323.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43323.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43323.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43323.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43323.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43323.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43323.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43323.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43323.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43323.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43323.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43323.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43323.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43323.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43323.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43323.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43323.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43323.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43323.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43323.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43323.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43323.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43323.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43323.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43323.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43323.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43323.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43323.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43323.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43323.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43323.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43323.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43323.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43323.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43323.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43323.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43323.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43323.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43323.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43323.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 43323.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 43323.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43323.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43323.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43323.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43323.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43323.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43323.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43323.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43323.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43323.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43323.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43323.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43323.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43323.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43323.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43323.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43324.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43324.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43324.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43324.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43324.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43324.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43324.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43324.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43324.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43324.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43324.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43324.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43324.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 43324.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 43324.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ec50]
>[ 43324.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ec50] width 1920 pitch 7680 (/4 1920)
>[ 43324.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43324.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43324.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43324.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43324.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43324.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43324.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43324.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43324.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43324.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43324.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43324.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43324.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc290]
>[ 43324.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc290] width 1920 pitch 7680 (/4 1920)
>[ 43324.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022130]
>[ 43324.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022130] width 1920 pitch 7680 (/4 1920)
>[ 43324.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43324.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43324.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43324.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43324.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43324.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43324.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43324.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43324.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 43324.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 43324.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43324.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43324.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43324.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43324.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 43324.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 43324.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43324.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43324.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43324.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43324.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43324.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43329.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47a90]
>[ 43329.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47a90] width 1920 pitch 7680 (/4 1920)
>[ 43329.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43329.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43329.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43329.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43329.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43329.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43329.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43329.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43329.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43329.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43329.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 43329.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 43329.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43329.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43329.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43329.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43329.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43329.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43329.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022d10]
>[ 43329.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022d10] width 1920 pitch 7680 (/4 1920)
>[ 43329.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf28f0]
>[ 43329.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf28f0] width 1920 pitch 7680 (/4 1920)
>[ 43329.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43329.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43329.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43329.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43330.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43330.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43330.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43330.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43330.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43330.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43330.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43330.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43330.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43330.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43330.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43330.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43330.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43330.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43330.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43330.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43330.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43330.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43330.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43330.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43330.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43330.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43330.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43330.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43331.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43331.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43331.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43331.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43331.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43331.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43331.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43331.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43331.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f80]
>[ 43331.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f80] width 1920 pitch 7680 (/4 1920)
>[ 43331.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43331.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43331.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43331.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43331.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43331.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43331.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc0a0]
>[ 43331.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc0a0] width 1920 pitch 7680 (/4 1920)
>[ 43410.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43410.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43410.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43410.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43410.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43410.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43410.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43410.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43410.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43410.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43410.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43410.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43410.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43410.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43410.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43410.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43410.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43410.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43411.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43411.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43411.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43411.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43411.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43411.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43411.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43411.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43412.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43412.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43412.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43412.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43412.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eddc50]
>[ 43412.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eddc50] width 1920 pitch 7680 (/4 1920)
>[ 43412.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43412.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43412.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea1290]
>[ 43412.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea1290] width 1920 pitch 7680 (/4 1920)
>[ 43412.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43412.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43412.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea1290]
>[ 43412.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea1290] width 1920 pitch 7680 (/4 1920)
>[ 43412.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a090]
>[ 43412.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a090] width 1920 pitch 7680 (/4 1920)
>[ 43412.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e520]
>[ 43413.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e520] width 1920 pitch 7680 (/4 1920)
>[ 43413.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a090]
>[ 43413.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a090] width 1920 pitch 7680 (/4 1920)
>[ 43413.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e520]
>[ 43413.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e520] width 1920 pitch 7680 (/4 1920)
>[ 43413.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43413.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43413.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43413.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43413.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43414.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43414.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43414.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43414.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43414.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43414.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43414.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43414.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f79400]
>[ 43414.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f79400] width 1920 pitch 7680 (/4 1920)
>[ 43414.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43414.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43414.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43414.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43414.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286e4a0]
>[ 43414.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286e4a0] width 1920 pitch 7680 (/4 1920)
>[ 43414.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43414.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43478.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f790f0]
>[ 43478.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f790f0] width 1920 pitch 7680 (/4 1920)
>[ 43480.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42d20]
>[ 43480.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42d20] width 1920 pitch 7680 (/4 1920)
>[ 43480.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07ef0]
>[ 43480.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07ef0] width 1920 pitch 7680 (/4 1920)
>[ 43480.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f791c0]
>[ 43480.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f791c0] width 1920 pitch 7680 (/4 1920)
>[ 43480.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404f270]
>[ 43480.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404f270] width 1920 pitch 7680 (/4 1920)
>[ 43480.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43480.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43480.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43480.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43480.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43480.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43480.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79bd0]
>[ 43480.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79bd0] width 1920 pitch 7680 (/4 1920)
>[ 43480.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43480.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88520]
>[ 43480.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88520] width 1920 pitch 7680 (/4 1920)
>[ 43482.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3d0]
>[ 43482.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3d0] width 1920 pitch 7680 (/4 1920)
>[ 43507.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c760]
>[ 43507.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c760] width 1920 pitch 7680 (/4 1920)
>[ 43507.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad6110]
>[ 43507.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad6110] width 1920 pitch 7680 (/4 1920)
>[ 43507.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e60]
>[ 43507.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e60] width 1920 pitch 7680 (/4 1920)
>[ 43507.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c760]
>[ 43507.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c760] width 1920 pitch 7680 (/4 1920)
>[ 43507.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e60]
>[ 43507.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e60] width 1920 pitch 7680 (/4 1920)
>[ 43507.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c760]
>[ 43507.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c760] width 1920 pitch 7680 (/4 1920)
>[ 43507.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e60]
>[ 43507.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e60] width 1920 pitch 7680 (/4 1920)
>[ 43507.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c760]
>[ 43507.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c760] width 1920 pitch 7680 (/4 1920)
>[ 43526.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43526.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43526.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51e40]
>[ 43526.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51e40] width 1920 pitch 7680 (/4 1920)
>[ 43526.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43526.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43526.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e520]
>[ 43526.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e520] width 1920 pitch 7680 (/4 1920)
>[ 43526.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43526.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43526.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c870]
>[ 43526.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c870] width 1920 pitch 7680 (/4 1920)
>[ 43526.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43526.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43526.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51e40]
>[ 43526.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51e40] width 1920 pitch 7680 (/4 1920)
>[ 43526.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43526.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43527.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43527.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43527.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e570]
>[ 43527.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e570] width 1920 pitch 7680 (/4 1920)
>[ 43527.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc650]
>[ 43527.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc650] width 1920 pitch 7680 (/4 1920)
>[ 43527.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43527.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43527.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e520]
>[ 43527.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e520] width 1920 pitch 7680 (/4 1920)
>[ 43527.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43527.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43527.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e70]
>[ 43527.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e70] width 1920 pitch 7680 (/4 1920)
>[ 43527.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e3b0]
>[ 43528.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e3b0] width 1920 pitch 7680 (/4 1920)
>[ 43528.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e70]
>[ 43528.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e70] width 1920 pitch 7680 (/4 1920)
>[ 43528.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e570]
>[ 43528.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e570] width 1920 pitch 7680 (/4 1920)
>[ 43528.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7e520]
>[ 43528.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7e520] width 1920 pitch 7680 (/4 1920)
>[ 43528.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad5e70]
>[ 43528.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad5e70] width 1920 pitch 7680 (/4 1920)
>[ 43528.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43528.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad60c0]
>[ 43528.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad60c0] width 1920 pitch 7680 (/4 1920)
>[ 43536.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e9d0]
>[ 43536.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e9d0] width 1920 pitch 7680 (/4 1920)
>[ 43537.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30f50]
>[ 43537.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30f50] width 1920 pitch 7680 (/4 1920)
>[ 43540.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30dc0]
>[ 43540.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30dc0] width 1920 pitch 7680 (/4 1920)
>[ 43540.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43540.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43540.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43540.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43540.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43541.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43541.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43541.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43541.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43542.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43542.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43542.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43542.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43543.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43543.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43543.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43543.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43544.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95fe0]
>[ 43544.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95fe0] width 1920 pitch 7680 (/4 1920)
>[ 43544.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc10]
>[ 43544.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc10] width 1920 pitch 7680 (/4 1920)
>[ 43552.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131cc0]
>[ 43552.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131cc0] width 1920 pitch 7680 (/4 1920)
>[ 43605.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f200a0]
>[ 43605.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f200a0] width 1920 pitch 7680 (/4 1920)
>[ 43605.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18150]
>[ 43605.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18150] width 1920 pitch 7680 (/4 1920)
>[ 43608.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43608.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43608.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5ea70]
>[ 43608.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5ea70] width 1920 pitch 7680 (/4 1920)
>[ 43608.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43608.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43608.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43608.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43608.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43608.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43608.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43608.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43608.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43608.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43608.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43608.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43608.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43608.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43608.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43608.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43608.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43608.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43608.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43608.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43608.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43608.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43608.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43608.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43609.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43609.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43609.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43609.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43609.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43609.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43609.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43609.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43609.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43609.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43609.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43609.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43609.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43609.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43609.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43609.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43609.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43609.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43609.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43609.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43609.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43609.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43609.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43609.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43609.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43609.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43609.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43609.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43609.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43609.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43609.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43609.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43609.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43610.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43610.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43610.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43610.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43610.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43610.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43610.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43610.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43610.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43610.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43610.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43610.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43610.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43610.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eaee0]
>[ 43610.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eaee0] width 1920 pitch 7680 (/4 1920)
>[ 43610.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43610.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43610.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43610.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43610.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43610.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43610.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43610.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43610.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43610.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43610.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43610.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43610.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43610.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43610.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43610.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43610.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43610.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43611.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43611.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43611.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43611.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43611.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43611.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43611.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43611.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43612.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43612.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43612.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43612.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43612.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43612.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43612.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43612.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43613.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43613.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43613.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43613.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43613.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43613.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43613.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43613.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43614.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43614.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43614.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43614.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43614.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43614.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43614.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43614.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43615.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43615.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43615.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43615.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43615.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43615.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43615.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43615.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43615.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e47c00]
>[ 43615.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e47c00] width 1920 pitch 7680 (/4 1920)
>[ 43615.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43615.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43615.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43615.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43615.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2700370]
>[ 43615.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2700370] width 1920 pitch 7680 (/4 1920)
>[ 43635.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43635.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43635.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43635.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43635.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102110]
>[ 43635.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102110] width 1920 pitch 7680 (/4 1920)
>[ 43635.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3965450]
>[ 43635.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3965450] width 1920 pitch 7680 (/4 1920)
>[ 43635.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43635.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43635.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43635.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43635.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43635.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43635.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102110]
>[ 43635.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102110] width 1920 pitch 7680 (/4 1920)
>[ 43635.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43635.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43636.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43636.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43636.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43636.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43636.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f253b0]
>[ 43636.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f253b0] width 1920 pitch 7680 (/4 1920)
>[ 43636.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43636.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43636.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43636.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43636.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bc30]
>[ 43636.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bc30] width 1920 pitch 7680 (/4 1920)
>[ 43636.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394c000]
>[ 43636.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394c000] width 1920 pitch 7680 (/4 1920)
>[ 43636.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3965450]
>[ 43636.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3965450] width 1920 pitch 7680 (/4 1920)
>[ 43681.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f194b0]
>[ 43681.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f194b0] width 1920 pitch 7680 (/4 1920)
>[ 43681.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43681.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879300]
>[ 43681.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879300] width 1920 pitch 7680 (/4 1920)
>[ 43681.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43681.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43697.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131c30]
>[ 43697.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131c30] width 1920 pitch 7680 (/4 1920)
>[ 43739.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa23e0]
>[ 43739.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa23e0] width 1920 pitch 7680 (/4 1920)
>[ 43741.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5049180]
>[ 43741.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5049180] width 1920 pitch 7680 (/4 1920)
>[ 43752.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 43752.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 43752.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 43752.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 43752.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43752.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43752.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 43752.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 43752.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17ba0]
>[ 43752.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17ba0] width 1920 pitch 7680 (/4 1920)
>[ 43752.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 43752.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 43752.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 43752.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 43752.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 43752.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 43752.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17ba0]
>[ 43752.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17ba0] width 1920 pitch 7680 (/4 1920)
>[ 43752.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43752.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43752.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43752.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43752.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 43752.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 43752.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17ba0]
>[ 43752.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17ba0] width 1920 pitch 7680 (/4 1920)
>[ 43753.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17ba0]
>[ 43753.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17ba0] width 1920 pitch 7680 (/4 1920)
>[ 43753.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f17ba0]
>[ 43753.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f17ba0] width 1920 pitch 7680 (/4 1920)
>[ 43753.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 43753.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 43753.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43753.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43753.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43753.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43753.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 43753.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 43753.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8660]
>[ 43754.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8660] width 1920 pitch 7680 (/4 1920)
>[ 43754.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052910]
>[ 43754.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052910] width 1920 pitch 7680 (/4 1920)
>[ 43754.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43754.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43754.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43754.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43754.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43754.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43754.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 43754.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 43754.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8660]
>[ 43754.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8660] width 1920 pitch 7680 (/4 1920)
>[ 43754.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8660]
>[ 43754.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8660] width 1920 pitch 7680 (/4 1920)
>[ 43755.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 43755.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 43755.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8660]
>[ 43755.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8660] width 1920 pitch 7680 (/4 1920)
>[ 43755.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43755.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43755.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43755.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43755.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43755.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43755.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 43755.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 43755.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8660]
>[ 43755.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8660] width 1920 pitch 7680 (/4 1920)
>[ 43755.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43755.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43755.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43755.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43755.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 43755.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 43767.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43767.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43767.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43767.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43767.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43767.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43767.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 43767.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 43767.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43767.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43767.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43767.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43767.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43767.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43767.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 43767.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 43767.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43767.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43767.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43767.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43768.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43768.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43768.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 43768.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 43768.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 43768.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 43768.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 43768.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 43768.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43769.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43769.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43769.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43769.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40582a0]
>[ 43769.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40582a0] width 1920 pitch 7680 (/4 1920)
>[ 43769.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43769.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43769.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 43769.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 43769.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77700]
>[ 43769.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77700] width 1920 pitch 7680 (/4 1920)
>[ 43769.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 43769.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 43769.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c7410]
>[ 43769.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c7410] width 1920 pitch 7680 (/4 1920)
>[ 43769.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 43769.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 43769.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf5580]
>[ 43769.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf5580] width 1920 pitch 7680 (/4 1920)
>[ 43769.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4b80]
>[ 43769.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4b80] width 1920 pitch 7680 (/4 1920)
>[ 43769.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 43769.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 43769.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 43769.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 43769.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43769.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 43769.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 43769.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 43769.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504e670]
>[ 43769.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504e670] width 1920 pitch 7680 (/4 1920)
>[ 43769.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 43769.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 43769.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ec40]
>[ 43770.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ec40] width 1920 pitch 7680 (/4 1920)
>[ 43770.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 43770.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 44087.465] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 44087.465] (II) RADEON(0): Using hsync ranges from config file
>[ 44087.465] (II) RADEON(0): Using vrefresh ranges from config file
>[ 44087.465] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 44087.465] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 44087.465] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 44087.465] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 44177.746] (II) RADEON(0): RADEONSaveScreen(2)
>[ 44177.746] (II) RADEON(0): RADEONSaveScreen(0)
>[ 45797.937] (II) RADEON(0): RADEONSaveScreen(1)
>[ 45811.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45811.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45811.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 45811.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 45812.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45813.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45813.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81120]
>[ 45813.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81120] width 1920 pitch 7680 (/4 1920)
>[ 45813.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 45813.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 45813.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 45813.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 45813.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 45813.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 45813.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a4f0]
>[ 45813.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a4f0] width 1920 pitch 7680 (/4 1920)
>[ 45813.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 45813.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 45813.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45813.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45813.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 45813.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 45813.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45813.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45813.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 45813.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 45814.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 45814.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 45814.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45814.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45814.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 45814.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 45816.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45816.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45816.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 45816.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 45816.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f261d0]
>[ 45816.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f261d0] width 1920 pitch 7680 (/4 1920)
>[ 45816.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 45816.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 45816.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45816.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45816.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 45816.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 45816.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 45816.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 45816.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45816.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45816.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45816.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45816.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b29ab0]
>[ 45816.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b29ab0] width 1920 pitch 7680 (/4 1920)
>[ 45816.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45816.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45816.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 45816.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 45816.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce6980]
>[ 45816.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce6980] width 1920 pitch 7680 (/4 1920)
>[ 45816.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45817.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45817.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45817.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45817.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b29ab0]
>[ 45817.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b29ab0] width 1920 pitch 7680 (/4 1920)
>[ 45817.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45817.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45817.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 45817.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 45817.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b29ab0]
>[ 45817.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b29ab0] width 1920 pitch 7680 (/4 1920)
>[ 45817.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45817.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45817.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 45817.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 45817.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce6980]
>[ 45817.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce6980] width 1920 pitch 7680 (/4 1920)
>[ 45817.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45817.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45817.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45817.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45817.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b29ab0]
>[ 45817.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b29ab0] width 1920 pitch 7680 (/4 1920)
>[ 45817.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45817.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45817.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 45817.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 45817.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45817.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45842.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45842.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45842.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45842.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45842.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45842.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45842.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45842.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45842.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45842.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45842.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45842.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45842.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45842.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45842.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45842.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45842.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 45842.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 45843.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 45843.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 45843.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 45843.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 45843.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 45843.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 45843.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 45843.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 45843.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45843.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45843.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee510]
>[ 45843.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee510] width 1920 pitch 7680 (/4 1920)
>[ 45843.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 45843.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 45843.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 45843.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 45843.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 45843.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 45843.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45843.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45843.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 45843.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 45844.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a080]
>[ 45844.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a080] width 1920 pitch 7680 (/4 1920)
>[ 45844.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 45844.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 45846.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 45846.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 45846.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096bc0]
>[ 45846.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096bc0] width 1920 pitch 7680 (/4 1920)
>[ 45846.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 45846.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 45846.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f30ad0]
>[ 45846.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f30ad0] width 1920 pitch 7680 (/4 1920)
>[ 45846.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45846.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45846.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee510]
>[ 45846.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee510] width 1920 pitch 7680 (/4 1920)
>[ 45846.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 45846.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 45846.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 45846.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 45846.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 45846.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 45846.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 45846.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 45846.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee510]
>[ 45846.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee510] width 1920 pitch 7680 (/4 1920)
>[ 45873.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45873.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45873.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee87d0]
>[ 45873.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee87d0] width 1920 pitch 7680 (/4 1920)
>[ 45873.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f30ad0]
>[ 45873.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f30ad0] width 1920 pitch 7680 (/4 1920)
>[ 45873.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 45873.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 45873.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 45873.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 45873.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 45873.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 45873.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89d90]
>[ 45873.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89d90] width 1920 pitch 7680 (/4 1920)
>[ 45873.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 45873.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 45874.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 45874.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 45874.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 45874.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 45874.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 45874.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 45875.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45875.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45875.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec4640]
>[ 45875.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec4640] width 1920 pitch 7680 (/4 1920)
>[ 45875.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db0c50]
>[ 45875.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db0c50] width 1920 pitch 7680 (/4 1920)
>[ 45875.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f37760]
>[ 45875.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f37760] width 1920 pitch 7680 (/4 1920)
>[ 45875.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45875.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45875.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1dca0]
>[ 45875.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1dca0] width 1920 pitch 7680 (/4 1920)
>[ 45875.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23800]
>[ 45875.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23800] width 1920 pitch 7680 (/4 1920)
>[ 45875.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94bd0]
>[ 45875.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94bd0] width 1920 pitch 7680 (/4 1920)
>[ 45875.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45875.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45875.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f37760]
>[ 45875.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f37760] width 1920 pitch 7680 (/4 1920)
>[ 45876.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1dca0]
>[ 45876.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1dca0] width 1920 pitch 7680 (/4 1920)
>[ 45876.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45876.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45876.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94bd0]
>[ 45876.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94bd0] width 1920 pitch 7680 (/4 1920)
>[ 45876.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45876.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45876.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[ 45876.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[ 45876.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45876.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45876.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec4640]
>[ 45876.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec4640] width 1920 pitch 7680 (/4 1920)
>[ 45876.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 45876.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 45876.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f37760]
>[ 45876.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f37760] width 1920 pitch 7680 (/4 1920)
>[ 45876.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e94bd0]
>[ 45876.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e94bd0] width 1920 pitch 7680 (/4 1920)
>[ 46243.622] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 46243.622] (II) RADEON(0): Using hsync ranges from config file
>[ 46243.622] (II) RADEON(0): Using vrefresh ranges from config file
>[ 46243.622] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 46243.622] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 46243.622] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 46243.622] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 46333.760] (II) RADEON(0): RADEONSaveScreen(2)
>[ 46333.760] (II) RADEON(0): RADEONSaveScreen(0)
>[ 46951.942] (II) RADEON(0): RADEONSaveScreen(1)
>[ 46964.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052e70]
>[ 46964.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052e70] width 1920 pitch 7680 (/4 1920)
>[ 46982.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052e70]
>[ 46982.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052e70] width 1920 pitch 7680 (/4 1920)
>[ 46982.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49230]
>[ 46982.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49230] width 1920 pitch 7680 (/4 1920)
>[ 46983.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 46983.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 46983.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 46983.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 46983.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 46983.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 46983.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052e70]
>[ 46983.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052e70] width 1920 pitch 7680 (/4 1920)
>[ 46983.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 46983.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 46983.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 46983.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 46983.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 46983.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 46983.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 46983.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 46983.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052e70]
>[ 46983.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052e70] width 1920 pitch 7680 (/4 1920)
>[ 46983.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9dd00]
>[ 46983.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9dd00] width 1920 pitch 7680 (/4 1920)
>[ 46990.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28164a0]
>[ 46990.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28164a0] width 1920 pitch 7680 (/4 1920)
>[ 46990.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30370]
>[ 46990.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30370] width 1920 pitch 7680 (/4 1920)
>[ 46990.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd560]
>[ 46990.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd560] width 1920 pitch 7680 (/4 1920)
>[ 46990.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f13b70]
>[ 46991.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f13b70] width 1920 pitch 7680 (/4 1920)
>[ 47021.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286f0d0]
>[ 47021.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286f0d0] width 1920 pitch 7680 (/4 1920)
>[ 47021.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084ce0]
>[ 47021.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084ce0] width 1920 pitch 7680 (/4 1920)
>[ 47021.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44ac0]
>[ 47021.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44ac0] width 1920 pitch 7680 (/4 1920)
>[ 47021.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47021.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47021.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286f0d0]
>[ 47021.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286f0d0] width 1920 pitch 7680 (/4 1920)
>[ 47021.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286f0d0]
>[ 47021.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286f0d0] width 1920 pitch 7680 (/4 1920)
>[ 47021.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286f0d0]
>[ 47021.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286f0d0] width 1920 pitch 7680 (/4 1920)
>[ 47021.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286f0d0]
>[ 47021.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286f0d0] width 1920 pitch 7680 (/4 1920)
>[ 47025.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47025.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47027.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47027.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47027.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47027.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47027.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47027.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47027.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47027.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47027.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47027.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47027.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47027.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47027.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47027.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47027.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47027.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47028.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47028.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47028.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47028.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47028.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47028.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47028.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47028.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47028.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47028.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47028.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47028.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47028.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47028.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47028.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47028.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47028.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47028.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47028.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47028.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47028.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47028.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47028.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47028.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47028.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47028.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47028.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47028.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47028.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47028.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47028.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47028.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47028.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47028.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47028.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47028.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47028.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47028.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47028.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47028.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47028.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47028.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47028.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47028.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47028.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47028.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47028.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47028.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47028.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47028.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47028.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47028.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47028.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47028.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47028.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47028.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47028.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47028.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47028.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47028.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47029.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47029.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47029.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47029.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47029.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47029.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47029.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47029.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47029.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47029.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47029.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47029.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47029.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47029.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47029.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47029.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47029.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47029.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47029.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47029.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47029.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47029.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47029.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47029.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47029.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47029.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47029.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47029.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47029.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47029.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47029.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47029.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47029.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47029.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47029.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47029.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47029.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47029.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47029.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 47029.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 47029.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ff0]
>[ 47029.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ff0] width 1920 pitch 7680 (/4 1920)
>[ 47029.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[ 47029.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1920 pitch 7680 (/4 1920)
>[ 47029.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432e0]
>[ 47029.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432e0] width 1920 pitch 7680 (/4 1920)
>[ 47029.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 47029.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 47029.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135b60]
>[ 47029.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135b60] width 1920 pitch 7680 (/4 1920)
>[ 47029.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 47029.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 47029.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75990]
>[ 47029.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75990] width 1920 pitch 7680 (/4 1920)
>[ 47245.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3540]
>[ 47245.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3540] width 1920 pitch 7680 (/4 1920)
>[ 47245.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 47245.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 47245.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea24e0]
>[ 47245.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea24e0] width 1920 pitch 7680 (/4 1920)
>[ 47245.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 47245.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 47245.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3540]
>[ 47245.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3540] width 1920 pitch 7680 (/4 1920)
>[ 47245.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 47245.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 47245.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 47245.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 47245.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f32a0]
>[ 47245.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f32a0] width 1920 pitch 7680 (/4 1920)
>[ 47333.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f143c0]
>[ 47333.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f143c0] width 1920 pitch 7680 (/4 1920)
>[ 47363.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47363.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47363.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9df00]
>[ 47363.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9df00] width 1920 pitch 7680 (/4 1920)
>[ 47363.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47363.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47363.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47364.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b240]
>[ 47364.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b240] width 1920 pitch 7680 (/4 1920)
>[ 47364.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522b8a0]
>[ 47364.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522b8a0] width 1920 pitch 7680 (/4 1920)
>[ 47375.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5190]
>[ 47375.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5190] width 1920 pitch 7680 (/4 1920)
>[ 47375.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d944f0]
>[ 47375.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d944f0] width 1920 pitch 7680 (/4 1920)
>[ 47375.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47375.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47375.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47375.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47375.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47375.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47375.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47375.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47375.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47375.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47375.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47375.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47375.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47375.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47375.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47376.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47376.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47376.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47376.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fcb0]
>[ 47376.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fcb0] width 1920 pitch 7680 (/4 1920)
>[ 47376.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47376.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47376.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47376.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47376.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47376.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47376.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47376.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47376.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47377.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135520]
>[ 47377.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135520] width 1920 pitch 7680 (/4 1920)
>[ 47377.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c00]
>[ 47377.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c00] width 1920 pitch 7680 (/4 1920)
>[ 47377.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fd7a0]
>[ 47377.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fd7a0] width 1920 pitch 7680 (/4 1920)
>[ 47377.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5080360]
>[ 47377.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5080360] width 1920 pitch 7680 (/4 1920)
>[ 47784.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a6e0]
>[ 47784.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a6e0] width 1920 pitch 7680 (/4 1920)
>[ 47785.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5a060]
>[ 47785.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5a060] width 1920 pitch 7680 (/4 1920)
>[ 47785.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5a060]
>[ 47785.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5a060] width 1920 pitch 7680 (/4 1920)
>[ 47786.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29d70]
>[ 47786.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29d70] width 1920 pitch 7680 (/4 1920)
>[ 47786.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29c70]
>[ 47786.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29c70] width 1920 pitch 7680 (/4 1920)
>[ 47794.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db9090]
>[ 47794.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db9090] width 1920 pitch 7680 (/4 1920)
>[ 47794.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28559e0]
>[ 47794.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28559e0] width 1920 pitch 7680 (/4 1920)
>[ 47795.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed22c0]
>[ 47795.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed22c0] width 1920 pitch 7680 (/4 1920)
>[ 47795.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54080]
>[ 47795.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54080] width 1920 pitch 7680 (/4 1920)
>[ 47795.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed22c0]
>[ 47795.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed22c0] width 1920 pitch 7680 (/4 1920)
>[ 47795.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54080]
>[ 47795.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54080] width 1920 pitch 7680 (/4 1920)
>[ 47795.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed22c0]
>[ 47795.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed22c0] width 1920 pitch 7680 (/4 1920)
>[ 47795.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54080]
>[ 47795.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54080] width 1920 pitch 7680 (/4 1920)
>[ 47795.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed22c0]
>[ 47795.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed22c0] width 1920 pitch 7680 (/4 1920)
>[ 47795.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54080]
>[ 47795.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54080] width 1920 pitch 7680 (/4 1920)
>[ 47795.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed22c0]
>[ 47795.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed22c0] width 1920 pitch 7680 (/4 1920)
>[ 47795.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54080]
>[ 47795.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54080] width 1920 pitch 7680 (/4 1920)
>[ 48069.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48069.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48069.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48069.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48069.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48069.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48069.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48069.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48069.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48069.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48069.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48069.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48069.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48069.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48069.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48069.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48070.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48070.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48070.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48070.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48070.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa9830]
>[ 48070.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa9830] width 1920 pitch 7680 (/4 1920)
>[ 48070.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48070.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48070.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eb140]
>[ 48070.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eb140] width 1920 pitch 7680 (/4 1920)
>[ 48071.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa9b0]
>[ 48071.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa9b0] width 1920 pitch 7680 (/4 1920)
>[ 48071.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb2080]
>[ 48071.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb2080] width 1920 pitch 7680 (/4 1920)
>[ 48071.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48071.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48071.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26f70]
>[ 48071.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26f70] width 1920 pitch 7680 (/4 1920)
>[ 48071.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48071.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48071.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14490]
>[ 48071.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14490] width 1920 pitch 7680 (/4 1920)
>[ 48071.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48071.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48071.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ca70]
>[ 48071.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ca70] width 1920 pitch 7680 (/4 1920)
>[ 48071.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48071.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48071.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5a890]
>[ 48071.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5a890] width 1920 pitch 7680 (/4 1920)
>[ 48071.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48071.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48072.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0620]
>[ 48072.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0620] width 1920 pitch 7680 (/4 1920)
>[ 48072.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48072.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48072.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0620]
>[ 48072.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0620] width 1920 pitch 7680 (/4 1920)
>[ 48072.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48072.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48072.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0620]
>[ 48072.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0620] width 1920 pitch 7680 (/4 1920)
>[ 48072.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48072.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48072.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0620]
>[ 48072.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0620] width 1920 pitch 7680 (/4 1920)
>[ 48072.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bf1d0]
>[ 48072.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bf1d0] width 1920 pitch 7680 (/4 1920)
>[ 48072.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0620]
>[ 48072.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0620] width 1920 pitch 7680 (/4 1920)
>[ 48434.614] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 48434.614] (II) RADEON(0): Using hsync ranges from config file
>[ 48434.614] (II) RADEON(0): Using vrefresh ranges from config file
>[ 48434.614] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 48434.614] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 48434.614] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 48434.614] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 48434.615] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 48523.756] (II) RADEON(0): RADEONSaveScreen(2)
>[ 48523.756] (II) RADEON(0): RADEONSaveScreen(0)
>[ 54026.299] (II) RADEON(0): RADEONSaveScreen(1)
>[ 54048.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 54048.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 54050.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54050.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54050.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f2880]
>[ 54050.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f2880] width 1920 pitch 7680 (/4 1920)
>[ 54051.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 54051.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 54051.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54051.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54052.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54052.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54052.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54052.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54052.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6680]
>[ 54052.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6680] width 1920 pitch 7680 (/4 1920)
>[ 54052.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54052.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54052.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6680]
>[ 54052.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6680] width 1920 pitch 7680 (/4 1920)
>[ 54052.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54052.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54052.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54052.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54052.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54052.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54052.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54052.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54053.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 54053.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 54053.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54053.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54053.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 54053.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 54053.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 54053.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 54054.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54054.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54054.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54054.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54055.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54055.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54055.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54055.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54055.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54055.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54055.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54055.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54055.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad0670]
>[ 54055.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad0670] width 1920 pitch 7680 (/4 1920)
>[ 54055.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54055.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54055.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51e70]
>[ 54055.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51e70] width 1920 pitch 7680 (/4 1920)
>[ 54055.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5133080]
>[ 54055.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5133080] width 1920 pitch 7680 (/4 1920)
>[ 54082.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39665d0]
>[ 54082.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39665d0] width 1920 pitch 7680 (/4 1920)
>[ 54082.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 54082.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 54083.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e840e0]
>[ 54083.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e840e0] width 1920 pitch 7680 (/4 1920)
>[ 54083.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 54083.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 54083.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 54083.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 54083.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54083.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54083.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54083.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54083.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 54083.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 54083.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54083.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54083.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4890]
>[ 54083.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4890] width 1920 pitch 7680 (/4 1920)
>[ 54083.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c9f0]
>[ 54083.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c9f0] width 1920 pitch 7680 (/4 1920)
>[ 54083.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 54083.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 54083.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 54083.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 54083.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 54083.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 54083.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39665d0]
>[ 54083.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39665d0] width 1920 pitch 7680 (/4 1920)
>[ 54083.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f770]
>[ 54083.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f770] width 1920 pitch 7680 (/4 1920)
>[ 54083.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54083.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54083.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3130]
>[ 54083.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3130] width 1920 pitch 7680 (/4 1920)
>[ 54083.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54083.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54083.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 54083.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 54083.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e840e0]
>[ 54083.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e840e0] width 1920 pitch 7680 (/4 1920)
>[ 54083.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 54083.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 54083.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 54083.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 54083.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54083.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54087.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 54087.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 54087.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f170]
>[ 54087.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f170] width 1920 pitch 7680 (/4 1920)
>[ 54087.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f770]
>[ 54087.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f770] width 1920 pitch 7680 (/4 1920)
>[ 54088.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54088.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54088.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f770]
>[ 54088.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f770] width 1920 pitch 7680 (/4 1920)
>[ 54088.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e840e0]
>[ 54088.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e840e0] width 1920 pitch 7680 (/4 1920)
>[ 54088.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 54088.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 54089.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f770]
>[ 54089.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f770] width 1920 pitch 7680 (/4 1920)
>[ 54089.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28774f0]
>[ 54089.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28774f0] width 1920 pitch 7680 (/4 1920)
>[ 54090.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54090.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54091.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54091.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54091.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 54091.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 54091.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4940]
>[ 54091.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4940] width 1920 pitch 7680 (/4 1920)
>[ 54091.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54091.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54091.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 54091.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 54091.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4890]
>[ 54091.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4890] width 1920 pitch 7680 (/4 1920)
>[ 54091.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54091.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54091.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3130]
>[ 54091.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3130] width 1920 pitch 7680 (/4 1920)
>[ 54091.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 54091.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 54091.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54091.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54091.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 54091.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 54091.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4940]
>[ 54091.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4940] width 1920 pitch 7680 (/4 1920)
>[ 54091.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54091.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54091.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 54091.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 54091.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4890]
>[ 54091.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4890] width 1920 pitch 7680 (/4 1920)
>[ 54091.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54091.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54091.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 54091.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 54091.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 54091.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 54091.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ae2ae0]
>[ 54091.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ae2ae0] width 1920 pitch 7680 (/4 1920)
>[ 54091.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b48590]
>[ 54091.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b48590] width 1920 pitch 7680 (/4 1920)
>[ 54091.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54091.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54091.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb7000]
>[ 54091.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb7000] width 1920 pitch 7680 (/4 1920)
>[ 54091.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f770]
>[ 54091.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f770] width 1920 pitch 7680 (/4 1920)
>[ 54091.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c9f0]
>[ 54091.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c9f0] width 1920 pitch 7680 (/4 1920)
>[ 54091.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e840e0]
>[ 54091.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e840e0] width 1920 pitch 7680 (/4 1920)
>[ 54091.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f8a0]
>[ 54091.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f8a0] width 1920 pitch 7680 (/4 1920)
>[ 54103.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54103.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54103.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54103.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54104.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb5e20]
>[ 54104.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb5e20] width 1920 pitch 7680 (/4 1920)
>[ 54104.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54104.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54104.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54104.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54104.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc41a0]
>[ 54104.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc41a0] width 1920 pitch 7680 (/4 1920)
>[ 54104.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 54104.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 54104.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54104.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54104.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e840e0]
>[ 54104.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e840e0] width 1920 pitch 7680 (/4 1920)
>[ 54104.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 54104.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 54104.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54104.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54104.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 54104.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 54104.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4890]
>[ 54104.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4890] width 1920 pitch 7680 (/4 1920)
>[ 54104.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 54105.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 54105.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb7000]
>[ 54105.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb7000] width 1920 pitch 7680 (/4 1920)
>[ 54105.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100b00]
>[ 54105.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100b00] width 1920 pitch 7680 (/4 1920)
>[ 54189.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2875050]
>[ 54189.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2875050] width 1920 pitch 7680 (/4 1920)
>[ 54189.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad9290]
>[ 54189.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad9290] width 1920 pitch 7680 (/4 1920)
>[ 54189.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fd50]
>[ 54189.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fd50] width 1920 pitch 7680 (/4 1920)
>[ 54189.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad9290]
>[ 54189.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad9290] width 1920 pitch 7680 (/4 1920)
>[ 54189.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54189.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54189.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f25740]
>[ 54189.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f25740] width 1920 pitch 7680 (/4 1920)
>[ 54189.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39665d0]
>[ 54189.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39665d0] width 1920 pitch 7680 (/4 1920)
>[ 54189.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54189.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54189.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f170]
>[ 54189.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f170] width 1920 pitch 7680 (/4 1920)
>[ 54189.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c270]
>[ 54189.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c270] width 1920 pitch 7680 (/4 1920)
>[ 54189.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2875050]
>[ 54190.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2875050] width 1920 pitch 7680 (/4 1920)
>[ 54190.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39375e0]
>[ 54190.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39375e0] width 1920 pitch 7680 (/4 1920)
>[ 54190.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54190.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54190.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 54190.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 54190.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54190.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54190.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54190.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54190.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fd50]
>[ 54190.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fd50] width 1920 pitch 7680 (/4 1920)
>[ 54190.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad9290]
>[ 54190.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad9290] width 1920 pitch 7680 (/4 1920)
>[ 54190.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54190.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54190.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f25740]
>[ 54190.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f25740] width 1920 pitch 7680 (/4 1920)
>[ 54190.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39665d0]
>[ 54190.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39665d0] width 1920 pitch 7680 (/4 1920)
>[ 54190.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54190.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54190.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f170]
>[ 54190.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f170] width 1920 pitch 7680 (/4 1920)
>[ 54190.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c270]
>[ 54190.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c270] width 1920 pitch 7680 (/4 1920)
>[ 54190.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2875050]
>[ 54190.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2875050] width 1920 pitch 7680 (/4 1920)
>[ 54190.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39375e0]
>[ 54190.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39375e0] width 1920 pitch 7680 (/4 1920)
>[ 54190.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54190.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54190.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 54190.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 54190.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54190.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54190.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23f90]
>[ 54190.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23f90] width 1920 pitch 7680 (/4 1920)
>[ 54190.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3fd50]
>[ 54190.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3fd50] width 1920 pitch 7680 (/4 1920)
>[ 54190.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad9290]
>[ 54190.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad9290] width 1920 pitch 7680 (/4 1920)
>[ 54190.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54190.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54190.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f25740]
>[ 54190.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f25740] width 1920 pitch 7680 (/4 1920)
>[ 54190.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f170]
>[ 54190.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f170] width 1920 pitch 7680 (/4 1920)
>[ 54190.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc5080]
>[ 54190.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc5080] width 1920 pitch 7680 (/4 1920)
>[ 54191.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc5080]
>[ 54191.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc5080] width 1920 pitch 7680 (/4 1920)
>[ 54191.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54191.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54192.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54192.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54192.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54192.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54192.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54192.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54192.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54192.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54192.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54192.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54192.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54192.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54192.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54192.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54192.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54192.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54192.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4049670]
>[ 54192.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4049670] width 1920 pitch 7680 (/4 1920)
>[ 54192.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5135c80]
>[ 54192.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5135c80] width 1920 pitch 7680 (/4 1920)
>[ 54192.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54192.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54192.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 54192.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 54192.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e10]
>[ 54192.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e10] width 1920 pitch 7680 (/4 1920)
>[ 54515.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064fb0]
>[ 54515.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064fb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3f490]
>[ 54515.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3f490] width 1920 pitch 7680 (/4 1920)
>[ 54515.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02be0]
>[ 54515.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02be0] width 1920 pitch 7680 (/4 1920)
>[ 54515.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07bc0]
>[ 54515.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07bc0] width 1920 pitch 7680 (/4 1920)
>[ 54515.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3f490]
>[ 54515.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3f490] width 1920 pitch 7680 (/4 1920)
>[ 54515.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cb0]
>[ 54515.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cb0]
>[ 54515.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3f490]
>[ 54515.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3f490] width 1920 pitch 7680 (/4 1920)
>[ 54515.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea31f0]
>[ 54515.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea31f0] width 1920 pitch 7680 (/4 1920)
>[ 54515.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cb0]
>[ 54515.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cb0]
>[ 54515.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cb0]
>[ 54515.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cb0] width 1920 pitch 7680 (/4 1920)
>[ 54515.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3f490]
>[ 54515.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3f490] width 1920 pitch 7680 (/4 1920)
>[ 54515.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073c30]
>[ 54515.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073c30] width 1920 pitch 7680 (/4 1920)
>[ 54822.420] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 54822.420] (II) RADEON(0): Using hsync ranges from config file
>[ 54822.420] (II) RADEON(0): Using vrefresh ranges from config file
>[ 54822.420] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 54822.420] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 54822.420] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 54822.420] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 54822.421] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 54912.745] (II) RADEON(0): RADEONSaveScreen(2)
>[ 54912.745] (II) RADEON(0): RADEONSaveScreen(0)
>[ 68427.515] (II) RADEON(0): RADEONSaveScreen(1)
>[ 68442.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 68442.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 68738.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[ 68738.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[ 68738.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7d8f0]
>[ 68738.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7d8f0] width 1920 pitch 7680 (/4 1920)
>[ 69123.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 69123.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 69123.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69123.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69123.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69123.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69123.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69123.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69123.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 69123.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 69123.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69123.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69123.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69123.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69123.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69123.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69123.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 69123.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 69123.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69123.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69123.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 69123.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 69124.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 69124.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 69124.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59c40]
>[ 69124.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59c40] width 1920 pitch 7680 (/4 1920)
>[ 69124.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69124.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69126.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69126.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69126.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59c40]
>[ 69126.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59c40] width 1920 pitch 7680 (/4 1920)
>[ 69126.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8850]
>[ 69126.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8850] width 1920 pitch 7680 (/4 1920)
>[ 69126.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69126.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69126.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 69126.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 69126.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69126.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69126.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69126.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69127.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59c40]
>[ 69127.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59c40] width 1920 pitch 7680 (/4 1920)
>[ 69127.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69127.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69127.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69127.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69127.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69127.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69127.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69127.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69127.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69127.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69127.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69127.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69127.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69127.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69127.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69127.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69127.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69128.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69128.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69128.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69128.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69128.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69128.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 69128.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 69128.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69128.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69128.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3010]
>[ 69128.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3010] width 1920 pitch 7680 (/4 1920)
>[ 69128.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab790]
>[ 69128.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab790] width 1920 pitch 7680 (/4 1920)
>[ 69128.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69128.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69128.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69128.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69128.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69128.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69128.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69128.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69128.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69128.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69128.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69129.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69129.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69129.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69129.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69129.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69129.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[ 69129.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1920 pitch 7680 (/4 1920)
>[ 69129.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061820]
>[ 69129.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061820] width 1920 pitch 7680 (/4 1920)
>[ 69634.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69634.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69634.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69634.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69634.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b90]
>[ 69634.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b90] width 1920 pitch 7680 (/4 1920)
>[ 69634.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69634.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69634.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69634.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69634.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40405a0]
>[ 69634.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40405a0] width 1920 pitch 7680 (/4 1920)
>[ 69634.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69635.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69635.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40405a0]
>[ 69635.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40405a0] width 1920 pitch 7680 (/4 1920)
>[ 69635.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69635.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69635.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40405a0]
>[ 69635.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40405a0] width 1920 pitch 7680 (/4 1920)
>[ 69635.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69635.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69635.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40405a0]
>[ 69635.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40405a0] width 1920 pitch 7680 (/4 1920)
>[ 69635.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69635.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69635.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69635.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69635.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282abc0]
>[ 69635.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282abc0] width 1920 pitch 7680 (/4 1920)
>[ 69635.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69635.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69635.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1420]
>[ 69635.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1420] width 1920 pitch 7680 (/4 1920)
>[ 69635.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61870]
>[ 69635.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61870] width 1920 pitch 7680 (/4 1920)
>[ 69706.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1880]
>[ 69706.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1880] width 1920 pitch 7680 (/4 1920)
>[ 69708.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eecf60]
>[ 69708.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eecf60] width 1920 pitch 7680 (/4 1920)
>[ 69709.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a590]
>[ 69709.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a590] width 1920 pitch 7680 (/4 1920)
>[ 69709.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac630]
>[ 69709.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac630] width 1920 pitch 7680 (/4 1920)
>[ 69709.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92ee0]
>[ 69709.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92ee0] width 1920 pitch 7680 (/4 1920)
>[ 69709.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb3d80]
>[ 69709.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb3d80] width 1920 pitch 7680 (/4 1920)
>[ 69709.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0d40]
>[ 69709.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0d40] width 1920 pitch 7680 (/4 1920)
>[ 69709.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb31e0]
>[ 69709.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb31e0] width 1920 pitch 7680 (/4 1920)
>[ 69709.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adae00]
>[ 69709.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adae00] width 1920 pitch 7680 (/4 1920)
>[ 69709.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f66480]
>[ 69709.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f66480] width 1920 pitch 7680 (/4 1920)
>[ 69709.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69709.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01e80]
>[ 69709.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01e80] width 1920 pitch 7680 (/4 1920)
>[ 69709.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5a50]
>[ 69709.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5a50] width 1920 pitch 7680 (/4 1920)
>[ 69713.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc780]
>[ 69713.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc780] width 1920 pitch 7680 (/4 1920)
>[ 69713.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa3f0]
>[ 69713.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa3f0] width 1920 pitch 7680 (/4 1920)
>[ 69713.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa3f0]
>[ 69713.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa3f0] width 1920 pitch 7680 (/4 1920)
>[ 69713.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa3f0]
>[ 69713.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa3f0] width 1920 pitch 7680 (/4 1920)
>[ 69713.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa3f0]
>[ 69713.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa3f0] width 1920 pitch 7680 (/4 1920)
>[ 69713.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc750]
>[ 69713.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc750] width 1920 pitch 7680 (/4 1920)
>[ 69713.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa290]
>[ 69713.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa290] width 1920 pitch 7680 (/4 1920)
>[ 69713.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7bb80]
>[ 69713.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7bb80] width 1920 pitch 7680 (/4 1920)
>[ 69713.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69713.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69713.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7bb80]
>[ 69713.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7bb80] width 1920 pitch 7680 (/4 1920)
>[ 69713.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1480]
>[ 69714.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1480] width 1920 pitch 7680 (/4 1920)
>[ 69714.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa3f0]
>[ 69714.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa3f0] width 1920 pitch 7680 (/4 1920)
>[ 69714.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7bb80]
>[ 69714.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7bb80] width 1920 pitch 7680 (/4 1920)
>[ 69714.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed3b0]
>[ 69714.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed3b0] width 1920 pitch 7680 (/4 1920)
>[ 69733.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69733.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69733.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69733.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69733.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69733.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69733.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69733.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69733.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69733.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69733.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69733.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69733.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69733.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69733.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69733.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69733.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69734.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69734.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69734.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69734.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69734.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69734.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69734.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69734.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69735.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69735.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69735.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69735.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69735.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69735.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69735.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69735.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69736.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69736.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69736.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69736.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69736.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69736.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69736.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69736.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69737.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69737.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69737.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69737.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69737.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69737.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69738.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69738.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69738.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69738.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69738.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69738.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69738.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69738.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69739.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69739.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69739.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69739.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69739.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69739.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69739.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69739.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69740.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69740.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69740.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69740.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69740.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69740.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69740.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69740.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69740.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69740.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69741.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69741.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69741.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69741.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69741.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69741.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69741.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69741.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69741.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69741.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69742.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69742.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69742.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69742.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69742.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69742.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69742.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69742.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69742.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69742.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f0b0]
>[ 69743.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f0b0] width 1920 pitch 7680 (/4 1920)
>[ 69743.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69743.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69743.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69743.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69743.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3720]
>[ 69743.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3720] width 1920 pitch 7680 (/4 1920)
>[ 69743.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69743.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69743.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3720]
>[ 69743.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3720] width 1920 pitch 7680 (/4 1920)
>[ 69743.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69743.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69743.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69743.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69743.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69743.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69743.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af50]
>[ 69743.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af50] width 1920 pitch 7680 (/4 1920)
>[ 69743.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69743.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69743.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3720]
>[ 69743.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3720] width 1920 pitch 7680 (/4 1920)
>[ 69743.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69743.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69743.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69743.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69743.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69743.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69743.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69743.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69743.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5c140]
>[ 69743.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5c140] width 1920 pitch 7680 (/4 1920)
>[ 69743.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69743.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69743.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69743.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69743.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69743.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69743.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed08e0]
>[ 69743.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed08e0] width 1920 pitch 7680 (/4 1920)
>[ 69743.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69743.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69744.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eccbb0]
>[ 69744.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eccbb0] width 1920 pitch 7680 (/4 1920)
>[ 69744.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69744.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69744.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3720]
>[ 69744.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3720] width 1920 pitch 7680 (/4 1920)
>[ 69744.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69744.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69744.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69744.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69744.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69744.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69744.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eecf00]
>[ 69744.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eecf00] width 1920 pitch 7680 (/4 1920)
>[ 69745.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69745.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69745.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69745.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69746.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69746.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69746.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69746.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69746.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c12b0]
>[ 69746.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c12b0] width 1920 pitch 7680 (/4 1920)
>[ 69746.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69746.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69746.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69746.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69746.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c12b0]
>[ 69746.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c12b0] width 1920 pitch 7680 (/4 1920)
>[ 69746.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69746.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c090]
>[ 69746.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c090] width 1920 pitch 7680 (/4 1920)
>[ 69746.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 69746.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 69746.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e356c0]
>[ 69746.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e356c0] width 1920 pitch 7680 (/4 1920)
>[ 69781.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69781.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69781.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69781.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69782.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69782.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69782.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69782.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69782.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69782.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69782.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69782.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69782.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69782.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69782.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69782.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69782.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 69782.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 69782.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69782.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 69782.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 69782.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69782.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69782.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69782.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69782.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69782.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69782.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69782.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69782.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69782.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69782.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 69782.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 69782.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69782.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69782.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69782.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69782.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69782.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 69782.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 69782.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69782.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69782.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69782.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 69782.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 69782.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69782.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69782.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69782.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69782.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69782.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69782.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69782.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69782.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 69782.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 69782.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69782.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69782.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69782.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69782.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 69782.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 69783.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69783.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69783.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69783.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69783.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69783.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69783.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69783.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69783.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69783.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69783.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e526a0]
>[ 69783.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e526a0] width 1920 pitch 7680 (/4 1920)
>[ 69783.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 69783.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 69783.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69783.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69783.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69783.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69783.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 69783.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 69783.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69783.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69783.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69783.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69783.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17050]
>[ 69783.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17050] width 1920 pitch 7680 (/4 1920)
>[ 69783.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 69783.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 69783.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 69783.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 69783.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed4b0]
>[ 69783.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed4b0] width 1920 pitch 7680 (/4 1920)
>[ 69783.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 69783.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 69783.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0cc0]
>[ 69783.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0cc0] width 1920 pitch 7680 (/4 1920)
>[ 69786.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2b630]
>[ 69786.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2b630] width 1920 pitch 7680 (/4 1920)
>[ 69791.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053f20]
>[ 69791.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053f20] width 1920 pitch 7680 (/4 1920)
>[ 69791.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869180]
>[ 69791.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869180] width 1920 pitch 7680 (/4 1920)
>[ 69791.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0af20]
>[ 69791.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0af20] width 1920 pitch 7680 (/4 1920)
>[ 69791.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f620e0]
>[ 69791.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f620e0] width 1920 pitch 7680 (/4 1920)
>[ 69791.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264220]
>[ 69791.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264220] width 1920 pitch 7680 (/4 1920)
>[ 69791.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59f30]
>[ 69791.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59f30] width 1920 pitch 7680 (/4 1920)
>[ 70125.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee160]
>[ 70125.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee160] width 1920 pitch 7680 (/4 1920)
>[ 70126.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec8e80]
>[ 70126.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec8e80] width 1920 pitch 7680 (/4 1920)
>[ 70128.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33360]
>[ 70128.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33360] width 1920 pitch 7680 (/4 1920)
>[ 70128.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33360]
>[ 70128.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33360] width 1920 pitch 7680 (/4 1920)
>[ 70128.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404bde0]
>[ 70128.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404bde0] width 1920 pitch 7680 (/4 1920)
>[ 70128.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33360]
>[ 70128.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33360] width 1920 pitch 7680 (/4 1920)
>[ 70129.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57970]
>[ 70129.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57970] width 1920 pitch 7680 (/4 1920)
>[ 70129.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33360]
>[ 70129.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33360] width 1920 pitch 7680 (/4 1920)
>[ 70129.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57970]
>[ 70129.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57970] width 1920 pitch 7680 (/4 1920)
>[ 70166.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70166.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70166.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b6c0]
>[ 70166.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b6c0] width 1920 pitch 7680 (/4 1920)
>[ 70166.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 70166.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 70166.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70166.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70166.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70166.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70166.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402fad0]
>[ 70166.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402fad0] width 1920 pitch 7680 (/4 1920)
>[ 70166.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70166.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70166.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef530]
>[ 70166.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef530] width 1920 pitch 7680 (/4 1920)
>[ 70166.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 70166.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 70167.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70167.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70167.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70167.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70167.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70167.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70167.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b6c0]
>[ 70167.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b6c0] width 1920 pitch 7680 (/4 1920)
>[ 70167.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70167.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70167.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70167.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70167.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059160]
>[ 70167.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059160] width 1920 pitch 7680 (/4 1920)
>[ 70167.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2adb0]
>[ 70167.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2adb0] width 1920 pitch 7680 (/4 1920)
>[ 70167.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70167.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70167.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70167.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70167.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70167.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70167.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402fad0]
>[ 70167.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402fad0] width 1920 pitch 7680 (/4 1920)
>[ 70167.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70167.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70167.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70167.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70167.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70167.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70167.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b6c0]
>[ 70167.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b6c0] width 1920 pitch 7680 (/4 1920)
>[ 70167.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70167.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70167.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70167.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70167.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70167.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70167.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855080]
>[ 70167.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855080] width 1920 pitch 7680 (/4 1920)
>[ 70167.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085380]
>[ 70167.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085380] width 1920 pitch 7680 (/4 1920)
>[ 70167.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70167.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70167.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 70167.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 70167.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402fad0]
>[ 70167.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402fad0] width 1920 pitch 7680 (/4 1920)
>[ 70167.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70167.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70167.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70167.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70167.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70167.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70167.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70167.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70167.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 70167.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 70167.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70167.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70167.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70167.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70167.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 70167.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 70167.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70167.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70167.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059160]
>[ 70167.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059160] width 1920 pitch 7680 (/4 1920)
>[ 70167.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2adb0]
>[ 70167.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2adb0] width 1920 pitch 7680 (/4 1920)
>[ 70167.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70167.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70167.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70167.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70167.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70167.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70167.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70167.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70167.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70167.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70167.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef530]
>[ 70167.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef530] width 1920 pitch 7680 (/4 1920)
>[ 70167.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 70167.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 70168.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70168.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70168.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70168.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70168.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70168.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70168.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70168.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70168.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 70168.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 70168.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70168.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70168.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855080]
>[ 70168.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855080] width 1920 pitch 7680 (/4 1920)
>[ 70168.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70168.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70168.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70168.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70168.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70168.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70168.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7cab0]
>[ 70168.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7cab0] width 1920 pitch 7680 (/4 1920)
>[ 70168.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70168.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70168.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 70168.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 70168.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70168.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70168.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70168.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70168.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed0b10]
>[ 70168.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed0b10] width 1920 pitch 7680 (/4 1920)
>[ 70168.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70168.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70168.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059160]
>[ 70168.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059160] width 1920 pitch 7680 (/4 1920)
>[ 70168.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2adb0]
>[ 70168.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2adb0] width 1920 pitch 7680 (/4 1920)
>[ 70168.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085380]
>[ 70168.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085380] width 1920 pitch 7680 (/4 1920)
>[ 70168.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70168.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70168.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70168.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70168.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70168.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70168.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402fad0]
>[ 70168.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402fad0] width 1920 pitch 7680 (/4 1920)
>[ 70168.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef530]
>[ 70168.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef530] width 1920 pitch 7680 (/4 1920)
>[ 70168.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40468f0]
>[ 70168.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40468f0] width 1920 pitch 7680 (/4 1920)
>[ 70183.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70183.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70183.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70184.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70184.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b6c0]
>[ 70184.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b6c0] width 1920 pitch 7680 (/4 1920)
>[ 70184.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043320]
>[ 70184.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043320] width 1920 pitch 7680 (/4 1920)
>[ 70184.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 70184.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 70184.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70184.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70190.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70190.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70190.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70190.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70190.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef530]
>[ 70190.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef530] width 1920 pitch 7680 (/4 1920)
>[ 70190.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 70190.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 70190.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70190.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70190.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70191.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70191.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70191.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70191.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70191.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70191.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70191.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70191.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7cab0]
>[ 70191.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7cab0] width 1920 pitch 7680 (/4 1920)
>[ 70191.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70191.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70191.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70191.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70191.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70191.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70191.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70191.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70191.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70191.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70191.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef530]
>[ 70191.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef530] width 1920 pitch 7680 (/4 1920)
>[ 70191.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 70191.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 70191.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70191.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70196.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70196.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70196.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70196.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70197.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70197.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70197.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70197.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70197.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70197.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70197.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70197.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70197.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70197.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70197.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70197.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70197.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70197.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70197.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70197.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70197.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70197.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70197.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70197.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70197.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70197.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70197.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70197.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70205.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284eb70]
>[ 70205.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284eb70] width 1920 pitch 7680 (/4 1920)
>[ 70205.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2adb0]
>[ 70205.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2adb0] width 1920 pitch 7680 (/4 1920)
>[ 70205.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be190]
>[ 70205.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be190] width 1920 pitch 7680 (/4 1920)
>[ 70206.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 70206.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 70222.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 70222.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 70222.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70222.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70222.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70222.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbdb60]
>[ 70223.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbdb60] width 1920 pitch 7680 (/4 1920)
>[ 70223.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f63540]
>[ 70223.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f63540] width 1920 pitch 7680 (/4 1920)
>[ 70223.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e69ac0]
>[ 70223.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e69ac0] width 1920 pitch 7680 (/4 1920)
>[ 70223.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb510]
>[ 70223.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb510] width 1920 pitch 7680 (/4 1920)
>[ 70223.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9380]
>[ 70223.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9380] width 1920 pitch 7680 (/4 1920)
>[ 70223.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2c180]
>[ 70223.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2c180] width 1920 pitch 7680 (/4 1920)
>[ 70223.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f50a00]
>[ 70223.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f50a00] width 1920 pitch 7680 (/4 1920)
>[ 70223.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fec30]
>[ 70223.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fec30] width 1920 pitch 7680 (/4 1920)
>[ 70223.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc420]
>[ 70223.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc420] width 1920 pitch 7680 (/4 1920)
>[ 70223.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a51a0]
>[ 70223.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a51a0] width 1920 pitch 7680 (/4 1920)
>[ 70223.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40225c0]
>[ 70223.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40225c0] width 1920 pitch 7680 (/4 1920)
>[ 70223.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f167f0]
>[ 70223.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f167f0] width 1920 pitch 7680 (/4 1920)
>[ 70223.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fec30]
>[ 70223.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fec30] width 1920 pitch 7680 (/4 1920)
>[ 70223.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70223.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a240]
>[ 70223.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a240] width 1920 pitch 7680 (/4 1920)
>[ 70249.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc2750]
>[ 70249.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc2750] width 1920 pitch 7680 (/4 1920)
>[ 70249.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70249.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70249.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc2750]
>[ 70249.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc2750] width 1920 pitch 7680 (/4 1920)
>[ 70249.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70249.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70249.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc2750]
>[ 70249.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc2750] width 1920 pitch 7680 (/4 1920)
>[ 70249.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2830c30]
>[ 70249.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2830c30] width 1920 pitch 7680 (/4 1920)
>[ 70249.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7e080]
>[ 70249.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7e080] width 1920 pitch 7680 (/4 1920)
>[ 70249.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70249.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70249.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7e080]
>[ 70249.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7e080] width 1920 pitch 7680 (/4 1920)
>[ 70250.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbdb60]
>[ 70250.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbdb60] width 1920 pitch 7680 (/4 1920)
>[ 70250.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25110]
>[ 70250.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25110] width 1920 pitch 7680 (/4 1920)
>[ 70250.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70250.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70250.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70250.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70250.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70250.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70250.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70251.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70251.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc50e0]
>[ 70251.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc50e0] width 1920 pitch 7680 (/4 1920)
>[ 70251.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70251.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70251.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70252.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70252.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70252.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70252.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70253.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70253.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70253.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70253.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70254.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70254.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70254.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70254.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70255.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70255.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70255.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70255.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70256.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70256.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70256.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70256.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70257.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70257.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70257.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70257.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70258.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70258.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70258.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70258.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70259.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70259.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70259.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70259.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70260.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70260.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70260.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70260.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70261.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70261.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70261.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70261.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70262.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70262.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70262.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70262.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70263.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70263.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70263.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28340d0]
>[ 70263.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28340d0] width 1920 pitch 7680 (/4 1920)
>[ 70275.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b7d0]
>[ 70275.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b7d0] width 1920 pitch 7680 (/4 1920)
>[ 70275.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 70275.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 70276.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70276.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70276.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace940]
>[ 70276.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace940] width 1920 pitch 7680 (/4 1920)
>[ 70276.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70276.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70276.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd5e0]
>[ 70276.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd5e0] width 1920 pitch 7680 (/4 1920)
>[ 70276.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70276.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70276.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 70276.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 70276.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 70276.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 70276.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70276.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70276.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 70276.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 70276.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5e4a0]
>[ 70276.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5e4a0] width 1920 pitch 7680 (/4 1920)
>[ 70276.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e640]
>[ 70276.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e640] width 1920 pitch 7680 (/4 1920)
>[ 70276.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 70276.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 70276.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50590e0]
>[ 70276.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50590e0] width 1920 pitch 7680 (/4 1920)
>[ 70276.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c68eb0]
>[ 70276.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c68eb0] width 1920 pitch 7680 (/4 1920)
>[ 70276.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5eb0]
>[ 70276.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5eb0] width 1920 pitch 7680 (/4 1920)
>[ 70276.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2adb0]
>[ 70276.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2adb0] width 1920 pitch 7680 (/4 1920)
>[ 70276.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace940]
>[ 70276.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace940] width 1920 pitch 7680 (/4 1920)
>[ 70276.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70276.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70276.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7cab0]
>[ 70276.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7cab0] width 1920 pitch 7680 (/4 1920)
>[ 70276.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70276.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70276.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504c120]
>[ 70276.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504c120] width 1920 pitch 7680 (/4 1920)
>[ 70276.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 70276.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 70276.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 70276.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 70276.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b7d0]
>[ 70276.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b7d0] width 1920 pitch 7680 (/4 1920)
>[ 70276.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0c600]
>[ 70276.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0c600] width 1920 pitch 7680 (/4 1920)
>[ 70276.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70a20]
>[ 70276.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70a20] width 1920 pitch 7680 (/4 1920)
>[ 70276.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70276.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70276.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147520]
>[ 70276.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147520] width 1920 pitch 7680 (/4 1920)
>[ 70276.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1820]
>[ 70276.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1820] width 1920 pitch 7680 (/4 1920)
>[ 70314.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147520]
>[ 70314.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147520] width 1920 pitch 7680 (/4 1920)
>[ 70314.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7470]
>[ 70314.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7470] width 1920 pitch 7680 (/4 1920)
>[ 70315.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 70315.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 70315.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147520]
>[ 70315.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147520] width 1920 pitch 7680 (/4 1920)
>[ 70315.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 70315.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 70315.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5e4a0]
>[ 70315.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5e4a0] width 1920 pitch 7680 (/4 1920)
>[ 70318.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70318.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70318.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[ 70318.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1920 pitch 7680 (/4 1920)
>[ 70319.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63ca0]
>[ 70319.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63ca0] width 1920 pitch 7680 (/4 1920)
>[ 70319.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9de0]
>[ 70319.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9de0] width 1920 pitch 7680 (/4 1920)
>[ 70319.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70319.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70319.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70319.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70319.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 70319.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 70319.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 70319.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 70319.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70319.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70319.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70319.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70319.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70319.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70319.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70319.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70319.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9de0]
>[ 70319.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9de0] width 1920 pitch 7680 (/4 1920)
>[ 70319.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa50d0]
>[ 70319.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa50d0] width 1920 pitch 7680 (/4 1920)
>[ 70319.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2b090]
>[ 70319.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2b090] width 1920 pitch 7680 (/4 1920)
>[ 70322.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284e110]
>[ 70322.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284e110] width 1920 pitch 7680 (/4 1920)
>[ 70322.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f15990]
>[ 70322.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f15990] width 1920 pitch 7680 (/4 1920)
>[ 70322.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 70322.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 70467.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057640]
>[ 70467.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057640] width 1920 pitch 7680 (/4 1920)
>[ 70467.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70467.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70468.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b830]
>[ 70468.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b830] width 1920 pitch 7680 (/4 1920)
>[ 70468.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 70468.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 70468.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d27c0]
>[ 70468.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d27c0] width 1920 pitch 7680 (/4 1920)
>[ 70468.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 70468.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 70468.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70468.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70468.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70468.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70469.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70469.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70469.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab6e0]
>[ 70469.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab6e0] width 1920 pitch 7680 (/4 1920)
>[ 70470.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 70470.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 70470.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fad430]
>[ 70470.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fad430] width 1920 pitch 7680 (/4 1920)
>[ 70470.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 70470.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 70470.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f15990]
>[ 70470.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f15990] width 1920 pitch 7680 (/4 1920)
>[ 70470.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70470.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70470.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 70470.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 70470.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab6e0]
>[ 70470.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab6e0] width 1920 pitch 7680 (/4 1920)
>[ 70470.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29ed0]
>[ 70470.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29ed0] width 1920 pitch 7680 (/4 1920)
>[ 70470.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70470.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70470.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 70470.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 70470.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 70470.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 70470.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 70470.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 70470.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70470.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70470.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70470.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70470.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70470.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70470.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 70470.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 70470.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 70470.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 70470.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 70470.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 70470.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70470.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70470.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2b090]
>[ 70470.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2b090] width 1920 pitch 7680 (/4 1920)
>[ 70470.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 70470.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 70470.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 70470.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 70470.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 70470.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 70470.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70470.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70470.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5eb0]
>[ 70470.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5eb0] width 1920 pitch 7680 (/4 1920)
>[ 70470.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e640]
>[ 70470.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e640] width 1920 pitch 7680 (/4 1920)
>[ 70470.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 70470.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 70470.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 70470.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 70470.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e873c0]
>[ 70470.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e873c0] width 1920 pitch 7680 (/4 1920)
>[ 70470.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f15990]
>[ 70470.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f15990] width 1920 pitch 7680 (/4 1920)
>[ 70470.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70470.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70470.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 70470.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 70470.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab6e0]
>[ 70471.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab6e0] width 1920 pitch 7680 (/4 1920)
>[ 70471.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29ed0]
>[ 70471.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29ed0] width 1920 pitch 7680 (/4 1920)
>[ 70471.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70471.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70471.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 70471.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 70471.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 70471.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 70471.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 70471.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 70471.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70471.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70471.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70471.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70471.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70471.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70471.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50451f0]
>[ 70471.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50451f0] width 1920 pitch 7680 (/4 1920)
>[ 70473.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 70473.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 70473.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 70473.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 70474.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70474.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70474.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70474.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70474.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70474.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70474.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70474.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70474.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70475.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70475.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70475.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70475.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70475.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70475.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70475.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70475.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70475.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70475.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70475.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70475.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 70475.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 70475.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512b9f0]
>[ 70475.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512b9f0] width 1920 pitch 7680 (/4 1920)
>[ 70475.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70475.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70475.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70475.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70475.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70475.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70476.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 70476.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 70476.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 70476.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 70476.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 70476.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 70476.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 70476.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 70476.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa50d0]
>[ 70476.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa50d0] width 1920 pitch 7680 (/4 1920)
>[ 70476.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70476.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70476.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5eb0]
>[ 70476.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5eb0] width 1920 pitch 7680 (/4 1920)
>[ 70476.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70476.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70476.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70476.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70476.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70476.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70499.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b340]
>[ 70499.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b340] width 1920 pitch 7680 (/4 1920)
>[ 70598.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f606b0]
>[ 70598.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f606b0] width 1920 pitch 7680 (/4 1920)
>[ 70641.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3130]
>[ 70641.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3130] width 1920 pitch 7680 (/4 1920)
>[ 70641.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f100]
>[ 70641.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f100] width 1920 pitch 7680 (/4 1920)
>[ 70641.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70642.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70642.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[ 70642.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1920 pitch 7680 (/4 1920)
>[ 70643.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70643.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c617a0]
>[ 70643.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c617a0] width 1920 pitch 7680 (/4 1920)
>[ 70647.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70647.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70647.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074d10]
>[ 70647.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074d10] width 1920 pitch 7680 (/4 1920)
>[ 70647.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 70647.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 70648.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23bf0]
>[ 70648.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23bf0] width 1920 pitch 7680 (/4 1920)
>[ 70648.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f141a0]
>[ 70648.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f141a0] width 1920 pitch 7680 (/4 1920)
>[ 70648.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70648.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70648.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70648.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70648.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70648.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 70648.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 70648.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 70648.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 70649.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 70649.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 70649.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e873c0]
>[ 70649.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e873c0] width 1920 pitch 7680 (/4 1920)
>[ 70649.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70649.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70649.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70649.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70649.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70649.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70649.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70649.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70649.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70649.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70649.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c010]
>[ 70649.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c010] width 1920 pitch 7680 (/4 1920)
>[ 70649.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70649.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70649.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 70649.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 70649.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70649.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70649.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e873c0]
>[ 70649.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e873c0] width 1920 pitch 7680 (/4 1920)
>[ 70649.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 70649.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 70649.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70649.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70649.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa4170]
>[ 70649.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa4170] width 1920 pitch 7680 (/4 1920)
>[ 70650.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa4170]
>[ 70650.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa4170] width 1920 pitch 7680 (/4 1920)
>[ 70650.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 70650.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 70650.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70650.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70650.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60d70]
>[ 70650.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60d70] width 1920 pitch 7680 (/4 1920)
>[ 70650.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70650.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70650.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60d70]
>[ 70650.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60d70] width 1920 pitch 7680 (/4 1920)
>[ 70650.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70650.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70650.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60d70]
>[ 70650.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60d70] width 1920 pitch 7680 (/4 1920)
>[ 70650.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70650.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70650.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60d70]
>[ 70650.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60d70] width 1920 pitch 7680 (/4 1920)
>[ 70735.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e35600]
>[ 70735.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e35600] width 1920 pitch 7680 (/4 1920)
>[ 70736.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60d70]
>[ 70736.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60d70] width 1920 pitch 7680 (/4 1920)
>[ 70737.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22a30]
>[ 70737.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22a30] width 1920 pitch 7680 (/4 1920)
>[ 70737.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e09cb0]
>[ 70737.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e09cb0] width 1920 pitch 7680 (/4 1920)
>[ 70740.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70740.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70740.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 70740.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 70740.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70740.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70740.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 70740.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 70740.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70740.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70740.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70740.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70740.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 70740.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 70740.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70740.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70740.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70740.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70740.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 70740.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 70740.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70740.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70740.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56ab0]
>[ 70740.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56ab0] width 1920 pitch 7680 (/4 1920)
>[ 70740.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70740.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70740.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70740.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70740.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70740.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70740.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4ca0]
>[ 70740.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4ca0] width 1920 pitch 7680 (/4 1920)
>[ 70740.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505dc70]
>[ 70740.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505dc70] width 1920 pitch 7680 (/4 1920)
>[ 70740.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5050]
>[ 70740.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5050] width 1920 pitch 7680 (/4 1920)
>[ 70740.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5085380]
>[ 70740.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5085380] width 1920 pitch 7680 (/4 1920)
>[ 70740.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 70740.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 70740.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa50d0]
>[ 70740.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa50d0] width 1920 pitch 7680 (/4 1920)
>[ 70740.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70740.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70740.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70740.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70740.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828270]
>[ 70740.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828270] width 1920 pitch 7680 (/4 1920)
>[ 70740.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 70740.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 70740.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 70741.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 70741.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70741.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70741.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 70741.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 70741.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70741.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70741.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 70741.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 70741.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286fdc0]
>[ 70741.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286fdc0] width 1920 pitch 7680 (/4 1920)
>[ 70754.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f080c0]
>[ 70754.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f080c0] width 1920 pitch 7680 (/4 1920)
>[ 70868.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec50f0]
>[ 70868.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec50f0] width 1920 pitch 7680 (/4 1920)
>[ 70869.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7aad0]
>[ 70869.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7aad0] width 1920 pitch 7680 (/4 1920)
>[ 70874.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70874.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70874.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61c30]
>[ 70874.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61c30] width 1920 pitch 7680 (/4 1920)
>[ 70874.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70874.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70874.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea85b0]
>[ 70874.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea85b0] width 1920 pitch 7680 (/4 1920)
>[ 70874.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70874.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70874.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70874.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70874.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94f40]
>[ 70874.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94f40] width 1920 pitch 7680 (/4 1920)
>[ 70874.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286fdc0]
>[ 70874.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286fdc0] width 1920 pitch 7680 (/4 1920)
>[ 70874.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61c30]
>[ 70874.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61c30] width 1920 pitch 7680 (/4 1920)
>[ 70874.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 70874.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 70874.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 70874.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 70874.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61270]
>[ 70874.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61270] width 1920 pitch 7680 (/4 1920)
>[ 70874.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[ 70874.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[ 70874.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa50d0]
>[ 70874.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa50d0] width 1920 pitch 7680 (/4 1920)
>[ 70874.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70874.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70874.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 70874.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 70874.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70874.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70874.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5050]
>[ 70874.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5050] width 1920 pitch 7680 (/4 1920)
>[ 70874.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3cfc0]
>[ 70874.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3cfc0] width 1920 pitch 7680 (/4 1920)
>[ 70874.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70874.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70874.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb440]
>[ 70874.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb440] width 1920 pitch 7680 (/4 1920)
>[ 70891.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f310c0]
>[ 70891.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f310c0] width 1920 pitch 7680 (/4 1920)
>[ 70932.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87fb0]
>[ 70932.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87fb0] width 1920 pitch 7680 (/4 1920)
>[ 70934.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed60]
>[ 70934.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed60] width 1920 pitch 7680 (/4 1920)
>[ 70934.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62570]
>[ 70934.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62570] width 1920 pitch 7680 (/4 1920)
>[ 70934.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e6e0]
>[ 70934.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e6e0] width 1920 pitch 7680 (/4 1920)
>[ 70934.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa4f90]
>[ 70934.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa4f90] width 1920 pitch 7680 (/4 1920)
>[ 70962.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f2c0]
>[ 70962.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f2c0] width 1920 pitch 7680 (/4 1920)
>[ 70964.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6ffc0]
>[ 70964.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6ffc0] width 1920 pitch 7680 (/4 1920)
>[ 70964.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5074df0]
>[ 70964.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5074df0] width 1920 pitch 7680 (/4 1920)
>[ 70964.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 70964.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 70964.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 70964.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 70964.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70964.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70964.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 70964.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 70964.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505dc70]
>[ 70964.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505dc70] width 1920 pitch 7680 (/4 1920)
>[ 70964.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2fa80]
>[ 70964.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2fa80] width 1920 pitch 7680 (/4 1920)
>[ 70964.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b239c0]
>[ 70964.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b239c0] width 1920 pitch 7680 (/4 1920)
>[ 70972.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51102f0]
>[ 70972.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51102f0] width 1920 pitch 7680 (/4 1920)
>[ 70972.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[ 70972.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[ 70972.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 70972.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 70972.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e850]
>[ 70972.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e850] width 1920 pitch 7680 (/4 1920)
>[ 70972.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 70972.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 70972.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 70972.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 70972.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94f40]
>[ 70972.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94f40] width 1920 pitch 7680 (/4 1920)
>[ 70972.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c648f0]
>[ 70972.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c648f0] width 1920 pitch 7680 (/4 1920)
>[ 70972.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 70972.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 70972.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 70972.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 70972.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 70972.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 70972.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 70972.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 70972.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 70972.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 70974.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94f40]
>[ 70974.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94f40] width 1920 pitch 7680 (/4 1920)
>[ 70974.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56ab0]
>[ 70974.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56ab0] width 1920 pitch 7680 (/4 1920)
>[ 70974.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bb20]
>[ 70974.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bb20] width 1920 pitch 7680 (/4 1920)
>[ 70975.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80b70]
>[ 70975.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80b70] width 1920 pitch 7680 (/4 1920)
>[ 70975.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e770]
>[ 70975.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e770] width 1920 pitch 7680 (/4 1920)
>[ 70975.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9320]
>[ 70975.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9320] width 1920 pitch 7680 (/4 1920)
>[ 70975.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4fd20]
>[ 70975.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4fd20] width 1920 pitch 7680 (/4 1920)
>[ 70975.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3815da0]
>[ 70975.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3815da0] width 1920 pitch 7680 (/4 1920)
>[ 70975.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283e850]
>[ 70975.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283e850] width 1920 pitch 7680 (/4 1920)
>[ 70975.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e1d0]
>[ 70975.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e1d0] width 1920 pitch 7680 (/4 1920)
>[ 70975.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5fad0]
>[ 70975.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5fad0] width 1920 pitch 7680 (/4 1920)
>[ 70975.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0020]
>[ 70975.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0020] width 1920 pitch 7680 (/4 1920)
>[ 70975.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9310]
>[ 70975.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9310] width 1920 pitch 7680 (/4 1920)
>[ 70975.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b290]
>[ 70975.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b290] width 1920 pitch 7680 (/4 1920)
>[ 70984.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3815da0]
>[ 70984.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3815da0] width 1920 pitch 7680 (/4 1920)
>[ 70984.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2d60]
>[ 70984.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2d60] width 1920 pitch 7680 (/4 1920)
>[ 70986.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2d60]
>[ 70986.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2d60] width 1920 pitch 7680 (/4 1920)
>[ 70986.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeea30]
>[ 70986.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeea30] width 1920 pitch 7680 (/4 1920)
>[ 70986.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22a60]
>[ 70986.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22a60] width 1920 pitch 7680 (/4 1920)
>[ 70986.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2d60]
>[ 70987.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2d60] width 1920 pitch 7680 (/4 1920)
>[ 70987.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa6a20]
>[ 70987.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa6a20] width 1920 pitch 7680 (/4 1920)
>[ 71018.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2d60]
>[ 71018.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2d60] width 1920 pitch 7680 (/4 1920)
>[ 71019.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 71019.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 71020.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5eb0]
>[ 71020.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5eb0] width 1920 pitch 7680 (/4 1920)
>[ 71020.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 71020.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 71020.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 71020.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 71020.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61c30]
>[ 71020.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61c30] width 1920 pitch 7680 (/4 1920)
>[ 71020.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71020.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71020.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71020.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71020.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 71020.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 71020.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 71020.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 71020.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 71020.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 71020.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 71020.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 71020.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[ 71020.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[ 71020.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 71020.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 71020.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 71020.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 71020.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 71020.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 71020.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19b40]
>[ 71020.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19b40] width 1920 pitch 7680 (/4 1920)
>[ 71020.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5eb0]
>[ 71020.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5eb0] width 1920 pitch 7680 (/4 1920)
>[ 71020.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 71020.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 71020.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61c30]
>[ 71020.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61c30] width 1920 pitch 7680 (/4 1920)
>[ 71020.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71020.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71020.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71020.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71020.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 71020.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 71020.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 71020.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 71020.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 71020.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 71020.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 71020.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 71020.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[ 71020.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[ 71020.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 71020.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 71020.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 71020.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 71020.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 71020.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 71020.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 71020.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 71021.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 71021.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 71021.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61c30]
>[ 71021.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61c30] width 1920 pitch 7680 (/4 1920)
>[ 71021.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71021.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71021.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71021.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71021.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a50b0]
>[ 71021.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a50b0] width 1920 pitch 7680 (/4 1920)
>[ 71021.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 71021.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 71021.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 71021.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 71021.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 71021.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 71021.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[ 71021.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[ 71021.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f79a50]
>[ 71021.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f79a50] width 1920 pitch 7680 (/4 1920)
>[ 71021.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 71021.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 71021.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 71021.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 71021.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71021.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71022.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71022.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71022.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[ 71022.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1920 pitch 7680 (/4 1920)
>[ 71022.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71022.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71041.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[ 71041.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[ 71041.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 71041.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 71042.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505dc70]
>[ 71042.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505dc70] width 1920 pitch 7680 (/4 1920)
>[ 71042.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 71042.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 71042.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 71042.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 71042.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdf20]
>[ 71042.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdf20] width 1920 pitch 7680 (/4 1920)
>[ 71042.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e10]
>[ 71042.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e10] width 1920 pitch 7680 (/4 1920)
>[ 71042.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71110]
>[ 71042.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71110] width 1920 pitch 7680 (/4 1920)
>[ 71042.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f343a0]
>[ 71042.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f343a0] width 1920 pitch 7680 (/4 1920)
>[ 71042.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939b20]
>[ 71042.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939b20] width 1920 pitch 7680 (/4 1920)
>[ 71042.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4ca0]
>[ 71042.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4ca0] width 1920 pitch 7680 (/4 1920)
>[ 71042.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62a70]
>[ 71042.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62a70] width 1920 pitch 7680 (/4 1920)
>[ 71042.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa50d0]
>[ 71042.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa50d0] width 1920 pitch 7680 (/4 1920)
>[ 71042.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395ca40]
>[ 71042.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395ca40] width 1920 pitch 7680 (/4 1920)
>[ 71053.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71053.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71053.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71053.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71054.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ada8b0]
>[ 71054.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ada8b0] width 1920 pitch 7680 (/4 1920)
>[ 71054.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71054.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71058.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dec20]
>[ 71058.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dec20] width 1920 pitch 7680 (/4 1920)
>[ 71058.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f2a0]
>[ 71058.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f2a0] width 1920 pitch 7680 (/4 1920)
>[ 71059.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 71059.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 71069.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea0830]
>[ 71070.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea0830] width 1920 pitch 7680 (/4 1920)
>[ 71108.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa6c40]
>[ 71108.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa6c40] width 1920 pitch 7680 (/4 1920)
>[ 71108.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec6530]
>[ 71108.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec6530] width 1920 pitch 7680 (/4 1920)
>[ 71109.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeea30]
>[ 71109.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeea30] width 1920 pitch 7680 (/4 1920)
>[ 71109.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71109.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71109.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71109.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71109.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71109.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71109.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71109.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71110.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3590]
>[ 71110.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3590] width 1920 pitch 7680 (/4 1920)
>[ 71110.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3958860]
>[ 71110.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3958860] width 1920 pitch 7680 (/4 1920)
>[ 71132.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061420]
>[ 71132.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061420] width 1920 pitch 7680 (/4 1920)
>[ 71132.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08390]
>[ 71132.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08390] width 1920 pitch 7680 (/4 1920)
>[ 71132.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e396d0]
>[ 71132.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e396d0] width 1920 pitch 7680 (/4 1920)
>[ 71132.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82b50]
>[ 71132.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82b50] width 1920 pitch 7680 (/4 1920)
>[ 71132.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 71132.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 71133.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82b50]
>[ 71133.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82b50] width 1920 pitch 7680 (/4 1920)
>[ 71134.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 71134.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 71134.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e83010]
>[ 71134.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e83010] width 1920 pitch 7680 (/4 1920)
>[ 71134.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 71134.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 71134.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b7d0]
>[ 71134.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b7d0] width 1920 pitch 7680 (/4 1920)
>[ 71134.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3afc0]
>[ 71134.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3afc0] width 1920 pitch 7680 (/4 1920)
>[ 71134.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 71134.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 71134.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b7d0]
>[ 71134.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b7d0] width 1920 pitch 7680 (/4 1920)
>[ 71134.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3afc0]
>[ 71134.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3afc0] width 1920 pitch 7680 (/4 1920)
>[ 71134.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 71134.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 71134.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b7d0]
>[ 71134.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b7d0] width 1920 pitch 7680 (/4 1920)
>[ 71134.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3afc0]
>[ 71134.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3afc0] width 1920 pitch 7680 (/4 1920)
>[ 71134.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 71134.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 71134.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b7d0]
>[ 71134.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b7d0] width 1920 pitch 7680 (/4 1920)
>[ 71134.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3afc0]
>[ 71134.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3afc0] width 1920 pitch 7680 (/4 1920)
>[ 71250.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71250.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71250.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71250.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71251.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71251.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71251.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71284.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71284.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71284.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[ 71284.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[ 71285.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a820]
>[ 71285.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a820] width 1920 pitch 7680 (/4 1920)
>[ 71285.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2874a20]
>[ 71285.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2874a20] width 1920 pitch 7680 (/4 1920)
>[ 71285.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 71285.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 71285.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f26b0]
>[ 71285.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f26b0] width 1920 pitch 7680 (/4 1920)
>[ 71285.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cb20]
>[ 71285.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cb20] width 1920 pitch 7680 (/4 1920)
>[ 71285.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71285.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71285.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8df0]
>[ 71285.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8df0] width 1920 pitch 7680 (/4 1920)
>[ 71285.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb0a0]
>[ 71285.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb0a0] width 1920 pitch 7680 (/4 1920)
>[ 71285.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 71285.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 71285.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 71285.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 71285.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecde10]
>[ 71285.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecde10] width 1920 pitch 7680 (/4 1920)
>[ 71285.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71285.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71285.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71285.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71285.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e99de0]
>[ 71285.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e99de0] width 1920 pitch 7680 (/4 1920)
>[ 71285.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2a80]
>[ 71285.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2a80] width 1920 pitch 7680 (/4 1920)
>[ 71285.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51331b0]
>[ 71285.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51331b0] width 1920 pitch 7680 (/4 1920)
>[ 71285.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef61e0]
>[ 71285.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef61e0] width 1920 pitch 7680 (/4 1920)
>[ 71285.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 71285.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 71285.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[ 71285.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1920 pitch 7680 (/4 1920)
>[ 71285.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fac040]
>[ 71285.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fac040] width 1920 pitch 7680 (/4 1920)
>[ 71285.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a820]
>[ 71286.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a820] width 1920 pitch 7680 (/4 1920)
>[ 71286.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71286.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71286.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 71286.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 71286.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 71286.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 71286.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[ 71286.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[ 71286.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56c20]
>[ 71286.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56c20] width 1920 pitch 7680 (/4 1920)
>[ 71286.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71286.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71286.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 71286.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 71286.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 71286.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 71286.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecde10]
>[ 71286.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecde10] width 1920 pitch 7680 (/4 1920)
>[ 71286.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71286.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71286.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71286.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71286.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077ca0]
>[ 71286.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077ca0] width 1920 pitch 7680 (/4 1920)
>[ 71286.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e99de0]
>[ 71286.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e99de0] width 1920 pitch 7680 (/4 1920)
>[ 71286.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2a80]
>[ 71286.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2a80] width 1920 pitch 7680 (/4 1920)
>[ 71286.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb42e0]
>[ 71286.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb42e0] width 1920 pitch 7680 (/4 1920)
>[ 71286.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51331b0]
>[ 71286.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51331b0] width 1920 pitch 7680 (/4 1920)
>[ 71286.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 71286.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 71286.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 71286.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 71286.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb530]
>[ 71286.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb530] width 1920 pitch 7680 (/4 1920)
>[ 71286.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2874a20]
>[ 71286.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2874a20] width 1920 pitch 7680 (/4 1920)
>[ 71286.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 71286.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 71286.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f26b0]
>[ 71286.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f26b0] width 1920 pitch 7680 (/4 1920)
>[ 71286.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cb20]
>[ 71286.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cb20] width 1920 pitch 7680 (/4 1920)
>[ 71286.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71286.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71286.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8df0]
>[ 71286.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8df0] width 1920 pitch 7680 (/4 1920)
>[ 71286.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 71286.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 71286.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 71286.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 71286.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b260]
>[ 71286.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b260] width 1920 pitch 7680 (/4 1920)
>[ 71286.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecde10]
>[ 71286.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecde10] width 1920 pitch 7680 (/4 1920)
>[ 71286.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71286.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71286.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71286.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71286.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e99de0]
>[ 71287.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e99de0] width 1920 pitch 7680 (/4 1920)
>[ 71287.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2a80]
>[ 71287.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2a80] width 1920 pitch 7680 (/4 1920)
>[ 71287.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb42e0]
>[ 71287.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb42e0] width 1920 pitch 7680 (/4 1920)
>[ 71287.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51331b0]
>[ 71287.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51331b0] width 1920 pitch 7680 (/4 1920)
>[ 71287.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee0070]
>[ 71287.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee0070] width 1920 pitch 7680 (/4 1920)
>[ 71287.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 71287.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 71287.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 71287.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 71287.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb530]
>[ 71287.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb530] width 1920 pitch 7680 (/4 1920)
>[ 71287.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2874a20]
>[ 71287.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2874a20] width 1920 pitch 7680 (/4 1920)
>[ 71287.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 71287.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 71287.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f26b0]
>[ 71287.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f26b0] width 1920 pitch 7680 (/4 1920)
>[ 71287.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cb20]
>[ 71287.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cb20] width 1920 pitch 7680 (/4 1920)
>[ 71287.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71287.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71287.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8df0]
>[ 71287.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8df0] width 1920 pitch 7680 (/4 1920)
>[ 71287.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 71287.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 71287.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71287.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71287.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecde10]
>[ 71287.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecde10] width 1920 pitch 7680 (/4 1920)
>[ 71287.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71287.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71287.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71287.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71287.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e99de0]
>[ 71287.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e99de0] width 1920 pitch 7680 (/4 1920)
>[ 71287.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2a80]
>[ 71287.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2a80] width 1920 pitch 7680 (/4 1920)
>[ 71287.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb42e0]
>[ 71287.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb42e0] width 1920 pitch 7680 (/4 1920)
>[ 71287.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee0070]
>[ 71287.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee0070] width 1920 pitch 7680 (/4 1920)
>[ 71287.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9540]
>[ 71287.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9540] width 1920 pitch 7680 (/4 1920)
>[ 71287.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 71287.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 71307.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cb20]
>[ 71307.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cb20] width 1920 pitch 7680 (/4 1920)
>[ 71307.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9cb20]
>[ 71307.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9cb20] width 1920 pitch 7680 (/4 1920)
>[ 71308.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 71308.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 71308.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 71308.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 71308.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71308.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71308.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71309.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71309.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71309.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71309.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71309.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71309.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71309.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71309.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71309.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71309.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71309.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71309.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71309.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71309.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71309.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71309.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71309.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71318.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71318.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71318.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee0070]
>[ 71318.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee0070] width 1920 pitch 7680 (/4 1920)
>[ 71319.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 71319.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 71319.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2a80]
>[ 71319.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2a80] width 1920 pitch 7680 (/4 1920)
>[ 71319.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077ca0]
>[ 71319.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077ca0] width 1920 pitch 7680 (/4 1920)
>[ 71319.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f87d00]
>[ 71319.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f87d00] width 1920 pitch 7680 (/4 1920)
>[ 71319.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee0070]
>[ 71319.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee0070] width 1920 pitch 7680 (/4 1920)
>[ 71319.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51331b0]
>[ 71319.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51331b0] width 1920 pitch 7680 (/4 1920)
>[ 71319.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb530]
>[ 71319.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb530] width 1920 pitch 7680 (/4 1920)
>[ 71319.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fac040]
>[ 71319.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fac040] width 1920 pitch 7680 (/4 1920)
>[ 71319.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93f70]
>[ 71319.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93f70] width 1920 pitch 7680 (/4 1920)
>[ 71319.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[ 71319.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1920 pitch 7680 (/4 1920)
>[ 71319.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8df0]
>[ 71319.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8df0] width 1920 pitch 7680 (/4 1920)
>[ 71319.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 71319.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 71319.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 71319.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 71319.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e56c20]
>[ 71319.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e56c20] width 1920 pitch 7680 (/4 1920)
>[ 71319.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 71319.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 71319.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71319.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71319.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 71319.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 71319.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e99de0]
>[ 71319.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e99de0] width 1920 pitch 7680 (/4 1920)
>[ 71319.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b4d0]
>[ 71319.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b4d0] width 1920 pitch 7680 (/4 1920)
>[ 71320.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb42e0]
>[ 71320.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb42e0] width 1920 pitch 7680 (/4 1920)
>[ 71320.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f15b80]
>[ 71320.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f15b80] width 1920 pitch 7680 (/4 1920)
>[ 71320.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2874a20]
>[ 71320.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2874a20] width 1920 pitch 7680 (/4 1920)
>[ 71320.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 71320.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 71320.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[ 71320.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1920 pitch 7680 (/4 1920)
>[ 71320.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 71320.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 71320.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef61e0]
>[ 71320.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef61e0] width 1920 pitch 7680 (/4 1920)
>[ 71320.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71320.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71320.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a820]
>[ 71320.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a820] width 1920 pitch 7680 (/4 1920)
>[ 71320.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 71320.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 71320.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f784f0]
>[ 71320.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f784f0] width 1920 pitch 7680 (/4 1920)
>[ 71320.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb0a0]
>[ 71320.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb0a0] width 1920 pitch 7680 (/4 1920)
>[ 71320.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71320.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71320.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b260]
>[ 71320.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b260] width 1920 pitch 7680 (/4 1920)
>[ 71320.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71320.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71350.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71350.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71350.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71350.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71350.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71350.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71350.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71350.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71350.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71351.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71351.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71351.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71351.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71351.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71351.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71351.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71351.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 71351.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 71351.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c550c0]
>[ 71351.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c550c0] width 1920 pitch 7680 (/4 1920)
>[ 71351.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eafa00]
>[ 71351.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eafa00] width 1920 pitch 7680 (/4 1920)
>[ 71352.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e873a0]
>[ 71352.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e873a0] width 1920 pitch 7680 (/4 1920)
>[ 71352.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e873a0]
>[ 71352.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e873a0] width 1920 pitch 7680 (/4 1920)
>[ 71352.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfa990]
>[ 71352.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfa990] width 1920 pitch 7680 (/4 1920)
>[ 71352.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfa990]
>[ 71352.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfa990] width 1920 pitch 7680 (/4 1920)
>[ 71352.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc43e0]
>[ 71352.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc43e0] width 1920 pitch 7680 (/4 1920)
>[ 71380.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eed760]
>[ 71380.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eed760] width 1920 pitch 7680 (/4 1920)
>[ 71380.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71380.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71380.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 71380.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 71380.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eed760]
>[ 71380.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eed760] width 1920 pitch 7680 (/4 1920)
>[ 71380.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 71380.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 71380.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eed760]
>[ 71380.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eed760] width 1920 pitch 7680 (/4 1920)
>[ 71380.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246a0]
>[ 71380.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246a0] width 1920 pitch 7680 (/4 1920)
>[ 71380.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71380.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71380.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246a0]
>[ 71380.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246a0] width 1920 pitch 7680 (/4 1920)
>[ 71380.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71380.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71380.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71380.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71380.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 71380.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 71380.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71380.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71380.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71380.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71381.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfead0]
>[ 71381.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfead0] width 1920 pitch 7680 (/4 1920)
>[ 71381.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71381.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71381.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee0070]
>[ 71381.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee0070] width 1920 pitch 7680 (/4 1920)
>[ 71381.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71381.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71381.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 71381.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 71381.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16dd0]
>[ 71381.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16dd0] width 1920 pitch 7680 (/4 1920)
>[ 71381.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 71381.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 71381.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb280]
>[ 71381.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb280] width 1920 pitch 7680 (/4 1920)
>[ 71382.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 71382.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 71382.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c594e0]
>[ 71382.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c594e0] width 1920 pitch 7680 (/4 1920)
>[ 71382.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdf50]
>[ 71382.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdf50] width 1920 pitch 7680 (/4 1920)
>[ 71425.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71425.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71427.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6eed0]
>[ 71427.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6eed0] width 1920 pitch 7680 (/4 1920)
>[ 71427.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3f740]
>[ 71427.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3f740] width 1920 pitch 7680 (/4 1920)
>[ 71427.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed58d0]
>[ 71427.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed58d0] width 1920 pitch 7680 (/4 1920)
>[ 71427.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7ff0]
>[ 71427.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7ff0] width 1920 pitch 7680 (/4 1920)
>[ 71427.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 71427.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 71427.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 71427.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 71427.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 71427.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 71427.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 71427.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 71427.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011100]
>[ 71427.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011100] width 1920 pitch 7680 (/4 1920)
>[ 71427.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71427.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71427.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efeb80]
>[ 71427.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efeb80] width 1920 pitch 7680 (/4 1920)
>[ 71427.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e880]
>[ 71427.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e880] width 1920 pitch 7680 (/4 1920)
>[ 71427.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db710]
>[ 71427.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db710] width 1920 pitch 7680 (/4 1920)
>[ 71427.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e880]
>[ 71427.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e880] width 1920 pitch 7680 (/4 1920)
>[ 71427.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d590]
>[ 71427.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d590] width 1920 pitch 7680 (/4 1920)
>[ 71427.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efeb80]
>[ 71427.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efeb80] width 1920 pitch 7680 (/4 1920)
>[ 71427.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d590]
>[ 71427.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d590] width 1920 pitch 7680 (/4 1920)
>[ 71447.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0130]
>[ 71447.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0130] width 1920 pitch 7680 (/4 1920)
>[ 71447.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4940]
>[ 71447.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4940] width 1920 pitch 7680 (/4 1920)
>[ 71447.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4b70]
>[ 71447.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4b70] width 1920 pitch 7680 (/4 1920)
>[ 71447.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71447.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71447.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71447.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71447.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71447.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71447.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71447.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71447.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71447.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71447.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4a10]
>[ 71448.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4a10] width 1920 pitch 7680 (/4 1920)
>[ 71461.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe6f0]
>[ 71461.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe6f0] width 1920 pitch 7680 (/4 1920)
>[ 71461.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42ce0]
>[ 71461.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42ce0] width 1920 pitch 7680 (/4 1920)
>[ 71461.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71461.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71461.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42ce0]
>[ 71461.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42ce0] width 1920 pitch 7680 (/4 1920)
>[ 71461.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed58d0]
>[ 71461.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed58d0] width 1920 pitch 7680 (/4 1920)
>[ 71461.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42ce0]
>[ 71461.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42ce0] width 1920 pitch 7680 (/4 1920)
>[ 71461.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71461.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71461.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b330]
>[ 71461.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b330] width 1920 pitch 7680 (/4 1920)
>[ 71461.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3f740]
>[ 71461.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3f740] width 1920 pitch 7680 (/4 1920)
>[ 71461.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71461.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71461.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe6f0]
>[ 71461.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe6f0] width 1920 pitch 7680 (/4 1920)
>[ 71461.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b330]
>[ 71461.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b330] width 1920 pitch 7680 (/4 1920)
>[ 71461.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b330]
>[ 71461.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b330] width 1920 pitch 7680 (/4 1920)
>[ 71461.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71461.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71461.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71461.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71461.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71461.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71462.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71462.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71462.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71462.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71462.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71462.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71462.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe6f0]
>[ 71462.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe6f0] width 1920 pitch 7680 (/4 1920)
>[ 71462.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71462.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71462.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71462.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71462.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71462.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71462.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe6f0]
>[ 71462.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe6f0] width 1920 pitch 7680 (/4 1920)
>[ 71462.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71462.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71462.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71462.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71462.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71462.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71462.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71462.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71462.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71462.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71462.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71462.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe6f0]
>[ 71462.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe6f0] width 1920 pitch 7680 (/4 1920)
>[ 71462.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43c70]
>[ 71462.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43c70] width 1920 pitch 7680 (/4 1920)
>[ 71513.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71513.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71513.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71514.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71514.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71514.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71514.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71515.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71515.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71515.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71515.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71515.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71515.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71515.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63d70]
>[ 71515.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63d70] width 1920 pitch 7680 (/4 1920)
>[ 71515.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f09c50]
>[ 71515.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f09c50] width 1920 pitch 7680 (/4 1920)
>[ 71515.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdfb0]
>[ 71515.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdfb0] width 1920 pitch 7680 (/4 1920)
>[ 71515.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdfb0]
>[ 71515.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdfb0] width 1920 pitch 7680 (/4 1920)
>[ 71562.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eec360]
>[ 71562.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eec360] width 1920 pitch 7680 (/4 1920)
>[ 71562.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71562.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71562.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71562.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71562.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71562.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71562.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71562.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71562.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71562.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71562.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71562.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71562.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71562.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71562.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71562.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71563.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71563.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71563.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71563.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71563.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71563.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71563.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71563.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71563.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71563.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71563.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71563.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71563.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71563.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71563.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71563.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71563.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71563.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71563.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71563.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71563.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71563.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71563.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71563.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71563.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71563.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71563.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71563.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71563.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71563.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71563.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71563.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71563.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71563.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71563.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71563.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71563.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71563.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71563.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71563.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71563.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71563.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71563.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71563.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71563.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71563.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71563.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71563.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71563.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71563.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71563.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71563.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71563.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71563.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71563.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71563.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71563.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71563.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71563.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71563.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71564.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71564.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71564.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71564.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71564.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71564.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71564.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71564.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71564.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71564.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71564.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71564.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71564.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71564.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71564.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71564.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71564.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71564.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71564.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71564.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71564.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71564.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71564.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71564.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71564.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71564.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71564.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71564.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71564.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71564.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71564.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71564.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71564.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71564.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71564.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71564.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71564.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71564.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71564.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71564.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71564.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71564.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71564.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71564.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71564.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eec360]
>[ 71564.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eec360] width 1920 pitch 7680 (/4 1920)
>[ 71564.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71564.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71564.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71564.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71565.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71565.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71565.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71565.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71565.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71565.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71566.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71566.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71566.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71566.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71566.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71566.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71566.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71566.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71566.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71566.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71566.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71566.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71566.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71566.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71566.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71566.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71566.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71566.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71566.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71566.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71566.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71566.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71566.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71566.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71566.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71566.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71566.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71566.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71566.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71566.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71566.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71566.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71566.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71566.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71566.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71566.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71566.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71566.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71566.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71566.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71566.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71566.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71566.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71566.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71566.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71567.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71567.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71567.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71567.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71567.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71567.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71567.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71567.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71567.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71567.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71567.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71567.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71567.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71567.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71567.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71567.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71567.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71567.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71567.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71567.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71567.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71567.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71567.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71567.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71567.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71567.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71567.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71567.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71567.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71567.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71567.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71567.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71567.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71567.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71567.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71567.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71567.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71567.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71567.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71567.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71567.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71567.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71567.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71567.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71567.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71567.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71567.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71567.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71567.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71567.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71567.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71567.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71567.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71567.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71567.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71567.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71567.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71567.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71567.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71567.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71568.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71568.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71568.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71568.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71568.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71568.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71568.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71568.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71568.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71568.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71568.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71568.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71568.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71568.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71568.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71568.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71568.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71568.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71568.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71568.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71568.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71568.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71568.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71568.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71568.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71568.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71568.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71568.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71568.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71568.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71568.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71568.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71568.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71568.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71568.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71568.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71568.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71568.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71568.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71568.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71568.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71568.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71568.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71568.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6a70]
>[ 71568.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6a70] width 1920 pitch 7680 (/4 1920)
>[ 71568.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71568.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71568.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71568.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71568.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71568.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71568.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71568.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71568.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71568.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71568.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71568.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71568.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71568.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71568.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71568.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71568.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71568.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71569.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71569.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71569.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71569.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71569.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71569.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71569.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71569.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71569.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71569.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71569.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71569.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71569.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71569.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71569.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71569.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71569.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71569.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71569.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71569.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71569.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71569.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71569.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71569.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71569.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71569.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71569.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71569.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71569.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71569.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71569.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71569.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71569.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71569.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71569.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71569.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71569.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71569.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71569.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71569.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71569.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71569.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71569.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71569.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71569.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71569.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71569.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71569.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71569.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71569.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71569.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71569.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71569.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71569.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71569.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71569.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71569.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71569.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71569.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71569.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71569.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71569.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71569.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71569.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71570.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71570.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71570.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71570.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71570.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71570.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71570.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71570.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71570.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71570.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71570.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71570.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71570.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71570.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71570.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71570.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71570.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71570.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71570.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71570.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71570.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71570.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71570.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71570.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71570.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71570.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71570.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71570.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71570.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71570.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71570.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71570.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71570.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71570.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71570.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71570.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71570.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71570.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71570.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71570.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71570.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71570.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71570.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71570.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71570.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71570.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71570.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71570.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71570.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71570.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71570.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71570.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71570.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71570.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71570.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71570.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71570.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71570.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71570.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71570.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71570.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71570.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71570.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71570.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71571.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71571.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71571.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71571.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71571.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71571.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71571.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71571.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71571.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71571.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71571.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71571.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71571.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71571.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71571.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71571.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71571.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71572.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71572.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71572.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71572.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71572.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71572.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71572.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71572.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71572.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1170]
>[ 71572.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1170] width 1920 pitch 7680 (/4 1920)
>[ 71572.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c3e0]
>[ 71572.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c3e0] width 1920 pitch 7680 (/4 1920)
>[ 71628.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71628.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71628.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71629.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71629.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71629.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71629.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71629.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71629.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71629.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71629.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71629.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71629.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71629.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71629.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71629.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71629.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71629.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71629.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71629.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71629.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71629.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71629.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71629.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71629.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71629.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71629.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71630.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71630.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71630.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71630.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71630.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71630.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71630.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71630.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71630.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71630.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71630.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71630.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71630.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71630.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71630.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71630.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71630.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71630.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71630.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71630.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71630.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71630.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71630.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71630.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71630.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71630.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71630.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71630.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71630.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71630.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71630.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71630.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71630.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71630.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71630.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71630.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71630.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71630.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71630.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71630.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71630.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71630.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71630.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71630.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71630.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71630.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71630.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71630.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71630.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71630.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71630.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71630.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71630.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71630.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71630.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71630.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71630.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71630.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71630.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71631.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71631.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71631.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71631.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71631.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71631.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71631.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71631.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71631.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71631.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71631.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71631.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71631.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71631.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71631.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71631.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71631.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71631.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71631.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71631.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71631.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71631.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71631.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71631.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71631.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71631.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71631.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71631.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71631.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71631.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71631.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71631.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71631.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71631.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71631.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71631.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71631.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71631.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71631.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71631.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71631.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71631.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71631.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71631.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71631.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71631.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71631.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71631.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71631.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71631.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71631.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71631.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71631.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71631.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71631.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71631.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71631.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71631.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71631.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71631.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71631.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71631.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71632.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71632.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71632.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71632.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71632.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71632.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71632.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71632.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71632.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71632.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71632.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71632.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71632.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71632.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71632.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71632.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71632.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71632.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71632.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71632.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71632.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71632.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71632.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71632.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71632.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71632.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71632.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71632.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71632.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71632.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71632.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71632.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71632.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71632.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71632.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71632.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71632.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71632.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71632.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71632.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71632.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71632.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71632.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71632.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71632.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71632.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71632.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71632.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71632.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71632.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71632.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71632.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71632.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71632.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71632.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71632.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71632.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71632.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71632.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71632.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71633.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71633.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71633.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71633.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71633.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71633.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71633.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71633.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71633.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71633.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71633.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71633.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71633.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71633.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71633.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71633.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71633.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71633.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71633.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71633.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71633.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71633.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71633.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71633.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71633.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71633.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71633.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71633.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71633.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71633.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71633.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71633.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71633.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71633.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71633.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71633.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71633.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71633.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71633.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71633.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71633.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71633.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71633.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71633.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71633.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71633.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71633.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71633.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71633.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71633.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71633.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71633.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71633.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71633.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71633.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71633.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71633.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71633.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71633.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71633.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71633.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71633.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71634.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71634.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71634.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71634.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71634.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71634.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71634.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71634.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71634.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71634.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71634.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71634.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71634.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71634.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71634.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71634.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71634.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71634.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71634.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71634.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71634.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71634.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71634.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71634.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71634.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71634.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71634.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71634.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71634.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71634.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71634.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71634.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71634.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71634.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71634.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71634.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71634.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71634.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71634.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71634.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71634.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71634.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71634.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71634.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71634.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71634.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71634.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71634.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71634.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71634.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71634.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71634.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71634.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71634.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71634.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71634.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71634.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71634.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71634.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71634.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71635.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71635.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71635.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71635.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71635.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71635.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71635.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71635.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71635.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71635.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71635.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71635.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71635.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71635.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71635.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71635.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71635.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71635.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71635.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71635.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71635.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71635.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71635.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71635.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71635.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71635.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71635.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71635.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71635.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71635.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71635.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71635.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71635.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71635.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71635.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71635.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71635.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71635.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71635.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71635.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71635.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71635.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71635.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71635.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71635.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71635.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71635.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71635.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71635.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71635.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71635.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71635.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71635.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71635.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71635.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71635.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71635.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71635.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71635.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71635.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71635.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71635.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71636.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71636.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71636.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71636.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71636.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71636.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71636.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71636.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71636.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71636.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71636.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71636.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71636.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71636.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71636.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71636.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71636.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71636.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71636.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71636.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71636.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71636.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71636.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71636.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71636.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71636.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71636.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71636.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71636.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71636.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71636.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71636.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71636.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71636.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71636.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71636.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71636.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71636.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71636.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71636.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71636.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71636.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71636.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71636.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71636.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71636.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71636.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71636.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71636.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71636.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71636.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71636.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71636.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71636.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71636.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71636.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71636.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71636.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71636.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71636.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71636.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71636.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71637.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71637.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71637.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71637.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71637.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71637.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71637.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71637.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71637.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71637.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71637.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71637.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71637.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71637.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71637.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71637.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71637.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71637.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71637.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71637.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71637.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71637.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71637.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71637.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71637.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71637.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71637.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71637.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71637.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71637.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71637.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71637.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71637.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71637.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71637.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71637.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71637.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71637.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71637.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71637.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71637.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71637.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71637.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71637.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71637.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71637.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71637.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71637.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71637.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71637.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71637.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71637.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71637.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71637.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71637.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71637.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71637.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71637.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71637.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71637.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71637.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71637.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71637.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71638.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71638.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71638.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71638.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71638.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71638.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71638.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71638.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71638.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71638.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71638.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71638.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71638.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71638.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71638.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71638.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71638.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71638.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71638.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71638.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71638.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71638.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71638.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71638.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71638.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71638.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71638.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71638.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71638.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71638.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71638.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71638.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71638.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71638.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71638.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71638.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71638.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71638.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71638.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71638.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71638.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71638.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71638.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71638.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71638.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71638.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71638.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71638.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71638.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71638.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e050e0]
>[ 71638.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e050e0] width 1920 pitch 7680 (/4 1920)
>[ 71638.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71638.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71638.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71638.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71638.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71638.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71638.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71638.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71638.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71638.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71638.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71638.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71638.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71639.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71639.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71639.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71639.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71639.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71640.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71640.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71640.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087900]
>[ 71640.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087900] width 1920 pitch 7680 (/4 1920)
>[ 71640.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087900]
>[ 71640.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087900] width 1920 pitch 7680 (/4 1920)
>[ 71640.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087900]
>[ 71640.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087900] width 1920 pitch 7680 (/4 1920)
>[ 71640.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087900]
>[ 71640.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087900] width 1920 pitch 7680 (/4 1920)
>[ 71640.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5087900]
>[ 71640.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5087900] width 1920 pitch 7680 (/4 1920)
>[ 71640.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71640.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71640.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71640.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71678.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71678.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71679.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71679.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71680.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71680.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71680.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71680.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71680.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71680.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71680.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71680.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71680.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71680.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71680.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71680.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71680.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71680.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71680.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71680.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71680.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71680.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71680.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71680.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71680.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71680.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71680.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71680.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71680.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71680.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71680.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71680.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71680.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71680.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71680.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71680.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71680.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71680.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71680.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71680.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71680.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71680.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71680.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71680.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71680.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71680.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71680.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71680.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71680.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71680.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71680.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71680.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71680.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71680.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71680.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71680.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71680.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71680.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71680.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71680.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71681.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71681.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71681.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71681.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71681.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71681.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71681.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71681.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71681.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71681.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71681.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71681.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71681.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c710]
>[ 71681.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c710] width 1920 pitch 7680 (/4 1920)
>[ 71681.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71681.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71681.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510ea90]
>[ 71681.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510ea90] width 1920 pitch 7680 (/4 1920)
>[ 71681.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71681.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71681.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71681.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71681.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71681.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71681.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71681.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71681.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71681.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71681.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71681.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71681.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71681.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71681.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71681.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71681.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 71681.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 71681.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71681.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71681.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71681.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71681.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71681.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71681.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71681.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71681.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71681.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71681.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71681.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71681.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71681.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71681.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71681.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71681.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71681.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71681.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71681.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71681.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71681.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71681.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71681.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71681.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71681.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71681.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71682.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71682.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71682.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71682.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71682.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71682.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71682.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71682.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71682.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71682.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71682.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71682.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71682.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71682.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71682.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71682.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71682.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71682.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71682.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71682.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71682.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71682.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71682.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71682.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71682.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71682.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71682.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71682.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71682.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71682.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71682.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71682.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71682.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71682.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71682.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71682.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71682.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71705.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71705.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71705.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71705.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71705.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71705.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71705.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71705.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71705.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71705.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71705.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71705.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71705.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 71705.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 71705.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71705.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71705.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71706.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71706.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71706.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71706.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71706.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71706.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71706.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71706.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71706.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71706.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71706.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71707.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b9f0]
>[ 71707.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b9f0] width 1920 pitch 7680 (/4 1920)
>[ 71765.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71765.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71765.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71765.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71766.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71766.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71766.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71766.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71766.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71766.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71766.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71766.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71766.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71766.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71766.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71766.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71766.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71766.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71766.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71766.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71766.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71766.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71766.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71766.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71766.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71766.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71766.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71766.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71766.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71766.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71766.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71766.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71766.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71766.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71766.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71766.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71766.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71766.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71766.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71766.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71766.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71766.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71766.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71766.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71766.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71766.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71766.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71766.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71766.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71766.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71766.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71766.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71766.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71766.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71766.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71766.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71766.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71766.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71766.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71766.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71766.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71766.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71767.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71767.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71767.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71767.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71767.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71767.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71767.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71767.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71767.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71767.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71767.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71767.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71767.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71767.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71767.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71767.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71767.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71767.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71767.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71767.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71767.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71767.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71767.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71767.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71767.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71767.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71767.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71767.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71767.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71767.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71767.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71767.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71767.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71767.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71767.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71767.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71767.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71767.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71767.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71767.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71767.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71767.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71767.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71767.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71767.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71767.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71767.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71767.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71767.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71767.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71767.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71767.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71767.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71767.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71767.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71767.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71767.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71767.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71767.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71767.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71767.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71767.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71767.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71768.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71768.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71768.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71768.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71768.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71768.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71768.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71768.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71768.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71768.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71768.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71768.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71768.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71768.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71768.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71768.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71768.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71768.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71768.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71768.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71768.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71768.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71768.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71768.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71768.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71768.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71768.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71768.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71768.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71768.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71768.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71768.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71768.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71768.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71768.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71768.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71768.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71768.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71768.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71768.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71768.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71768.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71768.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71768.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71768.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71768.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71768.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71768.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71768.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71768.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71768.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71768.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71768.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71768.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71768.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71768.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71768.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71768.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71768.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71768.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71768.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71768.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71768.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71769.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71769.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71769.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71769.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71769.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71769.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71769.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71769.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71769.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71769.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71769.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71769.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71769.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71769.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71769.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71769.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71769.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71769.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71769.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71769.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71769.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71769.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71769.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71769.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71769.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71769.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71769.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71769.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71769.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71769.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71769.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71769.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71769.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71769.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71769.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71769.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71769.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71769.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71769.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71769.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71769.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71769.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71769.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71769.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71769.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71769.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71769.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71769.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71769.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71769.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71769.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71769.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71769.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71769.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71769.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71769.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71769.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71769.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71769.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71769.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71769.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71769.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71769.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71770.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71770.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71770.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71770.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71770.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71770.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71770.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71770.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71770.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71770.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71770.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71770.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71770.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71770.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71770.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71770.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71770.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71770.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71770.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71770.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71770.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71770.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71770.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71770.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71770.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71770.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71770.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71770.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71770.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71770.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71770.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71770.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71770.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71770.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71770.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71770.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71770.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71770.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71770.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71770.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71770.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71770.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71770.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71770.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71770.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71770.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71770.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71770.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71770.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71770.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71770.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71770.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71770.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71770.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71770.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71770.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71770.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71770.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71770.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71770.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71770.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71770.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71770.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71770.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71770.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71771.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71771.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71771.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71771.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71771.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71771.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71771.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71771.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71771.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71771.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71771.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71771.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71771.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71771.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71771.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71771.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71771.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71771.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71771.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71771.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71771.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71771.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71771.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71771.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71771.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71771.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71771.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71771.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71771.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71771.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71771.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71771.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71771.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71771.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71771.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71771.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71771.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71771.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71771.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71771.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71771.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71771.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71771.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71771.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71771.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71771.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71771.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71771.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71771.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71771.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71771.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71771.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71771.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71771.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71771.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71771.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71771.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71771.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71771.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71771.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71771.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71771.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71771.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71771.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71772.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71772.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71772.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71772.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71772.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71772.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71772.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71772.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71772.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71772.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71772.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71772.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71772.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71772.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71772.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71772.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71772.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71772.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71772.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71772.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71772.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71772.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71772.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71772.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71772.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71772.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71772.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71772.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71772.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71772.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71772.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71772.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71772.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71772.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71772.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71772.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71772.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71772.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71772.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71772.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71772.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71772.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71772.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71772.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71772.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71772.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71772.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71772.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71772.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71772.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71772.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71772.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71772.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71772.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71772.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71772.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71772.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71772.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71772.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71772.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71772.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71772.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71772.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71772.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71773.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71773.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71773.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71773.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71773.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71773.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71773.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71773.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71773.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71773.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71773.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71773.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71773.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71773.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71773.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71773.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71773.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71773.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71773.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71773.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71773.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71773.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71773.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71773.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71773.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71773.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71773.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71773.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71773.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71773.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71773.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71773.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71773.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71773.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71773.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71773.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71773.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71773.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71773.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71773.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71773.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71773.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71773.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71773.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71773.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71773.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71773.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71773.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71773.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71773.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71773.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71773.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71773.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71773.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71773.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71773.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71773.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71773.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71773.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71773.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71773.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71773.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71774.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71774.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71774.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71774.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71774.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71774.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71774.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71774.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71774.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71774.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71774.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71774.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71774.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71774.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71774.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71774.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71774.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71774.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71774.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71774.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71774.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71774.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71774.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71774.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71774.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71774.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71774.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71774.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71774.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71774.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71774.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71774.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71774.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71774.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71774.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71774.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71774.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71774.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71774.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71774.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71774.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71774.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71774.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71774.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71774.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71774.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71774.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71774.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71774.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71774.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71774.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71774.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71774.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71774.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71774.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71774.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71774.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71774.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71774.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71774.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71774.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71774.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71774.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71775.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71775.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71775.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71775.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71775.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71775.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71775.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71775.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71775.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71775.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71775.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71775.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71775.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71775.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71775.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71775.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71775.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71775.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71775.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71775.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71775.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71775.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71775.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71775.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71775.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71775.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71775.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71775.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71775.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71775.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71775.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71775.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71775.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71775.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71775.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71775.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71775.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71775.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71775.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71775.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71775.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71775.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71775.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71775.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71775.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71775.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71775.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71775.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71775.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71775.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71775.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71775.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71775.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71775.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71775.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71775.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71775.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71775.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71775.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71775.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71775.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71775.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71775.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71775.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71776.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71776.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71776.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71776.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71776.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71776.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71776.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71776.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71776.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71776.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71776.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71776.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71776.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71776.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71776.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71776.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71776.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71776.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71776.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71776.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71776.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71776.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71776.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71776.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71776.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71776.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71776.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71776.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71776.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71776.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71776.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71776.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71776.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71776.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71776.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71776.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71776.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71776.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71776.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71776.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71776.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71776.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2857cb0]
>[ 71776.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2857cb0] width 1920 pitch 7680 (/4 1920)
>[ 71776.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71776.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71776.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71776.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71776.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71776.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71776.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71776.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71776.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71776.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71776.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71776.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71776.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71776.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71776.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71776.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71776.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71776.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71776.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71776.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71776.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71777.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71777.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71777.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71777.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71777.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71777.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71777.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71777.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71777.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71777.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71777.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71777.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71777.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71777.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71777.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71777.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71777.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71777.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71777.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71777.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71777.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71777.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71777.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71777.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71777.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71777.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71777.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71777.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71777.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71777.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71777.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71777.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71777.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71777.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71777.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71777.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71777.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71777.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71777.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71777.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71777.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71777.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71777.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71777.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71777.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71777.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71777.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71777.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71777.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71777.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71777.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71777.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71777.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71777.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71777.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71777.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71777.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71816.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71816.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71816.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71816.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71817.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71817.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71817.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71817.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71817.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71817.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71818.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71818.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71818.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71818.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71818.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71818.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71818.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71818.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71818.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71818.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71818.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71818.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71818.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71818.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71818.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71818.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71818.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71818.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71818.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71818.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71818.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71818.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71818.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71818.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71818.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71818.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71818.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71818.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71818.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71818.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71818.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71818.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71818.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71818.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71818.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71818.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71818.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71818.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71818.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71818.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71818.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71818.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71818.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71818.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71818.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71818.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71818.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71818.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71818.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71818.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71818.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71818.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71818.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71818.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71818.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71818.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71818.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71818.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71818.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71818.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71818.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71818.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71818.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71818.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71819.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71819.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71819.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71819.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71819.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71819.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71819.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71819.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71819.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71819.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71819.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71819.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71819.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71819.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71819.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71819.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71819.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71819.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71819.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71819.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71819.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71819.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71819.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c609f0]
>[ 71819.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c609f0] width 1920 pitch 7680 (/4 1920)
>[ 71820.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71820.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71820.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71820.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71820.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71820.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71820.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71820.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71820.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71820.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71820.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c609f0]
>[ 71820.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c609f0] width 1920 pitch 7680 (/4 1920)
>[ 71820.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71820.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71820.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71820.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71820.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71820.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71820.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71820.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71820.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71820.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71820.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71820.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71820.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71820.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71820.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c609f0]
>[ 71820.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c609f0] width 1920 pitch 7680 (/4 1920)
>[ 71820.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71820.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71820.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71820.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71820.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71820.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71820.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c609f0]
>[ 71820.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c609f0] width 1920 pitch 7680 (/4 1920)
>[ 71820.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71820.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71820.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71820.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71820.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71820.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71820.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71820.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71820.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71820.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71820.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71820.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71820.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828540]
>[ 71820.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828540] width 1920 pitch 7680 (/4 1920)
>[ 71820.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c609f0]
>[ 71820.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c609f0] width 1920 pitch 7680 (/4 1920)
>[ 71820.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71820.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71820.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71820.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71820.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71820.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71820.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71821.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71821.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71821.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71821.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71821.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71822.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ab70]
>[ 71822.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ab70] width 1920 pitch 7680 (/4 1920)
>[ 71822.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71822.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71823.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71823.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71823.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71823.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71823.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71823.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71823.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71823.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71823.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71823.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71823.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71823.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71823.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71823.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71823.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71823.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71823.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71823.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71823.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71823.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71823.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71823.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71823.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71823.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71823.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71823.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71823.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71823.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71823.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71823.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71823.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71823.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71823.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71823.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71823.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71823.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71823.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71823.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71823.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71823.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71823.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71824.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71824.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71824.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71824.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71824.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71824.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71824.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71824.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71824.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71824.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71824.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71824.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71824.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71824.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71824.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71824.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71824.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71824.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71824.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71824.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71824.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71824.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71824.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71824.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71824.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71824.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71824.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71824.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71824.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71824.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71824.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71824.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71824.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71824.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71824.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71824.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71824.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71824.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71824.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71824.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71824.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71824.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71824.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71824.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71824.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71824.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71824.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71824.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71824.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71824.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71824.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71824.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71824.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71824.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71824.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71824.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71824.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71824.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71824.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71824.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71824.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71824.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71824.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71824.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71825.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71825.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71825.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71825.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71825.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71825.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71825.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71825.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71825.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71825.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71825.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71825.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71825.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71825.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71825.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71825.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71825.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71825.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71825.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71825.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71825.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71825.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71825.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71825.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71825.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71825.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71825.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71825.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71825.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71825.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71825.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71825.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71825.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71825.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71825.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71825.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71825.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71825.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71825.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71825.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71825.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71825.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71825.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71825.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71825.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71825.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71825.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71825.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71825.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71825.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71825.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71825.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71825.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71825.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71825.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71825.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71825.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71825.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71825.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71825.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71825.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71825.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71825.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71825.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71826.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71826.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71826.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71826.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71826.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71826.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71826.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71826.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71826.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71826.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71826.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71826.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71826.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71826.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71826.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71826.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71826.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71826.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71826.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71826.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71826.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71826.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71826.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71826.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71826.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71826.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71826.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71826.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71826.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71826.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71826.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71826.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71826.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71826.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71826.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71826.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71826.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71826.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71826.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71826.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71826.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71826.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71826.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71826.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71826.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71826.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71826.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71826.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71826.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71826.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71826.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71826.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71826.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71826.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71826.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71826.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71826.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71826.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71826.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71826.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71826.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71826.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71826.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71827.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71827.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71827.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71827.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71827.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40435f0]
>[ 71827.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40435f0] width 1920 pitch 7680 (/4 1920)
>[ 71827.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71827.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71827.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71827.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71827.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71827.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71827.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71827.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71827.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71827.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71827.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71827.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71827.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71827.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71827.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71827.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71827.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71827.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71827.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71827.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71827.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71827.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71827.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71827.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71827.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71827.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71827.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71827.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71827.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71827.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71827.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71827.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71827.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71827.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71827.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71827.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71827.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71827.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71827.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71827.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71827.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71827.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71827.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71827.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71827.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71827.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71827.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53f70]
>[ 71827.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53f70] width 1920 pitch 7680 (/4 1920)
>[ 71828.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71828.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71828.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71828.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71832.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71832.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71832.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71832.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71833.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee8db0]
>[ 71833.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee8db0] width 1920 pitch 7680 (/4 1920)
>[ 71833.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71833.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71833.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71833.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71833.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71833.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71833.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71833.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71833.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71833.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71833.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71833.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71833.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71833.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71833.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71833.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71833.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71833.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71833.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71833.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71833.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71833.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71833.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71833.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71833.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71833.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71833.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71833.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71833.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71833.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71833.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71833.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71833.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71833.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71833.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71833.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71833.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71833.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71833.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71833.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71833.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71833.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71833.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71833.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71833.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71833.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71833.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71833.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71833.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71833.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71834.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71834.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71834.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71834.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71834.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71834.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71834.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71834.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71834.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71834.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71834.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71834.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71834.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71834.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71834.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71834.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71834.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71834.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71834.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71834.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71835.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71835.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71835.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea37e0]
>[ 71835.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea37e0] width 1920 pitch 7680 (/4 1920)
>[ 71835.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71835.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71835.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71835.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71835.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71835.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71835.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71835.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71835.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71835.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71835.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71835.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71835.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71835.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71835.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71835.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71835.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71844.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71844.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71844.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71844.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71845.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71845.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71845.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71845.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71845.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71845.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71845.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71845.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71845.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a45c0]
>[ 71845.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a45c0] width 1920 pitch 7680 (/4 1920)
>[ 71845.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71845.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71845.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71845.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71845.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71845.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71845.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71845.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71845.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71845.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71845.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71845.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71845.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71845.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71845.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71846.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71846.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71846.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71846.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71846.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71846.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71846.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71846.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71846.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71846.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71846.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71846.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71846.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71846.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71846.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71846.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71846.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71846.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71846.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71846.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71846.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71846.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 71846.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 71846.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71846.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71846.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71846.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71846.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71846.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71846.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512a990]
>[ 71846.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512a990] width 1920 pitch 7680 (/4 1920)
>[ 71846.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 71846.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 71846.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71846.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71846.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71846.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71846.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c744e0]
>[ 71846.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c744e0] width 1920 pitch 7680 (/4 1920)
>[ 71846.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059f30]
>[ 71846.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059f30] width 1920 pitch 7680 (/4 1920)
>[ 71846.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71846.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71846.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71846.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71846.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011210]
>[ 71846.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011210] width 1920 pitch 7680 (/4 1920)
>[ 71846.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71846.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71846.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71846.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71846.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 71846.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 71846.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b33430]
>[ 71846.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b33430] width 1920 pitch 7680 (/4 1920)
>[ 71846.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebcc20]
>[ 71846.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebcc20] width 1920 pitch 7680 (/4 1920)
>[ 71846.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71846.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71846.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71846.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71846.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71846.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71846.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[ 71847.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[ 71847.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71847.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71847.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71847.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71847.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a45c0]
>[ 71847.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a45c0] width 1920 pitch 7680 (/4 1920)
>[ 71847.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3910]
>[ 71847.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3910] width 1920 pitch 7680 (/4 1920)
>[ 71847.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 71847.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 71847.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71847.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71847.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 71847.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 71847.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71847.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71847.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71847.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71847.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71847.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71847.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5070]
>[ 71847.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5070] width 1920 pitch 7680 (/4 1920)
>[ 71847.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[ 71847.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[ 71849.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71849.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71849.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71849.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71850.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71850.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71850.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71850.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71850.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71850.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71850.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71850.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71850.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71850.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71850.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71850.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71850.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71850.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71850.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 71850.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 71850.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71850.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71850.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71850.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71850.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71850.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71921.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71921.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71921.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb4c40]
>[ 71921.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb4c40] width 1920 pitch 7680 (/4 1920)
>[ 71922.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e900]
>[ 71922.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e900] width 1920 pitch 7680 (/4 1920)
>[ 71922.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71922.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71922.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e900]
>[ 71922.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e900] width 1920 pitch 7680 (/4 1920)
>[ 71922.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a45c0]
>[ 71923.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a45c0] width 1920 pitch 7680 (/4 1920)
>[ 71923.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 71923.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 71923.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71923.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71923.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ec9b0]
>[ 71923.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ec9b0] width 1920 pitch 7680 (/4 1920)
>[ 71923.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 71923.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 71923.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5104140]
>[ 71923.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5104140] width 1920 pitch 7680 (/4 1920)
>[ 71923.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 71923.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 71924.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5104f00]
>[ 71924.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5104f00] width 1920 pitch 7680 (/4 1920)
>[ 71924.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e900]
>[ 71924.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e900] width 1920 pitch 7680 (/4 1920)
>[ 71924.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebcc20]
>[ 71924.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebcc20] width 1920 pitch 7680 (/4 1920)
>[ 71925.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71925.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71925.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71925.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71925.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71925.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71925.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71925.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71925.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71925.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71925.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71925.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71925.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71925.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71925.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71925.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 71925.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 71925.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 71925.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 71925.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 71925.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 71925.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 71925.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef79c0]
>[ 71926.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef79c0] width 1920 pitch 7680 (/4 1920)
>[ 71926.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc740]
>[ 71926.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc740] width 1920 pitch 7680 (/4 1920)
>[ 71926.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 71926.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 71926.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4380]
>[ 71926.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4380] width 1920 pitch 7680 (/4 1920)
>[ 71926.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 71926.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 72041.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 72042.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 72042.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd90]
>[ 72042.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd90] width 1920 pitch 7680 (/4 1920)
>[ 72042.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd90]
>[ 72042.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd90] width 1920 pitch 7680 (/4 1920)
>[ 72042.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd90]
>[ 72042.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd90] width 1920 pitch 7680 (/4 1920)
>[ 72042.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd90]
>[ 72042.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd90] width 1920 pitch 7680 (/4 1920)
>[ 72042.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd90]
>[ 72042.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd90] width 1920 pitch 7680 (/4 1920)
>[ 72042.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 72042.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 72042.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72042.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72042.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72042.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72042.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72042.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4670]
>[ 72042.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4670] width 1920 pitch 7680 (/4 1920)
>[ 72043.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd40]
>[ 72043.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd40] width 1920 pitch 7680 (/4 1920)
>[ 72043.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5d870]
>[ 72043.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5d870] width 1920 pitch 7680 (/4 1920)
>[ 72043.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4620]
>[ 72043.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4620] width 1920 pitch 7680 (/4 1920)
>[ 72043.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286db30]
>[ 72043.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286db30] width 1920 pitch 7680 (/4 1920)
>[ 72043.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fd40]
>[ 72043.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fd40] width 1920 pitch 7680 (/4 1920)
>[ 72043.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 72043.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 72043.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284d0b0]
>[ 72043.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284d0b0] width 1920 pitch 7680 (/4 1920)
>[ 72043.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72043.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72043.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72043.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72043.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c600]
>[ 72043.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c600] width 1920 pitch 7680 (/4 1920)
>[ 72043.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72043.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72043.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c600]
>[ 72043.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c600] width 1920 pitch 7680 (/4 1920)
>[ 72043.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c600]
>[ 72043.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c600] width 1920 pitch 7680 (/4 1920)
>[ 72043.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c600]
>[ 72043.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c600] width 1920 pitch 7680 (/4 1920)
>[ 72043.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c600]
>[ 72043.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c600] width 1920 pitch 7680 (/4 1920)
>[ 72043.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72043.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72043.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72043.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40509d0]
>[ 72044.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40509d0] width 1920 pitch 7680 (/4 1920)
>[ 72044.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a1e0]
>[ 72044.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a1e0] width 1920 pitch 7680 (/4 1920)
>[ 72044.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72044.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72044.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72044.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72044.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4039110]
>[ 72045.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4039110] width 1920 pitch 7680 (/4 1920)
>[ 72045.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72045.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72045.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72045.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72045.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043a60]
>[ 72045.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043a60] width 1920 pitch 7680 (/4 1920)
>[ 72045.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72045.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72045.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72045.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72045.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f760d0]
>[ 72045.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f760d0] width 1920 pitch 7680 (/4 1920)
>[ 72045.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72045.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72045.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72045.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72045.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a1e0]
>[ 72045.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a1e0] width 1920 pitch 7680 (/4 1920)
>[ 72047.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72047.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72047.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72047.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72047.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72047.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72047.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72047.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72048.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72048.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72048.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72048.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72048.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72048.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72048.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72048.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72048.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72048.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72049.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72049.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72049.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72049.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72049.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72049.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72049.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72049.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72049.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72050.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72050.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72050.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72050.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72051.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72051.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72051.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72051.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72051.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72051.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72051.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72051.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 72051.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 72051.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb430]
>[ 72051.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb430] width 1920 pitch 7680 (/4 1920)
>[ 72051.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 72051.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 72051.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455f0]
>[ 72051.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455f0] width 1920 pitch 7680 (/4 1920)
>[ 72051.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076c40]
>[ 72051.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076c40] width 1920 pitch 7680 (/4 1920)
>[ 72051.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72051.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72051.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72051.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72051.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72051.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72051.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee2000]
>[ 72051.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee2000] width 1920 pitch 7680 (/4 1920)
>[ 72051.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72051.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72051.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72051.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72051.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72051.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72051.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72051.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72051.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72051.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72051.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72051.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72051.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72051.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72051.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72052.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72052.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72052.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72052.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72052.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72052.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb91a0]
>[ 72052.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb91a0] width 1920 pitch 7680 (/4 1920)
>[ 72052.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edba60]
>[ 72052.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edba60] width 1920 pitch 7680 (/4 1920)
>[ 72052.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72052.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72052.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c680]
>[ 72052.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c680] width 1920 pitch 7680 (/4 1920)
>[ 72052.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72052.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72052.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72053.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72053.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72053.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72053.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72053.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72053.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb390]
>[ 72054.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb390] width 1920 pitch 7680 (/4 1920)
>[ 72054.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30470]
>[ 72054.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30470] width 1920 pitch 7680 (/4 1920)
>[ 72054.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72054.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72054.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72055.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72055.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72055.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72055.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72055.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb760]
>[ 72055.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb760] width 1920 pitch 7680 (/4 1920)
>[ 72055.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5011030]
>[ 72055.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5011030] width 1920 pitch 7680 (/4 1920)
>[ 72055.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35640]
>[ 72055.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35640] width 1920 pitch 7680 (/4 1920)
>[ 72055.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31420]
>[ 72055.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31420] width 1920 pitch 7680 (/4 1920)
>[ 72055.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87b0]
>[ 72055.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87b0] width 1920 pitch 7680 (/4 1920)
>[ 72055.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31420]
>[ 72055.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31420] width 1920 pitch 7680 (/4 1920)
>[ 72055.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30600]
>[ 72055.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30600] width 1920 pitch 7680 (/4 1920)
>[ 72055.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31420]
>[ 72055.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31420] width 1920 pitch 7680 (/4 1920)
>[ 72055.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72055.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72055.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31420]
>[ 72055.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31420] width 1920 pitch 7680 (/4 1920)
>[ 72055.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72055.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72055.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50268b0]
>[ 72055.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50268b0] width 1920 pitch 7680 (/4 1920)
>[ 72055.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050ad0]
>[ 72055.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050ad0] width 1920 pitch 7680 (/4 1920)
>[ 72055.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c352d0]
>[ 72055.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c352d0] width 1920 pitch 7680 (/4 1920)
>[ 72055.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c34d60]
>[ 72055.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c34d60] width 1920 pitch 7680 (/4 1920)
>[ 72055.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c352d0]
>[ 72055.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c352d0] width 1920 pitch 7680 (/4 1920)
>[ 72055.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050d00]
>[ 72055.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050d00] width 1920 pitch 7680 (/4 1920)
>[ 72055.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc6140]
>[ 72055.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc6140] width 1920 pitch 7680 (/4 1920)
>[ 72055.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c34d20]
>[ 72055.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c34d20] width 1920 pitch 7680 (/4 1920)
>[ 72055.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1da00]
>[ 72055.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1da00] width 1920 pitch 7680 (/4 1920)
>[ 72055.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1da00]
>[ 72055.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1da00] width 1920 pitch 7680 (/4 1920)
>[ 72055.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6a50]
>[ 72055.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6a50] width 1920 pitch 7680 (/4 1920)
>[ 72055.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6ab0]
>[ 72055.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6ab0] width 1920 pitch 7680 (/4 1920)
>[ 72055.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6c70]
>[ 72055.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6c70] width 1920 pitch 7680 (/4 1920)
>[ 72055.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee6cb0]
>[ 72055.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee6cb0] width 1920 pitch 7680 (/4 1920)
>[ 72055.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9be0]
>[ 72055.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9be0] width 1920 pitch 7680 (/4 1920)
>[ 72055.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9c40]
>[ 72055.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9c40] width 1920 pitch 7680 (/4 1920)
>[ 72055.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9be0]
>[ 72055.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9be0] width 1920 pitch 7680 (/4 1920)
>[ 72055.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9ac0]
>[ 72056.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9ac0] width 1920 pitch 7680 (/4 1920)
>[ 72056.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9ac0]
>[ 72056.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9ac0] width 1920 pitch 7680 (/4 1920)
>[ 72056.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b25770]
>[ 72056.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b25770] width 1920 pitch 7680 (/4 1920)
>[ 72056.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9ac0]
>[ 72056.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9ac0] width 1920 pitch 7680 (/4 1920)
>[ 72056.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9be0]
>[ 72056.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9be0] width 1920 pitch 7680 (/4 1920)
>[ 72056.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9ac0]
>[ 72056.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9ac0] width 1920 pitch 7680 (/4 1920)
>[ 72056.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9be0]
>[ 72056.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9be0] width 1920 pitch 7680 (/4 1920)
>[ 72056.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9ac0]
>[ 72056.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9ac0] width 1920 pitch 7680 (/4 1920)
>[ 72056.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9be0]
>[ 72056.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9be0] width 1920 pitch 7680 (/4 1920)
>[ 72056.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1090]
>[ 72056.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1090] width 1920 pitch 7680 (/4 1920)
>[ 72056.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72056.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72056.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1db70]
>[ 72056.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1db70] width 1920 pitch 7680 (/4 1920)
>[ 72056.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a1e0]
>[ 72056.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a1e0] width 1920 pitch 7680 (/4 1920)
>[ 72056.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72056.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72056.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1db70]
>[ 72056.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1db70] width 1920 pitch 7680 (/4 1920)
>[ 72056.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d0b20]
>[ 72056.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d0b20] width 1920 pitch 7680 (/4 1920)
>[ 72056.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e218b0]
>[ 72056.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e218b0] width 1920 pitch 7680 (/4 1920)
>[ 72056.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f760d0]
>[ 72056.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f760d0] width 1920 pitch 7680 (/4 1920)
>[ 72056.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d0b20]
>[ 72056.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d0b20] width 1920 pitch 7680 (/4 1920)
>[ 72056.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e218b0]
>[ 72056.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e218b0] width 1920 pitch 7680 (/4 1920)
>[ 72056.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f760d0]
>[ 72056.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f760d0] width 1920 pitch 7680 (/4 1920)
>[ 72056.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d0b20]
>[ 72056.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d0b20] width 1920 pitch 7680 (/4 1920)
>[ 72056.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e218b0]
>[ 72056.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e218b0] width 1920 pitch 7680 (/4 1920)
>[ 72056.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f760d0]
>[ 72056.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f760d0] width 1920 pitch 7680 (/4 1920)
>[ 72056.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[ 72056.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1920 pitch 7680 (/4 1920)
>[ 72056.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72056.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72056.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb310]
>[ 72056.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb310] width 1920 pitch 7680 (/4 1920)
>[ 72056.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 72056.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 72056.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22780]
>[ 72056.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22780] width 1920 pitch 7680 (/4 1920)
>[ 72056.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72056.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72057.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb310]
>[ 72057.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb310] width 1920 pitch 7680 (/4 1920)
>[ 72057.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 72057.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 72057.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22780]
>[ 72057.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22780] width 1920 pitch 7680 (/4 1920)
>[ 72057.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72057.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72057.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb310]
>[ 72057.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb310] width 1920 pitch 7680 (/4 1920)
>[ 72057.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01d30]
>[ 72057.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01d30] width 1920 pitch 7680 (/4 1920)
>[ 72057.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22780]
>[ 72057.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22780] width 1920 pitch 7680 (/4 1920)
>[ 72057.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72057.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72057.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb310]
>[ 72057.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb310] width 1920 pitch 7680 (/4 1920)
>[ 72057.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea8f80]
>[ 72057.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea8f80] width 1920 pitch 7680 (/4 1920)
>[ 72057.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505cff0]
>[ 72057.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505cff0] width 1920 pitch 7680 (/4 1920)
>[ 72057.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edb310]
>[ 72057.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edb310] width 1920 pitch 7680 (/4 1920)
>[ 72057.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72057.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72057.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72057.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72057.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72058.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72058.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72058.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72058.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72059.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72059.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72059.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72059.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7b990]
>[ 72060.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7b990] width 1920 pitch 7680 (/4 1920)
>[ 72060.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72060.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31290]
>[ 72060.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31290] width 1920 pitch 7680 (/4 1920)
>[ 72067.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb2080]
>[ 72067.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb2080] width 1920 pitch 7680 (/4 1920)
>[ 72072.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37cf0]
>[ 72072.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37cf0] width 1920 pitch 7680 (/4 1920)
>[ 72072.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37a80]
>[ 72072.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37a80] width 1920 pitch 7680 (/4 1920)
>[ 72072.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0d80]
>[ 72073.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0d80] width 1920 pitch 7680 (/4 1920)
>[ 72073.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37a80]
>[ 72073.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37a80] width 1920 pitch 7680 (/4 1920)
>[ 72073.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c10]
>[ 72073.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c10] width 1920 pitch 7680 (/4 1920)
>[ 72073.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce540]
>[ 72073.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce540] width 1920 pitch 7680 (/4 1920)
>[ 72073.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdbd0]
>[ 72073.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdbd0] width 1920 pitch 7680 (/4 1920)
>[ 72073.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0bc0]
>[ 72073.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0bc0] width 1920 pitch 7680 (/4 1920)
>[ 72073.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce540]
>[ 72073.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce540] width 1920 pitch 7680 (/4 1920)
>[ 72073.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdbd0]
>[ 72073.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdbd0] width 1920 pitch 7680 (/4 1920)
>[ 72073.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c60]
>[ 72073.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c60] width 1920 pitch 7680 (/4 1920)
>[ 72073.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b375b0]
>[ 72073.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b375b0] width 1920 pitch 7680 (/4 1920)
>[ 72073.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b409a0]
>[ 72073.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b409a0] width 1920 pitch 7680 (/4 1920)
>[ 72073.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b40940]
>[ 72073.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b40940] width 1920 pitch 7680 (/4 1920)
>[ 72073.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b40ca0]
>[ 72073.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b40ca0] width 1920 pitch 7680 (/4 1920)
>[ 72073.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b40c40]
>[ 72073.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b40c40] width 1920 pitch 7680 (/4 1920)
>[ 72075.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b40c20]
>[ 72075.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b40c20] width 1920 pitch 7680 (/4 1920)
>[ 72075.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0e20]
>[ 72075.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0e20] width 1920 pitch 7680 (/4 1920)
>[ 72075.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37a20]
>[ 72075.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37a20] width 1920 pitch 7680 (/4 1920)
>[ 72075.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0e20]
>[ 72075.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0e20] width 1920 pitch 7680 (/4 1920)
>[ 72075.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b40c20]
>[ 72075.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b40c20] width 1920 pitch 7680 (/4 1920)
>[ 72112.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72112.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72112.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72112.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72112.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72112.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72112.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72113.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72113.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72113.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72113.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72113.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbb70]
>[ 72113.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbb70] width 1920 pitch 7680 (/4 1920)
>[ 72113.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72113.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72113.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72113.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72113.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72114.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72114.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50509d0]
>[ 72114.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50509d0] width 1920 pitch 7680 (/4 1920)
>[ 72114.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72114.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72114.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3babdc0]
>[ 72114.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3babdc0] width 1920 pitch 7680 (/4 1920)
>[ 72119.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebff80]
>[ 72119.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebff80] width 1920 pitch 7680 (/4 1920)
>[ 72157.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48cf0]
>[ 72157.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48cf0] width 1920 pitch 7680 (/4 1920)
>[ 72161.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72161.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72161.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e050]
>[ 72161.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e050] width 1920 pitch 7680 (/4 1920)
>[ 72161.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72161.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72161.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72161.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72161.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72161.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72161.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72161.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72161.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72161.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72161.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72162.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72162.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72162.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72162.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72162.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72162.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72162.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72162.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72162.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72162.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72162.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72162.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72162.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72162.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d860]
>[ 72162.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d860] width 1920 pitch 7680 (/4 1920)
>[ 72162.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e030]
>[ 72162.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e030] width 1920 pitch 7680 (/4 1920)
>[ 72168.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba36a0]
>[ 72168.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba36a0] width 1920 pitch 7680 (/4 1920)
>[ 72168.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e915d0]
>[ 72168.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e915d0] width 1920 pitch 7680 (/4 1920)
>[ 72168.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba36a0]
>[ 72168.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba36a0] width 1920 pitch 7680 (/4 1920)
>[ 72168.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e915d0]
>[ 72168.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e915d0] width 1920 pitch 7680 (/4 1920)
>[ 72168.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e915d0]
>[ 72168.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e915d0] width 1920 pitch 7680 (/4 1920)
>[ 72168.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba36a0]
>[ 72168.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba36a0] width 1920 pitch 7680 (/4 1920)
>[ 72168.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e915d0]
>[ 72168.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e915d0] width 1920 pitch 7680 (/4 1920)
>[ 72168.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ae40]
>[ 72168.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ae40] width 1920 pitch 7680 (/4 1920)
>[ 72168.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e010]
>[ 72168.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e010] width 1920 pitch 7680 (/4 1920)
>[ 72168.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e60]
>[ 72168.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e60] width 1920 pitch 7680 (/4 1920)
>[ 72168.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e915d0]
>[ 72168.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e915d0] width 1920 pitch 7680 (/4 1920)
>[ 72168.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba36a0]
>[ 72168.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba36a0] width 1920 pitch 7680 (/4 1920)
>[ 72174.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b534d0]
>[ 72174.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b534d0] width 1920 pitch 7680 (/4 1920)
>[ 72212.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91c10]
>[ 72212.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91c10] width 1920 pitch 7680 (/4 1920)
>[ 72219.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72219.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72219.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74e90]
>[ 72219.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74e90] width 1920 pitch 7680 (/4 1920)
>[ 72219.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baab00]
>[ 72219.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baab00] width 1920 pitch 7680 (/4 1920)
>[ 72219.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74e90]
>[ 72219.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74e90] width 1920 pitch 7680 (/4 1920)
>[ 72219.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72219.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72219.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f1a0]
>[ 72219.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f1a0] width 1920 pitch 7680 (/4 1920)
>[ 72219.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e4c0]
>[ 72219.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e4c0] width 1920 pitch 7680 (/4 1920)
>[ 72219.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74e90]
>[ 72219.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74e90] width 1920 pitch 7680 (/4 1920)
>[ 72219.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74e90]
>[ 72219.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74e90] width 1920 pitch 7680 (/4 1920)
>[ 72219.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72219.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72223.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72223.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72223.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea19b0]
>[ 72223.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea19b0] width 1920 pitch 7680 (/4 1920)
>[ 72223.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72223.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72223.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea19b0]
>[ 72223.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea19b0] width 1920 pitch 7680 (/4 1920)
>[ 72223.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72223.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72223.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea19b0]
>[ 72223.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea19b0] width 1920 pitch 7680 (/4 1920)
>[ 72223.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72223.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72223.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea19b0]
>[ 72223.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea19b0] width 1920 pitch 7680 (/4 1920)
>[ 72223.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72223.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72223.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72223.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72223.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ea00]
>[ 72224.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ea00] width 1920 pitch 7680 (/4 1920)
>[ 72224.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72224.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72224.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ea00]
>[ 72224.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ea00] width 1920 pitch 7680 (/4 1920)
>[ 72224.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd10]
>[ 72224.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd10] width 1920 pitch 7680 (/4 1920)
>[ 72224.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ea00]
>[ 72224.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ea00] width 1920 pitch 7680 (/4 1920)
>[ 72224.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 72224.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 72224.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 72224.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 72224.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 72224.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 72224.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72224.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32570]
>[ 72224.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32570] width 1920 pitch 7680 (/4 1920)
>[ 72224.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 72224.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 72224.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72224.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3c7e0]
>[ 72227.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3c7e0] width 1920 pitch 7680 (/4 1920)
>[ 72227.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72227.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91fa0]
>[ 72227.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91fa0] width 1920 pitch 7680 (/4 1920)
>[ 72227.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8d60]
>[ 72227.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8d60] width 1920 pitch 7680 (/4 1920)
>[ 72235.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72235.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72235.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72235.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72235.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72236.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72236.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72236.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72236.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9ef40]
>[ 72236.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9ef40] width 1920 pitch 7680 (/4 1920)
>[ 72236.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72236.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72236.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72236.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72253.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d56100]
>[ 72253.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d56100] width 1920 pitch 7680 (/4 1920)
>[ 72265.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e320]
>[ 72265.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e320] width 1920 pitch 7680 (/4 1920)
>[ 72270.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72270.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72274.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72274.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72274.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72274.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72274.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72274.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72274.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72274.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72274.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72274.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72274.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72274.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72274.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72274.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72275.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72275.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72275.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72275.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72275.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72275.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72275.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72275.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72275.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72275.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72275.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72275.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72275.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72275.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72275.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb480]
>[ 72275.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb480] width 1920 pitch 7680 (/4 1920)
>[ 72275.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4dec0]
>[ 72275.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4dec0] width 1920 pitch 7680 (/4 1920)
>[ 72275.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2fc0]
>[ 72275.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2fc0] width 1920 pitch 7680 (/4 1920)
>[ 72288.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397d840]
>[ 72288.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397d840] width 1920 pitch 7680 (/4 1920)
>[ 72288.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aba0]
>[ 72288.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aba0] width 1920 pitch 7680 (/4 1920)
>[ 72288.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5104f00]
>[ 72288.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5104f00] width 1920 pitch 7680 (/4 1920)
>[ 72288.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72288.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72289.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc43e0]
>[ 72289.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc43e0] width 1920 pitch 7680 (/4 1920)
>[ 72289.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72289.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72289.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 72289.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 72290.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72290.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72290.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058b80]
>[ 72290.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058b80] width 1920 pitch 7680 (/4 1920)
>[ 72290.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 72290.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 72290.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f86a60]
>[ 72290.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f86a60] width 1920 pitch 7680 (/4 1920)
>[ 72290.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 72290.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 72290.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72290.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72290.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058b80]
>[ 72290.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058b80] width 1920 pitch 7680 (/4 1920)
>[ 72290.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 72290.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 72290.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 72290.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 72290.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 72290.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 72290.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d910]
>[ 72290.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d910] width 1920 pitch 7680 (/4 1920)
>[ 72290.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 72290.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 72290.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72290.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72290.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 72290.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 72290.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[ 72290.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1920 pitch 7680 (/4 1920)
>[ 72290.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 72290.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 72290.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dca970]
>[ 72290.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dca970] width 1920 pitch 7680 (/4 1920)
>[ 72335.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058b80]
>[ 72335.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058b80] width 1920 pitch 7680 (/4 1920)
>[ 72335.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72335.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f224b0]
>[ 72336.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f224b0] width 1920 pitch 7680 (/4 1920)
>[ 72336.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053630]
>[ 72336.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053630] width 1920 pitch 7680 (/4 1920)
>[ 72336.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be25e0]
>[ 72336.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be25e0] width 1920 pitch 7680 (/4 1920)
>[ 72336.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868f40]
>[ 72336.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868f40] width 1920 pitch 7680 (/4 1920)
>[ 72336.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30770]
>[ 72336.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30770] width 1920 pitch 7680 (/4 1920)
>[ 72336.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 72337.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 72337.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 72337.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 72337.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20720]
>[ 72337.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20720] width 1920 pitch 7680 (/4 1920)
>[ 72338.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b531a0]
>[ 72338.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b531a0] width 1920 pitch 7680 (/4 1920)
>[ 72338.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b531a0]
>[ 72338.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b531a0] width 1920 pitch 7680 (/4 1920)
>[ 72338.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72338.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72338.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72339.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72339.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72339.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1be70]
>[ 72339.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1be70] width 1920 pitch 7680 (/4 1920)
>[ 72340.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58090]
>[ 72340.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58090] width 1920 pitch 7680 (/4 1920)
>[ 72343.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d58090]
>[ 72343.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d58090] width 1920 pitch 7680 (/4 1920)
>[ 72346.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae770]
>[ 72346.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae770] width 1920 pitch 7680 (/4 1920)
>[ 72346.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051ee0]
>[ 72346.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051ee0] width 1920 pitch 7680 (/4 1920)
>[ 72346.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 72346.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 72347.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfdf90]
>[ 72347.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfdf90] width 1920 pitch 7680 (/4 1920)
>[ 72347.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 72347.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 72347.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 72347.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 72348.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05620]
>[ 72348.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05620] width 1920 pitch 7680 (/4 1920)
>[ 72348.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72348.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72367.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2869ed0]
>[ 72367.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2869ed0] width 1920 pitch 7680 (/4 1920)
>[ 72367.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b45600]
>[ 72367.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b45600] width 1920 pitch 7680 (/4 1920)
>[ 72368.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a900]
>[ 72368.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a900] width 1920 pitch 7680 (/4 1920)
>[ 72368.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2830d70]
>[ 72368.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2830d70] width 1920 pitch 7680 (/4 1920)
>[ 72368.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9eb30]
>[ 72368.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9eb30] width 1920 pitch 7680 (/4 1920)
>[ 72368.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b45600]
>[ 72368.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b45600] width 1920 pitch 7680 (/4 1920)
>[ 72368.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a900]
>[ 72368.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a900] width 1920 pitch 7680 (/4 1920)
>[ 72368.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2830d70]
>[ 72368.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2830d70] width 1920 pitch 7680 (/4 1920)
>[ 72368.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9eb30]
>[ 72368.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9eb30] width 1920 pitch 7680 (/4 1920)
>[ 72464.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8f90]
>[ 72464.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8f90] width 1920 pitch 7680 (/4 1920)
>[ 72464.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 72464.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 72465.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72465.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72483.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecbd60]
>[ 72483.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecbd60] width 1920 pitch 7680 (/4 1920)
>[ 72483.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 72483.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 72484.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f26f10]
>[ 72484.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f26f10] width 1920 pitch 7680 (/4 1920)
>[ 72485.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e831c0]
>[ 72485.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e831c0] width 1920 pitch 7680 (/4 1920)
>[ 72485.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 72485.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 72485.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 72485.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 72485.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8f90]
>[ 72485.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8f90] width 1920 pitch 7680 (/4 1920)
>[ 72485.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72485.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72485.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f10f20]
>[ 72485.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f10f20] width 1920 pitch 7680 (/4 1920)
>[ 72485.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7040]
>[ 72485.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7040] width 1920 pitch 7680 (/4 1920)
>[ 72485.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbd6b0]
>[ 72485.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbd6b0] width 1920 pitch 7680 (/4 1920)
>[ 72485.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eceae0]
>[ 72485.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eceae0] width 1920 pitch 7680 (/4 1920)
>[ 72485.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d670]
>[ 72485.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d670] width 1920 pitch 7680 (/4 1920)
>[ 72485.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c6e0]
>[ 72485.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c6e0] width 1920 pitch 7680 (/4 1920)
>[ 72485.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 72485.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 72485.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 72485.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 72485.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 72485.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 72485.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7dfd0]
>[ 72485.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7dfd0] width 1920 pitch 7680 (/4 1920)
>[ 72485.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ec40]
>[ 72485.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ec40] width 1920 pitch 7680 (/4 1920)
>[ 72485.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 72485.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 72485.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a900]
>[ 72485.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a900] width 1920 pitch 7680 (/4 1920)
>[ 72485.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[ 72485.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1920 pitch 7680 (/4 1920)
>[ 72485.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 72485.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 72485.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72485.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72485.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72485.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72485.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 72485.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 72502.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f110]
>[ 72502.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f110] width 1920 pitch 7680 (/4 1920)
>[ 72518.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33a80]
>[ 72518.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33a80] width 1920 pitch 7680 (/4 1920)
>[ 72518.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7b380]
>[ 72518.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7b380] width 1920 pitch 7680 (/4 1920)
>[ 72518.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33920]
>[ 72518.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33920] width 1920 pitch 7680 (/4 1920)
>[ 72567.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9240]
>[ 72567.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9240] width 1920 pitch 7680 (/4 1920)
>[ 72569.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 72569.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 72570.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9210]
>[ 72570.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9210] width 1920 pitch 7680 (/4 1920)
>[ 72570.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 72570.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 72570.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edfff0]
>[ 72570.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edfff0] width 1920 pitch 7680 (/4 1920)
>[ 72571.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8e10]
>[ 72571.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8e10] width 1920 pitch 7680 (/4 1920)
>[ 72571.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33a80]
>[ 72571.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33a80] width 1920 pitch 7680 (/4 1920)
>[ 72571.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b340]
>[ 72571.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b340] width 1920 pitch 7680 (/4 1920)
>[ 72571.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33a80]
>[ 72571.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33a80] width 1920 pitch 7680 (/4 1920)
>[ 72571.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50890f0]
>[ 72571.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50890f0] width 1920 pitch 7680 (/4 1920)
>[ 72571.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8e10]
>[ 72571.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8e10] width 1920 pitch 7680 (/4 1920)
>[ 72571.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33a80]
>[ 72571.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33a80] width 1920 pitch 7680 (/4 1920)
>[ 72571.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aee40]
>[ 72571.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aee40] width 1920 pitch 7680 (/4 1920)
>[ 72571.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f33a80]
>[ 72571.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f33a80] width 1920 pitch 7680 (/4 1920)
>[ 72571.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50890f0]
>[ 72571.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50890f0] width 1920 pitch 7680 (/4 1920)
>[ 72571.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edfff0]
>[ 72571.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edfff0] width 1920 pitch 7680 (/4 1920)
>[ 72571.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8e10]
>[ 72571.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8e10] width 1920 pitch 7680 (/4 1920)
>[ 72571.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bb80]
>[ 72571.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bb80] width 1920 pitch 7680 (/4 1920)
>[ 72617.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ec40]
>[ 72617.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ec40] width 1920 pitch 7680 (/4 1920)
>[ 72617.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[ 72617.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[ 72617.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72617.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72617.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 72617.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 72618.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 72618.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 72618.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 72618.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 72618.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8f90]
>[ 72618.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8f90] width 1920 pitch 7680 (/4 1920)
>[ 72618.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c210]
>[ 72618.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c210] width 1920 pitch 7680 (/4 1920)
>[ 72618.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f10f20]
>[ 72618.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f10f20] width 1920 pitch 7680 (/4 1920)
>[ 72618.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbd6b0]
>[ 72618.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbd6b0] width 1920 pitch 7680 (/4 1920)
>[ 72620.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 72620.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 72620.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 72620.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 72620.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a390]
>[ 72620.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a390] width 1920 pitch 7680 (/4 1920)
>[ 72623.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 72623.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 72623.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a900]
>[ 72623.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a900] width 1920 pitch 7680 (/4 1920)
>[ 72623.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7040]
>[ 72623.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7040] width 1920 pitch 7680 (/4 1920)
>[ 72623.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4850]
>[ 72623.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4850] width 1920 pitch 7680 (/4 1920)
>[ 72623.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 72623.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 72623.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72623.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72623.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 72623.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 72623.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 72623.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 72623.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ec40]
>[ 72624.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ec40] width 1920 pitch 7680 (/4 1920)
>[ 72624.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[ 72624.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[ 72624.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 72624.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 72624.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 72624.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 72624.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72624.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72624.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284ceb0]
>[ 72624.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284ceb0] width 1920 pitch 7680 (/4 1920)
>[ 72624.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b30770]
>[ 72624.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b30770] width 1920 pitch 7680 (/4 1920)
>[ 72624.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ec40]
>[ 72624.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ec40] width 1920 pitch 7680 (/4 1920)
>[ 72624.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 72624.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 72624.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 72624.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 72624.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 72624.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 72625.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ffa0]
>[ 72625.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ffa0] width 1920 pitch 7680 (/4 1920)
>[ 72625.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 72625.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 72625.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 72625.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 72625.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f41250]
>[ 72625.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f41250] width 1920 pitch 7680 (/4 1920)
>[ 72625.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72625.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033f30]
>[ 72626.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033f30] width 1920 pitch 7680 (/4 1920)
>[ 72626.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72626.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f089b0]
>[ 72626.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f089b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7660]
>[ 72626.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7660] width 1920 pitch 7680 (/4 1920)
>[ 72626.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72626.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72626.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72626.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f089b0]
>[ 72626.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f089b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7660]
>[ 72626.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7660] width 1920 pitch 7680 (/4 1920)
>[ 72626.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72626.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72626.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72626.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f089b0]
>[ 72626.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f089b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7660]
>[ 72626.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7660] width 1920 pitch 7680 (/4 1920)
>[ 72626.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72626.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72626.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72626.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f089b0]
>[ 72626.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f089b0] width 1920 pitch 7680 (/4 1920)
>[ 72626.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7660]
>[ 72627.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7660] width 1920 pitch 7680 (/4 1920)
>[ 72627.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033f30]
>[ 72627.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033f30] width 1920 pitch 7680 (/4 1920)
>[ 72627.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72627.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72627.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72627.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72627.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f089b0]
>[ 72627.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f089b0] width 1920 pitch 7680 (/4 1920)
>[ 72627.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 72627.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 72627.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72627.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72627.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba4b0]
>[ 72627.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba4b0] width 1920 pitch 7680 (/4 1920)
>[ 72627.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[ 72627.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1920 pitch 7680 (/4 1920)
>[ 72627.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e50]
>[ 72627.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e50] width 1920 pitch 7680 (/4 1920)
>[ 72627.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 72627.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 72628.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[ 72628.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[ 72628.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[ 72628.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1920 pitch 7680 (/4 1920)
>[ 72628.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 72628.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 72628.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71c10]
>[ 72628.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71c10] width 1920 pitch 7680 (/4 1920)
>[ 72628.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7620]
>[ 72628.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7620] width 1920 pitch 7680 (/4 1920)
>[ 72628.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 72628.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 72628.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 72628.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 72628.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3ab0]
>[ 72628.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3ab0] width 1920 pitch 7680 (/4 1920)
>[ 72628.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 72628.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 72628.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 72628.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 72628.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 72628.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 72628.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 72628.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 72628.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6fd50]
>[ 72628.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6fd50] width 1920 pitch 7680 (/4 1920)
>[ 72628.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 72628.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 72628.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 72628.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 72628.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 72628.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 72628.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72628.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72628.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e831c0]
>[ 72628.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e831c0] width 1920 pitch 7680 (/4 1920)
>[ 72628.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72628.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72628.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72628.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72628.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 72628.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 72628.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4d670]
>[ 72628.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4d670] width 1920 pitch 7680 (/4 1920)
>[ 72628.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f234a0]
>[ 72628.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f234a0] width 1920 pitch 7680 (/4 1920)
>[ 72628.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8f90]
>[ 72628.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8f90] width 1920 pitch 7680 (/4 1920)
>[ 72628.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 72628.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 72628.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c6e0]
>[ 72628.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c6e0] width 1920 pitch 7680 (/4 1920)
>[ 72628.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 72628.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 72628.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a390]
>[ 72629.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a390] width 1920 pitch 7680 (/4 1920)
>[ 72629.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 72629.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 72629.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051ee0]
>[ 72629.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051ee0] width 1920 pitch 7680 (/4 1920)
>[ 72629.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85be0]
>[ 72629.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85be0] width 1920 pitch 7680 (/4 1920)
>[ 72629.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 72629.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 72629.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 72629.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 72629.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7b6c0]
>[ 72629.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7b6c0] width 1920 pitch 7680 (/4 1920)
>[ 72629.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 72629.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 72629.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 72629.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 72629.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76520]
>[ 72629.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76520] width 1920 pitch 7680 (/4 1920)
>[ 72629.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057fc0]
>[ 72629.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057fc0] width 1920 pitch 7680 (/4 1920)
>[ 72629.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48c40]
>[ 72629.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48c40] width 1920 pitch 7680 (/4 1920)
>[ 72629.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba470]
>[ 72629.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba470] width 1920 pitch 7680 (/4 1920)
>[ 72629.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820cc0]
>[ 72629.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820cc0] width 1920 pitch 7680 (/4 1920)
>[ 72629.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 72629.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 72629.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11280]
>[ 72629.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11280] width 1920 pitch 7680 (/4 1920)
>[ 72629.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06970]
>[ 72629.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06970] width 1920 pitch 7680 (/4 1920)
>[ 72629.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 72629.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 72629.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0700]
>[ 72629.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0700] width 1920 pitch 7680 (/4 1920)
>[ 72629.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 72629.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 72645.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb3e90]
>[ 72645.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb3e90] width 1920 pitch 7680 (/4 1920)
>[ 72645.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f10f20]
>[ 72645.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f10f20] width 1920 pitch 7680 (/4 1920)
>[ 72645.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bdb0]
>[ 72645.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bdb0] width 1920 pitch 7680 (/4 1920)
>[ 72646.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f207c0]
>[ 72646.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f207c0] width 1920 pitch 7680 (/4 1920)
>[ 72646.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72646.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72650.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e50]
>[ 72650.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e50] width 1920 pitch 7680 (/4 1920)
>[ 72650.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e50]
>[ 72650.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e50] width 1920 pitch 7680 (/4 1920)
>[ 72650.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 72650.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 72651.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72651.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72651.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 72651.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 72651.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72651.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72652.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c000]
>[ 72652.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c000] width 1920 pitch 7680 (/4 1920)
>[ 72652.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c000]
>[ 72652.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c000] width 1920 pitch 7680 (/4 1920)
>[ 72652.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c000]
>[ 72652.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c000] width 1920 pitch 7680 (/4 1920)
>[ 72652.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 72652.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 72652.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b43200]
>[ 72652.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b43200] width 1920 pitch 7680 (/4 1920)
>[ 72652.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2c40]
>[ 72652.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2c40] width 1920 pitch 7680 (/4 1920)
>[ 72652.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c000]
>[ 72652.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c000] width 1920 pitch 7680 (/4 1920)
>[ 72652.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72652.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72652.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fe70]
>[ 72652.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fe70] width 1920 pitch 7680 (/4 1920)
>[ 72652.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72652.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72652.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72652.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72653.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72653.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72653.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72653.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72653.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72653.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72653.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72653.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72653.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048520]
>[ 72653.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048520] width 1920 pitch 7680 (/4 1920)
>[ 72653.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 72653.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 72663.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aca0]
>[ 72663.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aca0] width 1920 pitch 7680 (/4 1920)
>[ 72663.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 72663.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 72663.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 72663.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 72663.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 72663.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 72664.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72664.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72664.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72664.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72664.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72664.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72664.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72665.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72665.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72665.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72665.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72665.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72665.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72665.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72665.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72665.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72665.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72665.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72665.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72665.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72665.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72665.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72665.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72665.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72665.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72665.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72665.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72665.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72665.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72665.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72665.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72665.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72665.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72665.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72665.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72665.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72665.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72665.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72665.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72665.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72665.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72665.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72665.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72665.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72665.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72665.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72665.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72665.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72665.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72665.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72665.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72665.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72666.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72666.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72666.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72666.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72666.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72666.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72666.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72666.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72666.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72666.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72666.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72666.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72666.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72666.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72666.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72666.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72666.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72666.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72666.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72666.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72666.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72666.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72666.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72666.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72667.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72667.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72667.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72667.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72667.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72667.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72667.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72667.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72667.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72667.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72667.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72667.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72667.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72667.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72667.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72667.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72667.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72667.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72667.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72667.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72667.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72667.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72667.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72667.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72667.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72667.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72667.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72667.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72667.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72667.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72667.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72667.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72667.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72667.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72667.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72667.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72667.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72667.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72667.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72667.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72667.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72667.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72667.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72667.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72667.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72667.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72667.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72667.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72667.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72667.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72667.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72667.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72667.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72667.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72668.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72668.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72668.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72668.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72668.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72668.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72668.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72668.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72668.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72668.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72668.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72668.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72668.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72668.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72668.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72668.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72668.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72668.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72668.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72668.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72668.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72668.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72668.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72668.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72668.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72668.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72668.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72668.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72668.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72668.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72668.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72668.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72668.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72668.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72668.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72668.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72668.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72668.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72668.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72668.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72668.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72668.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72668.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72668.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72668.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72668.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72668.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72668.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72668.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72668.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72668.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72668.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72668.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72668.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72669.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72669.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72669.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72669.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72669.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72669.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72669.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72669.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72669.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72669.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72669.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72669.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72669.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72669.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72669.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72669.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72669.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72669.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72669.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72669.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72669.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72669.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72669.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72669.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72669.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72669.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72669.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72669.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72669.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72669.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72669.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72669.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72669.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72669.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72669.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72669.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72669.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72669.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72669.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72670.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72670.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72670.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72670.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72670.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72670.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72670.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72670.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72670.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72670.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72670.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72670.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72670.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72670.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72670.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72670.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72670.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72670.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72670.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72670.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72670.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72670.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72670.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72670.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72670.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72670.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72670.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72670.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72670.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72670.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72670.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72670.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72670.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72670.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72670.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72670.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72670.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72670.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72670.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72671.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72671.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72671.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72671.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72671.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72671.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72671.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72671.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72671.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72671.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72671.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72671.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72671.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72671.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72671.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72671.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72671.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72671.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72671.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72671.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72671.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72671.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72671.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72671.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72671.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72671.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72671.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72671.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72671.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72671.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72671.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72671.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72671.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72671.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72672.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72672.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72672.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72672.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72672.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72672.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72672.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72672.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72672.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72672.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72672.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72672.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72672.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72672.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72672.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72672.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72672.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72672.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72672.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72672.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72672.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72672.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72672.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72672.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72672.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72672.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72672.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72672.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72672.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72672.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72672.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72672.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72672.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72672.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72672.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72672.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72672.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72672.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72672.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72672.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72672.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72672.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72672.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72672.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72672.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72672.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72672.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72672.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72672.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72672.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72672.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72672.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72672.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72673.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72673.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72673.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72673.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72673.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72673.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72673.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72673.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72673.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72674.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72674.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72674.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72674.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72674.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72674.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72674.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72674.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72674.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72674.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72674.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72674.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72674.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72675.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72675.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72675.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72675.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72675.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72675.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72675.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72675.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72675.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72675.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511efa0]
>[ 72675.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511efa0] width 1920 pitch 7680 (/4 1920)
>[ 72675.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51197f0]
>[ 72675.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51197f0] width 1920 pitch 7680 (/4 1920)
>[ 72676.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72676.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72676.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72676.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72676.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72676.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72676.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72676.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72676.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72676.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72676.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72676.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72676.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72676.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72676.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72676.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72676.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72676.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72676.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72676.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72676.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72676.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72676.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72676.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72676.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72676.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72676.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72676.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72676.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 72676.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 72676.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 72676.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 72676.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 72676.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 72676.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0bba0]
>[ 72676.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0bba0] width 1920 pitch 7680 (/4 1920)
>[ 72676.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d957b0]
>[ 72676.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d957b0] width 1920 pitch 7680 (/4 1920)
>[ 72676.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 72676.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 72676.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 72676.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 72676.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa82c0]
>[ 72676.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa82c0] width 1920 pitch 7680 (/4 1920)
>[ 72676.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 72676.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 72720.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece7f0]
>[ 72720.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece7f0] width 1920 pitch 7680 (/4 1920)
>[ 72720.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72720.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72721.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72721.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72721.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72721.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72721.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72721.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72721.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72721.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72721.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72721.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72721.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72721.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72722.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72722.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72722.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109ea0]
>[ 72722.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109ea0] width 1920 pitch 7680 (/4 1920)
>[ 72761.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8f0]
>[ 72761.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8f0] width 1920 pitch 7680 (/4 1920)
>[ 72761.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72761.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72762.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72762.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f219a0]
>[ 72762.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f219a0] width 1920 pitch 7680 (/4 1920)
>[ 72762.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72762.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72762.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72762.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72762.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72762.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72762.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72762.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eed470]
>[ 72763.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eed470] width 1920 pitch 7680 (/4 1920)
>[ 72763.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72763.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72763.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72763.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68070]
>[ 72763.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68070] width 1920 pitch 7680 (/4 1920)
>[ 72772.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72772.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72772.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72772.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72773.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72773.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72773.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72773.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72773.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 72773.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 72773.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72773.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72773.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72773.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72773.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72773.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72773.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72773.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72773.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72773.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72773.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72773.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72773.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72773.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72773.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72773.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72773.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72773.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72773.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 72773.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 72773.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72773.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72773.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72773.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72773.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72773.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72773.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72774.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72774.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72774.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72774.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 72774.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 72774.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72774.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72774.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72774.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72774.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72774.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72774.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72774.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72774.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72774.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72774.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72774.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72774.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72774.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72774.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72774.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72774.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72774.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72774.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 72774.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 72774.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72774.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72774.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72774.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72774.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72774.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72774.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72774.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72774.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032330]
>[ 72774.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032330] width 1920 pitch 7680 (/4 1920)
>[ 72774.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2c10]
>[ 72774.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2c10] width 1920 pitch 7680 (/4 1920)
>[ 72774.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72774.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72774.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 72774.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 72774.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7f0f0]
>[ 72774.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7f0f0] width 1920 pitch 7680 (/4 1920)
>[ 72774.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb710]
>[ 72774.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb710] width 1920 pitch 7680 (/4 1920)
>[ 72774.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 72774.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 72838.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72838.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72839.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72839.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72840.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72840.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72840.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7eb0]
>[ 72840.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7eb0] width 1920 pitch 7680 (/4 1920)
>[ 72950.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efe350]
>[ 72950.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efe350] width 1920 pitch 7680 (/4 1920)
>[ 72950.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72950.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72951.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72951.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72951.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72951.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72951.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72951.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72951.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72951.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72951.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72951.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72951.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72951.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72951.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72951.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72951.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72951.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72951.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72951.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72951.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72951.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72951.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72951.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72951.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72951.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72951.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72951.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72951.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72951.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72951.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72951.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72952.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72952.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72952.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72952.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72952.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72952.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72952.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72952.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72952.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72952.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72952.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72952.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72952.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72952.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72952.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72952.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72952.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72952.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72952.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72952.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72952.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72952.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72952.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72952.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72952.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72952.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72952.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72952.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72953.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee0160]
>[ 72953.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee0160] width 1920 pitch 7680 (/4 1920)
>[ 72953.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 72953.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 72953.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b464d0]
>[ 72953.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b464d0] width 1920 pitch 7680 (/4 1920)
>[ 72954.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72954.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72954.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72954.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72954.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72954.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72954.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72954.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72954.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72954.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72954.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72954.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72954.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72954.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72954.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72954.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72955.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72955.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72955.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72955.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72955.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72955.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72955.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72955.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72955.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72955.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72955.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72955.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72955.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72955.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72955.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72955.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72955.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efd1e0]
>[ 72955.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efd1e0] width 1920 pitch 7680 (/4 1920)
>[ 72955.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 72955.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 72955.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 72955.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 72955.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c62dc0]
>[ 72955.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c62dc0] width 1920 pitch 7680 (/4 1920)
>[ 72966.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8700]
>[ 72966.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8700] width 1920 pitch 7680 (/4 1920)
>[ 72966.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72966.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72967.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3960]
>[ 72967.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3960] width 1920 pitch 7680 (/4 1920)
>[ 72967.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 72967.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 72967.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 72967.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 72979.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 72979.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 72979.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 72979.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 72979.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 72979.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 72979.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3afa0]
>[ 72979.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3afa0] width 1920 pitch 7680 (/4 1920)
>[ 73008.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74720]
>[ 73008.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74720] width 1920 pitch 7680 (/4 1920)
>[ 73008.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73008.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73009.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73009.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73009.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73009.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73009.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73009.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73009.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73009.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73009.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73009.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73009.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73009.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73009.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73009.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73009.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73009.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73009.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73009.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73009.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73009.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73009.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73009.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73009.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73009.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73009.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73009.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73009.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73009.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73009.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73009.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73009.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73009.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73009.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73009.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73009.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73009.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73009.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73009.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73009.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73009.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73009.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73009.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73009.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73009.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73009.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73009.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73009.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73009.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73009.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73009.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73009.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73009.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73009.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73010.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73010.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73010.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73010.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73010.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73010.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73010.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73010.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73010.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73010.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73010.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73010.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73010.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73010.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73010.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73010.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73010.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73010.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73010.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73010.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73010.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73010.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73010.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73010.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73010.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73010.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73010.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73010.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73010.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73010.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73010.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73010.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73010.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73010.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73010.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73010.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73010.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73010.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73010.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73010.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73010.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73010.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73010.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73010.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73010.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73010.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73010.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73010.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73010.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73010.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73010.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73010.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73010.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73010.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73010.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73010.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73010.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73010.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73010.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73010.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73010.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73010.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73010.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73010.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73011.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73011.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73011.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73011.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73011.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73011.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73011.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73011.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73011.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73011.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73011.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73011.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73011.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73011.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73011.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73011.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73011.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73011.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73011.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73011.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73011.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73011.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73011.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73011.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73011.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73011.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73011.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73011.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73011.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73011.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73011.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73011.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73011.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73011.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73011.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73011.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73011.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73011.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73011.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73011.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73011.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73011.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73011.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73011.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73011.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73011.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73011.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73011.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73011.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73011.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73011.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73011.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73011.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73011.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73011.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73011.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73011.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73011.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73011.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73011.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73011.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73011.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73011.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73011.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73011.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73011.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73012.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73012.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73012.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73012.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73012.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73012.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73012.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73012.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73012.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73012.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73012.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73012.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73012.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73012.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73012.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73012.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73012.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73012.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73012.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73012.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73012.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73012.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73012.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73012.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73012.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73012.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73012.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73012.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73012.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73012.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73012.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73012.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73012.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73012.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4ab0]
>[ 73012.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4ab0] width 1920 pitch 7680 (/4 1920)
>[ 73012.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73012.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73012.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73012.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73012.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73012.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73012.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73012.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73012.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73012.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73012.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73012.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73012.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73012.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73012.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73012.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73012.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73012.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73012.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73012.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73012.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73012.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73012.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73012.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73012.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73013.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73013.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73013.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73013.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73013.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73013.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73013.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73013.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73013.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73013.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73013.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73013.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73013.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73013.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73013.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73013.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73013.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73013.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73013.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73013.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73013.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73013.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73013.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73013.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73013.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73013.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73013.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73013.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73013.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73013.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73013.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73013.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73013.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73014.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73014.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73014.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73014.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73014.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73014.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73014.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73014.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73014.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73014.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73014.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73014.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73014.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73014.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73014.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73014.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73014.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73014.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73014.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73014.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73014.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73014.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73014.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73014.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73014.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73014.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73014.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73014.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73014.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73014.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73014.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73014.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73014.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73014.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73014.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73015.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73016.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73016.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73016.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73016.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73016.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73016.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73016.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73016.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73016.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73016.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73016.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73016.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73016.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73016.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73016.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73016.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73016.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73016.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73016.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73016.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73016.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73016.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73016.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73016.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73016.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73016.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73017.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73017.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73017.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73017.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73017.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73017.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73017.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73017.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73017.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73017.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73017.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73017.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73017.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73017.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73017.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73017.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73017.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73017.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73017.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73017.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73017.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73017.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73017.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73017.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73017.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73017.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73017.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73017.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73017.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73017.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73017.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73017.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73017.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73017.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73017.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73017.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73017.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73017.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73017.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73017.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73017.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73017.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73017.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73017.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73017.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73017.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73017.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73017.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73017.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73017.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73017.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73017.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73017.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73017.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73017.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73017.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73017.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73017.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73017.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73017.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73017.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73017.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73017.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73017.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73018.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73018.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73018.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73018.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73018.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73018.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73018.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73018.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73018.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73018.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73018.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73018.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73018.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73018.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73018.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73018.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73018.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73018.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73018.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73018.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73018.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73018.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73018.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73018.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73018.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73018.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73018.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73018.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73018.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73018.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73018.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73018.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73018.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73018.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73018.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73018.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73018.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73018.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73018.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73018.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73018.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73018.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73018.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73018.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73018.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73018.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73018.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73018.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73018.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73018.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73018.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73018.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73018.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73018.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73018.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73018.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73018.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73018.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73018.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73018.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73018.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73018.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73018.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73018.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73019.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73019.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73019.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73019.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73019.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73019.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73019.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73019.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73019.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73019.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73019.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73019.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73019.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73019.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73019.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73019.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73019.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73019.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73019.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73019.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73019.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73019.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73019.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73019.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73019.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73019.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73019.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73019.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73019.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73019.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73019.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73019.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73019.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73019.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73019.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73019.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73019.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73019.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73019.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73019.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73019.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73019.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73019.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73019.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73019.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73019.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73019.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73019.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73019.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73019.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73019.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73019.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73019.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73019.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73019.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73019.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73019.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73019.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73019.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73019.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73020.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73020.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73020.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73020.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73020.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73020.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73020.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73020.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73020.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73020.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73020.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73020.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73020.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73020.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73020.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73020.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73020.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73020.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73020.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73020.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73020.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73020.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73020.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73020.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73020.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73020.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73020.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73020.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73020.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73020.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73020.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73020.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73020.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73020.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73020.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73020.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73020.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73020.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73020.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73020.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73020.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73020.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73020.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73020.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73020.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73020.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73020.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73020.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73020.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73020.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73020.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73020.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73020.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73020.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73020.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73020.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73020.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73020.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73020.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73020.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73020.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73021.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73021.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73021.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73021.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73021.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73021.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73021.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73021.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73021.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73021.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73021.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73021.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73021.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73021.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73021.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73021.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73021.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73021.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73021.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73021.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73021.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73021.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73021.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73021.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73021.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73021.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73021.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73021.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73021.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73021.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73021.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73021.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73021.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73021.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73021.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73021.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73021.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73021.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73021.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73021.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73021.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73021.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73021.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73021.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73021.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73021.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73021.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73021.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73021.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73021.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73021.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73021.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73021.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73021.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73021.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73021.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73021.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73021.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73021.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861490]
>[ 73022.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861490] width 1920 pitch 7680 (/4 1920)
>[ 73022.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73022.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73022.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73022.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73022.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5310]
>[ 73022.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5310] width 1920 pitch 7680 (/4 1920)
>[ 73022.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73022.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73022.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73022.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73022.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73022.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73022.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73022.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73022.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73022.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73022.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73022.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73022.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73022.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73022.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73022.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73022.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73022.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73022.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73022.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73022.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73022.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73022.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73022.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73022.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73022.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73022.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73022.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73022.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73022.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73022.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73022.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73022.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73022.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73022.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73022.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73022.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73022.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73022.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73022.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73022.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73022.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73022.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73022.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73022.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73022.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73022.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73022.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73022.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73022.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73022.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73022.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73022.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73022.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73022.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73022.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73022.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73022.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73023.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73023.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73023.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73023.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73023.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73023.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73023.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73023.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73023.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73023.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73023.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73023.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73023.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73023.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73023.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73023.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73023.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73023.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73023.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73023.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73023.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73023.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73023.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73023.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73023.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73023.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73023.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73023.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73023.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73023.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73023.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73023.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73023.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73023.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73023.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73023.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73023.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73023.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73023.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73023.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73023.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73023.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73023.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73023.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73023.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73023.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73023.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73023.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73023.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73023.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73023.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73023.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73023.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 73023.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 73023.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73023.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73023.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9210]
>[ 73023.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9210] width 1920 pitch 7680 (/4 1920)
>[ 73023.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098c00]
>[ 73023.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098c00] width 1920 pitch 7680 (/4 1920)
>[ 73023.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73024.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73024.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73024.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73024.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73024.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73024.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bf20]
>[ 73024.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bf20] width 1920 pitch 7680 (/4 1920)
>[ 73024.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4037b60]
>[ 73024.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4037b60] width 1920 pitch 7680 (/4 1920)
>[ 73024.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73024.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73026.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73026.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73026.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73026.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f20780]
>[ 73027.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f20780] width 1920 pitch 7680 (/4 1920)
>[ 73027.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73027.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73027.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73027.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 73027.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 73030.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b170]
>[ 73030.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b170] width 1920 pitch 7680 (/4 1920)
>[ 73030.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73030.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73031.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 73031.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 73031.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 73031.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 73032.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f24730]
>[ 73032.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f24730] width 1920 pitch 7680 (/4 1920)
>[ 73032.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5eda0]
>[ 73032.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5eda0] width 1920 pitch 7680 (/4 1920)
>[ 73032.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94f40]
>[ 73032.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94f40] width 1920 pitch 7680 (/4 1920)
>[ 73032.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73032.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73033.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73033.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73033.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73033.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093cb0]
>[ 73034.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093cb0] width 1920 pitch 7680 (/4 1920)
>[ 73034.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73034.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73034.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73034.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73034.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73041.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73041.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73041.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73041.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73042.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73042.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73042.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73042.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73042.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00b30]
>[ 73042.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00b30] width 1920 pitch 7680 (/4 1920)
>[ 73042.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5c6e0]
>[ 73042.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5c6e0] width 1920 pitch 7680 (/4 1920)
>[ 73042.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405a160]
>[ 73043.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405a160] width 1920 pitch 7680 (/4 1920)
>[ 73043.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4bd20]
>[ 73043.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4bd20] width 1920 pitch 7680 (/4 1920)
>[ 73043.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73043.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73044.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2c30]
>[ 73044.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2c30] width 1920 pitch 7680 (/4 1920)
>[ 73044.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef6780]
>[ 73044.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef6780] width 1920 pitch 7680 (/4 1920)
>[ 73044.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad630]
>[ 73044.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad630] width 1920 pitch 7680 (/4 1920)
>[ 73044.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef6780]
>[ 73044.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef6780] width 1920 pitch 7680 (/4 1920)
>[ 73044.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077610]
>[ 73044.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077610] width 1920 pitch 7680 (/4 1920)
>[ 73044.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019b10]
>[ 73044.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019b10] width 1920 pitch 7680 (/4 1920)
>[ 73044.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042a40]
>[ 73044.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042a40] width 1920 pitch 7680 (/4 1920)
>[ 73044.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019b10]
>[ 73044.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019b10] width 1920 pitch 7680 (/4 1920)
>[ 73044.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015310]
>[ 73044.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015310] width 1920 pitch 7680 (/4 1920)
>[ 73044.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019b10]
>[ 73044.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019b10] width 1920 pitch 7680 (/4 1920)
>[ 73044.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7ba40]
>[ 73044.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7ba40] width 1920 pitch 7680 (/4 1920)
>[ 73044.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019b10]
>[ 73044.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019b10] width 1920 pitch 7680 (/4 1920)
>[ 73044.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfb880]
>[ 73044.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfb880] width 1920 pitch 7680 (/4 1920)
>[ 73044.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019b10]
>[ 73044.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019b10] width 1920 pitch 7680 (/4 1920)
>[ 73044.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73044.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73044.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73044.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73044.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73044.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73044.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73044.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73044.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73044.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73044.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73044.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73044.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73045.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73045.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73045.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73045.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73045.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73045.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73045.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7b380]
>[ 73045.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7b380] width 1920 pitch 7680 (/4 1920)
>[ 73045.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405c8e0]
>[ 73045.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405c8e0] width 1920 pitch 7680 (/4 1920)
>[ 73045.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73045.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 73045.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 73056.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee8c0]
>[ 73056.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee8c0] width 1920 pitch 7680 (/4 1920)
>[ 73060.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74b20]
>[ 73060.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74b20] width 1920 pitch 7680 (/4 1920)
>[ 73060.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73060.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73060.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73060.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73060.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73060.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73060.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73060.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73060.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73060.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73060.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 73060.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 73060.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 73060.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 73060.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19c30]
>[ 73060.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19c30] width 1920 pitch 7680 (/4 1920)
>[ 73060.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 73060.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 73061.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e8f0]
>[ 73061.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e8f0] width 1920 pitch 7680 (/4 1920)
>[ 73061.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73061.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73061.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73061.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73061.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 73061.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 73061.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 73061.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 73061.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c442d0]
>[ 73061.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c442d0] width 1920 pitch 7680 (/4 1920)
>[ 73081.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add970]
>[ 73081.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add970] width 1920 pitch 7680 (/4 1920)
>[ 73081.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add970]
>[ 73081.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add970] width 1920 pitch 7680 (/4 1920)
>[ 73081.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add970]
>[ 73081.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add970] width 1920 pitch 7680 (/4 1920)
>[ 73081.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114830]
>[ 73081.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114830] width 1920 pitch 7680 (/4 1920)
>[ 73081.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0340]
>[ 73081.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0340] width 1920 pitch 7680 (/4 1920)
>[ 73081.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114830]
>[ 73081.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114830] width 1920 pitch 7680 (/4 1920)
>[ 73081.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba0b50]
>[ 73081.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba0b50] width 1920 pitch 7680 (/4 1920)
>[ 73081.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba0b50]
>[ 73081.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba0b50] width 1920 pitch 7680 (/4 1920)
>[ 73081.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0340]
>[ 73081.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0340] width 1920 pitch 7680 (/4 1920)
>[ 73081.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0340]
>[ 73081.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0340] width 1920 pitch 7680 (/4 1920)
>[ 73081.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add970]
>[ 73081.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add970] width 1920 pitch 7680 (/4 1920)
>[ 73081.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba0b50]
>[ 73081.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba0b50] width 1920 pitch 7680 (/4 1920)
>[ 73081.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501f150]
>[ 73081.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501f150] width 1920 pitch 7680 (/4 1920)
>[ 73081.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73081.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73081.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73081.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73081.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114830]
>[ 73081.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114830] width 1920 pitch 7680 (/4 1920)
>[ 73081.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73082.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73082.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add970]
>[ 73082.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add970] width 1920 pitch 7680 (/4 1920)
>[ 73082.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048c40]
>[ 73082.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048c40] width 1920 pitch 7680 (/4 1920)
>[ 73082.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2920]
>[ 73082.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2920] width 1920 pitch 7680 (/4 1920)
>[ 73082.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44390]
>[ 73082.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44390] width 1920 pitch 7680 (/4 1920)
>[ 73082.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048c40]
>[ 73082.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048c40] width 1920 pitch 7680 (/4 1920)
>[ 73082.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba0b50]
>[ 73082.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba0b50] width 1920 pitch 7680 (/4 1920)
>[ 73086.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 73086.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 73124.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a330]
>[ 73124.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a330] width 1920 pitch 7680 (/4 1920)
>[ 73129.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45130]
>[ 73129.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45130] width 1920 pitch 7680 (/4 1920)
>[ 73129.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a840]
>[ 73129.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a840] width 1920 pitch 7680 (/4 1920)
>[ 73129.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45130]
>[ 73129.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45130] width 1920 pitch 7680 (/4 1920)
>[ 73129.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a880]
>[ 73129.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a880] width 1920 pitch 7680 (/4 1920)
>[ 73129.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a880]
>[ 73129.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a880] width 1920 pitch 7680 (/4 1920)
>[ 73129.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a880]
>[ 73129.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a880] width 1920 pitch 7680 (/4 1920)
>[ 73129.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45130]
>[ 73129.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45130] width 1920 pitch 7680 (/4 1920)
>[ 73129.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a880]
>[ 73129.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a880] width 1920 pitch 7680 (/4 1920)
>[ 73129.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a9b0]
>[ 73129.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a9b0] width 1920 pitch 7680 (/4 1920)
>[ 73129.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a880]
>[ 73129.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a880] width 1920 pitch 7680 (/4 1920)
>[ 73140.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73140.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73140.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c451d0]
>[ 73140.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c451d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73140.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73140.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c46350]
>[ 73140.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c46350] width 1920 pitch 7680 (/4 1920)
>[ 73140.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73140.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73140.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73140.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73140.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c451d0]
>[ 73140.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c451d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73140.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73140.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c46350]
>[ 73140.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c46350] width 1920 pitch 7680 (/4 1920)
>[ 73140.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73140.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73140.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73140.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73140.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c451d0]
>[ 73140.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c451d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73140.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73140.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda8d0]
>[ 73140.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda8d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73140.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73140.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73140.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73140.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c451d0]
>[ 73140.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c451d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73140.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73140.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda8d0]
>[ 73140.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda8d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73140.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73140.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea00b0]
>[ 73140.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea00b0] width 1920 pitch 7680 (/4 1920)
>[ 73140.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73140.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73140.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c451d0]
>[ 73140.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c451d0] width 1920 pitch 7680 (/4 1920)
>[ 73140.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73140.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84150]
>[ 73142.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84150] width 1920 pitch 7680 (/4 1920)
>[ 73142.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46930]
>[ 73142.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46930] width 1920 pitch 7680 (/4 1920)
>[ 73142.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46930]
>[ 73142.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46930] width 1920 pitch 7680 (/4 1920)
>[ 73142.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51147f0]
>[ 73142.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51147f0] width 1920 pitch 7680 (/4 1920)
>[ 73142.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31e50]
>[ 73142.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31e50] width 1920 pitch 7680 (/4 1920)
>[ 73142.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51147f0]
>[ 73142.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51147f0] width 1920 pitch 7680 (/4 1920)
>[ 73142.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51147f0]
>[ 73142.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51147f0] width 1920 pitch 7680 (/4 1920)
>[ 73142.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b340]
>[ 73142.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b340] width 1920 pitch 7680 (/4 1920)
>[ 73142.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395a790]
>[ 73142.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395a790] width 1920 pitch 7680 (/4 1920)
>[ 73142.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73142.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395a790]
>[ 73142.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395a790] width 1920 pitch 7680 (/4 1920)
>[ 73142.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1010]
>[ 73142.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1010] width 1920 pitch 7680 (/4 1920)
>[ 73148.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73148.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73148.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73148.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73148.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73148.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73148.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73148.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73148.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73148.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73148.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73148.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73148.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73148.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73148.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73148.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73148.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73148.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73148.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73148.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73148.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73148.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73148.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73148.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73148.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73148.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73148.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73148.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73148.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73148.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73149.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73149.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73149.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73149.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73149.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73149.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73149.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73149.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b200]
>[ 73149.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b200] width 1920 pitch 7680 (/4 1920)
>[ 73149.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45840]
>[ 73149.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45840] width 1920 pitch 7680 (/4 1920)
>[ 73149.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5018050]
>[ 73149.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5018050] width 1920 pitch 7680 (/4 1920)
>[ 73149.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e841d0]
>[ 73149.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e841d0] width 1920 pitch 7680 (/4 1920)
>[ 73152.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28370b0]
>[ 73152.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28370b0] width 1920 pitch 7680 (/4 1920)
>[ 73184.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea11d0]
>[ 73184.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea11d0] width 1920 pitch 7680 (/4 1920)
>[ 73184.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3070]
>[ 73184.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3070] width 1920 pitch 7680 (/4 1920)
>[ 73185.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b531a0]
>[ 73185.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b531a0] width 1920 pitch 7680 (/4 1920)
>[ 73185.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 73185.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 73185.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 73185.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 73186.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 73186.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 73186.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73186.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73186.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73186.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73186.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73186.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73186.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73186.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73186.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73186.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73186.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73186.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73186.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73186.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73186.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89610]
>[ 73186.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89610] width 1920 pitch 7680 (/4 1920)
>[ 73186.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 73186.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 73186.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73186.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73186.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73186.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73186.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b130]
>[ 73186.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b130] width 1920 pitch 7680 (/4 1920)
>[ 73186.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 73186.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 73186.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 73186.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 73186.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73186.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73186.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 73186.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 73186.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 73186.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 73186.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73186.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73186.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73186.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73186.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73186.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73186.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 73187.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 73187.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec8d60]
>[ 73187.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec8d60] width 1920 pitch 7680 (/4 1920)
>[ 73187.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e940b0]
>[ 73187.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e940b0] width 1920 pitch 7680 (/4 1920)
>[ 73187.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 73187.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 73187.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73187.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73187.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73187.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73187.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73187.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73187.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 73187.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 73187.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 73187.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 73187.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73187.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73187.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73187.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73187.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73187.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73187.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 73187.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 73187.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec8d60]
>[ 73187.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec8d60] width 1920 pitch 7680 (/4 1920)
>[ 73187.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e940b0]
>[ 73187.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e940b0] width 1920 pitch 7680 (/4 1920)
>[ 73187.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 73187.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 73187.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73187.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73187.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73187.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73187.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392e850]
>[ 73187.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392e850] width 1920 pitch 7680 (/4 1920)
>[ 73187.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88090]
>[ 73187.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88090] width 1920 pitch 7680 (/4 1920)
>[ 73187.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37730]
>[ 73187.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37730] width 1920 pitch 7680 (/4 1920)
>[ 73188.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 73188.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 73188.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73188.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73188.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89610]
>[ 73188.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89610] width 1920 pitch 7680 (/4 1920)
>[ 73188.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 73188.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 73188.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 73188.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 73188.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 73188.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 73188.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 73188.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 73188.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 73188.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 73188.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdabf0]
>[ 73188.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdabf0] width 1920 pitch 7680 (/4 1920)
>[ 73188.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 73188.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 73188.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88090]
>[ 73188.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88090] width 1920 pitch 7680 (/4 1920)
>[ 73188.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40437e0]
>[ 73188.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40437e0] width 1920 pitch 7680 (/4 1920)
>[ 73188.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 73188.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 73188.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b130]
>[ 73188.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b130] width 1920 pitch 7680 (/4 1920)
>[ 73188.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872990]
>[ 73189.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872990] width 1920 pitch 7680 (/4 1920)
>[ 73189.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81780]
>[ 73189.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81780] width 1920 pitch 7680 (/4 1920)
>[ 73189.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5129ad0]
>[ 73189.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5129ad0] width 1920 pitch 7680 (/4 1920)
>[ 73189.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 73189.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 73189.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada4b0]
>[ 73189.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada4b0] width 1920 pitch 7680 (/4 1920)
>[ 73189.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed8350]
>[ 73189.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed8350] width 1920 pitch 7680 (/4 1920)
>[ 73189.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5670]
>[ 73189.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5670] width 1920 pitch 7680 (/4 1920)
>[ 73189.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 73189.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 73373.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece990]
>[ 73373.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece990] width 1920 pitch 7680 (/4 1920)
>[ 73373.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b531a0]
>[ 73373.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b531a0] width 1920 pitch 7680 (/4 1920)
>[ 73374.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94f40]
>[ 73374.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94f40] width 1920 pitch 7680 (/4 1920)
>[ 73374.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cfd50]
>[ 73374.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cfd50] width 1920 pitch 7680 (/4 1920)
>[ 73374.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 73374.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 73374.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6fd50]
>[ 73374.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6fd50] width 1920 pitch 7680 (/4 1920)
>[ 73374.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73374.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73374.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 73374.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 73374.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da8d10]
>[ 73374.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da8d10] width 1920 pitch 7680 (/4 1920)
>[ 73374.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 73374.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 73374.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 73374.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 73374.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eceae0]
>[ 73374.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eceae0] width 1920 pitch 7680 (/4 1920)
>[ 73374.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820cc0]
>[ 73374.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820cc0] width 1920 pitch 7680 (/4 1920)
>[ 73374.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 73374.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 73374.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5eda0]
>[ 73374.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5eda0] width 1920 pitch 7680 (/4 1920)
>[ 73374.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 73374.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 73374.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6fd50]
>[ 73374.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6fd50] width 1920 pitch 7680 (/4 1920)
>[ 73375.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 73375.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 73378.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 73378.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 73378.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 73378.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 73378.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73378.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 73379.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 73379.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4aaf0]
>[ 73379.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4aaf0] width 1920 pitch 7680 (/4 1920)
>[ 73379.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1680]
>[ 73379.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1680] width 1920 pitch 7680 (/4 1920)
>[ 73552.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de3420]
>[ 73552.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de3420] width 1920 pitch 7680 (/4 1920)
>[ 73552.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8c3e0]
>[ 73552.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8c3e0] width 1920 pitch 7680 (/4 1920)
>[ 73552.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 73552.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 73552.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 73552.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 73552.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de3420]
>[ 73553.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de3420] width 1920 pitch 7680 (/4 1920)
>[ 73553.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50544b0]
>[ 73553.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50544b0] width 1920 pitch 7680 (/4 1920)
>[ 73553.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[ 73553.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[ 73553.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284afa0]
>[ 73553.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284afa0] width 1920 pitch 7680 (/4 1920)
>[ 73553.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f627a0]
>[ 73553.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f627a0] width 1920 pitch 7680 (/4 1920)
>[ 73553.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 73553.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 73553.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57b20]
>[ 73553.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57b20] width 1920 pitch 7680 (/4 1920)
>[ 73553.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2874a20]
>[ 73553.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2874a20] width 1920 pitch 7680 (/4 1920)
>[ 73553.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fac040]
>[ 73553.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fac040] width 1920 pitch 7680 (/4 1920)
>[ 73553.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 73553.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 73553.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 73553.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 73553.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 73553.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 73553.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb6260]
>[ 73553.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb6260] width 1920 pitch 7680 (/4 1920)
>[ 73553.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f57c40]
>[ 73553.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f57c40] width 1920 pitch 7680 (/4 1920)
>[ 73553.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73553.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73587.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8a1d0]
>[ 73587.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8a1d0] width 1920 pitch 7680 (/4 1920)
>[ 73587.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 73587.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 73588.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09050]
>[ 73588.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09050] width 1920 pitch 7680 (/4 1920)
>[ 73588.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb530]
>[ 73588.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb530] width 1920 pitch 7680 (/4 1920)
>[ 73588.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73588.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73588.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5120]
>[ 73588.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5120] width 1920 pitch 7680 (/4 1920)
>[ 73588.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e5a0]
>[ 73588.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e5a0] width 1920 pitch 7680 (/4 1920)
>[ 73588.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fac040]
>[ 73588.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fac040] width 1920 pitch 7680 (/4 1920)
>[ 73588.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 73588.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 73588.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73588.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73588.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 73588.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 73588.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[ 73588.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1920 pitch 7680 (/4 1920)
>[ 73588.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 73588.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 73588.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb6260]
>[ 73588.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb6260] width 1920 pitch 7680 (/4 1920)
>[ 73588.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb42e0]
>[ 73588.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb42e0] width 1920 pitch 7680 (/4 1920)
>[ 73588.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ddf0]
>[ 73588.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ddf0] width 1920 pitch 7680 (/4 1920)
>[ 73588.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09130]
>[ 73588.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09130] width 1920 pitch 7680 (/4 1920)
>[ 73588.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73588.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73588.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 73588.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 73588.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8c3e0]
>[ 73588.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8c3e0] width 1920 pitch 7680 (/4 1920)
>[ 73600.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 73600.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 73600.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef4290]
>[ 73600.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef4290] width 1920 pitch 7680 (/4 1920)
>[ 73601.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ca00]
>[ 73601.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ca00] width 1920 pitch 7680 (/4 1920)
>[ 73601.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73601.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73601.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73601.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73601.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 73601.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 73601.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c56ef0]
>[ 73601.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c56ef0] width 1920 pitch 7680 (/4 1920)
>[ 73601.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 73601.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 73601.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 73601.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 73601.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 73601.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 73601.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73601.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73601.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7470]
>[ 73601.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7470] width 1920 pitch 7680 (/4 1920)
>[ 73601.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 73601.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 73601.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73601.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73601.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c710]
>[ 73601.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c710] width 1920 pitch 7680 (/4 1920)
>[ 73601.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 73601.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 73601.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 73601.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 73601.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 73601.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 73601.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73601.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73601.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 73601.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 73601.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f627a0]
>[ 73601.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f627a0] width 1920 pitch 7680 (/4 1920)
>[ 73601.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 73601.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 73601.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73601.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73601.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc1710]
>[ 73601.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc1710] width 1920 pitch 7680 (/4 1920)
>[ 73601.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06b90]
>[ 73601.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06b90] width 1920 pitch 7680 (/4 1920)
>[ 73601.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 73601.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 73601.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 73601.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 73601.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 73601.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 73601.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 73602.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 73602.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051ee0]
>[ 73602.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051ee0] width 1920 pitch 7680 (/4 1920)
>[ 73602.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 73602.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 73602.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 73602.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 73602.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 73602.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 73602.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 73602.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 73602.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdf50]
>[ 73602.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdf50] width 1920 pitch 7680 (/4 1920)
>[ 73602.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 73602.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 73602.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73602.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73602.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7470]
>[ 73602.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7470] width 1920 pitch 7680 (/4 1920)
>[ 73602.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 73602.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 73602.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73602.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73602.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c710]
>[ 73602.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c710] width 1920 pitch 7680 (/4 1920)
>[ 73602.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 73602.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 73602.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 73602.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 73602.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 73602.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 73602.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73602.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73602.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 73602.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 73602.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f627a0]
>[ 73602.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f627a0] width 1920 pitch 7680 (/4 1920)
>[ 73602.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 73602.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 73620.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73620.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73620.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c56ef0]
>[ 73620.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c56ef0] width 1920 pitch 7680 (/4 1920)
>[ 73620.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 73620.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 73620.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 73620.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 73620.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 73620.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 73620.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73620.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73620.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[ 73620.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[ 73620.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 73620.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 73620.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f627a0]
>[ 73620.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f627a0] width 1920 pitch 7680 (/4 1920)
>[ 73620.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 73620.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 73620.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf200]
>[ 73620.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf200] width 1920 pitch 7680 (/4 1920)
>[ 73620.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 73620.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 73624.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 73624.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 73624.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 73624.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 73624.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 73624.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 73624.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ca00]
>[ 73624.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ca00] width 1920 pitch 7680 (/4 1920)
>[ 73624.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 73624.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 73624.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 73624.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 73624.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73624.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73624.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 73625.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 73625.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 73625.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 73625.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 73625.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 73625.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf200]
>[ 73626.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf200] width 1920 pitch 7680 (/4 1920)
>[ 73626.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdf50]
>[ 73626.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdf50] width 1920 pitch 7680 (/4 1920)
>[ 73626.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 73626.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 73626.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1260]
>[ 73626.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1260] width 1920 pitch 7680 (/4 1920)
>[ 73626.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 73626.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 73626.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 73626.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 73626.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 73626.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 73626.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 73626.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 73626.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 73626.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 73626.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 73626.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 73626.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 73626.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 73626.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c56ef0]
>[ 73626.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c56ef0] width 1920 pitch 7680 (/4 1920)
>[ 73626.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 73626.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 73626.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051ee0]
>[ 73626.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051ee0] width 1920 pitch 7680 (/4 1920)
>[ 73626.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 73626.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 73626.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40210f0]
>[ 73626.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40210f0] width 1920 pitch 7680 (/4 1920)
>[ 73626.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 73626.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 73626.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 73626.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 73626.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 73626.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 73626.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 73626.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 73626.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 73626.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 73626.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 73626.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 73640.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e5a0]
>[ 73640.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e5a0] width 1920 pitch 7680 (/4 1920)
>[ 73640.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73640.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73640.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73640.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73641.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73641.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73641.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73641.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73641.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73641.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73641.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73641.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73641.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73641.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73641.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73641.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73641.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73641.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73641.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73641.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73642.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73642.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73642.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73642.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73642.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73642.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73642.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73642.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73642.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73642.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73642.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73642.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73642.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73642.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73642.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73642.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73642.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73642.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73642.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73642.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73645.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73645.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73645.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73645.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73645.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73646.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73646.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73646.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73646.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73646.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73646.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73646.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73646.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73646.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73646.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73646.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73646.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73646.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73646.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73646.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73646.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73646.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73646.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73646.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73646.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bf80]
>[ 73646.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bf80] width 1920 pitch 7680 (/4 1920)
>[ 73646.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73646.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73646.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73646.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73646.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73647.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73647.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73647.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73647.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73647.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73647.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73647.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73647.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 73647.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 73647.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73647.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73647.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 73647.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 73851.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73851.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73852.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73852.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73852.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73852.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73852.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73852.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73852.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73852.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73852.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e5a0]
>[ 73852.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e5a0] width 1920 pitch 7680 (/4 1920)
>[ 73852.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73852.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73853.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73853.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73853.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73853.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73853.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73853.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73853.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73853.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73853.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73853.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73853.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73853.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73853.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73853.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73853.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73853.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73853.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73853.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73854.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73854.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73854.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73854.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73854.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73854.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73854.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73854.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73854.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73854.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73855.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73855.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73855.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73855.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73855.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73855.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73855.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73855.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73855.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73855.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73856.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73856.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73856.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73856.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73856.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73856.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73856.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73856.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73856.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73856.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73857.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73857.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73857.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73857.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73857.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73857.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73857.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73857.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73858.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73858.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73858.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73858.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73858.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73858.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73858.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73858.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73858.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73858.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73859.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73859.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73859.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73859.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73859.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73859.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73859.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73859.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73859.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73859.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73860.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73860.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73860.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73860.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73860.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73860.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73860.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73860.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73860.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73860.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73861.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73861.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73861.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73861.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73861.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73861.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73861.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73861.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73861.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73861.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73862.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73862.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73862.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73862.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73862.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73862.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73862.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73862.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73862.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73862.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73863.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73863.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73863.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73863.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73863.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73863.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73863.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73863.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73863.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73863.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73864.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73864.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73864.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73864.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73864.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73864.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73864.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73864.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73864.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73864.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73864.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73864.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73864.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73864.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73864.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73864.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73864.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73864.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73864.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73864.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73864.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73864.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73864.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73864.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73864.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73864.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73864.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73864.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73864.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73864.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73865.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73865.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73865.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73865.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73865.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73865.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73865.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73865.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73865.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73865.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73866.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73866.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73866.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73866.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73866.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73866.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73866.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73866.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73867.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73867.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73867.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73867.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73867.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73867.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73868.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73868.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73868.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73868.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73868.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73868.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73868.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73868.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73868.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73868.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73869.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73869.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73869.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73869.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb1d20]
>[ 73869.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb1d20] width 1920 pitch 7680 (/4 1920)
>[ 73869.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73869.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73869.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73869.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73869.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73870.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73870.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73870.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73870.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73870.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73870.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73870.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73870.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73870.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23920]
>[ 73870.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23920] width 1920 pitch 7680 (/4 1920)
>[ 73870.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef030]
>[ 73870.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef030] width 1920 pitch 7680 (/4 1920)
>[ 73893.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08bb0]
>[ 73893.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08bb0] width 1920 pitch 7680 (/4 1920)
>[ 73896.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73896.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73896.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f5e0]
>[ 73896.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f5e0] width 1920 pitch 7680 (/4 1920)
>[ 73896.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2881c60]
>[ 73896.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2881c60] width 1920 pitch 7680 (/4 1920)
>[ 73896.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73896.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73896.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053040]
>[ 73896.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053040] width 1920 pitch 7680 (/4 1920)
>[ 73896.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70ac0]
>[ 73896.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70ac0] width 1920 pitch 7680 (/4 1920)
>[ 73896.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053040]
>[ 73896.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053040] width 1920 pitch 7680 (/4 1920)
>[ 73896.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36210]
>[ 73896.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36210] width 1920 pitch 7680 (/4 1920)
>[ 73896.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053040]
>[ 73896.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053040] width 1920 pitch 7680 (/4 1920)
>[ 73896.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36200]
>[ 73896.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36200] width 1920 pitch 7680 (/4 1920)
>[ 73896.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053040]
>[ 73896.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053040] width 1920 pitch 7680 (/4 1920)
>[ 73896.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36200]
>[ 73896.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36200] width 1920 pitch 7680 (/4 1920)
>[ 73896.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053040]
>[ 73896.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053040] width 1920 pitch 7680 (/4 1920)
>[ 73896.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e361c0]
>[ 73896.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e361c0] width 1920 pitch 7680 (/4 1920)
>[ 73896.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06620]
>[ 73896.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06620] width 1920 pitch 7680 (/4 1920)
>[ 73896.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e361c0]
>[ 73896.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e361c0] width 1920 pitch 7680 (/4 1920)
>[ 73896.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06620]
>[ 73896.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06620] width 1920 pitch 7680 (/4 1920)
>[ 73896.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2ec70]
>[ 73896.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2ec70] width 1920 pitch 7680 (/4 1920)
>[ 73896.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06620]
>[ 73896.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06620] width 1920 pitch 7680 (/4 1920)
>[ 73896.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2ec70]
>[ 73896.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2ec70] width 1920 pitch 7680 (/4 1920)
>[ 73896.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06620]
>[ 73896.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06620] width 1920 pitch 7680 (/4 1920)
>[ 73896.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f027b0]
>[ 73896.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f027b0] width 1920 pitch 7680 (/4 1920)
>[ 73896.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f02860]
>[ 73896.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f02860] width 1920 pitch 7680 (/4 1920)
>[ 73897.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7ea0]
>[ 73897.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7ea0] width 1920 pitch 7680 (/4 1920)
>[ 73897.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5880]
>[ 73897.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5880] width 1920 pitch 7680 (/4 1920)
>[ 73903.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 73903.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 73903.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa4c0]
>[ 73903.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa4c0] width 1920 pitch 7680 (/4 1920)
>[ 73903.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73903.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73903.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd8ea0]
>[ 73903.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd8ea0] width 1920 pitch 7680 (/4 1920)
>[ 73903.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa4c0]
>[ 73903.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa4c0] width 1920 pitch 7680 (/4 1920)
>[ 73903.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc1360]
>[ 73903.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc1360] width 1920 pitch 7680 (/4 1920)
>[ 73903.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 73903.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 73903.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd8ea0]
>[ 73903.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd8ea0] width 1920 pitch 7680 (/4 1920)
>[ 73905.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa5e0]
>[ 73905.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa5e0] width 1920 pitch 7680 (/4 1920)
>[ 73905.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73905.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73905.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73905.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73905.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73905.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73905.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73905.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73905.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 73905.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 73905.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73905.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 73906.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 73906.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baab40]
>[ 73906.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baab40] width 1920 pitch 7680 (/4 1920)
>[ 73906.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 73906.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 73906.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73906.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73906.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 73906.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 73906.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73906.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73906.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73906.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73906.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73906.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73906.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73906.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73906.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73906.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73906.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73906.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73906.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73906.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73906.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73907.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73907.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73907.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73907.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73907.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73907.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73907.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73907.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73908.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e98a60]
>[ 73908.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e98a60] width 1920 pitch 7680 (/4 1920)
>[ 73908.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73908.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73908.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73908.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73908.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73908.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73908.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73908.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73908.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73908.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73908.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73908.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73908.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73908.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73908.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baab40]
>[ 73908.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baab40] width 1920 pitch 7680 (/4 1920)
>[ 73908.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[ 73908.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[ 73908.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76400]
>[ 73908.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76400] width 1920 pitch 7680 (/4 1920)
>[ 73908.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07ff0]
>[ 73908.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07ff0] width 1920 pitch 7680 (/4 1920)
>[ 73908.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baab40]
>[ 73908.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baab40] width 1920 pitch 7680 (/4 1920)
>[ 73908.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 73908.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 73917.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51044d0]
>[ 73917.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51044d0] width 1920 pitch 7680 (/4 1920)
>[ 73917.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ced80]
>[ 73917.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ced80] width 1920 pitch 7680 (/4 1920)
>[ 73917.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73917.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 73982.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b317f0]
>[ 73982.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b317f0] width 1920 pitch 7680 (/4 1920)
>[ 73982.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 73982.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 74163.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[ 74163.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[ 74163.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506f020]
>[ 74163.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506f020] width 1920 pitch 7680 (/4 1920)
>[ 74163.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72460]
>[ 74164.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72460] width 1920 pitch 7680 (/4 1920)
>[ 74164.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1e90]
>[ 74164.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1e90] width 1920 pitch 7680 (/4 1920)
>[ 74164.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74164.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74164.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e63e30]
>[ 74164.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e63e30] width 1920 pitch 7680 (/4 1920)
>[ 74164.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 74164.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 74164.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74164.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74164.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64750]
>[ 74164.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64750] width 1920 pitch 7680 (/4 1920)
>[ 74164.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74164.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74164.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74164.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74164.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74164.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74165.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d740]
>[ 74165.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d740] width 1920 pitch 7680 (/4 1920)
>[ 74165.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72460]
>[ 74165.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72460] width 1920 pitch 7680 (/4 1920)
>[ 74165.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72460]
>[ 74165.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72460] width 1920 pitch 7680 (/4 1920)
>[ 74165.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[ 74165.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[ 74165.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1e90]
>[ 74165.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1e90] width 1920 pitch 7680 (/4 1920)
>[ 74165.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 74165.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 74165.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d740]
>[ 74165.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d740] width 1920 pitch 7680 (/4 1920)
>[ 74165.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51c20]
>[ 74165.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51c20] width 1920 pitch 7680 (/4 1920)
>[ 74165.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74165.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74165.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74165.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74166.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64750]
>[ 74166.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64750] width 1920 pitch 7680 (/4 1920)
>[ 74166.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 74166.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 74166.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d740]
>[ 74166.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d740] width 1920 pitch 7680 (/4 1920)
>[ 74166.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51c20]
>[ 74166.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51c20] width 1920 pitch 7680 (/4 1920)
>[ 74166.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506f020]
>[ 74166.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506f020] width 1920 pitch 7680 (/4 1920)
>[ 74166.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74166.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74166.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e63e30]
>[ 74166.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e63e30] width 1920 pitch 7680 (/4 1920)
>[ 74166.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74166.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74166.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51c20]
>[ 74166.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51c20] width 1920 pitch 7680 (/4 1920)
>[ 74167.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72230]
>[ 74167.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72230] width 1920 pitch 7680 (/4 1920)
>[ 74167.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7340]
>[ 74167.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7340] width 1920 pitch 7680 (/4 1920)
>[ 74168.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69990d0]
>[ 74168.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69990d0] width 1920 pitch 7680 (/4 1920)
>[ 74168.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2e4e0]
>[ 74168.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2e4e0] width 1920 pitch 7680 (/4 1920)
>[ 74168.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4c30]
>[ 74169.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4c30] width 1920 pitch 7680 (/4 1920)
>[ 74169.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a836e0]
>[ 74169.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a836e0] width 1920 pitch 7680 (/4 1920)
>[ 74169.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a836e0]
>[ 74169.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a836e0] width 1920 pitch 7680 (/4 1920)
>[ 74169.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 74169.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 74187.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d51c20]
>[ 74187.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d51c20] width 1920 pitch 7680 (/4 1920)
>[ 74192.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74192.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74192.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74192.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74192.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74192.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74192.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02ea0]
>[ 74192.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02ea0] width 1920 pitch 7680 (/4 1920)
>[ 74192.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18c60]
>[ 74192.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18c60] width 1920 pitch 7680 (/4 1920)
>[ 74192.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 74192.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 74192.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69997e0]
>[ 74192.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69997e0] width 1920 pitch 7680 (/4 1920)
>[ 74192.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506f020]
>[ 74192.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506f020] width 1920 pitch 7680 (/4 1920)
>[ 74192.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74192.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74192.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74192.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74192.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d740]
>[ 74192.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d740] width 1920 pitch 7680 (/4 1920)
>[ 74192.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e63e30]
>[ 74192.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e63e30] width 1920 pitch 7680 (/4 1920)
>[ 74192.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69997e0]
>[ 74192.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69997e0] width 1920 pitch 7680 (/4 1920)
>[ 74192.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506f020]
>[ 74192.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506f020] width 1920 pitch 7680 (/4 1920)
>[ 74192.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74192.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74192.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74192.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74192.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d740]
>[ 74192.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d740] width 1920 pitch 7680 (/4 1920)
>[ 74192.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e63e30]
>[ 74192.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e63e30] width 1920 pitch 7680 (/4 1920)
>[ 74192.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69997e0]
>[ 74192.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69997e0] width 1920 pitch 7680 (/4 1920)
>[ 74192.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506f020]
>[ 74192.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506f020] width 1920 pitch 7680 (/4 1920)
>[ 74192.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cbf0]
>[ 74192.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cbf0] width 1920 pitch 7680 (/4 1920)
>[ 74192.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74192.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74192.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74192.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74294.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44590]
>[ 74294.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44590] width 1920 pitch 7680 (/4 1920)
>[ 74294.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74294.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2ea0]
>[ 74295.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2ea0] width 1920 pitch 7680 (/4 1920)
>[ 74295.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5910]
>[ 74295.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5910] width 1920 pitch 7680 (/4 1920)
>[ 74295.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a2500]
>[ 74295.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a2500] width 1920 pitch 7680 (/4 1920)
>[ 74444.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856f20]
>[ 74444.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856f20] width 1920 pitch 7680 (/4 1920)
>[ 74444.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74444.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74445.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 74445.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 74445.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 74445.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 74445.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74445.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74445.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 74445.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 74445.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30000]
>[ 74445.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30000] width 1920 pitch 7680 (/4 1920)
>[ 74445.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 74445.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 74445.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 74445.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 74445.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856f20]
>[ 74445.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856f20] width 1920 pitch 7680 (/4 1920)
>[ 74445.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 74446.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 74446.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74446.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74446.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 74446.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 74446.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30000]
>[ 74446.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30000] width 1920 pitch 7680 (/4 1920)
>[ 74446.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 74446.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 74446.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 74446.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 74446.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856f20]
>[ 74446.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856f20] width 1920 pitch 7680 (/4 1920)
>[ 74446.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74446.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74446.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74446.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74446.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f15e80]
>[ 74446.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f15e80] width 1920 pitch 7680 (/4 1920)
>[ 74446.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae40]
>[ 74446.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae40] width 1920 pitch 7680 (/4 1920)
>[ 74446.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74446.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74446.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 74446.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 74446.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e63e30]
>[ 74446.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e63e30] width 1920 pitch 7680 (/4 1920)
>[ 74446.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 74446.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 74446.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74446.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74446.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856f20]
>[ 74446.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856f20] width 1920 pitch 7680 (/4 1920)
>[ 74446.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 74446.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 74446.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30000]
>[ 74446.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30000] width 1920 pitch 7680 (/4 1920)
>[ 74446.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 74446.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 74446.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74446.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74446.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 74446.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 74446.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74446.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74446.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74446.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74446.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 74446.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 74446.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74446.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74446.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae40]
>[ 74446.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae40] width 1920 pitch 7680 (/4 1920)
>[ 74446.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f15e80]
>[ 74446.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f15e80] width 1920 pitch 7680 (/4 1920)
>[ 74446.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74446.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74446.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74446.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74446.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 74447.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 74447.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74447.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74447.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ae40]
>[ 74447.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ae40] width 1920 pitch 7680 (/4 1920)
>[ 74447.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f15e80]
>[ 74447.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f15e80] width 1920 pitch 7680 (/4 1920)
>[ 74447.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74447.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74447.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44530]
>[ 74447.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44530] width 1920 pitch 7680 (/4 1920)
>[ 74447.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28246c0]
>[ 74447.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28246c0] width 1920 pitch 7680 (/4 1920)
>[ 74447.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5edd0]
>[ 74447.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5edd0] width 1920 pitch 7680 (/4 1920)
>[ 74447.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 74447.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 74449.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74449.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74449.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6650]
>[ 74449.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6650] width 1920 pitch 7680 (/4 1920)
>[ 74450.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1f7d0]
>[ 74450.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1f7d0] width 1920 pitch 7680 (/4 1920)
>[ 74450.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59c40]
>[ 74450.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59c40] width 1920 pitch 7680 (/4 1920)
>[ 74450.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6650]
>[ 74450.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6650] width 1920 pitch 7680 (/4 1920)
>[ 74450.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b370]
>[ 74450.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b370] width 1920 pitch 7680 (/4 1920)
>[ 74450.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e1d0]
>[ 74450.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e1d0] width 1920 pitch 7680 (/4 1920)
>[ 74450.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fc10]
>[ 74450.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fc10] width 1920 pitch 7680 (/4 1920)
>[ 74450.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 74450.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 74450.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74450.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74450.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8060]
>[ 74450.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8060] width 1920 pitch 7680 (/4 1920)
>[ 74450.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37730]
>[ 74450.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37730] width 1920 pitch 7680 (/4 1920)
>[ 74450.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[ 74450.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[ 74450.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21bb0]
>[ 74450.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21bb0] width 1920 pitch 7680 (/4 1920)
>[ 74450.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 74450.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 74450.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 74450.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 74450.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59c40]
>[ 74450.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59c40] width 1920 pitch 7680 (/4 1920)
>[ 74450.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6650]
>[ 74450.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6650] width 1920 pitch 7680 (/4 1920)
>[ 74450.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b370]
>[ 74450.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b370] width 1920 pitch 7680 (/4 1920)
>[ 74450.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 74450.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 74450.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 74450.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 74450.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74450.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74489.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30000]
>[ 74489.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30000] width 1920 pitch 7680 (/4 1920)
>[ 74489.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 74489.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 74490.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[ 74490.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[ 74490.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 74490.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 74490.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 74490.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 74490.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6e000]
>[ 74490.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6e000] width 1920 pitch 7680 (/4 1920)
>[ 74490.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240]
>[ 74490.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1920 pitch 7680 (/4 1920)
>[ 74490.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5eb00]
>[ 74490.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5eb00] width 1920 pitch 7680 (/4 1920)
>[ 74490.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397e340]
>[ 74490.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397e340] width 1920 pitch 7680 (/4 1920)
>[ 74490.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa6250]
>[ 74490.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa6250] width 1920 pitch 7680 (/4 1920)
>[ 74490.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be58b0]
>[ 74490.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be58b0] width 1920 pitch 7680 (/4 1920)
>[ 74490.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 74490.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 74490.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509ca40]
>[ 74490.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509ca40] width 1920 pitch 7680 (/4 1920)
>[ 74490.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 74490.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 74490.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fc10]
>[ 74490.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fc10] width 1920 pitch 7680 (/4 1920)
>[ 74490.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 74490.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 74490.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e736c0]
>[ 74490.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e736c0] width 1920 pitch 7680 (/4 1920)
>[ 74490.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c2930]
>[ 74490.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c2930] width 1920 pitch 7680 (/4 1920)
>[ 74490.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 74490.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 74490.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74490.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74490.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74490.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74579.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74579.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74579.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74579.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74580.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74580.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74580.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74580.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74581.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74581.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74581.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74581.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74581.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74581.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74581.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74581.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74581.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 74581.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 74581.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 74581.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 74581.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 74581.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 74581.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 74581.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 74582.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051ee0]
>[ 74582.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051ee0] width 1920 pitch 7680 (/4 1920)
>[ 74582.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 74582.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 74582.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74582.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74582.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74582.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74583.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74583.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74583.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74583.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74583.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74583.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74583.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74583.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74583.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74583.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74583.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74583.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74583.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74583.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5ae40]
>[ 74583.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5ae40] width 1920 pitch 7680 (/4 1920)
>[ 74583.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74583.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5ae40]
>[ 74584.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5ae40] width 1920 pitch 7680 (/4 1920)
>[ 74584.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 74584.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 74584.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74584.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74584.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74585.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077120]
>[ 74585.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077120] width 1920 pitch 7680 (/4 1920)
>[ 74588.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c800]
>[ 74588.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c800] width 1920 pitch 7680 (/4 1920)
>[ 74900.087] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 74900.087] (II) RADEON(0): Using hsync ranges from config file
>[ 74900.087] (II) RADEON(0): Using vrefresh ranges from config file
>[ 74900.087] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 74900.087] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 74900.087] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 74900.087] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 74900.088] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 74900.088] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 74900.088] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 74990.741] (II) RADEON(0): RADEONSaveScreen(2)
>[ 74990.741] (II) RADEON(0): RADEONSaveScreen(0)
>[ 77347.994] (II) RADEON(0): RADEONSaveScreen(1)
>[ 77366.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5081300]
>[ 77366.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5081300] width 1920 pitch 7680 (/4 1920)
>[ 77367.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146b40]
>[ 77367.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146b40] width 1920 pitch 7680 (/4 1920)
>[ 77367.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5081300]
>[ 77367.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5081300] width 1920 pitch 7680 (/4 1920)
>[ 77367.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad3380]
>[ 77367.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad3380] width 1920 pitch 7680 (/4 1920)
>[ 77367.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d940]
>[ 77367.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d940] width 1920 pitch 7680 (/4 1920)
>[ 77367.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3b710]
>[ 77367.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3b710] width 1920 pitch 7680 (/4 1920)
>[ 77367.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfcf60]
>[ 77367.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfcf60] width 1920 pitch 7680 (/4 1920)
>[ 77367.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f51c0]
>[ 77367.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f51c0] width 1920 pitch 7680 (/4 1920)
>[ 77367.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77367.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77367.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54f90]
>[ 77367.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54f90] width 1920 pitch 7680 (/4 1920)
>[ 77367.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146b40]
>[ 77367.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146b40] width 1920 pitch 7680 (/4 1920)
>[ 77368.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e58fc0]
>[ 77368.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e58fc0] width 1920 pitch 7680 (/4 1920)
>[ 77371.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa72f0]
>[ 77371.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa72f0] width 1920 pitch 7680 (/4 1920)
>[ 77371.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad3380]
>[ 77371.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad3380] width 1920 pitch 7680 (/4 1920)
>[ 77371.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a6d0]
>[ 77371.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a6d0] width 1920 pitch 7680 (/4 1920)
>[ 77371.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e58fc0]
>[ 77371.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e58fc0] width 1920 pitch 7680 (/4 1920)
>[ 77371.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146b40]
>[ 77371.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146b40] width 1920 pitch 7680 (/4 1920)
>[ 77371.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa72f0]
>[ 77371.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa72f0] width 1920 pitch 7680 (/4 1920)
>[ 77371.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d3b0]
>[ 77371.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d3b0] width 1920 pitch 7680 (/4 1920)
>[ 77371.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa72f0]
>[ 77371.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa72f0] width 1920 pitch 7680 (/4 1920)
>[ 77371.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d940]
>[ 77371.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d940] width 1920 pitch 7680 (/4 1920)
>[ 77371.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54f90]
>[ 77371.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54f90] width 1920 pitch 7680 (/4 1920)
>[ 77371.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5081300]
>[ 77371.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5081300] width 1920 pitch 7680 (/4 1920)
>[ 77371.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54f90]
>[ 77371.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54f90] width 1920 pitch 7680 (/4 1920)
>[ 77371.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f51c0]
>[ 77371.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f51c0] width 1920 pitch 7680 (/4 1920)
>[ 77371.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfcf60]
>[ 77371.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfcf60] width 1920 pitch 7680 (/4 1920)
>[ 77371.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa7060]
>[ 77371.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa7060] width 1920 pitch 7680 (/4 1920)
>[ 77371.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfcf60]
>[ 77371.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfcf60] width 1920 pitch 7680 (/4 1920)
>[ 77371.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3b710]
>[ 77371.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3b710] width 1920 pitch 7680 (/4 1920)
>[ 77371.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e58fc0]
>[ 77371.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e58fc0] width 1920 pitch 7680 (/4 1920)
>[ 77371.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b90]
>[ 77371.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b90] width 1920 pitch 7680 (/4 1920)
>[ 77371.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd6b0]
>[ 77371.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd6b0] width 1920 pitch 7680 (/4 1920)
>[ 77371.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99680]
>[ 77371.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99680] width 1920 pitch 7680 (/4 1920)
>[ 77371.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019900]
>[ 77371.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019900] width 1920 pitch 7680 (/4 1920)
>[ 77371.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b90]
>[ 77371.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b90] width 1920 pitch 7680 (/4 1920)
>[ 77371.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99460]
>[ 77371.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99460] width 1920 pitch 7680 (/4 1920)
>[ 77371.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea44f0]
>[ 77371.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea44f0] width 1920 pitch 7680 (/4 1920)
>[ 77371.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99460]
>[ 77371.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99460] width 1920 pitch 7680 (/4 1920)
>[ 77371.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99460]
>[ 77371.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99460] width 1920 pitch 7680 (/4 1920)
>[ 77371.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea45b0]
>[ 77371.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea45b0] width 1920 pitch 7680 (/4 1920)
>[ 77371.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99460]
>[ 77371.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99460] width 1920 pitch 7680 (/4 1920)
>[ 77371.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea45b0]
>[ 77371.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea45b0] width 1920 pitch 7680 (/4 1920)
>[ 77373.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6160]
>[ 77373.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6160] width 1920 pitch 7680 (/4 1920)
>[ 77373.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c40d50]
>[ 77373.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c40d50] width 1920 pitch 7680 (/4 1920)
>[ 77373.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54b20]
>[ 77373.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54b20] width 1920 pitch 7680 (/4 1920)
>[ 77373.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ca40]
>[ 77373.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ca40] width 1920 pitch 7680 (/4 1920)
>[ 77373.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1ea50]
>[ 77373.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1ea50] width 1920 pitch 7680 (/4 1920)
>[ 77373.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ca40]
>[ 77373.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ca40] width 1920 pitch 7680 (/4 1920)
>[ 77373.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf50]
>[ 77373.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf50] width 1920 pitch 7680 (/4 1920)
>[ 77373.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf960]
>[ 77373.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf960] width 1920 pitch 7680 (/4 1920)
>[ 77373.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ca40]
>[ 77373.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ca40] width 1920 pitch 7680 (/4 1920)
>[ 77373.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf960]
>[ 77373.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf960] width 1920 pitch 7680 (/4 1920)
>[ 77373.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ca40]
>[ 77373.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ca40] width 1920 pitch 7680 (/4 1920)
>[ 77373.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a4f0]
>[ 77373.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a4f0] width 1920 pitch 7680 (/4 1920)
>[ 77373.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3ca40]
>[ 77373.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3ca40] width 1920 pitch 7680 (/4 1920)
>[ 77373.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a4f0]
>[ 77373.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a4f0] width 1920 pitch 7680 (/4 1920)
>[ 77840.784] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 77840.784] (II) RADEON(0): Using hsync ranges from config file
>[ 77840.784] (II) RADEON(0): Using vrefresh ranges from config file
>[ 77840.784] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 77840.784] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 77840.784] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 77840.785] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 77930.761] (II) RADEON(0): RADEONSaveScreen(2)
>[ 77930.761] (II) RADEON(0): RADEONSaveScreen(0)
>[ 79974.953] (II) RADEON(0): RADEONSaveScreen(1)
>[ 79990.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acda80]
>[ 79990.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acda80] width 1920 pitch 7680 (/4 1920)
>[ 80000.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b0a0]
>[ 80000.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b0a0] width 1920 pitch 7680 (/4 1920)
>[ 80000.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80000.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80000.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80000.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80000.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80001.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80001.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80001.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80001.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80001.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80001.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80001.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80001.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80001.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80001.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80001.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80001.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17530]
>[ 80001.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17530] width 1920 pitch 7680 (/4 1920)
>[ 80001.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a6d0]
>[ 80001.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a6d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc6cb0]
>[ 80001.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc6cb0] width 1920 pitch 7680 (/4 1920)
>[ 80001.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80001.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80001.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52c70]
>[ 80001.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52c70] width 1920 pitch 7680 (/4 1920)
>[ 80001.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80001.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80001.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80001.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80001.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80001.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80001.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a3d0]
>[ 80001.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a3d0] width 1920 pitch 7680 (/4 1920)
>[ 80001.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a410]
>[ 80001.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a410] width 1920 pitch 7680 (/4 1920)
>[ 80001.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80001.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80001.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a410]
>[ 80001.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a410] width 1920 pitch 7680 (/4 1920)
>[ 80001.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80001.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80001.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80001.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80002.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 80002.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 80002.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 80002.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 80002.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 80002.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 80002.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 80002.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 80002.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 80002.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 80002.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 80002.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 80002.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 80002.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 80002.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 80002.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 80002.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 80002.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 80002.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06b90]
>[ 80002.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06b90] width 1920 pitch 7680 (/4 1920)
>[ 80002.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 80002.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 80002.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 80002.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 80002.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 80002.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 80002.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 80002.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 80002.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 80002.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 80002.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed3bd0]
>[ 80002.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed3bd0] width 1920 pitch 7680 (/4 1920)
>[ 80002.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 80002.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 80002.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06b90]
>[ 80002.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06b90] width 1920 pitch 7680 (/4 1920)
>[ 80002.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 80002.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 80002.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 80002.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 80002.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec160]
>[ 80002.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec160] width 1920 pitch 7680 (/4 1920)
>[ 80002.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42723d0]
>[ 80002.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42723d0] width 1920 pitch 7680 (/4 1920)
>[ 80002.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba7f0]
>[ 80002.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba7f0] width 1920 pitch 7680 (/4 1920)
>[ 80002.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45000]
>[ 80002.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45000] width 1920 pitch 7680 (/4 1920)
>[ 80002.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1260]
>[ 80002.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1260] width 1920 pitch 7680 (/4 1920)
>[ 80002.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f627a0]
>[ 80002.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f627a0] width 1920 pitch 7680 (/4 1920)
>[ 80002.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdf50]
>[ 80003.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdf50] width 1920 pitch 7680 (/4 1920)
>[ 80003.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf200]
>[ 80003.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf200] width 1920 pitch 7680 (/4 1920)
>[ 80003.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287a000]
>[ 80003.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287a000] width 1920 pitch 7680 (/4 1920)
>[ 80003.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7770]
>[ 80003.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7770] width 1920 pitch 7680 (/4 1920)
>[ 80003.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebf910]
>[ 80003.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebf910] width 1920 pitch 7680 (/4 1920)
>[ 80003.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9b970]
>[ 80003.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9b970] width 1920 pitch 7680 (/4 1920)
>[ 80003.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d700]
>[ 80003.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d700] width 1920 pitch 7680 (/4 1920)
>[ 80003.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1260]
>[ 80003.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1260] width 1920 pitch 7680 (/4 1920)
>[ 80003.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eba470]
>[ 80003.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eba470] width 1920 pitch 7680 (/4 1920)
>[ 80003.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f39e80]
>[ 80003.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f39e80] width 1920 pitch 7680 (/4 1920)
>[ 80003.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c56ef0]
>[ 80003.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c56ef0] width 1920 pitch 7680 (/4 1920)
>[ 80003.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ab0]
>[ 80003.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ab0] width 1920 pitch 7680 (/4 1920)
>[ 80003.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5600]
>[ 80003.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5600] width 1920 pitch 7680 (/4 1920)
>[ 80003.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06b90]
>[ 80003.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06b90] width 1920 pitch 7680 (/4 1920)
>[ 80003.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405cab0]
>[ 80003.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405cab0] width 1920 pitch 7680 (/4 1920)
>[ 80003.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d280]
>[ 80003.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d280] width 1920 pitch 7680 (/4 1920)
>[ 80059.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c564a0]
>[ 80059.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c564a0] width 1920 pitch 7680 (/4 1920)
>[ 80059.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa310]
>[ 80059.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa310] width 1920 pitch 7680 (/4 1920)
>[ 80059.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80059.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80111.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80111.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80111.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80111.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80111.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80111.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80111.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80111.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80111.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80111.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80111.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80111.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80111.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80111.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80111.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80111.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80111.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80111.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80111.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80111.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80111.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80112.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80112.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80112.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80112.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80112.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80112.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80112.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80112.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80112.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80112.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80112.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80112.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80112.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80112.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80112.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80112.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80112.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80112.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80112.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80112.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80112.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80112.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80112.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80112.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80112.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80112.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80112.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80112.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80112.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80112.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80112.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80112.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80112.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80112.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80112.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80112.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80112.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80112.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80112.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80112.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97630]
>[ 80112.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97630] width 1920 pitch 7680 (/4 1920)
>[ 80112.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80112.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80112.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80112.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80112.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80112.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80112.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[ 80112.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1920 pitch 7680 (/4 1920)
>[ 80112.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80112.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80112.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80112.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80112.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80112.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80112.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80112.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80112.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80112.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80113.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80113.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80113.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80113.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80113.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80113.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80113.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80113.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80113.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80113.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80113.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80113.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80113.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80113.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80113.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80113.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80113.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80113.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80113.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80113.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80113.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80113.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80113.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80113.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80113.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80113.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80113.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80113.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80113.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80113.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80113.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80113.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80113.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80113.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80113.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80113.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80113.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80113.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80113.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80113.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80113.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80113.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80113.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80113.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80113.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80113.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80113.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80113.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80113.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80113.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80113.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80113.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80113.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80113.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80113.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80113.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80113.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80113.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80113.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80113.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80113.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80113.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80113.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80113.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80114.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80114.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80114.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80114.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80114.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80114.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80114.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80114.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80114.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80114.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80114.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80114.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80114.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80114.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80114.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80114.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80114.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80114.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80114.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80114.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80114.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80114.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80114.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80114.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80114.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80114.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80114.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80114.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80114.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80114.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80114.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80114.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80114.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80114.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80114.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80114.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80114.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80114.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80114.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80114.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80114.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80114.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80114.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80114.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80114.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80114.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80114.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80114.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80114.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80114.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80114.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80114.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80114.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80114.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80114.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80114.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80114.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80114.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80114.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80114.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80114.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80114.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80114.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80114.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80115.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80115.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80115.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80115.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80115.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80115.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80115.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80115.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80115.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80115.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80115.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80115.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80115.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80115.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80115.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80115.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80115.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80115.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80115.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80115.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80115.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80115.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80115.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80115.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80115.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80115.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80115.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80115.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80115.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80115.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80115.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80115.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80115.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80115.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80115.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80115.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80115.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80115.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80115.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80115.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80115.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80115.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80115.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80115.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80115.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80115.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80115.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80115.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80115.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80115.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80115.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80115.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80115.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80115.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80115.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80115.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80115.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80115.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80115.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80115.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80115.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80115.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80115.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80115.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80116.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80116.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80116.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80116.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80116.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80116.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80116.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80116.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80116.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80116.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80116.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80116.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80116.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80116.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80116.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80116.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80116.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80116.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80116.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80116.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80116.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80116.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80116.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80116.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80116.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80116.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80116.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80116.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80116.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80116.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80116.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80116.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80116.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80116.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80116.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80116.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80116.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80116.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80116.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80116.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80116.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80116.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80116.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80116.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80116.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80116.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80116.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80116.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80116.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80116.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80116.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80116.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80116.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80116.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80116.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80116.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80116.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80116.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80116.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80116.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80116.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80117.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80117.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80117.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80117.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80117.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80117.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80117.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80117.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80117.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80117.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80117.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80117.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80117.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80117.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80117.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80117.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80117.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80117.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80117.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80117.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80117.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80117.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80117.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80117.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80117.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80117.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80117.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80117.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80117.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80117.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80117.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80117.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80117.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80117.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80117.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80117.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80117.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80117.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80117.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80117.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80117.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80117.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80117.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80117.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80117.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80117.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80117.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80117.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80117.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80117.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80117.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80117.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80117.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80117.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80117.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80117.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80117.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80117.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80117.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80117.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80117.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80117.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80118.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80118.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80118.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80118.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80118.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80118.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80118.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80118.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80118.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80118.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80118.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80118.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80118.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80118.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80118.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80118.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80118.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80118.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80118.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80118.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80118.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80118.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80118.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80118.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80118.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80118.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80118.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80118.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80118.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80118.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80118.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80118.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80118.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80118.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80118.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80118.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80118.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80118.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80118.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80118.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80118.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80118.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80118.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80118.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80118.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80118.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80118.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80118.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80118.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80118.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80118.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80118.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80118.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80118.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80118.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80118.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 80118.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 80118.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80118.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80118.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80118.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80118.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80119.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80119.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80119.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80119.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80119.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80119.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80119.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80119.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80119.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80119.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80119.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80119.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80119.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80119.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80119.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80119.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80119.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80119.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80119.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80119.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80119.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80119.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80119.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80119.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80119.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80119.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80119.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80119.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80119.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80119.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80119.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80119.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80119.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80119.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80119.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80119.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80119.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80119.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80119.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80119.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80119.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80119.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80119.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80119.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80119.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80119.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80119.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80119.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80119.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80119.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80119.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80119.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80119.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80119.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80120.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80120.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80120.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80120.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80120.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80120.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80120.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80120.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80121.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80121.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80121.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80121.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80121.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80121.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80121.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80121.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80121.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80121.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80121.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80121.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80121.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80121.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80121.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80121.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80121.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80121.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80121.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80121.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80121.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80121.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855980]
>[ 80121.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855980] width 1920 pitch 7680 (/4 1920)
>[ 80121.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80121.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80121.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80122.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80122.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80122.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80122.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80122.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80122.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80122.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80122.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80122.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80122.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80122.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80122.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80122.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80122.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80122.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80122.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80122.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80122.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034a10]
>[ 80122.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034a10] width 1920 pitch 7680 (/4 1920)
>[ 80122.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80122.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80122.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80122.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80122.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80122.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80122.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd0d0]
>[ 80122.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd0d0] width 1920 pitch 7680 (/4 1920)
>[ 80122.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80122.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80122.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80122.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80122.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834cf0]
>[ 80122.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834cf0] width 1920 pitch 7680 (/4 1920)
>[ 80122.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80122.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80122.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80122.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80194.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7470]
>[ 80194.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7470] width 1920 pitch 7680 (/4 1920)
>[ 80194.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80194.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80194.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80194.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80203.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80203.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80203.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80203.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80203.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80203.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80204.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80204.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80204.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b850]
>[ 80204.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b850] width 1920 pitch 7680 (/4 1920)
>[ 80204.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[ 80204.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[ 80204.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4045700]
>[ 80204.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4045700] width 1920 pitch 7680 (/4 1920)
>[ 80204.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80204.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80204.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7dfd0]
>[ 80204.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7dfd0] width 1920 pitch 7680 (/4 1920)
>[ 80204.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80204.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80204.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80204.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80204.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb7470]
>[ 80204.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb7470] width 1920 pitch 7680 (/4 1920)
>[ 80204.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80204.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80204.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a580]
>[ 80204.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a580] width 1920 pitch 7680 (/4 1920)
>[ 80204.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80204.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80204.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80204.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80204.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80204.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80204.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeaa90]
>[ 80204.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeaa90] width 1920 pitch 7680 (/4 1920)
>[ 80204.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80204.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80204.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 80204.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 80204.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1d20]
>[ 80204.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1d20] width 1920 pitch 7680 (/4 1920)
>[ 80204.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb45c0]
>[ 80204.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb45c0] width 1920 pitch 7680 (/4 1920)
>[ 80207.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80207.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80207.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80208.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80208.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858d20]
>[ 80208.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858d20] width 1920 pitch 7680 (/4 1920)
>[ 80208.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fc10]
>[ 80208.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fc10] width 1920 pitch 7680 (/4 1920)
>[ 80209.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5071350]
>[ 80209.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5071350] width 1920 pitch 7680 (/4 1920)
>[ 80209.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80209.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80209.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80209.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80209.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80209.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80209.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80209.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80210.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80210.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80210.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c1c0]
>[ 80210.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c1c0] width 1920 pitch 7680 (/4 1920)
>[ 80210.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5071350]
>[ 80210.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5071350] width 1920 pitch 7680 (/4 1920)
>[ 80210.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80210.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7460]
>[ 80210.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7460] width 1920 pitch 7680 (/4 1920)
>[ 80281.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8e8f0]
>[ 80281.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8e8f0] width 1920 pitch 7680 (/4 1920)
>[ 80281.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80281.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8e8f0]
>[ 80282.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8e8f0] width 1920 pitch 7680 (/4 1920)
>[ 80282.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80282.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80282.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8e8f0]
>[ 80282.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8e8f0] width 1920 pitch 7680 (/4 1920)
>[ 80282.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80282.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80282.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80282.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80282.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80282.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80282.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80282.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80282.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80282.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80282.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80282.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80282.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80282.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80282.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80282.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80282.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80282.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80282.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80282.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80282.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80283.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80283.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80283.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80283.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d92940]
>[ 80283.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d92940] width 1920 pitch 7680 (/4 1920)
>[ 80283.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80283.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80283.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80283.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80283.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80283.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80283.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80283.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80283.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80283.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ccb0]
>[ 80283.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ccb0] width 1920 pitch 7680 (/4 1920)
>[ 80283.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6edd0]
>[ 80283.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6edd0] width 1920 pitch 7680 (/4 1920)
>[ 80291.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80291.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80291.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80291.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff670]
>[ 80292.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff670] width 1920 pitch 7680 (/4 1920)
>[ 80292.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80292.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80292.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80292.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80292.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff670]
>[ 80292.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff670] width 1920 pitch 7680 (/4 1920)
>[ 80292.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80292.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80292.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80292.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80292.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff670]
>[ 80292.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff670] width 1920 pitch 7680 (/4 1920)
>[ 80292.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80292.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80292.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80292.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80292.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff670]
>[ 80292.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff670] width 1920 pitch 7680 (/4 1920)
>[ 80292.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f46680]
>[ 80292.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f46680] width 1920 pitch 7680 (/4 1920)
>[ 80292.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21bb0]
>[ 80292.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21bb0] width 1920 pitch 7680 (/4 1920)
>[ 80293.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f05a00]
>[ 80293.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f05a00] width 1920 pitch 7680 (/4 1920)
>[ 80293.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f05a00]
>[ 80293.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f05a00] width 1920 pitch 7680 (/4 1920)
>[ 80293.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80293.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80293.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbb2c0]
>[ 80293.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbb2c0] width 1920 pitch 7680 (/4 1920)
>[ 80293.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80293.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80293.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285e290]
>[ 80293.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285e290] width 1920 pitch 7680 (/4 1920)
>[ 80293.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 80293.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 80293.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f05a00]
>[ 80293.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f05a00] width 1920 pitch 7680 (/4 1920)
>[ 80293.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80293.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80293.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbb2c0]
>[ 80293.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbb2c0] width 1920 pitch 7680 (/4 1920)
>[ 80294.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80294.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80294.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285e290]
>[ 80294.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285e290] width 1920 pitch 7680 (/4 1920)
>[ 80294.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 80294.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 80294.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f05a00]
>[ 80294.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f05a00] width 1920 pitch 7680 (/4 1920)
>[ 80294.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80294.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80294.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285e250]
>[ 80294.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285e250] width 1920 pitch 7680 (/4 1920)
>[ 80294.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80294.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80294.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 80294.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 80295.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03fa0]
>[ 80295.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03fa0] width 1920 pitch 7680 (/4 1920)
>[ 80295.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86dc0]
>[ 80295.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86dc0] width 1920 pitch 7680 (/4 1920)
>[ 80295.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80295.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80295.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f010]
>[ 80295.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f010] width 1920 pitch 7680 (/4 1920)
>[ 80295.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86dc0]
>[ 80295.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86dc0] width 1920 pitch 7680 (/4 1920)
>[ 80296.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80296.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80296.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03fa0]
>[ 80296.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03fa0] width 1920 pitch 7680 (/4 1920)
>[ 80296.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f010]
>[ 80296.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f010] width 1920 pitch 7680 (/4 1920)
>[ 80296.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86dc0]
>[ 80296.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86dc0] width 1920 pitch 7680 (/4 1920)
>[ 80296.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80296.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80296.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03fa0]
>[ 80296.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03fa0] width 1920 pitch 7680 (/4 1920)
>[ 80296.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80296.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80296.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86dc0]
>[ 80296.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86dc0] width 1920 pitch 7680 (/4 1920)
>[ 80296.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03fa0]
>[ 80296.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03fa0] width 1920 pitch 7680 (/4 1920)
>[ 80296.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f010]
>[ 80296.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f010] width 1920 pitch 7680 (/4 1920)
>[ 80296.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80296.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80296.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ab00]
>[ 80296.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ab00] width 1920 pitch 7680 (/4 1920)
>[ 80296.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116520]
>[ 80296.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116520] width 1920 pitch 7680 (/4 1920)
>[ 80505.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80505.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80505.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faba20]
>[ 80505.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faba20] width 1920 pitch 7680 (/4 1920)
>[ 80506.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80506.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80506.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80506.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80506.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80507.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80507.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80507.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80507.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5117cb0]
>[ 80507.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5117cb0] width 1920 pitch 7680 (/4 1920)
>[ 80507.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80507.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80507.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a91930]
>[ 80507.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a91930] width 1920 pitch 7680 (/4 1920)
>[ 80507.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3f560]
>[ 80507.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3f560] width 1920 pitch 7680 (/4 1920)
>[ 80509.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25e60]
>[ 80509.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25e60] width 1920 pitch 7680 (/4 1920)
>[ 80509.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80509.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80509.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5a4f0]
>[ 80509.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5a4f0] width 1920 pitch 7680 (/4 1920)
>[ 80509.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80509.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80510.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 80510.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 80510.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80510.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80510.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80510.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80510.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80510.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80510.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80510.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80510.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80510.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80510.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80511.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80511.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80511.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80511.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80511.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80511.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80511.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80511.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80511.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80511.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80511.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80511.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80511.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80511.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80512.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80512.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80512.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80512.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80512.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80512.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80513.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80513.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80513.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80513.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80513.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80513.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80513.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80513.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80514.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80514.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80514.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80514.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80514.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80514.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80515.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28166a0]
>[ 80515.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28166a0] width 1920 pitch 7680 (/4 1920)
>[ 80515.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 80515.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 80580.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80580.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80580.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62100]
>[ 80580.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62100] width 1920 pitch 7680 (/4 1920)
>[ 80581.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca790]
>[ 80581.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca790] width 1920 pitch 7680 (/4 1920)
>[ 80581.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80581.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80581.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80581.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80581.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80581.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80581.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca790]
>[ 80581.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca790] width 1920 pitch 7680 (/4 1920)
>[ 80581.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62100]
>[ 80581.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62100] width 1920 pitch 7680 (/4 1920)
>[ 80581.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80581.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80581.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80581.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80581.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80581.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80581.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80581.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80581.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca790]
>[ 80581.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca790] width 1920 pitch 7680 (/4 1920)
>[ 80581.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62100]
>[ 80581.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62100] width 1920 pitch 7680 (/4 1920)
>[ 80581.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80582.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80582.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca790]
>[ 80582.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca790] width 1920 pitch 7680 (/4 1920)
>[ 80582.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80582.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80582.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80582.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80582.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80582.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80582.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9da70]
>[ 80582.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9da70] width 1920 pitch 7680 (/4 1920)
>[ 80582.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9da70]
>[ 80582.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9da70] width 1920 pitch 7680 (/4 1920)
>[ 80583.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc10]
>[ 80583.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc10] width 1920 pitch 7680 (/4 1920)
>[ 80583.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80583.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80583.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80583.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80583.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 80583.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 80584.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80584.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80584.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240]
>[ 80584.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1920 pitch 7680 (/4 1920)
>[ 80584.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[ 80584.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[ 80584.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397e340]
>[ 80584.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397e340] width 1920 pitch 7680 (/4 1920)
>[ 80584.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80584.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80584.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80584.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80584.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 80584.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 80584.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80584.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80584.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80584.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80584.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbe90]
>[ 80584.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbe90] width 1920 pitch 7680 (/4 1920)
>[ 80584.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80584.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80584.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37730]
>[ 80584.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37730] width 1920 pitch 7680 (/4 1920)
>[ 80584.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[ 80584.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[ 80584.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edf00]
>[ 80584.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edf00] width 1920 pitch 7680 (/4 1920)
>[ 80584.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858d20]
>[ 80584.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858d20] width 1920 pitch 7680 (/4 1920)
>[ 80584.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80584.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80584.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 80584.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 80584.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbfd30]
>[ 80584.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbfd30] width 1920 pitch 7680 (/4 1920)
>[ 80584.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30000]
>[ 80584.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30000] width 1920 pitch 7680 (/4 1920)
>[ 80586.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858d20]
>[ 80586.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858d20] width 1920 pitch 7680 (/4 1920)
>[ 80586.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ddb0]
>[ 80586.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ddb0] width 1920 pitch 7680 (/4 1920)
>[ 80587.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80587.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80587.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80587.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80587.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62100]
>[ 80587.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62100] width 1920 pitch 7680 (/4 1920)
>[ 80587.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858d20]
>[ 80587.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858d20] width 1920 pitch 7680 (/4 1920)
>[ 80587.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80587.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80587.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ccc0]
>[ 80587.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ccc0] width 1920 pitch 7680 (/4 1920)
>[ 80587.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd750]
>[ 80587.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd750] width 1920 pitch 7680 (/4 1920)
>[ 80587.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 80587.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 80587.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62100]
>[ 80587.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62100] width 1920 pitch 7680 (/4 1920)
>[ 80587.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858d20]
>[ 80587.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858d20] width 1920 pitch 7680 (/4 1920)
>[ 80587.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 80587.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 80588.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd750]
>[ 80588.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd750] width 1920 pitch 7680 (/4 1920)
>[ 80588.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9da90]
>[ 80588.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9da90] width 1920 pitch 7680 (/4 1920)
>[ 80588.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80588.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80588.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 80588.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 80598.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80598.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80603.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80603.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80603.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80603.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80635.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504a290]
>[ 80635.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504a290] width 1920 pitch 7680 (/4 1920)
>[ 80635.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80635.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80635.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 80635.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 80635.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80635.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80635.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80635.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80635.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80635.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80635.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 80635.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 80635.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80635.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80635.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[ 80635.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[ 80635.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef6650]
>[ 80635.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef6650] width 1920 pitch 7680 (/4 1920)
>[ 80635.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 80635.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 80635.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 80635.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 80636.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 80636.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 80636.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 80636.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 80636.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 80636.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 80636.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc7f0]
>[ 80636.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc7f0] width 1920 pitch 7680 (/4 1920)
>[ 80636.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 80636.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 80636.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc7f0]
>[ 80636.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc7f0] width 1920 pitch 7680 (/4 1920)
>[ 80636.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97d10]
>[ 80636.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97d10] width 1920 pitch 7680 (/4 1920)
>[ 80636.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb02e0]
>[ 80636.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb02e0] width 1920 pitch 7680 (/4 1920)
>[ 80636.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80636.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80636.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ddd0]
>[ 80636.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ddd0] width 1920 pitch 7680 (/4 1920)
>[ 80636.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 80636.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 80636.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 80636.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 80636.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80636.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80636.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[ 80636.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[ 80636.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 80636.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 80636.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 80636.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 80636.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 80636.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 80636.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 80636.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 80636.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 80636.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 80637.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc7f0]
>[ 80637.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc7f0] width 1920 pitch 7680 (/4 1920)
>[ 80637.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97d10]
>[ 80637.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97d10] width 1920 pitch 7680 (/4 1920)
>[ 80637.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb02e0]
>[ 80637.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb02e0] width 1920 pitch 7680 (/4 1920)
>[ 80637.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80637.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80637.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 80637.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 80637.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 80637.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 80637.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 80637.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 80637.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 80637.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 80637.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc7f0]
>[ 80637.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc7f0] width 1920 pitch 7680 (/4 1920)
>[ 80637.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80637.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80637.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 80637.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 80637.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 80637.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 80637.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ddd0]
>[ 80637.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ddd0] width 1920 pitch 7680 (/4 1920)
>[ 80637.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80637.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80637.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80637.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80638.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ddd0]
>[ 80638.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ddd0] width 1920 pitch 7680 (/4 1920)
>[ 80638.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e2c0]
>[ 80638.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e2c0] width 1920 pitch 7680 (/4 1920)
>[ 80638.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 80638.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 80638.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 80638.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 80638.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 80638.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 80638.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80638.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80638.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 80639.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 80639.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97d10]
>[ 80639.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97d10] width 1920 pitch 7680 (/4 1920)
>[ 80639.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb02e0]
>[ 80639.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb02e0] width 1920 pitch 7680 (/4 1920)
>[ 80639.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 80639.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ddd0]
>[ 80639.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ddd0] width 1920 pitch 7680 (/4 1920)
>[ 80639.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 80639.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 80639.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[ 80639.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[ 80639.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80639.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80639.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3859560]
>[ 80639.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3859560] width 1920 pitch 7680 (/4 1920)
>[ 80639.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 80639.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 80639.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80639.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97d10]
>[ 80639.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97d10] width 1920 pitch 7680 (/4 1920)
>[ 80639.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80639.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 80639.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 80639.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80639.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 80639.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 80639.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 80639.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb02e0]
>[ 80639.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb02e0] width 1920 pitch 7680 (/4 1920)
>[ 80639.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 80639.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 80639.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ddd0]
>[ 80639.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ddd0] width 1920 pitch 7680 (/4 1920)
>[ 80639.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 80639.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 80639.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef6650]
>[ 80639.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef6650] width 1920 pitch 7680 (/4 1920)
>[ 80639.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80639.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80639.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e2c0]
>[ 80639.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e2c0] width 1920 pitch 7680 (/4 1920)
>[ 80639.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80639.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80639.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 80639.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 80639.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80639.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80639.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3859560]
>[ 80639.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3859560] width 1920 pitch 7680 (/4 1920)
>[ 80639.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 80639.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 80639.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 80639.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 80639.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a550]
>[ 80639.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a550] width 1920 pitch 7680 (/4 1920)
>[ 80639.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 80639.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 80639.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 80639.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 80639.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 80639.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 80639.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 80639.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 80644.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc470]
>[ 80644.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc470] width 1920 pitch 7680 (/4 1920)
>[ 80644.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad2760]
>[ 80644.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad2760] width 1920 pitch 7680 (/4 1920)
>[ 80657.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10fe0]
>[ 80657.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10fe0] width 1920 pitch 7680 (/4 1920)
>[ 80660.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a39380]
>[ 80660.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a39380] width 1920 pitch 7680 (/4 1920)
>[ 80664.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0a250]
>[ 80664.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0a250] width 1920 pitch 7680 (/4 1920)
>[ 80664.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0a250]
>[ 80664.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0a250] width 1920 pitch 7680 (/4 1920)
>[ 80664.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 80664.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 80665.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80665.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80665.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80665.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80665.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80665.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80665.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80665.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80665.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b057e0]
>[ 80665.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b057e0] width 1920 pitch 7680 (/4 1920)
>[ 80665.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6976700]
>[ 80665.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6976700] width 1920 pitch 7680 (/4 1920)
>[ 80665.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69f5060]
>[ 80665.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69f5060] width 1920 pitch 7680 (/4 1920)
>[ 80665.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6976930]
>[ 80665.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6976930] width 1920 pitch 7680 (/4 1920)
>[ 80665.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb9a0]
>[ 80665.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb9a0] width 1920 pitch 7680 (/4 1920)
>[ 80665.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6976700]
>[ 80665.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6976700] width 1920 pitch 7680 (/4 1920)
>[ 80665.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80665.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80665.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b057e0]
>[ 80666.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b057e0] width 1920 pitch 7680 (/4 1920)
>[ 80666.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b112f0]
>[ 80666.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b112f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1660]
>[ 80666.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1660] width 1920 pitch 7680 (/4 1920)
>[ 80666.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80666.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80666.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80666.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80666.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80666.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80666.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80666.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80666.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80667.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80667.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80667.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80667.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80667.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80667.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80667.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80667.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80668.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80668.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80668.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80668.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80668.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80668.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80668.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80668.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80668.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80668.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80668.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80668.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80668.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80668.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 80668.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 80668.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967d30]
>[ 80668.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967d30] width 1920 pitch 7680 (/4 1920)
>[ 80668.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80668.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80668.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80668.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80668.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80668.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80668.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80668.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80668.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6968cd0]
>[ 80669.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6968cd0] width 1920 pitch 7680 (/4 1920)
>[ 80669.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6968cd0]
>[ 80669.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6968cd0] width 1920 pitch 7680 (/4 1920)
>[ 80669.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80669.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80669.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9e460]
>[ 80669.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9e460] width 1920 pitch 7680 (/4 1920)
>[ 80669.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80669.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80669.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80669.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80670.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88090]
>[ 80670.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88090] width 1920 pitch 7680 (/4 1920)
>[ 80670.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edf00]
>[ 80670.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edf00] width 1920 pitch 7680 (/4 1920)
>[ 80670.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[ 80670.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[ 80670.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca790]
>[ 80670.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca790] width 1920 pitch 7680 (/4 1920)
>[ 80670.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281e230]
>[ 80670.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281e230] width 1920 pitch 7680 (/4 1920)
>[ 80670.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 80670.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 80670.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37730]
>[ 80670.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37730] width 1920 pitch 7680 (/4 1920)
>[ 80670.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1f7d0]
>[ 80670.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1f7d0] width 1920 pitch 7680 (/4 1920)
>[ 80670.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e1d0]
>[ 80670.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e1d0] width 1920 pitch 7680 (/4 1920)
>[ 80670.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[ 80670.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[ 80670.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebbe90]
>[ 80670.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebbe90] width 1920 pitch 7680 (/4 1920)
>[ 80670.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[ 80670.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[ 80670.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6e000]
>[ 80670.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6e000] width 1920 pitch 7680 (/4 1920)
>[ 80670.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 80670.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 80670.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edbda0]
>[ 80670.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edbda0] width 1920 pitch 7680 (/4 1920)
>[ 80670.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80670.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80670.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 80670.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 80670.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[ 80670.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1920 pitch 7680 (/4 1920)
>[ 80670.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80670.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80670.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397e340]
>[ 80670.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397e340] width 1920 pitch 7680 (/4 1920)
>[ 80670.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[ 80670.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[ 80670.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 80670.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 80670.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 80670.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 80670.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f15e80]
>[ 80670.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f15e80] width 1920 pitch 7680 (/4 1920)
>[ 80670.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5eb00]
>[ 80670.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5eb00] width 1920 pitch 7680 (/4 1920)
>[ 80670.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240]
>[ 80670.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1920 pitch 7680 (/4 1920)
>[ 80670.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80670.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80670.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80670.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80670.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 80670.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 80670.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fc10]
>[ 80670.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fc10] width 1920 pitch 7680 (/4 1920)
>[ 80670.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80670.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80670.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4eac0]
>[ 80670.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4eac0] width 1920 pitch 7680 (/4 1920)
>[ 80670.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 80670.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 80670.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 80670.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 80670.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 80670.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 80670.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbfd30]
>[ 80670.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbfd30] width 1920 pitch 7680 (/4 1920)
>[ 80671.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 80671.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 80672.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80672.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80672.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80672.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80673.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c240]
>[ 80673.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c240] width 1920 pitch 7680 (/4 1920)
>[ 80673.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6976240]
>[ 80673.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6976240] width 1920 pitch 7680 (/4 1920)
>[ 80673.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acaaa0]
>[ 80673.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acaaa0] width 1920 pitch 7680 (/4 1920)
>[ 80673.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fc10]
>[ 80673.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fc10] width 1920 pitch 7680 (/4 1920)
>[ 80673.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 80673.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 80673.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80673.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80673.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 80673.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 80673.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 80673.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 80673.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 80673.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 80673.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80673.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80673.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37730]
>[ 80673.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37730] width 1920 pitch 7680 (/4 1920)
>[ 80673.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80673.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80907.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1dca0]
>[ 80907.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1dca0] width 1920 pitch 7680 (/4 1920)
>[ 80907.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3991180]
>[ 80907.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3991180] width 1920 pitch 7680 (/4 1920)
>[ 80908.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1dca0]
>[ 80908.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1dca0] width 1920 pitch 7680 (/4 1920)
>[ 80908.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80908.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80908.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4a0]
>[ 80908.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4a0] width 1920 pitch 7680 (/4 1920)
>[ 80908.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[ 80908.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1920 pitch 7680 (/4 1920)
>[ 80908.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a560]
>[ 80908.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a560] width 1920 pitch 7680 (/4 1920)
>[ 80908.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80908.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80908.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 80908.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 80908.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 80908.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 80908.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80908.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80908.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4a0]
>[ 80908.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4a0] width 1920 pitch 7680 (/4 1920)
>[ 80908.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[ 80908.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1920 pitch 7680 (/4 1920)
>[ 80908.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a560]
>[ 80908.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a560] width 1920 pitch 7680 (/4 1920)
>[ 80908.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80908.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80908.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80908.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80908.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 80908.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 80908.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 80908.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 80908.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80908.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80908.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 80908.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 80908.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a560]
>[ 80908.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a560] width 1920 pitch 7680 (/4 1920)
>[ 80909.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404a560]
>[ 80909.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404a560] width 1920 pitch 7680 (/4 1920)
>[ 80909.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[ 80909.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1920 pitch 7680 (/4 1920)
>[ 80909.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 80909.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 80909.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1dca0]
>[ 80909.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1dca0] width 1920 pitch 7680 (/4 1920)
>[ 80909.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e030]
>[ 80909.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e030] width 1920 pitch 7680 (/4 1920)
>[ 80909.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 80909.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 80909.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 80909.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 80909.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3950830]
>[ 80909.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3950830] width 1920 pitch 7680 (/4 1920)
>[ 80909.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecee80]
>[ 80909.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecee80] width 1920 pitch 7680 (/4 1920)
>[ 80910.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f241d0]
>[ 80910.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f241d0] width 1920 pitch 7680 (/4 1920)
>[ 80932.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 80932.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 80933.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace6a0]
>[ 80933.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace6a0] width 1920 pitch 7680 (/4 1920)
>[ 80952.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075010]
>[ 80952.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075010] width 1920 pitch 7680 (/4 1920)
>[ 80953.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40304e0]
>[ 80953.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40304e0] width 1920 pitch 7680 (/4 1920)
>[ 80953.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deea40]
>[ 80953.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deea40] width 1920 pitch 7680 (/4 1920)
>[ 80955.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb8a0]
>[ 80955.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb8a0] width 1920 pitch 7680 (/4 1920)
>[ 80996.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 80996.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 80996.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4edf0]
>[ 80996.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4edf0] width 1920 pitch 7680 (/4 1920)
>[ 80997.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975f00]
>[ 80997.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975f00] width 1920 pitch 7680 (/4 1920)
>[ 80998.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2740]
>[ 80998.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2740] width 1920 pitch 7680 (/4 1920)
>[ 80998.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3270]
>[ 80998.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3270] width 1920 pitch 7680 (/4 1920)
>[ 80998.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80998.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80998.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 80998.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 80998.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2ae0]
>[ 80998.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2ae0] width 1920 pitch 7680 (/4 1920)
>[ 80998.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 80998.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 80998.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80998.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80998.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975f00]
>[ 80998.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975f00] width 1920 pitch 7680 (/4 1920)
>[ 80998.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 80998.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 80998.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2740]
>[ 80998.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2740] width 1920 pitch 7680 (/4 1920)
>[ 80998.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3270]
>[ 80998.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3270] width 1920 pitch 7680 (/4 1920)
>[ 80998.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80998.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80998.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 80998.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 80998.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3270]
>[ 80998.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3270] width 1920 pitch 7680 (/4 1920)
>[ 80998.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f50]
>[ 80998.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f50] width 1920 pitch 7680 (/4 1920)
>[ 80998.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2740]
>[ 80998.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2740] width 1920 pitch 7680 (/4 1920)
>[ 80998.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 80998.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 80998.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975f00]
>[ 80998.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975f00] width 1920 pitch 7680 (/4 1920)
>[ 80998.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 80998.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 80998.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 80998.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 80998.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed2ae0]
>[ 80998.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed2ae0] width 1920 pitch 7680 (/4 1920)
>[ 80998.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393f1e0]
>[ 80998.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393f1e0] width 1920 pitch 7680 (/4 1920)
>[ 80998.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 80998.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 80998.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 80998.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 80999.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a277d0]
>[ 80999.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a277d0] width 1920 pitch 7680 (/4 1920)
>[ 80999.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80999.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80999.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89fa0]
>[ 80999.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89fa0] width 1920 pitch 7680 (/4 1920)
>[ 80999.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 80999.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81000.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de1920]
>[ 81000.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de1920] width 1920 pitch 7680 (/4 1920)
>[ 81000.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81000.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81001.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2864e70]
>[ 81001.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2864e70] width 1920 pitch 7680 (/4 1920)
>[ 81001.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdeb0]
>[ 81001.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdeb0] width 1920 pitch 7680 (/4 1920)
>[ 81001.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81001.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81001.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81001.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81001.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2864e70]
>[ 81001.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2864e70] width 1920 pitch 7680 (/4 1920)
>[ 81001.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acdf90]
>[ 81001.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acdf90] width 1920 pitch 7680 (/4 1920)
>[ 81001.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81001.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81001.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81001.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81001.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81001.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81001.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81001.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81001.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81001.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81001.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81002.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81002.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81002.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81002.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81002.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81002.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81002.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81002.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81002.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81002.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81002.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81002.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81002.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81002.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81002.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81002.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81002.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81002.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81002.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81002.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81002.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81002.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81002.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81002.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81002.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81002.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81002.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81002.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81002.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81002.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81002.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81002.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81002.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81002.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81002.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81002.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 81002.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 81002.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2df0]
>[ 81002.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2df0] width 1920 pitch 7680 (/4 1920)
>[ 81002.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81002.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81002.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81002.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81002.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81002.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81002.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81002.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81002.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81002.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81002.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81002.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81002.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd880]
>[ 81002.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd880] width 1920 pitch 7680 (/4 1920)
>[ 81002.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 81002.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 81002.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506bb10]
>[ 81003.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506bb10] width 1920 pitch 7680 (/4 1920)
>[ 81003.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acac40]
>[ 81003.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acac40] width 1920 pitch 7680 (/4 1920)
>[ 81003.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 81003.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 81003.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81003.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81007.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81007.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81007.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 81007.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 81007.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 81007.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 81009.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0460]
>[ 81009.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0460] width 1920 pitch 7680 (/4 1920)
>[ 81014.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e048b0]
>[ 81014.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e048b0] width 1920 pitch 7680 (/4 1920)
>[ 81014.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de87f0]
>[ 81014.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de87f0] width 1920 pitch 7680 (/4 1920)
>[ 81015.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b34270]
>[ 81015.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b34270] width 1920 pitch 7680 (/4 1920)
>[ 81015.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1ffa0]
>[ 81015.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1ffa0] width 1920 pitch 7680 (/4 1920)
>[ 81015.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x696ab20]
>[ 81015.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x696ab20] width 1920 pitch 7680 (/4 1920)
>[ 81016.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81016.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f22710]
>[ 81017.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f22710] width 1920 pitch 7680 (/4 1920)
>[ 81017.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81017.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c267e0]
>[ 81017.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c267e0] width 1920 pitch 7680 (/4 1920)
>[ 81017.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81017.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81017.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81017.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81041.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4be90]
>[ 81041.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4be90] width 1920 pitch 7680 (/4 1920)
>[ 81041.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81041.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81041.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81041.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81041.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81041.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81041.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24230]
>[ 81041.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24230] width 1920 pitch 7680 (/4 1920)
>[ 81041.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac0db0]
>[ 81041.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac0db0] width 1920 pitch 7680 (/4 1920)
>[ 81042.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac0db0]
>[ 81042.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac0db0] width 1920 pitch 7680 (/4 1920)
>[ 81042.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 81042.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 81042.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4e0]
>[ 81042.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4e0] width 1920 pitch 7680 (/4 1920)
>[ 81042.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81042.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81042.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac0db0]
>[ 81042.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac0db0] width 1920 pitch 7680 (/4 1920)
>[ 81042.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81042.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81042.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81042.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81043.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81043.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81043.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9ea0]
>[ 81043.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9ea0] width 1920 pitch 7680 (/4 1920)
>[ 81043.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec00a0]
>[ 81044.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec00a0] width 1920 pitch 7680 (/4 1920)
>[ 81044.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6e000]
>[ 81044.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6e000] width 1920 pitch 7680 (/4 1920)
>[ 81044.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de8540]
>[ 81044.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de8540] width 1920 pitch 7680 (/4 1920)
>[ 81044.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6e000]
>[ 81044.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6e000] width 1920 pitch 7680 (/4 1920)
>[ 81044.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81044.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81044.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de8540]
>[ 81044.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de8540] width 1920 pitch 7680 (/4 1920)
>[ 81044.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81044.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81044.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de8540]
>[ 81044.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de8540] width 1920 pitch 7680 (/4 1920)
>[ 81044.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81044.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81044.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de8540]
>[ 81044.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de8540] width 1920 pitch 7680 (/4 1920)
>[ 81044.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81044.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81044.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81044.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81045.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81045.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81045.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81045.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81045.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81045.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81046.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81046.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81046.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81046.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81046.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81046.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81047.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb9d0]
>[ 81047.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb9d0] width 1920 pitch 7680 (/4 1920)
>[ 81047.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 81047.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 81047.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81047.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81057.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33d50]
>[ 81057.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33d50] width 1920 pitch 7680 (/4 1920)
>[ 81057.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb78d0]
>[ 81057.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb78d0] width 1920 pitch 7680 (/4 1920)
>[ 81058.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd4a0]
>[ 81058.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd4a0] width 1920 pitch 7680 (/4 1920)
>[ 81058.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88090]
>[ 81058.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88090] width 1920 pitch 7680 (/4 1920)
>[ 81058.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00ff0]
>[ 81058.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00ff0] width 1920 pitch 7680 (/4 1920)
>[ 81059.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81059.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81059.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81059.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81059.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb7d0]
>[ 81060.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb7d0] width 1920 pitch 7680 (/4 1920)
>[ 81060.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a23f00]
>[ 81060.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a23f00] width 1920 pitch 7680 (/4 1920)
>[ 81060.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81060.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81060.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4e0]
>[ 81060.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4e0] width 1920 pitch 7680 (/4 1920)
>[ 81060.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 81060.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 81060.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81060.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81060.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00ff0]
>[ 81060.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00ff0] width 1920 pitch 7680 (/4 1920)
>[ 81060.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26240]
>[ 81060.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26240] width 1920 pitch 7680 (/4 1920)
>[ 81060.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24230]
>[ 81060.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24230] width 1920 pitch 7680 (/4 1920)
>[ 81060.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81060.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81060.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81060.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81060.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81060.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81060.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81060.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81060.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca7d0]
>[ 81060.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca7d0] width 1920 pitch 7680 (/4 1920)
>[ 81060.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a906a0]
>[ 81060.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a906a0] width 1920 pitch 7680 (/4 1920)
>[ 81060.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb7d0]
>[ 81060.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb7d0] width 1920 pitch 7680 (/4 1920)
>[ 81060.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a23f00]
>[ 81060.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a23f00] width 1920 pitch 7680 (/4 1920)
>[ 81060.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81060.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81060.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4e0]
>[ 81060.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4e0] width 1920 pitch 7680 (/4 1920)
>[ 81060.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 81060.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 81060.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06e90]
>[ 81060.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06e90] width 1920 pitch 7680 (/4 1920)
>[ 81060.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00ff0]
>[ 81060.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00ff0] width 1920 pitch 7680 (/4 1920)
>[ 81060.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26240]
>[ 81060.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26240] width 1920 pitch 7680 (/4 1920)
>[ 81060.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24230]
>[ 81060.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24230] width 1920 pitch 7680 (/4 1920)
>[ 81060.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81060.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81060.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81060.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81060.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81060.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81060.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc4640]
>[ 81060.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc4640] width 1920 pitch 7680 (/4 1920)
>[ 81060.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca7d0]
>[ 81060.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca7d0] width 1920 pitch 7680 (/4 1920)
>[ 81060.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a906a0]
>[ 81060.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a906a0] width 1920 pitch 7680 (/4 1920)
>[ 81060.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb7d0]
>[ 81060.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb7d0] width 1920 pitch 7680 (/4 1920)
>[ 81060.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a23f00]
>[ 81060.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a23f00] width 1920 pitch 7680 (/4 1920)
>[ 81119.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4cd50]
>[ 81119.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4cd50] width 1920 pitch 7680 (/4 1920)
>[ 81119.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed3460]
>[ 81119.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed3460] width 1920 pitch 7680 (/4 1920)
>[ 81119.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb4e0]
>[ 81119.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb4e0] width 1920 pitch 7680 (/4 1920)
>[ 81119.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94870]
>[ 81119.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94870] width 1920 pitch 7680 (/4 1920)
>[ 81133.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81133.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81133.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0eb20]
>[ 81133.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0eb20] width 1920 pitch 7680 (/4 1920)
>[ 81133.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf970]
>[ 81133.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf970] width 1920 pitch 7680 (/4 1920)
>[ 81133.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81133.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81133.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a906a0]
>[ 81133.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a906a0] width 1920 pitch 7680 (/4 1920)
>[ 81133.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf970]
>[ 81133.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf970] width 1920 pitch 7680 (/4 1920)
>[ 81133.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81133.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81133.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81133.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81134.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a906a0]
>[ 81134.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a906a0] width 1920 pitch 7680 (/4 1920)
>[ 81134.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf970]
>[ 81134.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf970] width 1920 pitch 7680 (/4 1920)
>[ 81134.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81134.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81134.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81134.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81134.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf970]
>[ 81134.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf970] width 1920 pitch 7680 (/4 1920)
>[ 81134.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26550]
>[ 81134.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26550] width 1920 pitch 7680 (/4 1920)
>[ 81134.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 81134.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 81135.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81135.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81135.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfa120]
>[ 81135.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfa120] width 1920 pitch 7680 (/4 1920)
>[ 81135.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c11ff0]
>[ 81135.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c11ff0] width 1920 pitch 7680 (/4 1920)
>[ 81135.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5118780]
>[ 81135.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5118780] width 1920 pitch 7680 (/4 1920)
>[ 81135.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebdc60]
>[ 81135.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebdc60] width 1920 pitch 7680 (/4 1920)
>[ 81135.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ded0]
>[ 81135.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ded0] width 1920 pitch 7680 (/4 1920)
>[ 81169.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 81169.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 81169.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e050]
>[ 81169.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e050] width 1920 pitch 7680 (/4 1920)
>[ 81170.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be13d0]
>[ 81170.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be13d0] width 1920 pitch 7680 (/4 1920)
>[ 81170.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc0e50]
>[ 81170.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc0e50] width 1920 pitch 7680 (/4 1920)
>[ 81171.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed09b0]
>[ 81171.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed09b0] width 1920 pitch 7680 (/4 1920)
>[ 81171.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1060]
>[ 81171.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1060] width 1920 pitch 7680 (/4 1920)
>[ 81171.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3986dd0]
>[ 81171.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3986dd0] width 1920 pitch 7680 (/4 1920)
>[ 81172.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc0e50]
>[ 81172.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc0e50] width 1920 pitch 7680 (/4 1920)
>[ 81175.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc0e50]
>[ 81175.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc0e50] width 1920 pitch 7680 (/4 1920)
>[ 81175.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21c90]
>[ 81175.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21c90] width 1920 pitch 7680 (/4 1920)
>[ 81175.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c64440]
>[ 81175.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c64440] width 1920 pitch 7680 (/4 1920)
>[ 81175.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f560]
>[ 81175.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f560] width 1920 pitch 7680 (/4 1920)
>[ 81175.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81175.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81175.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21c90]
>[ 81175.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21c90] width 1920 pitch 7680 (/4 1920)
>[ 81175.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f560]
>[ 81175.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f560] width 1920 pitch 7680 (/4 1920)
>[ 81175.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5f240]
>[ 81175.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5f240] width 1920 pitch 7680 (/4 1920)
>[ 81176.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21c90]
>[ 81176.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21c90] width 1920 pitch 7680 (/4 1920)
>[ 81179.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81179.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81179.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81179.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81179.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81179.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81179.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81179.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81179.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81179.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81179.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81179.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81181.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81000]
>[ 81181.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81000] width 1920 pitch 7680 (/4 1920)
>[ 81181.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 81181.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 81181.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81181.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81181.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81181.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81181.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81181.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81181.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81181.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81181.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5700]
>[ 81181.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5700] width 1920 pitch 7680 (/4 1920)
>[ 81181.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098110]
>[ 81181.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098110] width 1920 pitch 7680 (/4 1920)
>[ 81181.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2881c60]
>[ 81181.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2881c60] width 1920 pitch 7680 (/4 1920)
>[ 81181.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81181.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81181.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2864a20]
>[ 81182.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2864a20] width 1920 pitch 7680 (/4 1920)
>[ 81182.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81182.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81182.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6c10]
>[ 81182.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6c10] width 1920 pitch 7680 (/4 1920)
>[ 81182.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfdf80]
>[ 81182.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfdf80] width 1920 pitch 7680 (/4 1920)
>[ 81237.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81237.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81237.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81237.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81238.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e9950]
>[ 81238.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e9950] width 1920 pitch 7680 (/4 1920)
>[ 81238.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81238.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81238.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9dc0]
>[ 81238.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9dc0] width 1920 pitch 7680 (/4 1920)
>[ 81238.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81238.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81238.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb6560]
>[ 81238.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb6560] width 1920 pitch 7680 (/4 1920)
>[ 81238.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f710]
>[ 81238.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f710] width 1920 pitch 7680 (/4 1920)
>[ 81238.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25a50]
>[ 81238.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25a50] width 1920 pitch 7680 (/4 1920)
>[ 81238.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be9070]
>[ 81238.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be9070] width 1920 pitch 7680 (/4 1920)
>[ 81238.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37c90]
>[ 81238.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37c90] width 1920 pitch 7680 (/4 1920)
>[ 81238.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f290]
>[ 81238.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f290] width 1920 pitch 7680 (/4 1920)
>[ 81238.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426b810]
>[ 81238.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426b810] width 1920 pitch 7680 (/4 1920)
>[ 81238.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 81238.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 81238.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7ba0]
>[ 81238.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7ba0] width 1920 pitch 7680 (/4 1920)
>[ 81238.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 81238.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 81238.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70bd0]
>[ 81238.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70bd0] width 1920 pitch 7680 (/4 1920)
>[ 81238.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81238.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81238.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 81238.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 81238.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 81238.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 81238.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e159c0]
>[ 81238.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e159c0] width 1920 pitch 7680 (/4 1920)
>[ 81238.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42b60]
>[ 81238.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42b60] width 1920 pitch 7680 (/4 1920)
>[ 81238.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb7000]
>[ 81238.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb7000] width 1920 pitch 7680 (/4 1920)
>[ 81238.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f74230]
>[ 81238.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f74230] width 1920 pitch 7680 (/4 1920)
>[ 81238.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7a90]
>[ 81238.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7a90] width 1920 pitch 7680 (/4 1920)
>[ 81238.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eee9b0]
>[ 81238.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eee9b0] width 1920 pitch 7680 (/4 1920)
>[ 81238.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4660]
>[ 81238.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4660] width 1920 pitch 7680 (/4 1920)
>[ 81238.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f369a0]
>[ 81238.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f369a0] width 1920 pitch 7680 (/4 1920)
>[ 81238.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81238.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81238.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b1c0]
>[ 81238.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b1c0] width 1920 pitch 7680 (/4 1920)
>[ 81238.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbe830]
>[ 81238.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbe830] width 1920 pitch 7680 (/4 1920)
>[ 81238.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 81238.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 81238.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17120]
>[ 81238.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17120] width 1920 pitch 7680 (/4 1920)
>[ 81238.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e16820]
>[ 81238.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e16820] width 1920 pitch 7680 (/4 1920)
>[ 81238.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5e80]
>[ 81238.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5e80] width 1920 pitch 7680 (/4 1920)
>[ 81238.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5105310]
>[ 81238.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5105310] width 1920 pitch 7680 (/4 1920)
>[ 81238.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1fd80]
>[ 81238.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1fd80] width 1920 pitch 7680 (/4 1920)
>[ 81238.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 81238.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 81238.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec85c0]
>[ 81238.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec85c0] width 1920 pitch 7680 (/4 1920)
>[ 81238.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 81238.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 81238.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 81238.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 81238.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19f90]
>[ 81238.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19f90] width 1920 pitch 7680 (/4 1920)
>[ 81238.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 81238.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 81238.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 81238.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 81238.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[ 81238.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1920 pitch 7680 (/4 1920)
>[ 81238.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f02050]
>[ 81238.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f02050] width 1920 pitch 7680 (/4 1920)
>[ 81238.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[ 81238.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1920 pitch 7680 (/4 1920)
>[ 81238.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015aa0]
>[ 81238.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015aa0] width 1920 pitch 7680 (/4 1920)
>[ 81238.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 81238.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 81238.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e09080]
>[ 81238.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e09080] width 1920 pitch 7680 (/4 1920)
>[ 81238.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 81238.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 81238.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e159c0]
>[ 81238.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e159c0] width 1920 pitch 7680 (/4 1920)
>[ 81238.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7740]
>[ 81239.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7740] width 1920 pitch 7680 (/4 1920)
>[ 81239.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36c30]
>[ 81239.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36c30] width 1920 pitch 7680 (/4 1920)
>[ 81279.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81279.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81279.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcfb00]
>[ 81279.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcfb00] width 1920 pitch 7680 (/4 1920)
>[ 81280.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be13d0]
>[ 81280.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be13d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3980]
>[ 81280.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3980] width 1920 pitch 7680 (/4 1920)
>[ 81280.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e07b0]
>[ 81280.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e07b0] width 1920 pitch 7680 (/4 1920)
>[ 81280.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3980]
>[ 81280.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3980] width 1920 pitch 7680 (/4 1920)
>[ 81280.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d6c0]
>[ 81280.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d6c0] width 1920 pitch 7680 (/4 1920)
>[ 81280.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be13d0]
>[ 81280.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be13d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1060]
>[ 81280.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1060] width 1920 pitch 7680 (/4 1920)
>[ 81280.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3980]
>[ 81280.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3980] width 1920 pitch 7680 (/4 1920)
>[ 81280.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4265cb0]
>[ 81280.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4265cb0] width 1920 pitch 7680 (/4 1920)
>[ 81280.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e810]
>[ 81280.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e810] width 1920 pitch 7680 (/4 1920)
>[ 81280.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a3980]
>[ 81280.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a3980] width 1920 pitch 7680 (/4 1920)
>[ 81280.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40219d0]
>[ 81280.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40219d0] width 1920 pitch 7680 (/4 1920)
>[ 81280.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07e20]
>[ 81280.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07e20] width 1920 pitch 7680 (/4 1920)
>[ 81280.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e350]
>[ 81280.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e350] width 1920 pitch 7680 (/4 1920)
>[ 81280.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81280.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81280.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81280.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81280.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e350]
>[ 81280.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e350] width 1920 pitch 7680 (/4 1920)
>[ 81280.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81280.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81280.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81280.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81280.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e350]
>[ 81280.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e350] width 1920 pitch 7680 (/4 1920)
>[ 81280.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9220]
>[ 81280.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9220] width 1920 pitch 7680 (/4 1920)
>[ 81280.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81280.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81280.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e350]
>[ 81280.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e350] width 1920 pitch 7680 (/4 1920)
>[ 81280.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f1dc0]
>[ 81280.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f1dc0] width 1920 pitch 7680 (/4 1920)
>[ 81280.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2b90]
>[ 81280.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2b90] width 1920 pitch 7680 (/4 1920)
>[ 81280.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f77400]
>[ 81280.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f77400] width 1920 pitch 7680 (/4 1920)
>[ 81281.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b456d0]
>[ 81281.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b456d0] width 1920 pitch 7680 (/4 1920)
>[ 81282.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504b9b0]
>[ 81282.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504b9b0] width 1920 pitch 7680 (/4 1920)
>[ 81282.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052d60]
>[ 81282.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052d60] width 1920 pitch 7680 (/4 1920)
>[ 81282.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eef0]
>[ 81282.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eef0] width 1920 pitch 7680 (/4 1920)
>[ 81282.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaebb0]
>[ 81282.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaebb0] width 1920 pitch 7680 (/4 1920)
>[ 81282.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052d60]
>[ 81282.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052d60] width 1920 pitch 7680 (/4 1920)
>[ 81282.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28329d0]
>[ 81282.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28329d0] width 1920 pitch 7680 (/4 1920)
>[ 81282.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eef0]
>[ 81282.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eef0] width 1920 pitch 7680 (/4 1920)
>[ 81282.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b940]
>[ 81282.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b940] width 1920 pitch 7680 (/4 1920)
>[ 81282.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052d60]
>[ 81282.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052d60] width 1920 pitch 7680 (/4 1920)
>[ 81282.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d98db0]
>[ 81282.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d98db0] width 1920 pitch 7680 (/4 1920)
>[ 81282.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eef0]
>[ 81282.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eef0] width 1920 pitch 7680 (/4 1920)
>[ 81282.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1b1c0]
>[ 81282.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1b1c0] width 1920 pitch 7680 (/4 1920)
>[ 81282.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5eef0]
>[ 81282.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5eef0] width 1920 pitch 7680 (/4 1920)
>[ 81283.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030600]
>[ 81283.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030600] width 1920 pitch 7680 (/4 1920)
>[ 81289.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb860]
>[ 81289.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb860] width 1920 pitch 7680 (/4 1920)
>[ 81289.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb860]
>[ 81289.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb860] width 1920 pitch 7680 (/4 1920)
>[ 81289.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81289.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81289.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb860]
>[ 81289.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb860] width 1920 pitch 7680 (/4 1920)
>[ 81289.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81289.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81289.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81289.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81289.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872640]
>[ 81289.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872640] width 1920 pitch 7680 (/4 1920)
>[ 81289.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df15d0]
>[ 81289.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df15d0] width 1920 pitch 7680 (/4 1920)
>[ 81289.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81289.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81290.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81290.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81290.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81290.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81290.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17bb0]
>[ 81290.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17bb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81290.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81290.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17bb0]
>[ 81290.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17bb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94010]
>[ 81290.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94010] width 1920 pitch 7680 (/4 1920)
>[ 81290.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17bb0]
>[ 81290.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17bb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51169a0]
>[ 81290.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51169a0] width 1920 pitch 7680 (/4 1920)
>[ 81290.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed2f10]
>[ 81290.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed2f10] width 1920 pitch 7680 (/4 1920)
>[ 81290.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9cb0]
>[ 81290.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9cb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148b80]
>[ 81290.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148b80] width 1920 pitch 7680 (/4 1920)
>[ 81290.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed2f10]
>[ 81290.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed2f10] width 1920 pitch 7680 (/4 1920)
>[ 81290.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17bb0]
>[ 81290.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17bb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148b80]
>[ 81290.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148b80] width 1920 pitch 7680 (/4 1920)
>[ 81290.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9cb0]
>[ 81290.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9cb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94010]
>[ 81290.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94010] width 1920 pitch 7680 (/4 1920)
>[ 81290.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059b60]
>[ 81290.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059b60] width 1920 pitch 7680 (/4 1920)
>[ 81290.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17bb0]
>[ 81290.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17bb0] width 1920 pitch 7680 (/4 1920)
>[ 81290.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81290.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6830]
>[ 81291.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6830] width 1920 pitch 7680 (/4 1920)
>[ 81291.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deb870]
>[ 81291.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deb870] width 1920 pitch 7680 (/4 1920)
>[ 81291.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e48dc0]
>[ 81291.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e48dc0] width 1920 pitch 7680 (/4 1920)
>[ 81291.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4540]
>[ 81291.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4540] width 1920 pitch 7680 (/4 1920)
>[ 81291.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f183a0]
>[ 81291.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f183a0] width 1920 pitch 7680 (/4 1920)
>[ 81291.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4540]
>[ 81291.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4540] width 1920 pitch 7680 (/4 1920)
>[ 81291.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de99f0]
>[ 81291.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de99f0] width 1920 pitch 7680 (/4 1920)
>[ 81291.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81291.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81291.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81291.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81291.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81292.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81292.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81292.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81292.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81293.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9f730]
>[ 81293.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9f730] width 1920 pitch 7680 (/4 1920)
>[ 81293.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa27e0]
>[ 81293.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa27e0] width 1920 pitch 7680 (/4 1920)
>[ 81337.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81337.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81337.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81337.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81337.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0a10]
>[ 81337.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0a10] width 1920 pitch 7680 (/4 1920)
>[ 81337.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81337.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81337.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81337.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81337.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efdde0]
>[ 81337.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efdde0] width 1920 pitch 7680 (/4 1920)
>[ 81337.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31fb0]
>[ 81337.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31fb0] width 1920 pitch 7680 (/4 1920)
>[ 81337.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc5640]
>[ 81337.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc5640] width 1920 pitch 7680 (/4 1920)
>[ 81337.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4effa50]
>[ 81337.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4effa50] width 1920 pitch 7680 (/4 1920)
>[ 81337.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0a10]
>[ 81337.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0a10] width 1920 pitch 7680 (/4 1920)
>[ 81337.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81337.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81337.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81337.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81337.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81337.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81337.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31fb0]
>[ 81337.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31fb0] width 1920 pitch 7680 (/4 1920)
>[ 81337.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4effa50]
>[ 81337.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4effa50] width 1920 pitch 7680 (/4 1920)
>[ 81337.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81337.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81337.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81337.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81337.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31fb0]
>[ 81337.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31fb0] width 1920 pitch 7680 (/4 1920)
>[ 81337.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81337.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81337.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4effa50]
>[ 81337.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4effa50] width 1920 pitch 7680 (/4 1920)
>[ 81339.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e077f0]
>[ 81339.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e077f0] width 1920 pitch 7680 (/4 1920)
>[ 81344.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc5640]
>[ 81344.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc5640] width 1920 pitch 7680 (/4 1920)
>[ 81345.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81345.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81345.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d6b0]
>[ 81345.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d6b0] width 1920 pitch 7680 (/4 1920)
>[ 81346.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d6b0]
>[ 81346.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d6b0] width 1920 pitch 7680 (/4 1920)
>[ 81348.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81348.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81348.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[ 81348.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1920 pitch 7680 (/4 1920)
>[ 81348.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81348.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81348.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[ 81348.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1920 pitch 7680 (/4 1920)
>[ 81348.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2b90]
>[ 81348.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2b90] width 1920 pitch 7680 (/4 1920)
>[ 81348.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[ 81348.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1920 pitch 7680 (/4 1920)
>[ 81348.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81348.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81348.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[ 81348.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1920 pitch 7680 (/4 1920)
>[ 81348.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff3980]
>[ 81348.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff3980] width 1920 pitch 7680 (/4 1920)
>[ 81348.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81348.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81348.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 81348.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 81348.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81348.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81348.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81348.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81348.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e159c0]
>[ 81348.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e159c0] width 1920 pitch 7680 (/4 1920)
>[ 81348.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 81348.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 81358.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 81358.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 81358.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81358.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81358.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81358.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81359.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7a90]
>[ 81359.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7a90] width 1920 pitch 7680 (/4 1920)
>[ 81359.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60c80]
>[ 81359.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60c80] width 1920 pitch 7680 (/4 1920)
>[ 81360.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e16820]
>[ 81360.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e16820] width 1920 pitch 7680 (/4 1920)
>[ 81360.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 81360.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 81360.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e050]
>[ 81360.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e050] width 1920 pitch 7680 (/4 1920)
>[ 81360.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 81360.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 81360.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c8f60]
>[ 81360.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c8f60] width 1920 pitch 7680 (/4 1920)
>[ 81360.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 81360.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 81360.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31fb0]
>[ 81360.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31fb0] width 1920 pitch 7680 (/4 1920)
>[ 81360.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5680]
>[ 81361.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5680] width 1920 pitch 7680 (/4 1920)
>[ 81361.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 81361.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 81361.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81361.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81361.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81361.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81361.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60c80]
>[ 81361.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60c80] width 1920 pitch 7680 (/4 1920)
>[ 81361.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e050]
>[ 81361.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e050] width 1920 pitch 7680 (/4 1920)
>[ 81361.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c8f60]
>[ 81361.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c8f60] width 1920 pitch 7680 (/4 1920)
>[ 81361.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 81361.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 81361.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e31fb0]
>[ 81361.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e31fb0] width 1920 pitch 7680 (/4 1920)
>[ 81361.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5680]
>[ 81361.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5680] width 1920 pitch 7680 (/4 1920)
>[ 81361.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81361.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81361.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d14130]
>[ 81361.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d14130] width 1920 pitch 7680 (/4 1920)
>[ 81361.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 81361.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 81361.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81361.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81363.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e050]
>[ 81363.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e050] width 1920 pitch 7680 (/4 1920)
>[ 81363.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81363.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81363.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81363.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81363.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148bd0]
>[ 81363.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148bd0] width 1920 pitch 7680 (/4 1920)
>[ 81363.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fad110]
>[ 81363.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fad110] width 1920 pitch 7680 (/4 1920)
>[ 81363.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fa30]
>[ 81363.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fa30] width 1920 pitch 7680 (/4 1920)
>[ 81363.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e050]
>[ 81363.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e050] width 1920 pitch 7680 (/4 1920)
>[ 81363.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac0ad0]
>[ 81363.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac0ad0] width 1920 pitch 7680 (/4 1920)
>[ 81363.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81363.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81363.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60c80]
>[ 81363.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60c80] width 1920 pitch 7680 (/4 1920)
>[ 81363.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81363.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81363.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81363.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81363.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb6a70]
>[ 81363.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb6a70] width 1920 pitch 7680 (/4 1920)
>[ 81363.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c8f60]
>[ 81363.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c8f60] width 1920 pitch 7680 (/4 1920)
>[ 81363.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81363.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81363.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81363.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81363.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 81363.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 81363.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a340]
>[ 81363.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a340] width 1920 pitch 7680 (/4 1920)
>[ 81363.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81363.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81363.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 81363.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 81363.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d14130]
>[ 81363.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d14130] width 1920 pitch 7680 (/4 1920)
>[ 81363.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 81363.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 81363.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebdc60]
>[ 81363.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebdc60] width 1920 pitch 7680 (/4 1920)
>[ 81363.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110740]
>[ 81363.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110740] width 1920 pitch 7680 (/4 1920)
>[ 81363.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81363.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81363.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4148bd0]
>[ 81363.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4148bd0] width 1920 pitch 7680 (/4 1920)
>[ 81363.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fa30]
>[ 81363.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fa30] width 1920 pitch 7680 (/4 1920)
>[ 81364.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac0ad0]
>[ 81364.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac0ad0] width 1920 pitch 7680 (/4 1920)
>[ 81364.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fad110]
>[ 81364.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fad110] width 1920 pitch 7680 (/4 1920)
>[ 81367.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 81367.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 81367.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81367.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81367.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81367.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81367.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbfc0]
>[ 81367.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbfc0] width 1920 pitch 7680 (/4 1920)
>[ 81367.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eee570]
>[ 81367.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eee570] width 1920 pitch 7680 (/4 1920)
>[ 81367.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81367.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81367.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbe330]
>[ 81367.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbe330] width 1920 pitch 7680 (/4 1920)
>[ 81367.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81367.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81367.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c5fd0]
>[ 81367.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c5fd0] width 1920 pitch 7680 (/4 1920)
>[ 81367.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 81367.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 81367.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 81367.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 81373.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81373.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81373.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60c80]
>[ 81373.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60c80] width 1920 pitch 7680 (/4 1920)
>[ 81374.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 81374.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 81374.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfa120]
>[ 81374.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfa120] width 1920 pitch 7680 (/4 1920)
>[ 81374.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81374.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81374.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81374.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81374.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acf2d0]
>[ 81374.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acf2d0] width 1920 pitch 7680 (/4 1920)
>[ 81375.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb01c0]
>[ 81375.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb01c0] width 1920 pitch 7680 (/4 1920)
>[ 81375.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6bf50]
>[ 81375.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6bf50] width 1920 pitch 7680 (/4 1920)
>[ 81375.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f710]
>[ 81375.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f710] width 1920 pitch 7680 (/4 1920)
>[ 81375.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f83d70]
>[ 81375.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f83d70] width 1920 pitch 7680 (/4 1920)
>[ 81375.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca09e0]
>[ 81375.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca09e0] width 1920 pitch 7680 (/4 1920)
>[ 81375.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81375.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81375.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510efb0]
>[ 81375.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510efb0] width 1920 pitch 7680 (/4 1920)
>[ 81375.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81375.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81375.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283e850]
>[ 81375.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283e850] width 1920 pitch 7680 (/4 1920)
>[ 81375.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07e20]
>[ 81375.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07e20] width 1920 pitch 7680 (/4 1920)
>[ 81375.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec4e20]
>[ 81375.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec4e20] width 1920 pitch 7680 (/4 1920)
>[ 81375.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec4e20]
>[ 81375.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec4e20] width 1920 pitch 7680 (/4 1920)
>[ 81376.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81376.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81377.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81377.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50938e0]
>[ 81377.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50938e0] width 1920 pitch 7680 (/4 1920)
>[ 81377.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81377.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50938e0]
>[ 81377.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50938e0] width 1920 pitch 7680 (/4 1920)
>[ 81377.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81377.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50938e0]
>[ 81377.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50938e0] width 1920 pitch 7680 (/4 1920)
>[ 81377.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81377.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81377.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81377.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81377.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81377.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81377.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81433.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7ef0]
>[ 81433.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7ef0] width 1920 pitch 7680 (/4 1920)
>[ 81433.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced360]
>[ 81433.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced360] width 1920 pitch 7680 (/4 1920)
>[ 81433.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81433.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81434.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81434.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81434.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81434.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81434.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81434.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81434.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81434.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81434.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81434.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81434.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81434.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81434.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81434.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81435.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81435.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81435.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81435.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81435.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81435.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81435.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81435.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81435.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81435.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81435.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81435.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81435.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81435.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a880]
>[ 81435.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a880] width 1920 pitch 7680 (/4 1920)
>[ 81436.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81436.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81436.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81452.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81452.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81452.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 81452.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 81453.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81453.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81453.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81453.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81453.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81453.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81453.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81453.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81453.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81453.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81453.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81453.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81453.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81453.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81453.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81453.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81453.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25570]
>[ 81453.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25570] width 1920 pitch 7680 (/4 1920)
>[ 81453.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81453.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81453.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 81453.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 81453.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 81453.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 81454.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6c10]
>[ 81454.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6c10] width 1920 pitch 7680 (/4 1920)
>[ 81454.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286d1a0]
>[ 81454.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286d1a0] width 1920 pitch 7680 (/4 1920)
>[ 81454.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81454.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81455.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6c10]
>[ 81455.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6c10] width 1920 pitch 7680 (/4 1920)
>[ 81455.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c18bf0]
>[ 81455.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c18bf0] width 1920 pitch 7680 (/4 1920)
>[ 81455.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286d1a0]
>[ 81455.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286d1a0] width 1920 pitch 7680 (/4 1920)
>[ 81455.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acbb50]
>[ 81455.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acbb50] width 1920 pitch 7680 (/4 1920)
>[ 81455.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 81455.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 81455.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81455.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81455.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6c10]
>[ 81455.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6c10] width 1920 pitch 7680 (/4 1920)
>[ 81455.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c18bf0]
>[ 81455.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c18bf0] width 1920 pitch 7680 (/4 1920)
>[ 81455.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286d1a0]
>[ 81455.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286d1a0] width 1920 pitch 7680 (/4 1920)
>[ 81455.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acbb50]
>[ 81455.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acbb50] width 1920 pitch 7680 (/4 1920)
>[ 81461.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acbb50]
>[ 81461.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acbb50] width 1920 pitch 7680 (/4 1920)
>[ 81461.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 81461.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 81461.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c18bf0]
>[ 81461.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c18bf0] width 1920 pitch 7680 (/4 1920)
>[ 81461.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 81461.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 81461.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7ba0]
>[ 81461.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7ba0] width 1920 pitch 7680 (/4 1920)
>[ 81461.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 81461.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 81461.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81461.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81464.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81464.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81476.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0aeb0]
>[ 81476.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0aeb0] width 1920 pitch 7680 (/4 1920)
>[ 81476.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284c790]
>[ 81476.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284c790] width 1920 pitch 7680 (/4 1920)
>[ 81476.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebb530]
>[ 81476.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebb530] width 1920 pitch 7680 (/4 1920)
>[ 81477.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81477.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81477.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 81477.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 81477.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 81477.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 81477.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81477.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81477.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81478.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81478.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81478.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81478.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81478.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81478.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81478.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81478.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81478.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81478.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81478.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81478.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81478.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81478.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbfc0]
>[ 81478.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbfc0] width 1920 pitch 7680 (/4 1920)
>[ 81478.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81478.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81478.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81478.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81478.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17120]
>[ 81478.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17120] width 1920 pitch 7680 (/4 1920)
>[ 81478.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81478.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81478.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81478.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81478.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81478.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81478.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbfc0]
>[ 81478.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbfc0] width 1920 pitch 7680 (/4 1920)
>[ 81479.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81479.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81479.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81479.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81479.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd390]
>[ 81479.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd390] width 1920 pitch 7680 (/4 1920)
>[ 81479.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81479.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81573.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81573.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81574.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2edf0]
>[ 81574.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2edf0] width 1920 pitch 7680 (/4 1920)
>[ 81574.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81574.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81575.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81575.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81575.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81575.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81575.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81575.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81575.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81575.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81575.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81575.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81575.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81575.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81575.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81575.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81575.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecd390]
>[ 81575.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecd390] width 1920 pitch 7680 (/4 1920)
>[ 81575.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81575.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81575.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81575.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81575.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81575.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81575.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81575.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81575.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81575.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81591.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fb3d0]
>[ 81591.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fb3d0] width 1920 pitch 7680 (/4 1920)
>[ 81591.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81591.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81591.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81591.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81595.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81595.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81595.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81595.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81596.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81596.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81596.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81596.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81596.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81596.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81596.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81596.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81596.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81596.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81596.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81596.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81596.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81597.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81597.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81597.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81597.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81597.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81597.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81598.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81598.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81598.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81598.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81598.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81598.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81598.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81598.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81598.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81598.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81599.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81599.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81599.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81599.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81599.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81599.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81600.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81600.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81600.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81600.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81600.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81600.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81601.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81601.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81601.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81601.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 81602.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 81602.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81602.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81602.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81610.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d69280]
>[ 81610.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d69280] width 1920 pitch 7680 (/4 1920)
>[ 81610.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81610.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81611.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[ 81611.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1920 pitch 7680 (/4 1920)
>[ 81611.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca9e0]
>[ 81611.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca9e0] width 1920 pitch 7680 (/4 1920)
>[ 81611.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b16b0]
>[ 81611.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b16b0] width 1920 pitch 7680 (/4 1920)
>[ 81611.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42b70]
>[ 81611.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42b70] width 1920 pitch 7680 (/4 1920)
>[ 81611.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 81611.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 81611.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9ed60]
>[ 81611.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9ed60] width 1920 pitch 7680 (/4 1920)
>[ 81611.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81611.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81611.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 81611.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 81611.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 81611.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 81611.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f56540]
>[ 81611.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f56540] width 1920 pitch 7680 (/4 1920)
>[ 81612.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 81612.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 81612.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 81612.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 81612.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c78980]
>[ 81612.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c78980] width 1920 pitch 7680 (/4 1920)
>[ 81613.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856e20]
>[ 81613.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856e20] width 1920 pitch 7680 (/4 1920)
>[ 81613.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81613.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81613.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 81613.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 81613.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab7000]
>[ 81613.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab7000] width 1920 pitch 7680 (/4 1920)
>[ 81613.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81613.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81613.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 81613.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 81613.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab7000]
>[ 81613.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab7000] width 1920 pitch 7680 (/4 1920)
>[ 81613.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 81613.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 81613.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 81613.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 81613.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab7000]
>[ 81613.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab7000] width 1920 pitch 7680 (/4 1920)
>[ 81616.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4de0]
>[ 81616.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4de0] width 1920 pitch 7680 (/4 1920)
>[ 81620.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4d20]
>[ 81620.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4d20] width 1920 pitch 7680 (/4 1920)
>[ 81620.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81620.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81620.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4d20]
>[ 81620.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4d20] width 1920 pitch 7680 (/4 1920)
>[ 81620.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb7ba0]
>[ 81620.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb7ba0] width 1920 pitch 7680 (/4 1920)
>[ 81620.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81620.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81620.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3800]
>[ 81620.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3800] width 1920 pitch 7680 (/4 1920)
>[ 81620.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81620.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81620.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3800]
>[ 81620.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3800] width 1920 pitch 7680 (/4 1920)
>[ 81620.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81620.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81621.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3800]
>[ 81621.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3800] width 1920 pitch 7680 (/4 1920)
>[ 81621.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81621.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81621.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd3800]
>[ 81621.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd3800] width 1920 pitch 7680 (/4 1920)
>[ 81621.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501b150]
>[ 81621.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501b150] width 1920 pitch 7680 (/4 1920)
>[ 81621.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ec710]
>[ 81621.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ec710] width 1920 pitch 7680 (/4 1920)
>[ 81635.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 81635.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 81635.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 81635.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 81635.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb6560]
>[ 81635.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb6560] width 1920 pitch 7680 (/4 1920)
>[ 81635.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdba0]
>[ 81635.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdba0] width 1920 pitch 7680 (/4 1920)
>[ 81636.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81636.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81636.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81636.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81636.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81636.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81636.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81636.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81636.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81636.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81636.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81636.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81636.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81636.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81636.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81636.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81636.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81636.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81636.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b3b0]
>[ 81636.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b3b0] width 1920 pitch 7680 (/4 1920)
>[ 81636.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81636.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81636.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81636.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81636.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81636.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81636.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81636.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81637.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd630]
>[ 81637.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd630] width 1920 pitch 7680 (/4 1920)
>[ 81637.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81637.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81637.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81637.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81637.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11050]
>[ 81637.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11050] width 1920 pitch 7680 (/4 1920)
>[ 81637.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 81637.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 81637.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 81637.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 81637.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 81637.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 81637.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81637.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81637.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81637.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81637.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81637.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81637.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81637.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81637.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81637.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81637.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f381b0]
>[ 81637.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f381b0] width 1920 pitch 7680 (/4 1920)
>[ 81637.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acbb50]
>[ 81637.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acbb50] width 1920 pitch 7680 (/4 1920)
>[ 81638.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 81638.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 81638.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec5d60]
>[ 81638.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec5d60] width 1920 pitch 7680 (/4 1920)
>[ 81638.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a850]
>[ 81638.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a850] width 1920 pitch 7680 (/4 1920)
>[ 81639.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81639.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077400]
>[ 81640.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077400] width 1920 pitch 7680 (/4 1920)
>[ 81640.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81640.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81640.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 81640.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 81640.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077400]
>[ 81640.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077400] width 1920 pitch 7680 (/4 1920)
>[ 81640.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81640.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81640.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81640.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81640.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81640.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 81640.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 81640.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5077400]
>[ 81640.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5077400] width 1920 pitch 7680 (/4 1920)
>[ 81640.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79b30]
>[ 81640.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79b30] width 1920 pitch 7680 (/4 1920)
>[ 81647.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81647.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81647.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 81647.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 81647.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025f90]
>[ 81647.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025f90] width 1920 pitch 7680 (/4 1920)
>[ 81647.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 81647.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 81647.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81647.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81648.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11050]
>[ 81648.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11050] width 1920 pitch 7680 (/4 1920)
>[ 81648.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81648.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81648.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81648.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81648.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81648.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81648.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81648.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81648.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 81648.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 81648.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 81648.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 81648.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 81648.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 81648.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 81648.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 81648.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 81648.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 81648.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acee50]
>[ 81648.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acee50] width 1920 pitch 7680 (/4 1920)
>[ 81648.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81648.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81648.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 81648.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 81648.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81648.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81648.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 81648.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 81648.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81648.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81649.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81649.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81649.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 81649.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 81649.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 81649.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 81681.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81681.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81681.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81681.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81682.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81682.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81682.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81682.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 81683.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 81683.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 81683.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 81683.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 81683.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 81683.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 81683.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 81683.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3bc50]
>[ 81683.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3bc50] width 1920 pitch 7680 (/4 1920)
>[ 81683.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50983b0]
>[ 81683.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50983b0] width 1920 pitch 7680 (/4 1920)
>[ 81684.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 81684.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 81684.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81684.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81685.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc640]
>[ 81685.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc640] width 1920 pitch 7680 (/4 1920)
>[ 81685.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81685.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81685.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 81685.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 81685.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81685.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81685.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 81685.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 81685.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81685.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81686.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 81686.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 81686.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81686.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81686.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81686.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81686.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 81686.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 81686.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81686.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81686.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 81686.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 81686.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 81686.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 81688.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30a80]
>[ 81688.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30a80] width 1920 pitch 7680 (/4 1920)
>[ 81688.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30a80]
>[ 81688.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30a80] width 1920 pitch 7680 (/4 1920)
>[ 81688.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5118780]
>[ 81688.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5118780] width 1920 pitch 7680 (/4 1920)
>[ 81715.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 81715.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 81715.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 81715.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 81716.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 81716.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 81716.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81716.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81716.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 81716.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 81716.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc640]
>[ 81716.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc640] width 1920 pitch 7680 (/4 1920)
>[ 81716.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 81716.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 81716.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 81716.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 81716.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 81716.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 81716.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 81716.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 81716.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c070]
>[ 81716.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c070] width 1920 pitch 7680 (/4 1920)
>[ 81716.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11050]
>[ 81716.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11050] width 1920 pitch 7680 (/4 1920)
>[ 81716.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 81716.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 81716.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 81716.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 81716.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 81716.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 81716.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 81716.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 81716.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 81716.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 81716.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 81716.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 81716.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 81716.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 81717.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81717.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81717.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81717.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81718.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81718.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81718.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81718.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 81719.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 81719.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 81719.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 81719.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2dda0]
>[ 81719.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2dda0] width 1920 pitch 7680 (/4 1920)
>[ 82055.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d1e0]
>[ 82055.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d1e0] width 1920 pitch 7680 (/4 1920)
>[ 82055.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82055.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82055.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059100]
>[ 82055.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059100] width 1920 pitch 7680 (/4 1920)
>[ 82056.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5bbd0]
>[ 82056.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82056.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa6770]
>[ 82056.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa6770] width 1920 pitch 7680 (/4 1920)
>[ 82056.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82056.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82056.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82056.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82056.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82057.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82057.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82057.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82057.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82057.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82057.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82057.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82057.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82057.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82057.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82057.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82057.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82057.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82057.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82057.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82057.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 82057.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 82057.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 82057.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 82076.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82076.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82076.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82076.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82076.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02350]
>[ 82076.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02350] width 1920 pitch 7680 (/4 1920)
>[ 82077.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 82077.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 82078.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5d900]
>[ 82078.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5d900] width 1920 pitch 7680 (/4 1920)
>[ 82078.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ba50]
>[ 82078.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ba50] width 1920 pitch 7680 (/4 1920)
>[ 82079.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67770]
>[ 82079.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67770] width 1920 pitch 7680 (/4 1920)
>[ 82079.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 82079.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 82079.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 82079.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 82079.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93550]
>[ 82079.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93550] width 1920 pitch 7680 (/4 1920)
>[ 82080.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82080.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82080.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82080.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82081.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82081.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82081.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82081.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82081.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82081.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82081.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82081.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82081.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82081.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82081.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82081.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82081.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 82081.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 82081.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82081.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82081.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82081.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82081.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82081.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82081.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82081.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82081.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82081.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82082.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82082.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82082.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82082.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82082.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 82082.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 82082.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82082.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82082.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82082.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82082.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82082.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82082.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82082.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82082.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82082.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82082.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 82082.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 82082.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82082.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82082.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82082.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82082.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82082.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82082.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82082.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82082.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82082.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82082.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82082.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82082.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1f00]
>[ 82082.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1f00] width 1920 pitch 7680 (/4 1920)
>[ 82082.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0200]
>[ 82082.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0200] width 1920 pitch 7680 (/4 1920)
>[ 82082.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc200]
>[ 82082.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc200] width 1920 pitch 7680 (/4 1920)
>[ 82082.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f937c0]
>[ 82082.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f937c0] width 1920 pitch 7680 (/4 1920)
>[ 82082.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea600]
>[ 82082.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea600] width 1920 pitch 7680 (/4 1920)
>[ 82082.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 82082.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 82188.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82188.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82188.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82188.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82189.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82189.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82189.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82189.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82189.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82189.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82189.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82189.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82189.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82189.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82189.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82189.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82189.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82189.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82189.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82189.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82189.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82189.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82189.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82189.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82189.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82189.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82189.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82189.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82189.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82189.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82189.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82189.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82189.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82189.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82189.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82189.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82189.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82190.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82190.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82190.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82190.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82190.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82190.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82190.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82190.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82190.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82190.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82190.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82190.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82190.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82190.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82190.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82190.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82190.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82190.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82190.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82190.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82190.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82190.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82190.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82198.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82198.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82199.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1da0]
>[ 82199.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1da0] width 1920 pitch 7680 (/4 1920)
>[ 82200.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0a4a0]
>[ 82200.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0a4a0] width 1920 pitch 7680 (/4 1920)
>[ 82200.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7f3c0]
>[ 82200.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7f3c0] width 1920 pitch 7680 (/4 1920)
>[ 82200.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9a450]
>[ 82200.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9a450] width 1920 pitch 7680 (/4 1920)
>[ 82200.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51138d0]
>[ 82200.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51138d0] width 1920 pitch 7680 (/4 1920)
>[ 82200.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109070]
>[ 82200.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109070] width 1920 pitch 7680 (/4 1920)
>[ 82200.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb59e0]
>[ 82200.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb59e0] width 1920 pitch 7680 (/4 1920)
>[ 82200.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f452c0]
>[ 82200.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f452c0] width 1920 pitch 7680 (/4 1920)
>[ 82200.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2813e00]
>[ 82200.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2813e00] width 1920 pitch 7680 (/4 1920)
>[ 82200.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a320]
>[ 82200.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a320] width 1920 pitch 7680 (/4 1920)
>[ 82200.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6800]
>[ 82200.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6800] width 1920 pitch 7680 (/4 1920)
>[ 82200.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1da0]
>[ 82200.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1da0] width 1920 pitch 7680 (/4 1920)
>[ 82200.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8e9b0]
>[ 82200.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8e9b0] width 1920 pitch 7680 (/4 1920)
>[ 82200.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0fa30]
>[ 82200.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0fa30] width 1920 pitch 7680 (/4 1920)
>[ 82200.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7f3c0]
>[ 82200.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7f3c0] width 1920 pitch 7680 (/4 1920)
>[ 82200.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0a4a0]
>[ 82200.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0a4a0] width 1920 pitch 7680 (/4 1920)
>[ 82200.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9a450]
>[ 82200.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9a450] width 1920 pitch 7680 (/4 1920)
>[ 82200.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51138d0]
>[ 82200.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51138d0] width 1920 pitch 7680 (/4 1920)
>[ 82200.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109070]
>[ 82200.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109070] width 1920 pitch 7680 (/4 1920)
>[ 82200.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb59e0]
>[ 82200.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb59e0] width 1920 pitch 7680 (/4 1920)
>[ 82200.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f452c0]
>[ 82200.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f452c0] width 1920 pitch 7680 (/4 1920)
>[ 82200.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2813e00]
>[ 82200.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2813e00] width 1920 pitch 7680 (/4 1920)
>[ 82200.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac56d0]
>[ 82200.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac56d0] width 1920 pitch 7680 (/4 1920)
>[ 82200.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6800]
>[ 82200.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6800] width 1920 pitch 7680 (/4 1920)
>[ 82201.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a320]
>[ 82201.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a320] width 1920 pitch 7680 (/4 1920)
>[ 82201.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8e9b0]
>[ 82201.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8e9b0] width 1920 pitch 7680 (/4 1920)
>[ 82201.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0fa30]
>[ 82201.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0fa30] width 1920 pitch 7680 (/4 1920)
>[ 82201.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7f3c0]
>[ 82201.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7f3c0] width 1920 pitch 7680 (/4 1920)
>[ 82201.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0a4a0]
>[ 82201.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0a4a0] width 1920 pitch 7680 (/4 1920)
>[ 82201.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9a450]
>[ 82201.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9a450] width 1920 pitch 7680 (/4 1920)
>[ 82201.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51138d0]
>[ 82201.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51138d0] width 1920 pitch 7680 (/4 1920)
>[ 82201.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109070]
>[ 82201.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109070] width 1920 pitch 7680 (/4 1920)
>[ 82201.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb59e0]
>[ 82201.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb59e0] width 1920 pitch 7680 (/4 1920)
>[ 82201.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f452c0]
>[ 82201.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f452c0] width 1920 pitch 7680 (/4 1920)
>[ 82201.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2813e00]
>[ 82201.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2813e00] width 1920 pitch 7680 (/4 1920)
>[ 82201.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac56d0]
>[ 82201.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac56d0] width 1920 pitch 7680 (/4 1920)
>[ 82201.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6800]
>[ 82201.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6800] width 1920 pitch 7680 (/4 1920)
>[ 82201.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a320]
>[ 82201.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a320] width 1920 pitch 7680 (/4 1920)
>[ 82201.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1da0]
>[ 82201.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1da0] width 1920 pitch 7680 (/4 1920)
>[ 82201.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0fa30]
>[ 82201.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0fa30] width 1920 pitch 7680 (/4 1920)
>[ 82201.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8e9b0]
>[ 82201.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8e9b0] width 1920 pitch 7680 (/4 1920)
>[ 82201.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0a4a0]
>[ 82201.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0a4a0] width 1920 pitch 7680 (/4 1920)
>[ 82201.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9a450]
>[ 82201.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9a450] width 1920 pitch 7680 (/4 1920)
>[ 82201.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51138d0]
>[ 82201.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51138d0] width 1920 pitch 7680 (/4 1920)
>[ 82201.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109070]
>[ 82201.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109070] width 1920 pitch 7680 (/4 1920)
>[ 82201.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb59e0]
>[ 82201.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb59e0] width 1920 pitch 7680 (/4 1920)
>[ 82201.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f452c0]
>[ 82201.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f452c0] width 1920 pitch 7680 (/4 1920)
>[ 82201.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2813e00]
>[ 82201.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2813e00] width 1920 pitch 7680 (/4 1920)
>[ 82201.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac56d0]
>[ 82201.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac56d0] width 1920 pitch 7680 (/4 1920)
>[ 82201.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6800]
>[ 82201.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6800] width 1920 pitch 7680 (/4 1920)
>[ 82201.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a320]
>[ 82201.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a320] width 1920 pitch 7680 (/4 1920)
>[ 82201.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1da0]
>[ 82201.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1da0] width 1920 pitch 7680 (/4 1920)
>[ 82201.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0fa30]
>[ 82201.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0fa30] width 1920 pitch 7680 (/4 1920)
>[ 82201.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8e9b0]
>[ 82201.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8e9b0] width 1920 pitch 7680 (/4 1920)
>[ 82201.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7f3c0]
>[ 82201.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7f3c0] width 1920 pitch 7680 (/4 1920)
>[ 82201.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9a450]
>[ 82201.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9a450] width 1920 pitch 7680 (/4 1920)
>[ 82202.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d0a4a0]
>[ 82202.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d0a4a0] width 1920 pitch 7680 (/4 1920)
>[ 82202.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109070]
>[ 82202.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109070] width 1920 pitch 7680 (/4 1920)
>[ 82202.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb59e0]
>[ 82202.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb59e0] width 1920 pitch 7680 (/4 1920)
>[ 82202.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f452c0]
>[ 82202.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f452c0] width 1920 pitch 7680 (/4 1920)
>[ 82202.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2813e00]
>[ 82202.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2813e00] width 1920 pitch 7680 (/4 1920)
>[ 82202.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac56d0]
>[ 82202.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac56d0] width 1920 pitch 7680 (/4 1920)
>[ 82202.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82202.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82202.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 82202.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 82202.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82202.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82202.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82202.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82202.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82202.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82202.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82203.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82203.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82203.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82203.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82203.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82203.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82203.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82203.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82203.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82203.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82203.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82203.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82203.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82203.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82203.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82203.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82203.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82203.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82203.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82203.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82203.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82203.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82203.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82203.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82203.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82203.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82203.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82203.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82203.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82220.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82220.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82220.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82220.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82220.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82220.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82220.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82220.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82220.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82220.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82220.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82220.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82220.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82220.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82220.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82220.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82224.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82224.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82225.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82225.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82225.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82225.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82225.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82225.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82225.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82225.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82225.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82225.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82225.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82225.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82225.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82225.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82225.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82225.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82225.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82225.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82225.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82225.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82225.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82225.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82225.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82225.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82226.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82226.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82226.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82226.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82226.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82226.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82226.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82226.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82226.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82226.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82226.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82226.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82226.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82226.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82226.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82226.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82226.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82226.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82226.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82226.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82226.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82226.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82226.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82226.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82226.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82226.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82226.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82226.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82226.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82226.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82226.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82226.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82226.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82226.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82226.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82226.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82226.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82226.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82226.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82226.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82226.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82226.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82226.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82226.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82226.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82226.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82226.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82226.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82226.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82226.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82226.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82226.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82226.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82226.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82226.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82226.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82226.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82226.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82226.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82227.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82227.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82227.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82227.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82227.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82227.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82227.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82227.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82227.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82227.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82227.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82227.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82227.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82227.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82227.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82227.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82227.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82227.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82227.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82227.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82227.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82227.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82227.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82227.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82227.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82227.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82227.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82227.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82227.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82227.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82227.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82227.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82227.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82227.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82227.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82227.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82227.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82227.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82227.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82227.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82227.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82227.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82227.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82227.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82227.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82227.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82227.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82227.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82227.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82227.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82227.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82227.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82227.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82227.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82227.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82227.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82227.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82227.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82227.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82227.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82227.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82227.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82227.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82227.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82228.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82228.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82228.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82228.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82228.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82228.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82228.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82228.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82228.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82228.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82228.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82228.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82228.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82228.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82228.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82228.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82228.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82228.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82228.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82228.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82228.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82228.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82228.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82228.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82228.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82228.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82228.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82228.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82228.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82228.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82228.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82228.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82228.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82228.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82228.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82228.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82228.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82228.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82228.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82228.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82228.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82228.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82228.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82228.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82228.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82228.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82228.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82228.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82228.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82228.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82228.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82228.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82228.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82228.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82228.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82228.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82228.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82228.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82228.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82228.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82228.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82228.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82228.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82228.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82228.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82228.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82228.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82228.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82229.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82229.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82229.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82229.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82229.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82229.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82229.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82229.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82229.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82229.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82229.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82229.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82229.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82229.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82229.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82229.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82229.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82229.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82229.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82229.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82229.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82229.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82229.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82229.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82229.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82229.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82229.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82229.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82229.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82229.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82229.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82229.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82229.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82229.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82229.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82229.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82229.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82229.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82229.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82229.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82229.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82229.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82229.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82229.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82229.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82229.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82229.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82229.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82229.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82229.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82229.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82229.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82229.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82229.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82229.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82229.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82229.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82229.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82229.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82229.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82229.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82229.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82229.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82229.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82230.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82230.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82230.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82230.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82230.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82230.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82230.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82230.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82230.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82230.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82230.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82230.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82230.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82230.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82230.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82230.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82230.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82230.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82230.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82230.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82230.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82230.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82230.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82230.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82230.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82230.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82230.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82230.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82230.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82230.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82230.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82230.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82230.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 82230.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 82230.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82230.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82230.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82230.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82230.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82230.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82230.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82230.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82230.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82230.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82230.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82230.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82230.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82230.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82230.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82230.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82230.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82230.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82230.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82230.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82230.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82230.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82230.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82230.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82230.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82230.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82230.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82230.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82230.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82230.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82231.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82231.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82231.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82231.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82231.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82231.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82231.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82231.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82231.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82231.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82231.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82231.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82231.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82231.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82231.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82231.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82231.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82231.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82231.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 82231.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 82231.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82231.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82231.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82231.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82231.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82231.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82231.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82231.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82231.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82231.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82231.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82231.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82231.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82231.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82231.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82231.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82231.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82231.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82231.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82231.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82231.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82231.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82231.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82231.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82231.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82231.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82231.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82231.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82231.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82231.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82231.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82231.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82231.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82231.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82231.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82231.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82231.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82231.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82231.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82231.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82231.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82231.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82231.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82231.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82232.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82232.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82232.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82232.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82232.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82232.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82232.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82232.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82232.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82232.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82232.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82232.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82232.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82232.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82232.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82232.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82232.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82232.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82232.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82232.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82232.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82232.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82232.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82232.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82232.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82232.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82232.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82232.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82232.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82232.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82232.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82232.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82232.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82232.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82232.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82232.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82232.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82232.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82232.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82232.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82232.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82232.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82232.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82232.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82232.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82232.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82232.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82232.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82232.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82232.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82232.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82232.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82232.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82232.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82232.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82232.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82232.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82232.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82232.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82232.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82232.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82232.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82232.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82232.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82233.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82233.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82233.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82233.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82233.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82233.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82233.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82233.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82233.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82233.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82233.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82233.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82233.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82233.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82233.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82233.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82233.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82233.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82233.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82233.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82233.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82233.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82233.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82233.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82233.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82233.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82233.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82233.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82233.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82233.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82233.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82233.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82233.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82233.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82233.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82233.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82233.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82233.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82233.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82233.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82233.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82233.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82233.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82233.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82233.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82233.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82233.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82233.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82233.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82233.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82233.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82233.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82233.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82233.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82233.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82233.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82233.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82233.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82233.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82233.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82233.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82234.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82234.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82234.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82234.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82234.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82234.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82234.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82234.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82234.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82234.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82234.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82234.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82234.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82234.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82234.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82234.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82234.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82234.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82234.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82234.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82234.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82234.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82234.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82234.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82234.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82234.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 82234.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 82234.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82234.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82234.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82234.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82234.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82234.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82234.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82234.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82234.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82234.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82234.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82234.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82234.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82234.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82234.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82234.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82234.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82234.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82234.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82234.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82234.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82234.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82234.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82234.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82234.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82234.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82234.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82234.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82234.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82234.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82234.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82234.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82234.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82234.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82234.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82234.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82234.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82234.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82235.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82235.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82235.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82235.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82235.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82235.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82235.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82235.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82235.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82235.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82235.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82235.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82235.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82235.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82235.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82235.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82235.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82235.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82235.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82235.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82235.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82235.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82235.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82235.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82235.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82235.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82235.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82235.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82235.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82235.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82235.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82235.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82235.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82235.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82235.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82235.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82235.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82235.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82235.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82235.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82235.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82235.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82235.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82235.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82235.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82235.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82235.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82235.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82235.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82235.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82235.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82235.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82235.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82235.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82235.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82235.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82235.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82235.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82235.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82235.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82235.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82235.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82235.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82235.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82236.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82236.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82236.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82236.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82236.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82236.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82236.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82236.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82236.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82236.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82236.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82236.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82236.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82236.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82236.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82236.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82236.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82236.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82236.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82236.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82236.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82236.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82236.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82236.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82236.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82236.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82236.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82236.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82236.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82236.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82236.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82236.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82236.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82236.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82236.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82236.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82236.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82236.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82236.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82236.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82236.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82236.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82236.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82236.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82236.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82236.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82236.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82236.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82236.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82236.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82236.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82236.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82236.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82236.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82236.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82236.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82236.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82236.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82236.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82237.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82237.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82237.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82237.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82237.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82237.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82237.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82237.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82237.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82237.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82237.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82237.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82237.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82237.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82237.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82237.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82237.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82237.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82237.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82237.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82237.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82237.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82237.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82237.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82237.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82237.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82237.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82237.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82237.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82237.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82237.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82237.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82237.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82237.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82237.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82237.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82237.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82237.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82237.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82237.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82237.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82237.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82237.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82237.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82237.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82237.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82237.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82237.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82237.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82237.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82237.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82237.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82237.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82237.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82237.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82237.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82237.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82237.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82237.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82237.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82237.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82237.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82237.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82238.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82238.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82238.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82238.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82238.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82238.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82238.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82238.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82238.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82238.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82238.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82238.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82238.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82238.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82238.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82238.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82238.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82238.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82238.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82238.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82238.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82238.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82238.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82238.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82238.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82238.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82238.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82238.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82238.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82238.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82238.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82238.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82238.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82238.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82238.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82238.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82238.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82238.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82238.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82238.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82238.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82238.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82238.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82238.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82238.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82238.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82238.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82238.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82238.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82238.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82238.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82238.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82238.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82238.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82238.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82238.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82238.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82238.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82238.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82238.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82238.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82238.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82238.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82238.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82239.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82239.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82239.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82239.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82239.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82239.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82239.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82239.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82239.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82239.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82239.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82239.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26d10]
>[ 82239.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26d10] width 1920 pitch 7680 (/4 1920)
>[ 82239.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82239.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82239.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82239.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82239.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82239.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82239.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82239.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82239.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82239.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82239.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82239.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82239.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82239.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82239.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82239.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82239.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82239.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82239.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82239.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82239.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82239.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82239.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82239.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82239.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82239.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82239.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82239.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82239.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82239.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82239.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82239.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82239.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82239.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82239.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82239.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82239.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82239.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82239.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82239.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82239.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82239.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82239.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82239.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82239.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82239.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82239.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82239.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82239.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82239.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82239.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82240.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82240.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82240.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82240.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82240.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82240.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82240.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82240.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82240.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82240.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82240.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82240.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82240.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82240.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82240.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82240.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507eab0]
>[ 82240.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507eab0] width 1920 pitch 7680 (/4 1920)
>[ 82240.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82240.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82240.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82240.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82240.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82240.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82240.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82240.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82240.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82240.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82240.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82240.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82240.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82240.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82240.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82240.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82240.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82240.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82240.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82240.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82240.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82240.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82240.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82240.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82240.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82240.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82240.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82240.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82240.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82240.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82240.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82240.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82240.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82240.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82240.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82240.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82240.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82240.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82240.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82240.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82240.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82240.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82240.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82240.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82241.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82241.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82241.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82241.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82241.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82241.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82241.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82241.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82241.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82241.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82241.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82241.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82243.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82243.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82243.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82243.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82244.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82244.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82244.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82244.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82244.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82244.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82244.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82244.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82244.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82244.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82244.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82244.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82244.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82244.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82244.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82244.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82244.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82244.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82244.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82244.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82244.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82244.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82244.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82244.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82244.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82244.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82244.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82244.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82244.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82244.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82244.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82244.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82244.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82244.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82244.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82244.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82244.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82244.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82245.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82245.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82245.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82245.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82246.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82246.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82246.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82246.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82246.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82246.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82246.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82246.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82246.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82246.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82246.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82246.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82246.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 82246.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 82246.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82246.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82246.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82246.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82246.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82246.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82246.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec0f10]
>[ 82246.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec0f10] width 1920 pitch 7680 (/4 1920)
>[ 82246.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82246.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82249.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82249.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82249.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82249.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82250.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82250.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82250.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82250.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82250.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82250.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82250.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82250.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82250.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82250.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82250.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82250.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82250.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82250.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82250.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82250.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82250.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82250.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82250.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82250.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82250.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82250.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82250.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82250.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82250.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82250.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82250.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82250.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82250.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82250.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82250.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82250.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82250.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82250.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82250.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82250.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82250.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82250.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82250.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82250.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82250.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82250.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82250.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82250.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82250.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82250.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82251.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82251.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82251.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82251.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82251.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82251.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82251.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82251.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82251.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82251.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82251.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82251.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82251.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82251.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82251.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82251.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82251.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82251.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82251.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82251.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82251.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82251.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82251.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82251.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82251.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82251.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82251.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82251.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82251.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82251.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82251.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82251.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82251.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82251.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82251.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82251.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82251.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82251.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82251.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82251.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82251.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82251.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82251.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82251.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82251.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82251.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82251.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82251.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82251.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82251.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82251.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82251.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82251.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82251.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82251.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82251.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82251.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82251.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82251.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82251.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82251.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82251.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82251.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82251.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82252.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82252.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82252.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82252.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82252.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82252.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82252.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82252.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82252.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82252.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82252.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82252.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82252.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82252.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82252.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82252.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82252.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82252.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82252.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82252.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82252.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82252.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82252.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82252.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82252.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82252.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82252.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82252.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82252.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82252.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82252.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82252.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82252.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82252.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82252.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82252.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82252.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82252.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82252.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82252.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82252.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82252.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82252.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82252.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82252.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82252.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82252.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82252.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82252.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82252.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82252.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82252.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82252.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82252.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82252.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82252.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82252.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82252.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82252.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82253.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82253.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82253.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82253.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82253.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82253.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82253.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82253.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82253.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82253.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82253.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82253.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82253.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82253.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82253.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82253.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82253.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82253.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82253.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82253.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82253.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82253.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82253.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82253.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82253.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82253.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82253.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82253.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82253.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82253.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82253.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82253.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82253.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82253.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82253.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82253.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82253.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82253.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82253.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82253.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82253.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82253.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82253.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82253.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82253.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82253.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82253.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82253.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82253.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82253.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82253.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82253.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82253.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82253.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82253.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82253.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82253.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82253.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82253.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82254.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82254.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82254.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82254.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82254.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82254.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82254.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82254.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82254.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82254.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82254.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82254.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82254.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82254.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82254.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82254.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82254.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82254.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82254.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82254.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82254.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82254.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82254.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82254.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82254.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82254.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82254.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82254.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82254.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82254.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82254.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82254.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82254.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82254.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82254.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82254.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82254.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82254.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82254.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82254.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82254.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82254.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82254.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82254.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82254.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82254.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82254.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82254.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82254.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82254.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82254.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82254.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82254.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82254.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82254.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82254.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82254.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82254.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82254.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82254.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82254.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82254.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82255.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82255.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82255.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82255.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82255.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82255.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82255.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82255.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82255.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82255.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82255.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82255.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82255.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82255.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82255.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82255.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82255.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82255.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82255.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82255.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82255.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82255.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82255.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82255.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82255.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c70030]
>[ 82255.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c70030] width 1920 pitch 7680 (/4 1920)
>[ 82256.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82256.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82256.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82256.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82256.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82256.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82256.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82256.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82256.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82256.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82256.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82256.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82256.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82256.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82256.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82256.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82261.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82262.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82262.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82262.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82262.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82262.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82262.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a20ba0]
>[ 82262.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a20ba0] width 1920 pitch 7680 (/4 1920)
>[ 82262.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82262.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82263.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82263.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82263.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82263.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82265.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82265.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82265.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82265.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82266.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82266.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82266.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82266.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82266.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82266.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82266.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82266.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82266.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82266.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82266.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82266.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82266.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82266.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82266.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82267.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82267.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82267.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82267.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82267.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82267.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82267.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82267.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82267.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82267.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82267.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82267.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82267.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82267.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82268.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82268.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82268.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82268.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82268.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82268.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82268.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82268.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82269.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82269.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82269.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82269.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82269.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82269.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82269.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82269.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82269.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82269.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82269.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82269.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82269.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82269.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82269.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82269.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82269.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82269.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82269.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82269.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82269.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82269.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82269.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82269.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82269.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82269.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82269.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82269.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82269.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82269.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82269.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82269.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82269.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82269.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82269.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82269.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82269.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82269.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82269.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82269.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82269.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82269.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82269.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82269.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82269.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82269.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82270.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82270.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82270.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82270.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82270.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82270.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82270.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82270.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82270.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82270.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82270.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82270.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82270.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82270.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82271.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82271.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82271.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82271.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82271.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82271.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82271.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82271.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82271.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82271.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82271.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82271.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82271.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82271.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82271.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82271.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82271.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82271.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82271.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82271.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82272.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82272.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82272.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82272.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82272.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82272.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82272.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82272.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82272.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82272.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82272.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82272.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82272.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82272.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82272.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82272.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82273.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82273.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82273.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82273.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82273.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82273.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82273.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82273.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82273.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82273.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82273.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82273.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82273.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82273.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82273.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82273.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82273.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82273.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82273.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82273.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82273.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82273.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82277.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82277.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82277.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82277.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82277.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82277.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82277.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82277.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82277.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82277.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82277.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82277.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82277.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82277.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82277.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82277.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82277.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82277.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82277.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82277.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82277.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82277.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82277.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82277.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82286.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82286.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82287.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82287.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82287.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82287.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82287.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82287.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82287.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82287.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82287.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82287.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82287.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82287.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82287.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82287.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82287.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82287.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82287.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82287.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82287.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82287.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82287.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82287.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82287.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82287.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82287.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82288.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82288.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82288.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82288.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82288.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82288.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82288.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82288.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82288.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82288.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82288.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82288.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82288.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82288.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82288.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82288.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82288.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82288.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82288.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82288.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82288.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82288.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82288.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82288.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82288.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82288.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82288.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82288.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82288.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82288.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82288.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82288.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82288.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82288.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82288.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82288.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82288.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82288.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82288.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82288.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82288.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82288.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82288.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82288.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82288.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82288.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82288.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82288.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82288.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82288.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82288.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82288.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82288.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82288.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82288.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82288.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82288.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82288.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82288.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82288.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82288.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82288.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82288.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82288.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82289.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82289.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82289.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82289.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82289.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82289.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82289.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82289.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82289.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82289.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82289.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82289.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82289.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82289.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82289.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82289.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82289.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82289.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82289.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82289.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82289.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82289.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82289.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82289.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82289.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82289.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82289.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82289.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82289.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82289.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82289.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82289.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82289.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82289.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82289.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82289.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82289.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82289.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82289.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82289.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82289.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82289.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82289.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82289.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82289.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82289.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82289.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82289.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82289.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82289.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82289.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82289.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82289.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82289.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82289.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82289.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82289.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82289.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82289.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82289.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82289.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82289.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82289.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82289.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82290.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82290.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82290.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82290.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82290.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82290.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82290.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82290.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82290.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82290.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82290.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82290.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82290.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82290.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82290.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82290.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82290.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82290.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82290.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82290.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82290.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82290.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82290.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82290.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82290.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82290.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82290.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82290.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82290.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82290.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82290.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82290.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82290.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82290.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82290.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82290.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82290.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82290.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82290.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82290.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82290.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82290.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82290.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82290.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82290.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82290.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82290.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82290.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82290.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82290.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82290.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82290.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82290.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82290.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82290.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82290.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82290.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82290.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82290.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82291.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82291.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82291.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82291.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82291.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82291.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82291.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82291.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82291.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82291.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82291.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82291.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82291.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82291.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82291.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82291.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82291.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82291.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82291.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82291.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82291.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82291.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82291.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82291.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82291.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82291.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82291.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82291.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82291.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82291.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82291.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82291.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82291.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82291.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82291.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82291.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82291.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82291.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82291.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82291.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82291.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82291.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82291.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82291.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82291.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82291.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82291.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82291.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82291.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82291.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82291.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82291.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82291.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82291.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82291.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82291.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82291.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82291.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82291.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82291.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82291.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82291.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82291.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82291.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82292.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82292.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82292.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82292.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82292.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82292.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82292.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82292.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82292.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82292.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82292.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82292.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82292.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82292.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82292.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82292.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82292.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82292.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82292.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82292.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82292.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82292.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82292.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82292.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82292.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82292.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82292.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82292.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82292.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82292.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82292.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82292.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82292.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82292.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82292.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82292.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82292.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82292.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82292.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82292.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82292.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82292.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82292.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82292.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82292.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82292.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82292.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82292.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82292.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82292.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82292.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82292.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82292.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82292.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82292.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82292.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82292.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82292.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82292.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82292.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82292.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82292.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82292.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82292.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82293.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82293.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82293.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82293.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82293.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82293.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82293.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82293.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82293.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82293.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82293.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82293.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82293.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82293.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82293.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82293.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82293.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82293.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82293.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82293.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82293.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82293.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82293.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82293.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82293.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82293.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82293.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82293.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82293.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82293.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82293.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82293.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82293.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82293.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82293.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82293.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82293.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82293.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82293.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82293.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82293.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82293.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82293.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82293.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82293.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82293.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82293.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82293.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82293.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82293.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82293.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82293.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82293.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82293.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82293.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82293.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82293.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82293.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82293.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82293.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82293.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82293.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82293.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82293.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82294.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82294.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82294.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82294.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82294.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82294.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82294.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82294.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82294.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82294.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82294.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82294.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82294.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82294.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82294.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82294.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82294.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82294.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82294.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82294.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82294.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82294.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82294.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82294.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82294.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82294.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82294.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82294.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82294.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82294.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82294.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82294.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82294.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82294.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82294.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82294.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82294.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82294.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82294.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82294.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82294.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82294.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82294.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82294.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82294.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82294.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82294.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82294.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82294.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82294.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82294.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82294.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82294.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82294.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82294.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82294.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82294.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82294.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82294.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82294.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82294.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82294.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82294.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82294.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82295.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82295.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82295.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82295.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82295.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82295.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82295.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82295.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82295.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82295.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82295.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82295.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82295.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82295.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82295.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82295.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3a9a0]
>[ 82295.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3a9a0] width 1920 pitch 7680 (/4 1920)
>[ 82295.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82295.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82295.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82295.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82295.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82295.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82295.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82295.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82295.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82295.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82296.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82296.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82397.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82397.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82397.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82397.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82398.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82398.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82398.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82398.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82398.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82398.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82398.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82398.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82398.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82398.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82398.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82398.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82398.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82398.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82398.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82398.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82398.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82398.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82398.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82398.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82398.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82398.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82398.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82398.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82398.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82398.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82398.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82398.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82398.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82398.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82398.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82398.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82398.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82398.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82398.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82398.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82398.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82398.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82398.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82399.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82399.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82399.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82399.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82399.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82399.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82399.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82399.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82399.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82399.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82399.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82399.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82399.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82399.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82399.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82399.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82399.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82399.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82399.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82399.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82399.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82399.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82399.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82399.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82399.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82399.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82399.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82399.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82399.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82399.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82399.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82399.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82399.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82399.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82399.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82399.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82399.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82399.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82399.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82399.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82399.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82399.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82399.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82399.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82399.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82399.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82399.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82399.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82399.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82399.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82399.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82399.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82399.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82399.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82399.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82399.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82399.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82399.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82399.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82399.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82399.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82399.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82400.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82400.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82400.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82400.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82400.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82400.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82400.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82400.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82400.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82400.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82400.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82400.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82400.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82400.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82400.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82400.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82400.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82400.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82400.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82400.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82400.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82400.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82400.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82400.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82400.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82400.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82400.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82400.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82400.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82400.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82400.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82400.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82400.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82400.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82400.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82400.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82400.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82400.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82400.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82400.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82400.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82400.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82400.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82400.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82400.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82400.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82400.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82400.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82400.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82400.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82400.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82400.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82400.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82400.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82400.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82400.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82400.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82400.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82400.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82400.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82400.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82400.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82400.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82400.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82401.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82401.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82401.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82401.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82401.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82401.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82401.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82401.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82401.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82401.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82401.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82401.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82401.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82401.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82401.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82401.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82401.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82401.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82401.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82401.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82401.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82401.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82401.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82401.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82401.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82401.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82401.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82401.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82401.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82401.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82401.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82401.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82401.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82401.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82401.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82401.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82401.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82401.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82401.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82401.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82401.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82401.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82401.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82401.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82401.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82401.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82401.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82401.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82401.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82401.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82401.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82401.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82401.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82401.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82401.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82401.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82401.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82401.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82401.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82401.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82401.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82401.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82401.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82401.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82402.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82402.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82402.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82402.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82402.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82402.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82402.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82402.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82402.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82402.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82402.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82402.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82402.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82402.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82402.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82402.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82402.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82402.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82402.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82402.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82402.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82402.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82402.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82402.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82402.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82402.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82402.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82402.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82402.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82402.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82402.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82402.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82402.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82402.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82402.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82402.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82402.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82402.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82402.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82402.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82402.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82402.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82402.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82402.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82402.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82402.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7d4c0]
>[ 82402.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7d4c0] width 1920 pitch 7680 (/4 1920)
>[ 82403.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82403.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82413.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82413.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82413.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82413.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82414.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82414.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82414.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82414.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82414.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82414.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82414.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82414.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82414.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82414.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82414.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82414.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82414.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82414.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82414.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82414.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82414.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82414.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82414.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82414.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82414.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82414.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82414.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82414.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82414.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82414.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82414.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82414.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82414.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82414.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82414.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82414.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82414.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82414.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82414.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82414.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82414.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5115ca0]
>[ 82414.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5115ca0] width 1920 pitch 7680 (/4 1920)
>[ 82414.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82414.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82415.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82415.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82415.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82415.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82415.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82415.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82415.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82415.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82415.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82415.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82415.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82415.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82415.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82415.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82415.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82415.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82415.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82415.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82415.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82415.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82415.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82415.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82415.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82415.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82415.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82415.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82415.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82415.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82415.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82415.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82415.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82415.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82415.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82415.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82415.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82415.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82415.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82415.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82415.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82415.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82415.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82415.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82415.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82415.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82415.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82415.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82415.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82415.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82415.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f520]
>[ 82415.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f520] width 1920 pitch 7680 (/4 1920)
>[ 82415.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82415.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82415.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82415.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82415.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82415.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82415.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82415.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82415.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82415.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82416.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82416.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82416.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82416.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82449.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82449.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82449.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82449.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82450.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82450.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82450.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82450.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82450.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82450.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82450.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82450.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82450.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82450.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82450.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82450.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82450.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82450.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82450.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82450.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82450.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82450.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82450.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82450.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82450.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82450.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82450.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82450.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82450.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82450.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82450.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82450.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82450.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82450.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82450.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82450.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82450.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82450.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82450.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82450.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82450.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82450.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82450.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82450.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82450.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82450.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82451.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82451.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82451.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82451.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82451.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82451.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82451.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82451.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82451.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82451.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82451.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82451.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82451.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82451.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82451.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82451.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82451.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82451.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82451.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82451.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82451.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82451.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82451.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82451.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82451.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82451.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82451.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82451.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82451.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82451.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82451.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82451.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82451.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82451.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82451.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82451.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82451.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82451.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82451.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82451.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82451.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82451.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82451.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82451.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82451.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82451.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82451.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82451.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82451.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82451.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82451.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82451.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82451.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82451.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82451.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82451.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82451.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82451.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82451.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82451.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82451.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82451.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82452.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82452.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82452.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 82452.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 82452.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82452.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82452.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82452.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82452.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82452.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82452.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82452.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82452.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82452.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82452.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82452.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82452.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 82452.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 82452.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82452.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82452.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 82452.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 82452.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82452.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82452.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82452.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82452.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82452.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82452.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82452.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82452.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82452.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82452.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82452.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82452.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3790]
>[ 82452.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3790] width 1920 pitch 7680 (/4 1920)
>[ 82452.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82452.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82452.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82452.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82452.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82452.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82452.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82452.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82452.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82452.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82452.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82452.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82452.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82452.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82452.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82452.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82452.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82452.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82452.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82452.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82452.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82452.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82452.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82452.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82452.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82452.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82453.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82453.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82453.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82453.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82453.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82453.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82453.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82453.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82453.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5100120]
>[ 82453.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5100120] width 1920 pitch 7680 (/4 1920)
>[ 82453.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82453.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82453.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ec70]
>[ 82453.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ec70] width 1920 pitch 7680 (/4 1920)
>[ 82453.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82453.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82453.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 82453.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 82453.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18140]
>[ 82453.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18140] width 1920 pitch 7680 (/4 1920)
>[ 82453.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 82453.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 82453.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 82453.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 82453.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae8a0]
>[ 82454.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae8a0] width 1920 pitch 7680 (/4 1920)
>[ 82454.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82454.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82454.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82454.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82454.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82454.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82454.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82454.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82454.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82454.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82454.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82454.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82454.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82454.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82564.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1fb40]
>[ 82564.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1fb40] width 1920 pitch 7680 (/4 1920)
>[ 82565.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82565.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82565.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82565.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82565.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82565.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82565.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82565.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82565.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82565.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82565.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82565.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82565.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82565.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82565.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82565.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82565.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82565.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82565.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82565.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82565.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82566.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82566.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82566.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82566.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82567.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82567.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82567.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82567.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82567.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82567.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82567.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82567.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82567.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82567.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82567.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82567.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82567.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82567.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82567.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82609.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82609.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82609.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82609.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82610.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82610.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82610.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82610.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82610.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82610.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82610.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82610.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82610.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82610.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82610.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82610.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82610.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd070]
>[ 82610.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd070] width 1920 pitch 7680 (/4 1920)
>[ 82610.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34410]
>[ 82610.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34410] width 1920 pitch 7680 (/4 1920)
>[ 82610.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82610.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82610.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82610.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82610.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82610.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82610.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82610.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82610.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82610.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82610.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82610.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82610.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82610.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82610.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82610.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82610.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f310a0]
>[ 82610.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f310a0] width 1920 pitch 7680 (/4 1920)
>[ 82610.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 82610.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 82610.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 82610.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 82610.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 82610.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 82610.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82611.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82611.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f110]
>[ 82611.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f110] width 1920 pitch 7680 (/4 1920)
>[ 82611.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 82611.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 82611.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82611.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82611.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51148e0]
>[ 82611.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51148e0] width 1920 pitch 7680 (/4 1920)
>[ 82611.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82611.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82611.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c07e0]
>[ 82611.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c07e0] width 1920 pitch 7680 (/4 1920)
>[ 82611.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 82611.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 82615.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82615.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82615.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 82615.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 82616.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb6560]
>[ 82616.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb6560] width 1920 pitch 7680 (/4 1920)
>[ 82616.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[ 82616.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1920 pitch 7680 (/4 1920)
>[ 82616.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824f40]
>[ 82616.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824f40] width 1920 pitch 7680 (/4 1920)
>[ 82616.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd820]
>[ 82616.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd820] width 1920 pitch 7680 (/4 1920)
>[ 82616.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 82616.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 82616.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508a760]
>[ 82616.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508a760] width 1920 pitch 7680 (/4 1920)
>[ 82616.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82616.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82616.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82616.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82616.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82616.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82617.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82617.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82617.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82617.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82617.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82617.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82617.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82617.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82617.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82617.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82617.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82617.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82617.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82617.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82617.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82617.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82618.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82618.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82618.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82618.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82618.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82618.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82618.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82618.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82618.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82618.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82618.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82618.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82620.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82620.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82620.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ad70]
>[ 82620.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ad70] width 1920 pitch 7680 (/4 1920)
>[ 82620.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeba60]
>[ 82620.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeba60] width 1920 pitch 7680 (/4 1920)
>[ 82687.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82687.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82687.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82687.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82687.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82687.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82687.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 82687.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 82687.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82687.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82687.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82687.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82704.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 82704.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 82704.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 82704.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 82705.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f62a80]
>[ 82705.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f62a80] width 1920 pitch 7680 (/4 1920)
>[ 82706.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 82706.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 82706.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 82706.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 82706.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 82706.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 82706.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbe830]
>[ 82706.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbe830] width 1920 pitch 7680 (/4 1920)
>[ 82706.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 82706.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 82706.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eae00]
>[ 82706.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eae00] width 1920 pitch 7680 (/4 1920)
>[ 82706.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eae00]
>[ 82706.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eae00] width 1920 pitch 7680 (/4 1920)
>[ 82707.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052af0]
>[ 82708.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052af0] width 1920 pitch 7680 (/4 1920)
>[ 82708.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 82708.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 82708.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 82708.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 82709.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f97740]
>[ 82709.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f97740] width 1920 pitch 7680 (/4 1920)
>[ 82709.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052af0]
>[ 82709.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052af0] width 1920 pitch 7680 (/4 1920)
>[ 82709.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2871b00]
>[ 82709.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2871b00] width 1920 pitch 7680 (/4 1920)
>[ 82709.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509bac0]
>[ 82709.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509bac0] width 1920 pitch 7680 (/4 1920)
>[ 82709.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3965140]
>[ 82709.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3965140] width 1920 pitch 7680 (/4 1920)
>[ 82709.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f33830]
>[ 82709.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f33830] width 1920 pitch 7680 (/4 1920)
>[ 82709.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f124b0]
>[ 82709.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f124b0] width 1920 pitch 7680 (/4 1920)
>[ 82709.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f95f0]
>[ 82709.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f95f0] width 1920 pitch 7680 (/4 1920)
>[ 82709.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f303b0]
>[ 82709.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f303b0] width 1920 pitch 7680 (/4 1920)
>[ 82709.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b9d0]
>[ 82709.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b9d0] width 1920 pitch 7680 (/4 1920)
>[ 82709.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eea2f0]
>[ 82709.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eea2f0] width 1920 pitch 7680 (/4 1920)
>[ 82720.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb560]
>[ 82720.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb560] width 1920 pitch 7680 (/4 1920)
>[ 82722.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c21500]
>[ 82722.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c21500] width 1920 pitch 7680 (/4 1920)
>[ 82734.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eba390]
>[ 82734.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eba390] width 1920 pitch 7680 (/4 1920)
>[ 82734.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3930530]
>[ 82734.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3930530] width 1920 pitch 7680 (/4 1920)
>[ 82734.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f939a0]
>[ 82734.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f939a0] width 1920 pitch 7680 (/4 1920)
>[ 82734.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82734.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82734.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82734.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82735.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82735.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82736.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82736.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82736.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82736.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82774.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82774.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82775.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3986dd0]
>[ 82775.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3986dd0] width 1920 pitch 7680 (/4 1920)
>[ 82775.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 82775.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 82776.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82776.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82776.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82776.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82776.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82776.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82776.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82776.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82776.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82776.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82776.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 82776.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 82776.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 82776.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 82776.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82776.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82776.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 82776.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 82776.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c96c60]
>[ 82776.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c96c60] width 1920 pitch 7680 (/4 1920)
>[ 82776.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 82776.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 82776.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc060]
>[ 82776.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc060] width 1920 pitch 7680 (/4 1920)
>[ 82776.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82776.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82776.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 82776.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 82776.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28531e0]
>[ 82776.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28531e0] width 1920 pitch 7680 (/4 1920)
>[ 82776.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82776.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82776.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82776.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82965.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5cd0]
>[ 82965.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5cd0] width 1920 pitch 7680 (/4 1920)
>[ 82965.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82965.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82965.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 82965.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 82965.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 82965.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 82965.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095a20]
>[ 82965.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095a20] width 1920 pitch 7680 (/4 1920)
>[ 82965.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510fb10]
>[ 82965.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510fb10] width 1920 pitch 7680 (/4 1920)
>[ 82965.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82965.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82965.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5cd0]
>[ 82965.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5cd0] width 1920 pitch 7680 (/4 1920)
>[ 82966.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 82966.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 82966.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 82966.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 82966.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82966.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82966.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82966.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82966.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82966.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82966.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82966.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82966.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82966.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82966.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82966.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82967.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82967.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82967.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82967.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82967.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82967.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82967.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82967.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82967.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82967.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82967.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82967.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82967.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82967.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 82967.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 82967.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 82967.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 82967.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 83323.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 83323.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 83323.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83323.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83324.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 83324.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 83324.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 83324.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 83324.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[ 83324.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[ 83324.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f4f0]
>[ 83324.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f4f0] width 1920 pitch 7680 (/4 1920)
>[ 83324.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 83324.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 83324.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 83324.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 83328.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd800]
>[ 83328.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd800] width 1920 pitch 7680 (/4 1920)
>[ 83328.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 83328.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 83329.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 83329.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 83329.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 83329.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 83329.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 83329.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 83329.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 83329.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 83329.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 83329.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 83329.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83329.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83329.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 83329.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 83329.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[ 83329.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[ 83329.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853310]
>[ 83329.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853310] width 1920 pitch 7680 (/4 1920)
>[ 83329.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f4f0]
>[ 83329.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f4f0] width 1920 pitch 7680 (/4 1920)
>[ 83329.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[ 83329.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1920 pitch 7680 (/4 1920)
>[ 83329.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6967610]
>[ 83329.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6967610] width 1920 pitch 7680 (/4 1920)
>[ 83329.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f147e0]
>[ 83329.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f147e0] width 1920 pitch 7680 (/4 1920)
>[ 83329.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[ 83329.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1920 pitch 7680 (/4 1920)
>[ 83329.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff130]
>[ 83329.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff130] width 1920 pitch 7680 (/4 1920)
>[ 83329.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095a20]
>[ 83329.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095a20] width 1920 pitch 7680 (/4 1920)
>[ 83329.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 83329.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 83329.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2e20]
>[ 83329.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2e20] width 1920 pitch 7680 (/4 1920)
>[ 83329.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 83329.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 83329.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 83329.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 83329.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82250]
>[ 83329.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82250] width 1920 pitch 7680 (/4 1920)
>[ 83329.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd800]
>[ 83329.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd800] width 1920 pitch 7680 (/4 1920)
>[ 83329.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 83329.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 83329.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 83329.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 83329.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[ 83329.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[ 83329.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28726a0]
>[ 83330.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28726a0] width 1920 pitch 7680 (/4 1920)
>[ 83330.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 83330.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 83330.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88650]
>[ 83330.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88650] width 1920 pitch 7680 (/4 1920)
>[ 83330.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28356d0]
>[ 83330.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28356d0] width 1920 pitch 7680 (/4 1920)
>[ 83330.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 83330.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 83330.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5cd0]
>[ 83330.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5cd0] width 1920 pitch 7680 (/4 1920)
>[ 83330.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 83330.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 83330.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 83330.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 83330.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 83330.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 83330.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 83330.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 83330.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 83330.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 83330.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 83330.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 83330.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 83330.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 83330.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83330.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83330.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 83330.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 83330.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[ 83330.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[ 83330.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28726a0]
>[ 83330.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28726a0] width 1920 pitch 7680 (/4 1920)
>[ 83330.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26fdc20]
>[ 83330.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26fdc20] width 1920 pitch 7680 (/4 1920)
>[ 83330.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88650]
>[ 83330.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88650] width 1920 pitch 7680 (/4 1920)
>[ 83330.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28356d0]
>[ 83330.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28356d0] width 1920 pitch 7680 (/4 1920)
>[ 83330.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 83330.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 83330.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5cd0]
>[ 83330.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5cd0] width 1920 pitch 7680 (/4 1920)
>[ 83330.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 83330.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 83330.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f255b0]
>[ 83330.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f255b0] width 1920 pitch 7680 (/4 1920)
>[ 83330.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 83330.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 83330.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 83330.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 83330.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 83330.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 83330.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4149330]
>[ 83330.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4149330] width 1920 pitch 7680 (/4 1920)
>[ 83330.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 83330.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 83330.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853310]
>[ 83330.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853310] width 1920 pitch 7680 (/4 1920)
>[ 83593.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83593.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83593.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83594.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83594.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83594.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83594.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83594.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83594.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83595.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83595.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 83595.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 83595.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83595.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83595.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26cc0]
>[ 83595.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26cc0] width 1920 pitch 7680 (/4 1920)
>[ 83595.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83595.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83595.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c105e0]
>[ 83595.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c105e0] width 1920 pitch 7680 (/4 1920)
>[ 83595.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83595.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83595.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83595.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83595.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdfb0]
>[ 83595.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdfb0] width 1920 pitch 7680 (/4 1920)
>[ 83595.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83595.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83595.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26cc0]
>[ 83595.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26cc0] width 1920 pitch 7680 (/4 1920)
>[ 83595.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83595.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83595.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c105e0]
>[ 83595.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c105e0] width 1920 pitch 7680 (/4 1920)
>[ 83595.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83595.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83606.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83606.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83606.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26cc0]
>[ 83606.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26cc0] width 1920 pitch 7680 (/4 1920)
>[ 83606.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83606.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83760.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83760.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83760.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83760.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83761.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[ 83761.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[ 83762.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83762.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83762.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83762.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83762.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83762.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83762.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83762.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83762.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83762.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83762.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[ 83762.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[ 83762.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83762.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83762.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83762.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83762.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83762.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83762.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83762.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83763.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 83763.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 83763.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83763.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83763.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c105e0]
>[ 83763.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c105e0] width 1920 pitch 7680 (/4 1920)
>[ 83763.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83763.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83763.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83763.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83769.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[ 83769.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[ 83769.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83769.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83769.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83769.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83769.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 83769.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 83769.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83769.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83769.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83769.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83769.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83769.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83770.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5afa0]
>[ 83770.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5afa0] width 1920 pitch 7680 (/4 1920)
>[ 83770.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83770.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83770.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83770.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83770.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c105e0]
>[ 83770.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c105e0] width 1920 pitch 7680 (/4 1920)
>[ 83771.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83771.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83771.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83771.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83771.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83771.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83771.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83771.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83771.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83771.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83771.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83771.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83771.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83771.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83771.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83771.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83771.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83771.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83771.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83771.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83771.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83771.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83771.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83771.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83771.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83771.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83771.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83771.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83771.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83771.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83771.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83771.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83771.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83771.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83771.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83771.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83771.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83771.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83771.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b246c0]
>[ 83771.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b246c0] width 1920 pitch 7680 (/4 1920)
>[ 83771.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83771.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83771.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83771.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83969.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83969.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83970.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83970.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83970.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83970.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83970.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83970.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83970.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83970.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83970.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83970.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83970.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83970.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83970.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 83970.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 83970.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83970.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83971.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83971.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83971.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83971.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83971.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83971.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83971.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bae940]
>[ 83971.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bae940] width 1920 pitch 7680 (/4 1920)
>[ 83971.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5280]
>[ 83971.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5280] width 1920 pitch 7680 (/4 1920)
>[ 83972.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286da10]
>[ 83972.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286da10] width 1920 pitch 7680 (/4 1920)
>[ 83972.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f774b0]
>[ 83972.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f774b0] width 1920 pitch 7680 (/4 1920)
>[ 83972.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83972.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83972.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83972.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83972.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[ 83972.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[ 83972.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83972.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83972.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af20]
>[ 83972.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af20] width 1920 pitch 7680 (/4 1920)
>[ 83972.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109010]
>[ 83972.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109010] width 1920 pitch 7680 (/4 1920)
>[ 83972.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42733b0]
>[ 83972.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42733b0] width 1920 pitch 7680 (/4 1920)
>[ 83972.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956060]
>[ 83972.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956060] width 1920 pitch 7680 (/4 1920)
>[ 83972.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fd20]
>[ 83972.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fd20] width 1920 pitch 7680 (/4 1920)
>[ 83972.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af20]
>[ 83972.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af20] width 1920 pitch 7680 (/4 1920)
>[ 83972.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f910]
>[ 83972.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f910] width 1920 pitch 7680 (/4 1920)
>[ 83972.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505af20]
>[ 83972.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505af20] width 1920 pitch 7680 (/4 1920)
>[ 84162.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c701c0]
>[ 84162.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c701c0] width 1920 pitch 7680 (/4 1920)
>[ 84162.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecb7f0]
>[ 84162.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecb7f0] width 1920 pitch 7680 (/4 1920)
>[ 84162.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4faaa60]
>[ 84162.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4faaa60] width 1920 pitch 7680 (/4 1920)
>[ 84162.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c242a0]
>[ 84162.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c242a0] width 1920 pitch 7680 (/4 1920)
>[ 84162.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6a660]
>[ 84162.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6a660] width 1920 pitch 7680 (/4 1920)
>[ 84162.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd2f0]
>[ 84162.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd2f0] width 1920 pitch 7680 (/4 1920)
>[ 84162.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63680]
>[ 84162.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63680] width 1920 pitch 7680 (/4 1920)
>[ 84162.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9a60]
>[ 84162.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9a60] width 1920 pitch 7680 (/4 1920)
>[ 84162.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3986dd0]
>[ 84162.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3986dd0] width 1920 pitch 7680 (/4 1920)
>[ 84162.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb8f60]
>[ 84162.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb8f60] width 1920 pitch 7680 (/4 1920)
>[ 84162.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6c4c0]
>[ 84162.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6c4c0] width 1920 pitch 7680 (/4 1920)
>[ 84162.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb45c0]
>[ 84162.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb45c0] width 1920 pitch 7680 (/4 1920)
>[ 84162.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5060900]
>[ 84162.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5060900] width 1920 pitch 7680 (/4 1920)
>[ 84162.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06ff0]
>[ 84162.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06ff0] width 1920 pitch 7680 (/4 1920)
>[ 84162.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5040]
>[ 84162.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5040] width 1920 pitch 7680 (/4 1920)
>[ 84162.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b0a0]
>[ 84162.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b0a0] width 1920 pitch 7680 (/4 1920)
>[ 84202.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb45c0]
>[ 84202.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb45c0] width 1920 pitch 7680 (/4 1920)
>[ 84202.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b0a0]
>[ 84202.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b0a0] width 1920 pitch 7680 (/4 1920)
>[ 84202.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecb7f0]
>[ 84202.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecb7f0] width 1920 pitch 7680 (/4 1920)
>[ 84382.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48530]
>[ 84382.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48530] width 1920 pitch 7680 (/4 1920)
>[ 84382.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48530]
>[ 84382.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48530] width 1920 pitch 7680 (/4 1920)
>[ 84383.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4faaa60]
>[ 84383.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4faaa60] width 1920 pitch 7680 (/4 1920)
>[ 84383.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa5040]
>[ 84383.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa5040] width 1920 pitch 7680 (/4 1920)
>[ 84384.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20380]
>[ 84384.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20380] width 1920 pitch 7680 (/4 1920)
>[ 84384.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bdfb0]
>[ 84384.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bdfb0] width 1920 pitch 7680 (/4 1920)
>[ 84445.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4054490]
>[ 84445.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4054490] width 1920 pitch 7680 (/4 1920)
>[ 84445.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb94c0]
>[ 84446.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb94c0] width 1920 pitch 7680 (/4 1920)
>[ 84446.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c58200]
>[ 84446.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c58200] width 1920 pitch 7680 (/4 1920)
>[ 84446.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb94c0]
>[ 84446.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb94c0] width 1920 pitch 7680 (/4 1920)
>[ 84446.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca1590]
>[ 84446.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca1590] width 1920 pitch 7680 (/4 1920)
>[ 84453.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfca00]
>[ 84453.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfca00] width 1920 pitch 7680 (/4 1920)
>[ 84453.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c9d0]
>[ 84453.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c9d0] width 1920 pitch 7680 (/4 1920)
>[ 84453.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979cd0]
>[ 84453.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979cd0] width 1920 pitch 7680 (/4 1920)
>[ 84453.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb2fb0]
>[ 84453.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb2fb0] width 1920 pitch 7680 (/4 1920)
>[ 84453.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84453.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979cd0]
>[ 84453.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979cd0] width 1920 pitch 7680 (/4 1920)
>[ 84453.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84453.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84453.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84453.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84453.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84453.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfa40]
>[ 84454.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfa40] width 1920 pitch 7680 (/4 1920)
>[ 84454.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84454.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262b90]
>[ 84454.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262b90] width 1920 pitch 7680 (/4 1920)
>[ 84527.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec6040]
>[ 84527.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec6040] width 1920 pitch 7680 (/4 1920)
>[ 84527.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8df0]
>[ 84527.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8df0] width 1920 pitch 7680 (/4 1920)
>[ 84528.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4052db0]
>[ 84528.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4052db0] width 1920 pitch 7680 (/4 1920)
>[ 84528.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4052db0]
>[ 84528.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4052db0] width 1920 pitch 7680 (/4 1920)
>[ 84528.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4052db0]
>[ 84528.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4052db0] width 1920 pitch 7680 (/4 1920)
>[ 84528.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4052db0]
>[ 84528.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4052db0] width 1920 pitch 7680 (/4 1920)
>[ 84528.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84528.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84528.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84528.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84528.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84529.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84529.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84631.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87c10]
>[ 84631.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87c10] width 1920 pitch 7680 (/4 1920)
>[ 84631.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 84631.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 84631.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b4b0]
>[ 84632.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b4b0] width 1920 pitch 7680 (/4 1920)
>[ 84632.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98f20]
>[ 84632.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98f20] width 1920 pitch 7680 (/4 1920)
>[ 84632.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 84632.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 84632.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98f20]
>[ 84632.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98f20] width 1920 pitch 7680 (/4 1920)
>[ 84632.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd490]
>[ 84632.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd490] width 1920 pitch 7680 (/4 1920)
>[ 84632.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 84632.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 84632.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84632.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84632.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 84632.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 84632.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 84632.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 84632.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504a010]
>[ 84632.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504a010] width 1920 pitch 7680 (/4 1920)
>[ 84632.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb65b0]
>[ 84632.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb65b0] width 1920 pitch 7680 (/4 1920)
>[ 84632.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 84632.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 84632.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07060]
>[ 84632.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07060] width 1920 pitch 7680 (/4 1920)
>[ 84632.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61030]
>[ 84632.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61030] width 1920 pitch 7680 (/4 1920)
>[ 84632.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073a00]
>[ 84632.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073a00] width 1920 pitch 7680 (/4 1920)
>[ 84632.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd360]
>[ 84632.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd360] width 1920 pitch 7680 (/4 1920)
>[ 84632.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[ 84632.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[ 84632.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87c10]
>[ 84632.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87c10] width 1920 pitch 7680 (/4 1920)
>[ 84632.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86bb0]
>[ 84632.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86bb0] width 1920 pitch 7680 (/4 1920)
>[ 84632.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13670]
>[ 84632.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13670] width 1920 pitch 7680 (/4 1920)
>[ 84632.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e68c90]
>[ 84632.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e68c90] width 1920 pitch 7680 (/4 1920)
>[ 84632.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ac00]
>[ 84632.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ac00] width 1920 pitch 7680 (/4 1920)
>[ 84632.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[ 84632.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1920 pitch 7680 (/4 1920)
>[ 84632.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f010]
>[ 84632.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f010] width 1920 pitch 7680 (/4 1920)
>[ 84632.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bbf0]
>[ 84632.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bbf0] width 1920 pitch 7680 (/4 1920)
>[ 84632.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b530]
>[ 84632.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b530] width 1920 pitch 7680 (/4 1920)
>[ 84632.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[ 84632.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1920 pitch 7680 (/4 1920)
>[ 84632.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbc70]
>[ 84632.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbc70] width 1920 pitch 7680 (/4 1920)
>[ 84632.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84632.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84632.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e65050]
>[ 84632.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e65050] width 1920 pitch 7680 (/4 1920)
>[ 84632.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45610]
>[ 84632.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45610] width 1920 pitch 7680 (/4 1920)
>[ 84632.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efba10]
>[ 84632.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efba10] width 1920 pitch 7680 (/4 1920)
>[ 84633.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 84633.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 84633.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd490]
>[ 84633.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd490] width 1920 pitch 7680 (/4 1920)
>[ 84633.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 84633.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 84633.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84633.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84633.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 84633.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 84633.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 84633.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 84633.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504a010]
>[ 84633.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504a010] width 1920 pitch 7680 (/4 1920)
>[ 84633.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb65b0]
>[ 84633.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb65b0] width 1920 pitch 7680 (/4 1920)
>[ 84633.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 84633.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 84633.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07060]
>[ 84633.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07060] width 1920 pitch 7680 (/4 1920)
>[ 84633.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde2e0]
>[ 84633.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde2e0] width 1920 pitch 7680 (/4 1920)
>[ 84633.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61030]
>[ 84633.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61030] width 1920 pitch 7680 (/4 1920)
>[ 84633.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25290]
>[ 84633.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25290] width 1920 pitch 7680 (/4 1920)
>[ 84633.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 84633.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 84633.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86bb0]
>[ 84633.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86bb0] width 1920 pitch 7680 (/4 1920)
>[ 84633.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13670]
>[ 84633.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13670] width 1920 pitch 7680 (/4 1920)
>[ 84633.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 84633.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 84633.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95cb0]
>[ 84633.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95cb0] width 1920 pitch 7680 (/4 1920)
>[ 84633.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3150]
>[ 84633.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3150] width 1920 pitch 7680 (/4 1920)
>[ 84633.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[ 84633.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1920 pitch 7680 (/4 1920)
>[ 84633.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110c00]
>[ 84633.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110c00] width 1920 pitch 7680 (/4 1920)
>[ 84633.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[ 84633.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1920 pitch 7680 (/4 1920)
>[ 84633.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[ 84633.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[ 84633.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f530]
>[ 84633.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f530] width 1920 pitch 7680 (/4 1920)
>[ 84633.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 84633.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 84633.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 84633.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 84633.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6500]
>[ 84633.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6500] width 1920 pitch 7680 (/4 1920)
>[ 84633.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5060]
>[ 84633.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5060] width 1920 pitch 7680 (/4 1920)
>[ 84633.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 84633.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 84633.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd490]
>[ 84633.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd490] width 1920 pitch 7680 (/4 1920)
>[ 84634.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 84634.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 84634.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98f20]
>[ 84634.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98f20] width 1920 pitch 7680 (/4 1920)
>[ 84634.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84634.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84634.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 84634.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 84634.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 84634.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 84634.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504a010]
>[ 84634.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504a010] width 1920 pitch 7680 (/4 1920)
>[ 84634.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb65b0]
>[ 84634.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb65b0] width 1920 pitch 7680 (/4 1920)
>[ 84634.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 84634.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 84634.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07060]
>[ 84634.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07060] width 1920 pitch 7680 (/4 1920)
>[ 84634.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde2e0]
>[ 84634.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde2e0] width 1920 pitch 7680 (/4 1920)
>[ 84634.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f61030]
>[ 84634.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f61030] width 1920 pitch 7680 (/4 1920)
>[ 84634.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25290]
>[ 84634.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25290] width 1920 pitch 7680 (/4 1920)
>[ 84634.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 84634.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 84634.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e86bb0]
>[ 84634.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e86bb0] width 1920 pitch 7680 (/4 1920)
>[ 84634.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87c10]
>[ 84634.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87c10] width 1920 pitch 7680 (/4 1920)
>[ 84634.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13670]
>[ 84634.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13670] width 1920 pitch 7680 (/4 1920)
>[ 84634.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e68c90]
>[ 84634.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e68c90] width 1920 pitch 7680 (/4 1920)
>[ 84634.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3150]
>[ 84634.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3150] width 1920 pitch 7680 (/4 1920)
>[ 84634.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[ 84634.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1920 pitch 7680 (/4 1920)
>[ 84634.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110c00]
>[ 84634.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110c00] width 1920 pitch 7680 (/4 1920)
>[ 84634.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[ 84634.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1920 pitch 7680 (/4 1920)
>[ 84634.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[ 84634.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[ 84634.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f530]
>[ 84634.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f530] width 1920 pitch 7680 (/4 1920)
>[ 84634.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 84634.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 84634.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 84634.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 84634.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6500]
>[ 84634.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6500] width 1920 pitch 7680 (/4 1920)
>[ 84634.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5060]
>[ 84634.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5060] width 1920 pitch 7680 (/4 1920)
>[ 84634.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 84634.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 84634.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd490]
>[ 84634.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd490] width 1920 pitch 7680 (/4 1920)
>[ 84634.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 84634.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 84634.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac330]
>[ 84634.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac330] width 1920 pitch 7680 (/4 1920)
>[ 84635.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 84635.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 84635.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec54d0]
>[ 84635.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec54d0] width 1920 pitch 7680 (/4 1920)
>[ 84635.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 84635.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 84635.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b170]
>[ 84635.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b170] width 1920 pitch 7680 (/4 1920)
>[ 84635.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 84635.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 84635.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f231a0]
>[ 84635.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f231a0] width 1920 pitch 7680 (/4 1920)
>[ 84635.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5109b40]
>[ 84635.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5109b40] width 1920 pitch 7680 (/4 1920)
>[ 84635.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9490]
>[ 84635.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9490] width 1920 pitch 7680 (/4 1920)
>[ 84635.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[ 84635.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1920 pitch 7680 (/4 1920)
>[ 84635.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073a00]
>[ 84635.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073a00] width 1920 pitch 7680 (/4 1920)
>[ 84635.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd360]
>[ 84635.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd360] width 1920 pitch 7680 (/4 1920)
>[ 84635.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[ 84635.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[ 84635.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5c50]
>[ 84635.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5c50] width 1920 pitch 7680 (/4 1920)
>[ 84635.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 84635.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 84635.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea3150]
>[ 84635.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea3150] width 1920 pitch 7680 (/4 1920)
>[ 84635.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[ 84635.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1920 pitch 7680 (/4 1920)
>[ 84635.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ac00]
>[ 84635.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ac00] width 1920 pitch 7680 (/4 1920)
>[ 84635.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5110c00]
>[ 84635.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5110c00] width 1920 pitch 7680 (/4 1920)
>[ 84635.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[ 84635.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1920 pitch 7680 (/4 1920)
>[ 84635.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[ 84635.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1920 pitch 7680 (/4 1920)
>[ 84635.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f530]
>[ 84635.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f530] width 1920 pitch 7680 (/4 1920)
>[ 84635.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 84635.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 84635.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[ 84635.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[ 84635.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6500]
>[ 84635.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6500] width 1920 pitch 7680 (/4 1920)
>[ 84635.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa5060]
>[ 84635.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa5060] width 1920 pitch 7680 (/4 1920)
>[ 84635.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 84635.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 84635.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd490]
>[ 84635.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd490] width 1920 pitch 7680 (/4 1920)
>[ 84687.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84687.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84687.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84687.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84688.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84688.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84688.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84688.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84689.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84689.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 84689.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84689.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84689.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 84689.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 84689.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5c50]
>[ 84689.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5c50] width 1920 pitch 7680 (/4 1920)
>[ 85006.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5079ab0]
>[ 85006.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5079ab0] width 1920 pitch 7680 (/4 1920)
>[ 85006.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 85006.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 85007.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85007.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85007.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 85007.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 85007.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85007.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85007.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85007.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85007.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85007.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85007.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 85007.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 85007.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85007.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85007.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85007.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85007.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85007.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85007.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85007.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85007.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85007.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85007.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85007.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85008.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85008.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85008.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85008.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85008.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 85008.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 85008.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85008.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85038.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2a390c0]
>[ 85038.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2a390c0] width 1920 pitch 7680 (/4 1920)
>[ 85038.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85038.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85038.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 85038.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 85038.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85038.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85038.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85038.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85038.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85038.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85038.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85038.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85038.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85038.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85038.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85038.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85038.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85038.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85038.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85038.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85038.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85038.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85039.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85039.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85039.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85039.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85039.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85039.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85039.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85039.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85039.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85039.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85039.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85039.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85039.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85039.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85039.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85039.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85039.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85039.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85039.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 85039.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 85084.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85084.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85084.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85084.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85084.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85084.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85084.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85084.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85085.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85085.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85085.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85085.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85085.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85085.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85085.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85085.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85085.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85085.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85085.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85085.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85085.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85085.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85085.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85085.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85085.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85085.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85085.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85085.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85085.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85085.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85085.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85085.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85085.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85085.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85085.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85085.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85085.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85085.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85085.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85085.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85085.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85085.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85085.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85085.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85085.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85085.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85085.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85085.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85085.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85085.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85085.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85085.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85085.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85085.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85085.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85085.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85085.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85085.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85085.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85085.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85085.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85085.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85085.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85085.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85085.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85085.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85085.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85085.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85085.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85085.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85085.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85085.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85086.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85086.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85086.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85086.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85086.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85086.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85086.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85086.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85086.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85086.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85086.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85086.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85086.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85086.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85086.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85086.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85086.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85086.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85086.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85086.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85086.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85086.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85086.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85086.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85086.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85086.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85086.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85086.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85086.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85086.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85086.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85086.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85086.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85086.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85086.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85086.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85086.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85086.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85086.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85086.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85086.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85086.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85086.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85086.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85086.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85086.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85086.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85086.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85086.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85086.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85086.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85086.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85086.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85086.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85086.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85086.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85086.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85086.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85086.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85086.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85086.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85086.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85086.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85086.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85087.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85087.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85087.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85087.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85087.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85087.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85087.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85087.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85087.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85087.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85087.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85087.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85087.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85087.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85087.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85087.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85087.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85087.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85087.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85087.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85087.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85087.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85087.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85087.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85087.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85087.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85087.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85087.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85087.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85087.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85087.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85087.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85087.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85087.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85087.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85087.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85087.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85087.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85087.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85087.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85087.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85087.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85087.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85087.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85087.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85087.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85087.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85087.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85087.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85087.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85087.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85087.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85087.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097810]
>[ 85087.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097810] width 1920 pitch 7680 (/4 1920)
>[ 85087.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85087.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85087.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85087.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85087.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85087.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85087.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85087.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85087.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85087.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85088.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85088.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85088.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85088.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85088.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85088.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85088.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85088.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85088.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85088.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85088.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85088.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85088.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85088.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85088.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 85088.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 85088.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[ 85088.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1920 pitch 7680 (/4 1920)
>[ 85088.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85088.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85088.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85088.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85088.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85089.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85101.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 85101.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 85101.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85101.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85101.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85101.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85101.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c148d0]
>[ 85101.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c148d0] width 1920 pitch 7680 (/4 1920)
>[ 85101.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85101.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85112.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85112.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85112.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85112.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85112.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85112.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85112.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85112.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85112.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85112.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85112.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85112.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85112.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85112.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85112.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85112.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85112.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85112.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85112.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85113.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85113.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85113.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85113.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85113.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85113.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85113.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85113.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85113.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85113.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85113.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85113.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85113.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85113.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85113.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85113.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85113.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85113.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85113.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85113.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85113.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85113.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85113.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85113.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85113.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85113.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85113.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85113.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85113.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85113.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85113.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85113.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85113.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85113.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85113.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85113.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85113.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85113.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85113.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85113.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85113.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85113.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85113.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85113.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85113.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85113.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85113.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85113.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85113.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85113.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85113.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85113.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85113.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85113.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85113.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85113.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85113.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85113.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85113.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85113.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85113.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85113.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85113.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85113.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85114.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85114.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85114.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85114.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85114.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85114.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85114.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85114.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85114.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85114.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85114.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85114.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85114.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85114.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85114.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85114.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85114.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85114.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85114.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85114.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85114.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85114.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85114.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85114.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85114.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85114.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85114.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85114.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85114.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85114.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85114.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85114.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85114.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85114.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85114.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85114.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85114.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85114.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85114.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85114.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85114.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85114.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85114.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85114.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85114.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85114.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85114.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85114.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85114.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85114.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85114.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85114.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85114.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85114.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85114.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85114.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85114.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85114.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85114.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85114.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85114.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85114.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85114.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85114.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85115.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85115.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85115.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85115.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85115.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85115.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85115.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85115.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85115.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85115.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85115.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85115.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85115.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85115.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85115.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85115.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85115.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85115.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85115.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85115.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85115.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85115.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85115.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85115.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85115.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85115.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85115.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85115.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85115.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85115.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85115.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85115.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85115.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85115.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85115.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85115.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85115.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85115.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85115.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85115.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85115.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85115.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85115.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85115.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85115.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85115.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85115.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85115.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85115.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85115.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85115.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85115.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85115.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85115.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85115.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85115.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85115.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85115.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85115.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85115.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85115.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85115.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85115.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85115.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85116.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85116.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85116.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85116.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85116.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85116.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85116.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85116.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85116.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85116.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85116.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85116.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85116.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85116.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85116.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85116.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85116.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85116.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85116.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85116.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85116.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85116.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85116.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85116.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85116.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85116.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85116.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85116.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85116.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85116.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85116.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85116.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85116.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85116.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85116.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85116.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85116.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85116.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85116.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85116.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85116.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85116.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85116.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85116.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85116.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85116.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85116.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85116.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85116.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85116.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85116.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85116.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85116.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85116.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85116.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85116.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85116.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85116.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85116.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85116.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85116.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85116.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85116.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85116.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85117.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85117.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85117.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85117.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85117.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85117.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85117.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85117.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85117.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85117.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85117.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85117.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85117.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85117.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85117.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85117.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85117.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85117.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85117.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85117.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85117.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85117.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85117.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85117.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85117.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85117.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85117.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85117.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85117.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85117.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85117.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85117.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85117.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85117.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85117.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85117.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85117.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85117.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85117.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85117.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85117.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85117.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85117.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85117.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85117.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85117.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85117.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85117.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85117.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85117.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85117.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85117.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85117.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85117.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85117.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85117.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85117.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85117.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85117.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85117.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85117.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85117.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85118.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85118.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85118.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85118.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85118.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85118.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85118.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85118.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85118.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85118.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85118.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85118.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85118.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85118.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85118.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85118.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85118.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85118.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[ 85118.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1920 pitch 7680 (/4 1920)
>[ 85118.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85118.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85118.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85118.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85118.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[ 85118.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[ 85118.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85118.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85118.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85118.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85118.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a38a20]
>[ 85118.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a38a20] width 1920 pitch 7680 (/4 1920)
>[ 85118.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85118.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85118.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85118.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85118.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85118.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85118.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85118.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85118.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85118.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85118.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85118.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85118.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85118.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85118.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85118.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85118.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85118.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85118.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85118.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85118.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85118.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85118.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85118.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85118.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85118.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85118.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 85118.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 85118.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85118.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85118.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85119.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85119.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d5390]
>[ 85119.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d5390] width 1920 pitch 7680 (/4 1920)
>[ 85119.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85119.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85119.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85119.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85119.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85119.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85119.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 85119.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 85119.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85119.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85119.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 85119.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 85119.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85119.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85119.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 85119.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 85119.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85119.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85122.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85122.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85122.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85122.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85122.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85122.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85122.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 85122.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 85198.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85198.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85198.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85198.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85199.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85199.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85199.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85199.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85199.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052860]
>[ 85199.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052860] width 1920 pitch 7680 (/4 1920)
>[ 85199.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85199.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85199.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85199.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85199.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85199.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85199.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85199.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85199.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85199.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85199.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85199.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85199.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85199.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85199.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85199.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85199.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85199.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85199.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85199.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85199.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85199.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85199.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 85199.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 85199.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85199.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85199.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85199.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85199.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6c30]
>[ 85199.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6c30] width 1920 pitch 7680 (/4 1920)
>[ 85199.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85199.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85199.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85199.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85199.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aa430]
>[ 85199.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aa430] width 1920 pitch 7680 (/4 1920)
>[ 85199.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f06dd0]
>[ 85199.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f06dd0] width 1920 pitch 7680 (/4 1920)
>[ 85199.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7adc0]
>[ 85199.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7adc0] width 1920 pitch 7680 (/4 1920)
>[ 85199.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc110]
>[ 85199.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc110] width 1920 pitch 7680 (/4 1920)
>[ 85199.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[ 85199.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[ 85199.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d52c90]
>[ 85199.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d52c90] width 1920 pitch 7680 (/4 1920)
>[ 85199.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85199.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85200.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[ 85200.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[ 85200.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85200.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85200.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85200.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85200.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85200.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85200.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85200.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85200.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efab00]
>[ 85200.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efab00] width 1920 pitch 7680 (/4 1920)
>[ 85200.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85200.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85200.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5f600]
>[ 85200.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5f600] width 1920 pitch 7680 (/4 1920)
>[ 85200.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85200.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85200.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d160]
>[ 85200.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d160] width 1920 pitch 7680 (/4 1920)
>[ 85232.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85232.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85232.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85232.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85233.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85233.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85233.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85233.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85233.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85233.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85233.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85233.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85233.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85233.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85233.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85233.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85233.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85233.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85319.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ec0]
>[ 85319.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ec0] width 1920 pitch 7680 (/4 1920)
>[ 85319.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85319.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85319.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85319.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85319.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85319.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85319.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85319.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85352.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39549c0]
>[ 85352.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39549c0] width 1920 pitch 7680 (/4 1920)
>[ 85352.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85352.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85353.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85353.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85353.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85353.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85353.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85353.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85353.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85353.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85353.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85353.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85353.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85353.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85353.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85353.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85353.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85353.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85353.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5db00]
>[ 85353.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5db00] width 1920 pitch 7680 (/4 1920)
>[ 85353.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39549c0]
>[ 85353.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39549c0] width 1920 pitch 7680 (/4 1920)
>[ 85353.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85353.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85353.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85353.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85353.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85353.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85353.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85353.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85353.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 85353.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 85353.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85353.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85353.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85353.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85353.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 85353.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 85353.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85353.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85353.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b23380]
>[ 85353.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b23380] width 1920 pitch 7680 (/4 1920)
>[ 85353.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39549c0]
>[ 85353.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39549c0] width 1920 pitch 7680 (/4 1920)
>[ 85353.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 85353.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 85353.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a950]
>[ 85353.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a950] width 1920 pitch 7680 (/4 1920)
>[ 85353.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 85353.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 85353.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85353.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85353.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85353.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85353.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85353.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85354.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85354.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85354.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85354.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85354.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85354.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85354.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85354.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85354.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85354.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85354.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 85354.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 85354.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5db00]
>[ 85354.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5db00] width 1920 pitch 7680 (/4 1920)
>[ 85354.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85354.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85354.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85354.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85354.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85354.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85354.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85354.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85354.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85354.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85354.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2620]
>[ 85354.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2620] width 1920 pitch 7680 (/4 1920)
>[ 85354.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85354.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85354.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85354.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85354.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85354.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85354.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85354.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85354.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 85354.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 85354.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5db00]
>[ 85354.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5db00] width 1920 pitch 7680 (/4 1920)
>[ 85354.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85354.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85354.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85354.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85354.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85354.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85354.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85354.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85354.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85354.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85354.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85354.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85354.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85354.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85354.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 85354.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 85354.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97a40]
>[ 85354.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97a40] width 1920 pitch 7680 (/4 1920)
>[ 85354.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 85354.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 85354.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5db00]
>[ 85354.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5db00] width 1920 pitch 7680 (/4 1920)
>[ 85354.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d9b0]
>[ 85354.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d9b0] width 1920 pitch 7680 (/4 1920)
>[ 85354.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85354.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85355.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 85355.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 85355.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85355.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85355.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85355.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85355.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b262a0]
>[ 85355.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b262a0] width 1920 pitch 7680 (/4 1920)
>[ 85355.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85355.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85355.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85355.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85355.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad1f0]
>[ 85355.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad1f0] width 1920 pitch 7680 (/4 1920)
>[ 85356.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef5580]
>[ 85356.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef5580] width 1920 pitch 7680 (/4 1920)
>[ 85356.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e329e0]
>[ 85356.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e329e0] width 1920 pitch 7680 (/4 1920)
>[ 85356.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 85356.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 85356.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[ 85356.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1920 pitch 7680 (/4 1920)
>[ 85356.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f77620]
>[ 85356.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f77620] width 1920 pitch 7680 (/4 1920)
>[ 85357.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b270]
>[ 85357.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b270] width 1920 pitch 7680 (/4 1920)
>[ 85357.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 85357.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 85357.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[ 85357.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[ 85357.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 85357.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 85357.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc72a0]
>[ 85357.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc72a0] width 1920 pitch 7680 (/4 1920)
>[ 85357.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059740]
>[ 85357.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059740] width 1920 pitch 7680 (/4 1920)
>[ 85357.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[ 85357.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1920 pitch 7680 (/4 1920)
>[ 85357.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 85357.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 85357.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 85357.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 85358.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4031cd0]
>[ 85358.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4031cd0] width 1920 pitch 7680 (/4 1920)
>[ 85358.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58be0]
>[ 85358.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58be0] width 1920 pitch 7680 (/4 1920)
>[ 85358.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebddf0]
>[ 85358.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebddf0] width 1920 pitch 7680 (/4 1920)
>[ 85358.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5a100]
>[ 85358.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5a100] width 1920 pitch 7680 (/4 1920)
>[ 85358.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de29e0]
>[ 85358.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de29e0] width 1920 pitch 7680 (/4 1920)
>[ 85358.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506eec0]
>[ 85358.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506eec0] width 1920 pitch 7680 (/4 1920)
>[ 85358.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb2d0]
>[ 85358.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb2d0] width 1920 pitch 7680 (/4 1920)
>[ 85358.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c561b0]
>[ 85358.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c561b0] width 1920 pitch 7680 (/4 1920)
>[ 85358.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30a30]
>[ 85358.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30a30] width 1920 pitch 7680 (/4 1920)
>[ 85358.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46050]
>[ 85358.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46050] width 1920 pitch 7680 (/4 1920)
>[ 85358.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2868c10]
>[ 85358.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2868c10] width 1920 pitch 7680 (/4 1920)
>[ 85358.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3600]
>[ 85358.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3600] width 1920 pitch 7680 (/4 1920)
>[ 85358.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506eec0]
>[ 85358.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506eec0] width 1920 pitch 7680 (/4 1920)
>[ 85358.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51074b0]
>[ 85358.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51074b0] width 1920 pitch 7680 (/4 1920)
>[ 85359.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d400]
>[ 85359.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d400] width 1920 pitch 7680 (/4 1920)
>[ 85359.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0cae0]
>[ 85359.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0cae0] width 1920 pitch 7680 (/4 1920)
>[ 85359.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30a30]
>[ 85359.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30a30] width 1920 pitch 7680 (/4 1920)
>[ 85359.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58be0]
>[ 85359.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58be0] width 1920 pitch 7680 (/4 1920)
>[ 85359.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059840]
>[ 85359.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059840] width 1920 pitch 7680 (/4 1920)
>[ 85359.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a3f0]
>[ 85359.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a3f0] width 1920 pitch 7680 (/4 1920)
>[ 85359.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f22ad0]
>[ 85359.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f22ad0] width 1920 pitch 7680 (/4 1920)
>[ 85412.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ec0]
>[ 85412.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ec0] width 1920 pitch 7680 (/4 1920)
>[ 85442.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bf70]
>[ 85442.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bf70] width 1920 pitch 7680 (/4 1920)
>[ 85442.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85442.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85443.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d930]
>[ 85443.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d930] width 1920 pitch 7680 (/4 1920)
>[ 85443.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 85443.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 85443.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 85443.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 85443.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 85443.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 85443.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75a60]
>[ 85443.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75a60] width 1920 pitch 7680 (/4 1920)
>[ 85443.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ec0]
>[ 85443.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ec0] width 1920 pitch 7680 (/4 1920)
>[ 85443.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 85443.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 85443.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[ 85443.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[ 85495.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 85495.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 85495.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12b90]
>[ 85495.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12b90] width 1920 pitch 7680 (/4 1920)
>[ 85496.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f114e0]
>[ 85496.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f114e0] width 1920 pitch 7680 (/4 1920)
>[ 85496.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 85496.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 85496.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f114e0]
>[ 85496.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f114e0] width 1920 pitch 7680 (/4 1920)
>[ 85496.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 85496.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 85496.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f114e0]
>[ 85496.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f114e0] width 1920 pitch 7680 (/4 1920)
>[ 85652.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb3910]
>[ 85652.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb3910] width 1920 pitch 7680 (/4 1920)
>[ 85684.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85684.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85684.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85684.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85685.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 85685.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 85685.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f268c0]
>[ 85685.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f268c0] width 1920 pitch 7680 (/4 1920)
>[ 85685.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40457f0]
>[ 85685.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40457f0] width 1920 pitch 7680 (/4 1920)
>[ 85685.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 85685.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 85685.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 85685.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 85686.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 85686.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 85686.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 85686.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 85686.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 85686.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 85686.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 85686.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 85686.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 85686.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 85686.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 85686.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 85686.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 85686.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 85686.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 85686.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 85686.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 85686.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 85686.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 85686.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 85686.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 85686.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 85686.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 85686.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 85686.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 85686.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 85686.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 85686.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 85686.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 85686.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 85686.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5083fc0]
>[ 85686.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5083fc0] width 1920 pitch 7680 (/4 1920)
>[ 85686.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 85686.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 85686.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 85686.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 85686.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 85686.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 85686.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 85686.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 85686.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 85686.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 85686.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 85686.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 85767.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9f20]
>[ 85767.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9f20] width 1920 pitch 7680 (/4 1920)
>[ 85785.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc9190]
>[ 85785.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc9190] width 1920 pitch 7680 (/4 1920)
>[ 85801.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f43cb0]
>[ 85801.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f43cb0] width 1920 pitch 7680 (/4 1920)
>[ 85801.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb1cd0]
>[ 85801.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb1cd0] width 1920 pitch 7680 (/4 1920)
>[ 85801.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 85801.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 85801.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f560]
>[ 85801.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f560] width 1920 pitch 7680 (/4 1920)
>[ 86100.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e70]
>[ 86100.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e70] width 1920 pitch 7680 (/4 1920)
>[ 86101.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd930]
>[ 86101.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd930] width 1920 pitch 7680 (/4 1920)
>[ 86101.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 86101.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 86101.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5090720]
>[ 86101.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5090720] width 1920 pitch 7680 (/4 1920)
>[ 86101.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810f70]
>[ 86102.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810f70] width 1920 pitch 7680 (/4 1920)
>[ 86102.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 86102.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 86107.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86107.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86107.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 86107.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 86107.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86107.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5083fc0]
>[ 86107.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5083fc0] width 1920 pitch 7680 (/4 1920)
>[ 86107.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 86107.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 86107.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86107.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86107.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86107.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86107.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 86107.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 86107.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86107.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 86107.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 86107.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86107.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 86107.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 86107.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86107.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86200.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86201.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86201.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40457f0]
>[ 86201.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40457f0] width 1920 pitch 7680 (/4 1920)
>[ 86201.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86201.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86202.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86202.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86202.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86202.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86202.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86202.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86202.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86202.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86203.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86203.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86203.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86203.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86203.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86203.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86203.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86203.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86203.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86203.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86203.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86203.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86203.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30ff0]
>[ 86203.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30ff0] width 1920 pitch 7680 (/4 1920)
>[ 86203.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86203.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86214.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86214.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86214.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86214.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86214.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86215.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09120]
>[ 86215.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09120] width 1920 pitch 7680 (/4 1920)
>[ 86302.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e6d0]
>[ 86302.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e6d0] width 1920 pitch 7680 (/4 1920)
>[ 86302.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 86302.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 86303.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 86303.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 86303.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e6d0]
>[ 86303.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e6d0] width 1920 pitch 7680 (/4 1920)
>[ 86303.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86303.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86303.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86303.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86304.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022d20]
>[ 86304.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022d20] width 1920 pitch 7680 (/4 1920)
>[ 86304.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86304.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86304.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86304.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86304.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86304.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86304.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022d20]
>[ 86304.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022d20] width 1920 pitch 7680 (/4 1920)
>[ 86304.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86304.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86304.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86304.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86304.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86304.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86304.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86304.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86304.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022d20]
>[ 86304.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022d20] width 1920 pitch 7680 (/4 1920)
>[ 86304.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86304.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86304.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86304.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86304.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86304.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86304.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022d20]
>[ 86304.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022d20] width 1920 pitch 7680 (/4 1920)
>[ 86304.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86304.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86304.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86304.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86304.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86304.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86304.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022d20]
>[ 86304.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022d20] width 1920 pitch 7680 (/4 1920)
>[ 86304.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86304.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86317.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86317.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86318.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86318.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86318.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86318.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86318.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86318.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86318.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 86318.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 86318.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03f50]
>[ 86318.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03f50] width 1920 pitch 7680 (/4 1920)
>[ 86318.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[ 86318.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[ 86318.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c69980]
>[ 86318.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c69980] width 1920 pitch 7680 (/4 1920)
>[ 86319.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86319.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf320]
>[ 86319.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf320] width 1920 pitch 7680 (/4 1920)
>[ 86319.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86319.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf320]
>[ 86319.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf320] width 1920 pitch 7680 (/4 1920)
>[ 86319.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86319.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf320]
>[ 86319.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf320] width 1920 pitch 7680 (/4 1920)
>[ 86319.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86319.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf320]
>[ 86319.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf320] width 1920 pitch 7680 (/4 1920)
>[ 86319.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86319.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbf320]
>[ 86319.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbf320] width 1920 pitch 7680 (/4 1920)
>[ 86319.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86319.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86701.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060940]
>[ 86701.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060940] width 1920 pitch 7680 (/4 1920)
>[ 86701.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b3a0]
>[ 86701.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b3a0] width 1920 pitch 7680 (/4 1920)
>[ 86702.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 86702.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 86702.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 86702.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 86702.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 86702.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 86702.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcfa00]
>[ 86702.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcfa00] width 1920 pitch 7680 (/4 1920)
>[ 86702.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 86702.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 86702.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 86702.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 86702.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 86702.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 86702.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2853180]
>[ 86702.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2853180] width 1920 pitch 7680 (/4 1920)
>[ 86702.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060940]
>[ 86702.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060940] width 1920 pitch 7680 (/4 1920)
>[ 86702.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[ 86702.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[ 86702.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86702.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86702.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 86702.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 86703.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055b90]
>[ 86703.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055b90] width 1920 pitch 7680 (/4 1920)
>[ 86703.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86703.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86703.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 86703.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 86703.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 86703.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 86703.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 86703.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 86703.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 86703.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 86703.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 86703.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 86703.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 86703.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 86703.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 86703.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 86703.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 86703.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 86703.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86703.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86703.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 86703.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 86703.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5083fc0]
>[ 86703.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5083fc0] width 1920 pitch 7680 (/4 1920)
>[ 86703.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[ 86703.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1920 pitch 7680 (/4 1920)
>[ 86703.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 86703.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 86703.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 86703.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 86703.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2836660]
>[ 86703.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2836660] width 1920 pitch 7680 (/4 1920)
>[ 86703.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055b90]
>[ 86703.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055b90] width 1920 pitch 7680 (/4 1920)
>[ 86703.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 86703.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 86703.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 86703.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 86703.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86703.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86703.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 86703.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 86703.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 86703.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 86703.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 86703.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 86703.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 86703.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 86703.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 86703.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 86703.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 86703.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 86703.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86703.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86703.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 86703.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 86703.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 86703.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 86704.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 86704.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 86704.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2836660]
>[ 86704.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2836660] width 1920 pitch 7680 (/4 1920)
>[ 86704.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 86704.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 86704.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 86704.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 86704.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86704.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86704.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64a80]
>[ 86704.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64a80] width 1920 pitch 7680 (/4 1920)
>[ 86704.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86704.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86705.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86705.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86705.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86705.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86705.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86705.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86705.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86705.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86705.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86705.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86705.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86705.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86705.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86705.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86705.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86705.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86706.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86706.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86706.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86706.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86706.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86706.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86706.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86706.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86706.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5c40]
>[ 86706.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5c40] width 1920 pitch 7680 (/4 1920)
>[ 86706.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86706.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 86706.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 86706.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 86706.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 86706.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86706.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86707.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3fd0]
>[ 86707.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3fd0] width 1920 pitch 7680 (/4 1920)
>[ 86707.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055b90]
>[ 86707.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055b90] width 1920 pitch 7680 (/4 1920)
>[ 86707.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 86707.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 86707.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 86707.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 86707.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 86707.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 86707.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 86707.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 86707.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 86707.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 86707.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 86707.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 86707.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c56e0]
>[ 86707.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c56e0] width 1920 pitch 7680 (/4 1920)
>[ 86708.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc02c0]
>[ 86708.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc02c0] width 1920 pitch 7680 (/4 1920)
>[ 86708.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053530]
>[ 86708.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053530] width 1920 pitch 7680 (/4 1920)
>[ 86708.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 86708.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 86709.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c56e0]
>[ 86709.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c56e0] width 1920 pitch 7680 (/4 1920)
>[ 86709.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 86709.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 86709.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c930]
>[ 86709.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c930] width 1920 pitch 7680 (/4 1920)
>[ 86710.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0cec0]
>[ 86710.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0cec0] width 1920 pitch 7680 (/4 1920)
>[ 86710.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6d60]
>[ 86710.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6d60] width 1920 pitch 7680 (/4 1920)
>[ 86710.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a462e0]
>[ 86710.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a462e0] width 1920 pitch 7680 (/4 1920)
>[ 86711.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38e80]
>[ 86711.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38e80] width 1920 pitch 7680 (/4 1920)
>[ 86711.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[ 86711.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1920 pitch 7680 (/4 1920)
>[ 86711.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[ 86711.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1920 pitch 7680 (/4 1920)
>[ 86711.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[ 86711.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1920 pitch 7680 (/4 1920)
>[ 86711.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[ 86711.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1920 pitch 7680 (/4 1920)
>[ 86730.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86731.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86731.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86731.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86732.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86732.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86732.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04a50]
>[ 86732.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04a50] width 1920 pitch 7680 (/4 1920)
>[ 86732.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86732.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86732.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86732.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86732.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 86732.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 86732.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 86732.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 86732.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86732.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86732.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86732.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86732.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f338b0]
>[ 86732.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f338b0] width 1920 pitch 7680 (/4 1920)
>[ 86732.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86732.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86732.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828f00]
>[ 86732.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828f00] width 1920 pitch 7680 (/4 1920)
>[ 86732.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 86732.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 86732.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[ 86732.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[ 86732.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04a50]
>[ 86732.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04a50] width 1920 pitch 7680 (/4 1920)
>[ 86732.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86732.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86732.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86732.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86732.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828f00]
>[ 86732.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828f00] width 1920 pitch 7680 (/4 1920)
>[ 86732.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 86732.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 86732.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[ 86732.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[ 86732.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04a50]
>[ 86732.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04a50] width 1920 pitch 7680 (/4 1920)
>[ 86732.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f338b0]
>[ 86732.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f338b0] width 1920 pitch 7680 (/4 1920)
>[ 86732.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86732.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86732.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86732.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86732.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 86732.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 86732.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 86732.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 86732.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86732.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86732.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86732.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86732.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86732.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86733.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828f00]
>[ 86733.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828f00] width 1920 pitch 7680 (/4 1920)
>[ 86733.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 86733.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 86733.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 86733.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 86733.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86733.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86733.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86733.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86733.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86733.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86733.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2828f00]
>[ 86733.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2828f00] width 1920 pitch 7680 (/4 1920)
>[ 86733.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71a90]
>[ 86733.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71a90] width 1920 pitch 7680 (/4 1920)
>[ 86733.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f185e0]
>[ 86733.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f185e0] width 1920 pitch 7680 (/4 1920)
>[ 86733.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[ 86733.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[ 86733.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04a50]
>[ 86733.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04a50] width 1920 pitch 7680 (/4 1920)
>[ 86733.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f338b0]
>[ 86733.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f338b0] width 1920 pitch 7680 (/4 1920)
>[ 86733.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86733.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86733.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86733.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86733.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 86733.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 86733.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86733.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86733.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86733.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86733.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2ab0]
>[ 86733.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2ab0] width 1920 pitch 7680 (/4 1920)
>[ 86733.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddec0]
>[ 86733.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddec0] width 1920 pitch 7680 (/4 1920)
>[ 86733.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c97870]
>[ 86733.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c97870] width 1920 pitch 7680 (/4 1920)
>[ 86733.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec7c20]
>[ 86733.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec7c20] width 1920 pitch 7680 (/4 1920)
>[ 86733.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86733.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86733.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576b0]
>[ 86733.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576b0] width 1920 pitch 7680 (/4 1920)
>[ 86733.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f338b0]
>[ 86733.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f338b0] width 1920 pitch 7680 (/4 1920)
>[ 86763.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86763.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86763.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86763.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86763.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093fa0]
>[ 86763.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093fa0] width 1920 pitch 7680 (/4 1920)
>[ 86763.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4650]
>[ 86763.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4650] width 1920 pitch 7680 (/4 1920)
>[ 86763.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86763.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86763.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4650]
>[ 86763.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4650] width 1920 pitch 7680 (/4 1920)
>[ 86763.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4650]
>[ 86763.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4650] width 1920 pitch 7680 (/4 1920)
>[ 86763.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86764.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86764.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146790]
>[ 86764.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146790] width 1920 pitch 7680 (/4 1920)
>[ 86764.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24af0]
>[ 86764.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24af0] width 1920 pitch 7680 (/4 1920)
>[ 86764.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282ede0]
>[ 86764.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282ede0] width 1920 pitch 7680 (/4 1920)
>[ 86764.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093fa0]
>[ 86764.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093fa0] width 1920 pitch 7680 (/4 1920)
>[ 86764.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86764.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86764.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24af0]
>[ 86764.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24af0] width 1920 pitch 7680 (/4 1920)
>[ 86764.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4146790]
>[ 86764.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4146790] width 1920 pitch 7680 (/4 1920)
>[ 86764.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5660]
>[ 86764.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5660] width 1920 pitch 7680 (/4 1920)
>[ 86764.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca09e0]
>[ 86764.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca09e0] width 1920 pitch 7680 (/4 1920)
>[ 86764.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a06e40]
>[ 86764.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a06e40] width 1920 pitch 7680 (/4 1920)
>[ 86764.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f85720]
>[ 86764.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f85720] width 1920 pitch 7680 (/4 1920)
>[ 86764.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834af0]
>[ 86764.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834af0] width 1920 pitch 7680 (/4 1920)
>[ 86764.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5660]
>[ 86764.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5660] width 1920 pitch 7680 (/4 1920)
>[ 86764.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca09e0]
>[ 86764.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca09e0] width 1920 pitch 7680 (/4 1920)
>[ 86764.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a06e40]
>[ 86764.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a06e40] width 1920 pitch 7680 (/4 1920)
>[ 86771.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e710]
>[ 86771.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e710] width 1920 pitch 7680 (/4 1920)
>[ 86771.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86771.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86771.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86771.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86771.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86771.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86771.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86772.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86772.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86772.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86772.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86772.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86772.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86772.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86772.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea7f10]
>[ 86772.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea7f10] width 1920 pitch 7680 (/4 1920)
>[ 86772.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508fbc0]
>[ 86772.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508fbc0] width 1920 pitch 7680 (/4 1920)
>[ 86772.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86772.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86772.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86779.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20e90]
>[ 86779.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20e90] width 1920 pitch 7680 (/4 1920)
>[ 86779.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9d50]
>[ 86779.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9d50] width 1920 pitch 7680 (/4 1920)
>[ 86779.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9d50]
>[ 86779.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9d50] width 1920 pitch 7680 (/4 1920)
>[ 86909.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86909.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86909.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86909.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86910.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cc180]
>[ 86910.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cc180] width 1920 pitch 7680 (/4 1920)
>[ 86910.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9d50]
>[ 86910.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9d50] width 1920 pitch 7680 (/4 1920)
>[ 86910.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9cda0]
>[ 86910.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9cda0] width 1920 pitch 7680 (/4 1920)
>[ 86910.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac8d0]
>[ 86910.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac8d0] width 1920 pitch 7680 (/4 1920)
>[ 86910.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72830]
>[ 86910.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72830] width 1920 pitch 7680 (/4 1920)
>[ 86910.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275ee0]
>[ 86910.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275ee0] width 1920 pitch 7680 (/4 1920)
>[ 86910.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac8d0]
>[ 86910.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac8d0] width 1920 pitch 7680 (/4 1920)
>[ 86910.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72830]
>[ 86911.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72830] width 1920 pitch 7680 (/4 1920)
>[ 86911.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275ee0]
>[ 86911.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275ee0] width 1920 pitch 7680 (/4 1920)
>[ 86911.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fac8d0]
>[ 86911.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fac8d0] width 1920 pitch 7680 (/4 1920)
>[ 86911.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275ee0]
>[ 86911.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275ee0] width 1920 pitch 7680 (/4 1920)
>[ 86932.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275ee0]
>[ 86932.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275ee0] width 1920 pitch 7680 (/4 1920)
>[ 86932.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86932.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86932.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86932.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86932.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86932.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86932.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3cd0]
>[ 86932.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3cd0] width 1920 pitch 7680 (/4 1920)
>[ 86932.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86932.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86932.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86933.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86933.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3cd0]
>[ 86933.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3cd0] width 1920 pitch 7680 (/4 1920)
>[ 86933.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86933.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86933.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86933.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86933.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3cd0]
>[ 86933.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3cd0] width 1920 pitch 7680 (/4 1920)
>[ 86933.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86933.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86933.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86933.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86933.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3cd0]
>[ 86933.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3cd0] width 1920 pitch 7680 (/4 1920)
>[ 86933.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86933.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86933.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86933.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86933.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3cd0]
>[ 86933.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3cd0] width 1920 pitch 7680 (/4 1920)
>[ 86933.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86933.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86933.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86933.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86933.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86933.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86933.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048d70]
>[ 86933.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048d70] width 1920 pitch 7680 (/4 1920)
>[ 86933.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4e390]
>[ 86933.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4e390] width 1920 pitch 7680 (/4 1920)
>[ 86933.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86933.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86933.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 86933.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 86933.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 86933.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 86934.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86934.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86934.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[ 86934.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[ 86934.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86934.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86934.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 86934.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 86934.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072390]
>[ 86934.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072390] width 1920 pitch 7680 (/4 1920)
>[ 86934.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 86934.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 86934.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 86934.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 86934.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 86934.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 86934.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 86934.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 86934.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 86934.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 86934.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 86934.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 86934.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 86934.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 86934.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cb90]
>[ 86934.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cb90] width 1920 pitch 7680 (/4 1920)
>[ 86934.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 86934.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 86934.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 86934.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 86934.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823e30]
>[ 86934.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823e30] width 1920 pitch 7680 (/4 1920)
>[ 86934.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[ 86934.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1920 pitch 7680 (/4 1920)
>[ 86934.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 86934.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 86934.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 86934.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 86934.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 86934.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 86934.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 86934.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 86940.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86940.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86940.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3a0]
>[ 86940.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3a0] width 1920 pitch 7680 (/4 1920)
>[ 86940.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86940.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86941.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4ba0]
>[ 86941.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4ba0] width 1920 pitch 7680 (/4 1920)
>[ 86941.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e3c0]
>[ 86941.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e3c0] width 1920 pitch 7680 (/4 1920)
>[ 86944.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505ad60]
>[ 86944.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505ad60] width 1920 pitch 7680 (/4 1920)
>[ 86944.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86944.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86944.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ec0]
>[ 86944.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ec0] width 1920 pitch 7680 (/4 1920)
>[ 86944.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86944.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86944.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86944.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86945.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6570]
>[ 86945.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6570] width 1920 pitch 7680 (/4 1920)
>[ 86945.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86945.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86945.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4060d20]
>[ 86945.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4060d20] width 1920 pitch 7680 (/4 1920)
>[ 86945.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86945.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86945.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505ad60]
>[ 86945.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505ad60] width 1920 pitch 7680 (/4 1920)
>[ 86945.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb9ec0]
>[ 86945.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb9ec0] width 1920 pitch 7680 (/4 1920)
>[ 86945.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86945.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 86945.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4e390]
>[ 86945.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4e390] width 1920 pitch 7680 (/4 1920)
>[ 86945.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 86945.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 86945.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25af0]
>[ 86945.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25af0] width 1920 pitch 7680 (/4 1920)
>[ 86945.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86945.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86945.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048d70]
>[ 86945.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048d70] width 1920 pitch 7680 (/4 1920)
>[ 86945.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c810]
>[ 86945.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c810] width 1920 pitch 7680 (/4 1920)
>[ 86945.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a9f0]
>[ 86945.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a9f0] width 1920 pitch 7680 (/4 1920)
>[ 86945.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca6d0]
>[ 86945.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca6d0] width 1920 pitch 7680 (/4 1920)
>[ 86945.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6570]
>[ 86945.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6570] width 1920 pitch 7680 (/4 1920)
>[ 86945.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6e70]
>[ 86945.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6e70] width 1920 pitch 7680 (/4 1920)
>[ 86945.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e25af0]
>[ 86945.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e25af0] width 1920 pitch 7680 (/4 1920)
>[ 86945.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048df0]
>[ 86945.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048df0] width 1920 pitch 7680 (/4 1920)
>[ 86945.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbc280]
>[ 86945.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbc280] width 1920 pitch 7680 (/4 1920)
>[ 87011.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87011.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87011.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87011.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87011.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87011.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87011.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87011.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87011.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87011.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87011.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87011.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87011.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87011.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87011.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87011.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87012.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1e790]
>[ 87012.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1e790] width 1920 pitch 7680 (/4 1920)
>[ 87013.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 87013.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 87013.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87013.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87013.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87013.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87013.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8560]
>[ 87013.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8560] width 1920 pitch 7680 (/4 1920)
>[ 87013.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8560]
>[ 87013.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8560] width 1920 pitch 7680 (/4 1920)
>[ 87013.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87013.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87013.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87013.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87013.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8560]
>[ 87013.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8560] width 1920 pitch 7680 (/4 1920)
>[ 87013.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 87013.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 87013.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87013.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87013.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87013.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87013.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8560]
>[ 87013.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8560] width 1920 pitch 7680 (/4 1920)
>[ 87013.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 87013.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 87013.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87013.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87013.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87013.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87013.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8560]
>[ 87013.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8560] width 1920 pitch 7680 (/4 1920)
>[ 87013.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f18170]
>[ 87013.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f18170] width 1920 pitch 7680 (/4 1920)
>[ 87013.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5db30]
>[ 87013.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5db30] width 1920 pitch 7680 (/4 1920)
>[ 87013.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[ 87013.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1920 pitch 7680 (/4 1920)
>[ 87054.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87054.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87054.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87054.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87055.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87055.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87055.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87055.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87056.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1f0]
>[ 87056.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1f0] width 1920 pitch 7680 (/4 1920)
>[ 87056.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e622b0]
>[ 87056.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e622b0] width 1920 pitch 7680 (/4 1920)
>[ 87090.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ed10]
>[ 87090.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ed10] width 1920 pitch 7680 (/4 1920)
>[ 87090.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87090.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87091.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ed10]
>[ 87091.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ed10] width 1920 pitch 7680 (/4 1920)
>[ 87091.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87091.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 87091.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 87091.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ed10]
>[ 87091.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ed10] width 1920 pitch 7680 (/4 1920)
>[ 87091.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87091.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 87091.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 87091.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ed10]
>[ 87091.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ed10] width 1920 pitch 7680 (/4 1920)
>[ 87091.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87091.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 87091.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 87091.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275780]
>[ 87091.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275780] width 1920 pitch 7680 (/4 1920)
>[ 87091.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[ 87091.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[ 87091.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87091.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87091.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508ed10]
>[ 87091.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508ed10] width 1920 pitch 7680 (/4 1920)
>[ 87101.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87101.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87101.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87102.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87102.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87102.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87102.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87102.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87102.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87102.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87102.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87103.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87103.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87103.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87103.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87103.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87103.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87103.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87103.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87103.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87103.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87103.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87103.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87108.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426c550]
>[ 87108.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426c550] width 1920 pitch 7680 (/4 1920)
>[ 87108.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[ 87108.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1920 pitch 7680 (/4 1920)
>[ 87109.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02350]
>[ 87109.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02350] width 1920 pitch 7680 (/4 1920)
>[ 87109.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286fcf0]
>[ 87109.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286fcf0] width 1920 pitch 7680 (/4 1920)
>[ 87110.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f910]
>[ 87110.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f910] width 1920 pitch 7680 (/4 1920)
>[ 87110.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f910]
>[ 87110.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f910] width 1920 pitch 7680 (/4 1920)
>[ 87110.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f910]
>[ 87110.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f910] width 1920 pitch 7680 (/4 1920)
>[ 87110.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f910]
>[ 87110.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f910] width 1920 pitch 7680 (/4 1920)
>[ 87110.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87110.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87110.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87110.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87110.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87110.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87110.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87110.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87110.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87111.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87111.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87111.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87111.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87111.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87111.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87111.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87111.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fb30]
>[ 87111.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fb30] width 1920 pitch 7680 (/4 1920)
>[ 87111.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87111.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87111.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edf930]
>[ 87111.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edf930] width 1920 pitch 7680 (/4 1920)
>[ 87111.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1400]
>[ 87111.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1400] width 1920 pitch 7680 (/4 1920)
>[ 87111.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eddff0]
>[ 87111.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eddff0] width 1920 pitch 7680 (/4 1920)
>[ 87111.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1380]
>[ 87111.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1380] width 1920 pitch 7680 (/4 1920)
>[ 87111.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac13e0]
>[ 87111.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac13e0] width 1920 pitch 7680 (/4 1920)
>[ 87111.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1380]
>[ 87111.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1380] width 1920 pitch 7680 (/4 1920)
>[ 87111.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac13e0]
>[ 87111.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac13e0] width 1920 pitch 7680 (/4 1920)
>[ 87111.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1380]
>[ 87111.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1380] width 1920 pitch 7680 (/4 1920)
>[ 87111.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac13e0]
>[ 87111.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac13e0] width 1920 pitch 7680 (/4 1920)
>[ 87111.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1380]
>[ 87111.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1380] width 1920 pitch 7680 (/4 1920)
>[ 87111.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac13e0]
>[ 87111.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac13e0] width 1920 pitch 7680 (/4 1920)
>[ 87111.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac1380]
>[ 87111.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac1380] width 1920 pitch 7680 (/4 1920)
>[ 87111.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac13e0]
>[ 87111.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac13e0] width 1920 pitch 7680 (/4 1920)
>[ 87111.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2848370]
>[ 87111.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2848370] width 1920 pitch 7680 (/4 1920)
>[ 87111.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed17d0]
>[ 87111.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed17d0] width 1920 pitch 7680 (/4 1920)
>[ 87111.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f74b50]
>[ 87111.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f74b50] width 1920 pitch 7680 (/4 1920)
>[ 87111.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed17d0]
>[ 87112.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed17d0] width 1920 pitch 7680 (/4 1920)
>[ 87112.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509ad40]
>[ 87112.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509ad40] width 1920 pitch 7680 (/4 1920)
>[ 87112.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed17d0]
>[ 87112.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed17d0] width 1920 pitch 7680 (/4 1920)
>[ 87112.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db6cf0]
>[ 87112.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db6cf0] width 1920 pitch 7680 (/4 1920)
>[ 87112.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed17d0]
>[ 87112.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed17d0] width 1920 pitch 7680 (/4 1920)
>[ 87112.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051d10]
>[ 87112.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051d10] width 1920 pitch 7680 (/4 1920)
>[ 87113.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dce40]
>[ 87113.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dce40] width 1920 pitch 7680 (/4 1920)
>[ 87113.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dc680]
>[ 87113.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dc680] width 1920 pitch 7680 (/4 1920)
>[ 87114.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057210]
>[ 87114.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057210] width 1920 pitch 7680 (/4 1920)
>[ 87114.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057210]
>[ 87114.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057210] width 1920 pitch 7680 (/4 1920)
>[ 87114.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa880]
>[ 87114.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa880] width 1920 pitch 7680 (/4 1920)
>[ 87114.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057210]
>[ 87114.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057210] width 1920 pitch 7680 (/4 1920)
>[ 87114.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d090]
>[ 87114.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d090] width 1920 pitch 7680 (/4 1920)
>[ 87114.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d030]
>[ 87114.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d030] width 1920 pitch 7680 (/4 1920)
>[ 87114.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4057210]
>[ 87114.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4057210] width 1920 pitch 7680 (/4 1920)
>[ 87114.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5d030]
>[ 87114.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5d030] width 1920 pitch 7680 (/4 1920)
>[ 87114.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87114.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87114.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87114.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87114.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87114.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87114.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87114.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87114.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87114.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87114.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87114.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87114.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87114.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87114.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87114.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87114.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87114.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87114.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87114.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87114.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87114.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87114.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87115.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87115.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87115.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87115.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87115.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87115.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87115.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87115.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87115.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87115.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87115.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87115.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87115.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87115.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2ea90]
>[ 87115.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2ea90] width 1920 pitch 7680 (/4 1920)
>[ 87115.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6dd30]
>[ 87115.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6dd30] width 1920 pitch 7680 (/4 1920)
>[ 87115.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116300]
>[ 87115.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116300] width 1920 pitch 7680 (/4 1920)
>[ 87134.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a9d60]
>[ 87134.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a9d60] width 1920 pitch 7680 (/4 1920)
>[ 87134.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12120]
>[ 87134.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12120] width 1920 pitch 7680 (/4 1920)
>[ 87142.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d260]
>[ 87142.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d260] width 1920 pitch 7680 (/4 1920)
>[ 87144.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87144.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f320]
>[ 87146.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f320] width 1920 pitch 7680 (/4 1920)
>[ 87146.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87146.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87146.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87146.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87146.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87146.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87146.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87146.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87146.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87146.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87146.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87146.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87146.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87146.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87146.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87147.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87147.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87147.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4330]
>[ 87147.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4330] width 1920 pitch 7680 (/4 1920)
>[ 87153.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc2b90]
>[ 87154.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc2b90] width 1920 pitch 7680 (/4 1920)
>[ 87154.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130d90]
>[ 87154.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130d90] width 1920 pitch 7680 (/4 1920)
>[ 87154.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87154.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87154.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87154.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87154.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87154.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87155.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87155.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be39e0]
>[ 87155.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be39e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87155.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87155.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be39e0]
>[ 87155.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be39e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87155.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87155.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be39e0]
>[ 87155.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be39e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e81ad0]
>[ 87155.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e81ad0] width 1920 pitch 7680 (/4 1920)
>[ 87155.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be39e0]
>[ 87155.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be39e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a80]
>[ 87155.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a80] width 1920 pitch 7680 (/4 1920)
>[ 87155.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87155.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[ 87155.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[ 87155.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[ 87155.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[ 87155.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a80]
>[ 87155.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a80] width 1920 pitch 7680 (/4 1920)
>[ 87155.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec180]
>[ 87155.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec180] width 1920 pitch 7680 (/4 1920)
>[ 87166.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e284c0]
>[ 87166.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e284c0] width 1920 pitch 7680 (/4 1920)
>[ 87218.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d550]
>[ 87218.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d550] width 1920 pitch 7680 (/4 1920)
>[ 87218.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87218.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87218.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e180]
>[ 87218.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e180] width 1920 pitch 7680 (/4 1920)
>[ 87219.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be690]
>[ 87219.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be690] width 1920 pitch 7680 (/4 1920)
>[ 87219.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 87219.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 87219.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 87219.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 87219.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87219.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87220.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 87220.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 87220.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d080]
>[ 87220.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d080] width 1920 pitch 7680 (/4 1920)
>[ 87220.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5570]
>[ 87220.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5570] width 1920 pitch 7680 (/4 1920)
>[ 87220.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87220.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87220.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 87220.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 87220.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87220.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87220.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87220.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87220.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d080]
>[ 87220.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d080] width 1920 pitch 7680 (/4 1920)
>[ 87220.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5570]
>[ 87220.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5570] width 1920 pitch 7680 (/4 1920)
>[ 87220.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b36d40]
>[ 87220.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b36d40] width 1920 pitch 7680 (/4 1920)
>[ 87220.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 87220.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 87220.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87220.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87220.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87220.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87220.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d080]
>[ 87220.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d080] width 1920 pitch 7680 (/4 1920)
>[ 87220.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87220.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87220.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1df50]
>[ 87220.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1df50] width 1920 pitch 7680 (/4 1920)
>[ 87220.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3953c80]
>[ 87220.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3953c80] width 1920 pitch 7680 (/4 1920)
>[ 87220.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87220.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87232.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87232.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87232.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d080]
>[ 87232.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d080] width 1920 pitch 7680 (/4 1920)
>[ 87233.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 87233.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 87233.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87233.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87233.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87233.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87233.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87233.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d683e0]
>[ 87233.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d683e0] width 1920 pitch 7680 (/4 1920)
>[ 87233.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87233.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87233.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87233.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87247.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3ecd0]
>[ 87247.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3ecd0] width 1920 pitch 7680 (/4 1920)
>[ 87247.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b52a10]
>[ 87247.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b52a10] width 1920 pitch 7680 (/4 1920)
>[ 87248.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44900]
>[ 87248.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44900] width 1920 pitch 7680 (/4 1920)
>[ 87280.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb4f80]
>[ 87280.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb4f80] width 1920 pitch 7680 (/4 1920)
>[ 87280.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87280.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87281.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87281.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863d40]
>[ 87281.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863d40] width 1920 pitch 7680 (/4 1920)
>[ 87281.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea1560]
>[ 87281.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea1560] width 1920 pitch 7680 (/4 1920)
>[ 87281.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94ee0]
>[ 87281.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94ee0] width 1920 pitch 7680 (/4 1920)
>[ 87282.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87282.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87282.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87282.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87283.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87283.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87283.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87283.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87283.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87283.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87283.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87283.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87283.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87283.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87283.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87283.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87283.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87283.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87283.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87283.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87283.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87283.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87283.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87283.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87283.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87283.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87283.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87283.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87283.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87283.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87283.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87283.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87283.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87283.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87283.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87283.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87283.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87283.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87284.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87284.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87284.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87284.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87284.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87284.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87284.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87284.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87284.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87284.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87284.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87284.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87284.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87284.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87284.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87284.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87284.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87284.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87284.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87284.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87284.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87284.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87284.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87284.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87284.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87284.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87284.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87284.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e400]
>[ 87284.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e400] width 1920 pitch 7680 (/4 1920)
>[ 87284.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87284.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87284.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ced0]
>[ 87284.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ced0] width 1920 pitch 7680 (/4 1920)
>[ 87284.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87284.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87550.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131380]
>[ 87550.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131380] width 1920 pitch 7680 (/4 1920)
>[ 87550.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 87550.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 87551.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 87551.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 87551.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa1f40]
>[ 87551.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa1f40] width 1920 pitch 7680 (/4 1920)
>[ 87551.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87551.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87551.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 87551.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 87551.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e264f0]
>[ 87551.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e264f0] width 1920 pitch 7680 (/4 1920)
>[ 87551.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84340]
>[ 87551.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84340] width 1920 pitch 7680 (/4 1920)
>[ 87551.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87551.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87551.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87551.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87551.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 87551.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 87551.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa1f40]
>[ 87551.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa1f40] width 1920 pitch 7680 (/4 1920)
>[ 87551.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87551.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87551.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87551.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87551.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87551.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87551.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 87551.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 87551.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87551.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87551.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 87551.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 87551.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e264f0]
>[ 87551.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e264f0] width 1920 pitch 7680 (/4 1920)
>[ 87551.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84340]
>[ 87551.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84340] width 1920 pitch 7680 (/4 1920)
>[ 87551.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87551.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87551.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 87551.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 87552.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84340]
>[ 87552.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84340] width 1920 pitch 7680 (/4 1920)
>[ 87552.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 87552.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 87553.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[ 87553.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1920 pitch 7680 (/4 1920)
>[ 87553.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 87553.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 87553.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 87553.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 87553.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be3610]
>[ 87553.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be3610] width 1920 pitch 7680 (/4 1920)
>[ 87553.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 87553.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 87553.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87553.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87553.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87553.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87553.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 87553.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 87553.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[ 87553.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1920 pitch 7680 (/4 1920)
>[ 87553.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 87553.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 87553.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837490]
>[ 87553.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837490] width 1920 pitch 7680 (/4 1920)
>[ 87553.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 87553.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 87553.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87553.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87553.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 87553.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 87553.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f8c0]
>[ 87553.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f8c0] width 1920 pitch 7680 (/4 1920)
>[ 87553.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 87553.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 87553.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87553.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87553.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87553.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87553.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 87553.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 87553.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[ 87553.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1920 pitch 7680 (/4 1920)
>[ 87553.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 87553.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 87553.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 87553.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 87553.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be3610]
>[ 87553.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be3610] width 1920 pitch 7680 (/4 1920)
>[ 87553.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 87553.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 87553.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87553.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87554.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87554.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87554.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 87554.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 87554.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87554.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87554.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87554.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87554.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837490]
>[ 87554.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837490] width 1920 pitch 7680 (/4 1920)
>[ 87554.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 87554.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 87554.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87554.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87554.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 87554.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 87554.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f8c0]
>[ 87554.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f8c0] width 1920 pitch 7680 (/4 1920)
>[ 87554.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7db0]
>[ 87554.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7db0] width 1920 pitch 7680 (/4 1920)
>[ 87554.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87554.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87554.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87554.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87554.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 87554.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 87554.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[ 87554.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1920 pitch 7680 (/4 1920)
>[ 87554.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea70a0]
>[ 87554.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea70a0] width 1920 pitch 7680 (/4 1920)
>[ 87554.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3e80]
>[ 87554.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3e80] width 1920 pitch 7680 (/4 1920)
>[ 87554.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be3610]
>[ 87554.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be3610] width 1920 pitch 7680 (/4 1920)
>[ 87554.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87554.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87554.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831700]
>[ 87554.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831700] width 1920 pitch 7680 (/4 1920)
>[ 87568.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[ 87568.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1920 pitch 7680 (/4 1920)
>[ 87568.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87568.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87568.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87568.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87568.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87569.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5097be0]
>[ 87569.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5097be0] width 1920 pitch 7680 (/4 1920)
>[ 87569.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87569.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[ 87569.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[ 87594.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db6740]
>[ 87594.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db6740] width 1920 pitch 7680 (/4 1920)
>[ 87594.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37e40]
>[ 87594.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37e40] width 1920 pitch 7680 (/4 1920)
>[ 87594.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87594.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87595.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87595.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87595.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd1c40]
>[ 87595.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd1c40] width 1920 pitch 7680 (/4 1920)
>[ 87595.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6cd0]
>[ 87596.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6cd0] width 1920 pitch 7680 (/4 1920)
>[ 87596.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[ 87596.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[ 87596.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[ 87596.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[ 87596.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6cd0]
>[ 87596.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6cd0] width 1920 pitch 7680 (/4 1920)
>[ 87596.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[ 87596.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[ 87596.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b80a0]
>[ 87596.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b80a0] width 1920 pitch 7680 (/4 1920)
>[ 87596.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6cd0]
>[ 87596.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6cd0] width 1920 pitch 7680 (/4 1920)
>[ 87596.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6cd0]
>[ 87596.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6cd0] width 1920 pitch 7680 (/4 1920)
>[ 87596.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87596.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87596.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6cd0]
>[ 87596.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6cd0] width 1920 pitch 7680 (/4 1920)
>[ 87596.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87596.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87596.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efccc0]
>[ 87596.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efccc0] width 1920 pitch 7680 (/4 1920)
>[ 87596.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87596.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87596.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87596.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87596.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[ 87596.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1920 pitch 7680 (/4 1920)
>[ 87596.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87596.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87596.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87596.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87596.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e82ff0]
>[ 87597.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e82ff0] width 1920 pitch 7680 (/4 1920)
>[ 87597.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[ 87597.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[ 87646.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861730]
>[ 87646.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861730] width 1920 pitch 7680 (/4 1920)
>[ 87646.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[ 87646.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1920 pitch 7680 (/4 1920)
>[ 87647.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f20d0]
>[ 87647.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f20d0] width 1920 pitch 7680 (/4 1920)
>[ 87647.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e00]
>[ 87647.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e00] width 1920 pitch 7680 (/4 1920)
>[ 87647.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 87647.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 87647.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 87647.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 87648.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99700]
>[ 87648.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99700] width 1920 pitch 7680 (/4 1920)
>[ 87648.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87648.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87648.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87648.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87648.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 87648.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 87648.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 87648.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 87648.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87648.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87648.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 87648.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 87648.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 87648.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 87648.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e807a0]
>[ 87648.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e807a0] width 1920 pitch 7680 (/4 1920)
>[ 87648.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[ 87648.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1920 pitch 7680 (/4 1920)
>[ 87648.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87648.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87648.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87648.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87648.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f8c0]
>[ 87648.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f8c0] width 1920 pitch 7680 (/4 1920)
>[ 87648.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94d70]
>[ 87648.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94d70] width 1920 pitch 7680 (/4 1920)
>[ 87648.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cefe70]
>[ 87648.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cefe70] width 1920 pitch 7680 (/4 1920)
>[ 87648.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[ 87648.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1920 pitch 7680 (/4 1920)
>[ 87648.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 87648.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 87648.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5083fc0]
>[ 87648.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5083fc0] width 1920 pitch 7680 (/4 1920)
>[ 87648.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[ 87648.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1920 pitch 7680 (/4 1920)
>[ 87648.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87648.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87648.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99700]
>[ 87648.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99700] width 1920 pitch 7680 (/4 1920)
>[ 87648.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87648.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87648.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87648.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87648.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 87648.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 87649.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 87649.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 87649.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87649.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87649.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 87649.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 87649.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c000]
>[ 87649.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c000] width 1920 pitch 7680 (/4 1920)
>[ 87649.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2a9e0]
>[ 87649.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2a9e0] width 1920 pitch 7680 (/4 1920)
>[ 87649.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99700]
>[ 87649.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99700] width 1920 pitch 7680 (/4 1920)
>[ 87649.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87649.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87649.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 87649.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 87649.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[ 87649.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1920 pitch 7680 (/4 1920)
>[ 87649.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e490]
>[ 87649.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e490] width 1920 pitch 7680 (/4 1920)
>[ 87649.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87649.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87649.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 87649.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 87649.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f2620]
>[ 87649.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f2620] width 1920 pitch 7680 (/4 1920)
>[ 87848.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0610]
>[ 87848.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0610] width 1920 pitch 7680 (/4 1920)
>[ 87848.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87849.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87849.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87849.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87849.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0610]
>[ 87849.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0610] width 1920 pitch 7680 (/4 1920)
>[ 87849.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 87849.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 87849.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87849.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87849.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ea60]
>[ 87849.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ea60] width 1920 pitch 7680 (/4 1920)
>[ 87849.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 87849.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 87849.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87849.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87849.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ea60]
>[ 87849.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ea60] width 1920 pitch 7680 (/4 1920)
>[ 87849.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87849.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87849.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87849.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87849.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0610]
>[ 87849.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0610] width 1920 pitch 7680 (/4 1920)
>[ 87849.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87849.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87849.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ea60]
>[ 87849.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ea60] width 1920 pitch 7680 (/4 1920)
>[ 87849.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87850.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87850.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 87850.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 87850.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e00]
>[ 87850.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e00] width 1920 pitch 7680 (/4 1920)
>[ 87850.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87850.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87850.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87850.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87850.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 87850.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 87850.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e00]
>[ 87850.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e00] width 1920 pitch 7680 (/4 1920)
>[ 87850.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87850.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87850.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87850.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87850.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 87850.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 87850.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48e00]
>[ 87850.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48e00] width 1920 pitch 7680 (/4 1920)
>[ 87850.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87850.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87850.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87850.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87850.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 87850.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 87853.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4ea60]
>[ 87853.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4ea60] width 1920 pitch 7680 (/4 1920)
>[ 87853.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501a860]
>[ 87853.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501a860] width 1920 pitch 7680 (/4 1920)
>[ 87854.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baafd0]
>[ 87854.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baafd0] width 1920 pitch 7680 (/4 1920)
>[ 87854.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275860]
>[ 87854.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275860] width 1920 pitch 7680 (/4 1920)
>[ 87854.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4275860]
>[ 87854.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4275860] width 1920 pitch 7680 (/4 1920)
>[ 87855.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87855.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87855.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc99b0]
>[ 87855.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc99b0] width 1920 pitch 7680 (/4 1920)
>[ 87855.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87856.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87856.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87856.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 87856.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 87856.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc99b0]
>[ 87856.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc99b0] width 1920 pitch 7680 (/4 1920)
>[ 87856.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87856.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87856.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87856.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87856.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87856.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87856.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 87856.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 87856.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc99b0]
>[ 87856.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc99b0] width 1920 pitch 7680 (/4 1920)
>[ 87856.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87856.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87856.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87856.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87856.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87856.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee53d0]
>[ 87856.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee53d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 87856.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 87856.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc99b0]
>[ 87856.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc99b0] width 1920 pitch 7680 (/4 1920)
>[ 87856.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 87856.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 87856.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef9d0]
>[ 87856.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef9d0] width 1920 pitch 7680 (/4 1920)
>[ 87856.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87856.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87856.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072510]
>[ 87856.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072510] width 1920 pitch 7680 (/4 1920)
>[ 87857.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc1820]
>[ 87857.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc1820] width 1920 pitch 7680 (/4 1920)
>[ 87870.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bb80]
>[ 87870.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bb80] width 1920 pitch 7680 (/4 1920)
>[ 87870.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f770a0]
>[ 87870.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f770a0] width 1920 pitch 7680 (/4 1920)
>[ 87870.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 87870.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 87870.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 87870.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 87870.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 87870.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 87870.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87870.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87870.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 87870.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 87870.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 87870.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 87870.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b090]
>[ 87870.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b090] width 1920 pitch 7680 (/4 1920)
>[ 87870.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a550]
>[ 87870.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a550] width 1920 pitch 7680 (/4 1920)
>[ 87870.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 87870.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 87870.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 87870.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 87870.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3859560]
>[ 87870.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3859560] width 1920 pitch 7680 (/4 1920)
>[ 87872.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073950]
>[ 87872.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073950] width 1920 pitch 7680 (/4 1920)
>[ 87874.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 87874.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 87874.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076fb0]
>[ 87874.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076fb0] width 1920 pitch 7680 (/4 1920)
>[ 87874.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 87874.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 87874.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 87874.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 87874.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2837110]
>[ 87874.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2837110] width 1920 pitch 7680 (/4 1920)
>[ 87874.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 87874.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 87874.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87874.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87874.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 87874.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 87874.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 87874.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 87874.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 87874.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 87874.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a550]
>[ 87874.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a550] width 1920 pitch 7680 (/4 1920)
>[ 87874.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda3a0]
>[ 87874.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda3a0] width 1920 pitch 7680 (/4 1920)
>[ 87874.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 87874.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 87894.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 87894.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 87934.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a550]
>[ 87934.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a550] width 1920 pitch 7680 (/4 1920)
>[ 87934.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 87934.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 87934.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87934.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87934.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87934.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87934.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40351f0]
>[ 87934.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40351f0] width 1920 pitch 7680 (/4 1920)
>[ 87934.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7a800]
>[ 87934.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7a800] width 1920 pitch 7680 (/4 1920)
>[ 87934.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87934.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87934.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3a050]
>[ 87934.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3a050] width 1920 pitch 7680 (/4 1920)
>[ 87934.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40351f0]
>[ 87934.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40351f0] width 1920 pitch 7680 (/4 1920)
>[ 87934.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7a800]
>[ 87934.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7a800] width 1920 pitch 7680 (/4 1920)
>[ 87934.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40351f0]
>[ 87934.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40351f0] width 1920 pitch 7680 (/4 1920)
>[ 87934.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09910]
>[ 87934.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09910] width 1920 pitch 7680 (/4 1920)
>[ 87934.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40351f0]
>[ 87934.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40351f0] width 1920 pitch 7680 (/4 1920)
>[ 87934.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3a050]
>[ 87934.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3a050] width 1920 pitch 7680 (/4 1920)
>[ 87934.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40351f0]
>[ 87934.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40351f0] width 1920 pitch 7680 (/4 1920)
>[ 87934.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7a800]
>[ 87934.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7a800] width 1920 pitch 7680 (/4 1920)
>[ 87938.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7a4a0]
>[ 87938.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7a4a0] width 1920 pitch 7680 (/4 1920)
>[ 87940.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 87940.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 87940.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87940.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87940.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42fc0]
>[ 87940.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42fc0] width 1920 pitch 7680 (/4 1920)
>[ 87940.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a39fc0]
>[ 87940.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a39fc0] width 1920 pitch 7680 (/4 1920)
>[ 87940.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 87940.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 87940.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 87940.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 87940.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87940.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87940.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87940.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87940.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87940.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87940.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87940.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87940.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42fc0]
>[ 87940.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42fc0] width 1920 pitch 7680 (/4 1920)
>[ 87941.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87941.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87941.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87941.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87941.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87941.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87941.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87941.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87941.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87941.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87941.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87941.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87941.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87941.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87941.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87941.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87941.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87941.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87941.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87941.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87941.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87941.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87941.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87941.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87941.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87941.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87941.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87941.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87941.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87941.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87941.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87941.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87941.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87941.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87942.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87942.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87942.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87942.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87942.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87942.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87942.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87942.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87942.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87942.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87942.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87942.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87942.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87942.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87942.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87942.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87942.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87942.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87942.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87942.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87942.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87942.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87942.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87942.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87942.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87942.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87942.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87942.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87942.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0330]
>[ 87942.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0330] width 1920 pitch 7680 (/4 1920)
>[ 87942.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87942.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87942.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 87942.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 87942.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87942.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87942.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87942.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87942.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87942.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87942.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87942.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87942.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87942.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87942.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87942.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87942.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87942.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87942.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87942.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87942.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87942.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87942.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 87942.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 87942.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87943.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87943.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87943.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87943.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87943.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87943.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87943.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87943.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87943.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87943.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 87943.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 87943.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87943.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87943.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87943.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87943.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8500]
>[ 87943.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8500] width 1920 pitch 7680 (/4 1920)
>[ 87943.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 87943.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 87949.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87949.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87949.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac8a40]
>[ 87949.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac8a40] width 1920 pitch 7680 (/4 1920)
>[ 87949.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87949.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87949.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac8a40]
>[ 87949.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac8a40] width 1920 pitch 7680 (/4 1920)
>[ 87949.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8b50]
>[ 87949.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8b50] width 1920 pitch 7680 (/4 1920)
>[ 87949.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac8a40]
>[ 87949.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac8a40] width 1920 pitch 7680 (/4 1920)
>[ 87949.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 87949.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 87949.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87949.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87949.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4031a70]
>[ 87949.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4031a70] width 1920 pitch 7680 (/4 1920)
>[ 87949.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87949.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87949.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[ 87949.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1920 pitch 7680 (/4 1920)
>[ 87949.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[ 87949.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1920 pitch 7680 (/4 1920)
>[ 87949.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd9a30]
>[ 87950.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd9a30] width 1920 pitch 7680 (/4 1920)
>[ 87950.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47890]
>[ 87950.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47890] width 1920 pitch 7680 (/4 1920)
>[ 87950.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39881e0]
>[ 87950.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39881e0] width 1920 pitch 7680 (/4 1920)
>[ 87951.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 87951.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 87951.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076fb0]
>[ 87951.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076fb0] width 1920 pitch 7680 (/4 1920)
>[ 87951.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e14e80]
>[ 87951.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e14e80] width 1920 pitch 7680 (/4 1920)
>[ 87951.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4031a70]
>[ 87951.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4031a70] width 1920 pitch 7680 (/4 1920)
>[ 87951.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef1930]
>[ 87951.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef1930] width 1920 pitch 7680 (/4 1920)
>[ 87951.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 87951.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 87951.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 87951.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 87951.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 87951.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 87951.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 87951.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 87951.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 88041.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e2c0]
>[ 88041.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e2c0] width 1920 pitch 7680 (/4 1920)
>[ 88041.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 88041.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 88042.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[ 88042.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[ 88043.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507fe80]
>[ 88043.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507fe80] width 1920 pitch 7680 (/4 1920)
>[ 88044.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4750]
>[ 88044.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4750] width 1920 pitch 7680 (/4 1920)
>[ 88044.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9560]
>[ 88044.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9560] width 1920 pitch 7680 (/4 1920)
>[ 88048.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45c60]
>[ 88048.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45c60] width 1920 pitch 7680 (/4 1920)
>[ 88048.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e45c60]
>[ 88048.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e45c60] width 1920 pitch 7680 (/4 1920)
>[ 88048.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88048.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b251c0]
>[ 88048.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b251c0] width 1920 pitch 7680 (/4 1920)
>[ 88048.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88048.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88050.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdbf0]
>[ 88050.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdbf0] width 1920 pitch 7680 (/4 1920)
>[ 88050.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edb90]
>[ 88050.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edb90] width 1920 pitch 7680 (/4 1920)
>[ 88050.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdbf0]
>[ 88051.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdbf0] width 1920 pitch 7680 (/4 1920)
>[ 88051.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edb90]
>[ 88051.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edb90] width 1920 pitch 7680 (/4 1920)
>[ 88051.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdbf0]
>[ 88051.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdbf0] width 1920 pitch 7680 (/4 1920)
>[ 88051.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50edb90]
>[ 88051.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50edb90] width 1920 pitch 7680 (/4 1920)
>[ 88051.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fdbf0]
>[ 88051.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fdbf0] width 1920 pitch 7680 (/4 1920)
>[ 88051.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a34700]
>[ 88051.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a34700] width 1920 pitch 7680 (/4 1920)
>[ 88051.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88051.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88051.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[ 88051.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[ 88051.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[ 88051.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[ 88051.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[ 88051.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[ 88051.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[ 88051.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[ 88051.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4270]
>[ 88051.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4270] width 1920 pitch 7680 (/4 1920)
>[ 88051.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 88051.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 88051.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88051.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[ 88051.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[ 88051.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88051.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88052.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8810]
>[ 88052.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8810] width 1920 pitch 7680 (/4 1920)
>[ 88052.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b29d20]
>[ 88052.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b29d20] width 1920 pitch 7680 (/4 1920)
>[ 88053.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 88053.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 88053.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 88053.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 88053.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 88053.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 88053.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 88053.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 88053.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88053.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88053.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01fd0]
>[ 88053.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01fd0] width 1920 pitch 7680 (/4 1920)
>[ 88054.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 88054.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 88054.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88054.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88055.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1ee0]
>[ 88055.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1ee0] width 1920 pitch 7680 (/4 1920)
>[ 88055.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76170]
>[ 88055.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76170] width 1920 pitch 7680 (/4 1920)
>[ 88056.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88056.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88056.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9bd70]
>[ 88056.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9bd70] width 1920 pitch 7680 (/4 1920)
>[ 88056.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc30]
>[ 88056.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc30] width 1920 pitch 7680 (/4 1920)
>[ 88057.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ef00]
>[ 88057.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ef00] width 1920 pitch 7680 (/4 1920)
>[ 88057.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4750]
>[ 88057.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4750] width 1920 pitch 7680 (/4 1920)
>[ 88058.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74b20]
>[ 88058.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74b20] width 1920 pitch 7680 (/4 1920)
>[ 88058.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 88058.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 88059.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88059.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88059.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88059.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88059.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88059.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8fe80]
>[ 88059.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8fe80] width 1920 pitch 7680 (/4 1920)
>[ 88060.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 88060.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 88060.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88060.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88060.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 88060.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 88060.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88060.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88060.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 88060.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 88060.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88060.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88060.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 88060.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 88060.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 88060.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 88060.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88060.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88060.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baafd0]
>[ 88060.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baafd0] width 1920 pitch 7680 (/4 1920)
>[ 88060.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88060.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88060.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88060.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88060.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021b60]
>[ 88060.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021b60] width 1920 pitch 7680 (/4 1920)
>[ 88060.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88060.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88061.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baafd0]
>[ 88061.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baafd0] width 1920 pitch 7680 (/4 1920)
>[ 88061.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88061.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88062.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88062.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88062.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021b60]
>[ 88062.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021b60] width 1920 pitch 7680 (/4 1920)
>[ 88063.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88063.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88063.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88063.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88063.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88063.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88063.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88063.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88064.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88064.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88065.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88065.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88065.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88065.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88066.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88066.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88066.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baafd0]
>[ 88066.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baafd0] width 1920 pitch 7680 (/4 1920)
>[ 88067.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88067.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88122.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88122.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88122.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88122.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88122.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88122.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88128.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88128.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88128.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88128.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88128.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88128.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88129.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3baafd0]
>[ 88129.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3baafd0] width 1920 pitch 7680 (/4 1920)
>[ 88129.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8550]
>[ 88129.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8550] width 1920 pitch 7680 (/4 1920)
>[ 88130.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f167b0]
>[ 88130.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f167b0] width 1920 pitch 7680 (/4 1920)
>[ 88139.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e5fba0]
>[ 88139.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e5fba0] width 1920 pitch 7680 (/4 1920)
>[ 88139.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50914e0]
>[ 88139.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50914e0] width 1920 pitch 7680 (/4 1920)
>[ 88139.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f587d0]
>[ 88139.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f587d0] width 1920 pitch 7680 (/4 1920)
>[ 88139.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69f33b0]
>[ 88140.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69f33b0] width 1920 pitch 7680 (/4 1920)
>[ 88140.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7ed0]
>[ 88140.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7ed0] width 1920 pitch 7680 (/4 1920)
>[ 88187.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14ac0]
>[ 88187.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14ac0] width 1920 pitch 7680 (/4 1920)
>[ 88187.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be11f0]
>[ 88187.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be11f0] width 1920 pitch 7680 (/4 1920)
>[ 88187.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40587c0]
>[ 88187.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40587c0] width 1920 pitch 7680 (/4 1920)
>[ 88188.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a86fb0]
>[ 88188.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a86fb0] width 1920 pitch 7680 (/4 1920)
>[ 88188.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102760]
>[ 88188.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102760] width 1920 pitch 7680 (/4 1920)
>[ 88188.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3ed0]
>[ 88188.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3ed0] width 1920 pitch 7680 (/4 1920)
>[ 88189.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88189.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88190.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cffa70]
>[ 88190.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cffa70] width 1920 pitch 7680 (/4 1920)
>[ 88434.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88434.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88434.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88434.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88434.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74b20]
>[ 88434.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74b20] width 1920 pitch 7680 (/4 1920)
>[ 88435.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4070]
>[ 88435.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4070] width 1920 pitch 7680 (/4 1920)
>[ 88437.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88437.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88437.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5ab0]
>[ 88437.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5ab0] width 1920 pitch 7680 (/4 1920)
>[ 88438.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39267c0]
>[ 88438.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39267c0] width 1920 pitch 7680 (/4 1920)
>[ 88438.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[ 88438.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1920 pitch 7680 (/4 1920)
>[ 88438.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2db0]
>[ 88438.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2db0] width 1920 pitch 7680 (/4 1920)
>[ 88439.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b00cb0]
>[ 88439.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b00cb0] width 1920 pitch 7680 (/4 1920)
>[ 88439.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c255e0]
>[ 88439.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c255e0] width 1920 pitch 7680 (/4 1920)
>[ 88440.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bf70]
>[ 88440.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bf70] width 1920 pitch 7680 (/4 1920)
>[ 88440.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 88440.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 88440.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88440.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88441.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88441.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88448.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501a860]
>[ 88448.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501a860] width 1920 pitch 7680 (/4 1920)
>[ 88448.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76170]
>[ 88448.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76170] width 1920 pitch 7680 (/4 1920)
>[ 88448.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db300]
>[ 88448.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db300] width 1920 pitch 7680 (/4 1920)
>[ 88449.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b29d20]
>[ 88449.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b29d20] width 1920 pitch 7680 (/4 1920)
>[ 88466.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[ 88466.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[ 88466.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de88a0]
>[ 88466.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de88a0] width 1920 pitch 7680 (/4 1920)
>[ 88466.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[ 88466.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[ 88485.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270510]
>[ 88485.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270510] width 1920 pitch 7680 (/4 1920)
>[ 88485.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[ 88485.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[ 88486.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88486.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88524.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 88524.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 88524.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021b60]
>[ 88524.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021b60] width 1920 pitch 7680 (/4 1920)
>[ 88524.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88524.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88524.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 88525.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 88525.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5c350]
>[ 88525.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5c350] width 1920 pitch 7680 (/4 1920)
>[ 88525.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88525.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88532.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f1f0]
>[ 88532.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f1f0] width 1920 pitch 7680 (/4 1920)
>[ 88532.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 88532.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 88533.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 88533.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 88533.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 88533.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 88533.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b7a0]
>[ 88533.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b7a0] width 1920 pitch 7680 (/4 1920)
>[ 88534.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de1170]
>[ 88534.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de1170] width 1920 pitch 7680 (/4 1920)
>[ 88552.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88552.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88552.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53890]
>[ 88552.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53890] width 1920 pitch 7680 (/4 1920)
>[ 88553.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 88553.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 88555.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1130]
>[ 88555.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1130] width 1920 pitch 7680 (/4 1920)
>[ 88555.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88555.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88555.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88555.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88555.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b29d20]
>[ 88556.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b29d20] width 1920 pitch 7680 (/4 1920)
>[ 88556.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88556.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88556.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88556.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88556.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88556.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88556.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88556.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88556.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88556.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88556.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88556.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88556.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88556.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88556.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88556.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88556.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88556.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88557.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88557.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88557.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88557.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88557.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88557.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88557.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88557.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88557.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88557.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88557.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88557.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88557.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88557.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88557.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88557.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88557.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88558.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88558.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cbe80]
>[ 88558.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cbe80] width 1920 pitch 7680 (/4 1920)
>[ 88560.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1130]
>[ 88560.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1130] width 1920 pitch 7680 (/4 1920)
>[ 88560.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 88560.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 88560.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 88561.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 88561.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88561.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88617.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50db300]
>[ 88617.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50db300] width 1920 pitch 7680 (/4 1920)
>[ 88617.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 88617.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 88618.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063f80]
>[ 88618.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063f80] width 1920 pitch 7680 (/4 1920)
>[ 88618.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 88618.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 88618.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[ 88618.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[ 88618.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1130]
>[ 88618.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1130] width 1920 pitch 7680 (/4 1920)
>[ 88619.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 88619.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 88620.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5f40]
>[ 88620.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5f40] width 1920 pitch 7680 (/4 1920)
>[ 88620.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5f40]
>[ 88620.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5f40] width 1920 pitch 7680 (/4 1920)
>[ 88797.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf5f0]
>[ 88797.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf5f0] width 1920 pitch 7680 (/4 1920)
>[ 88797.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88797.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 88797.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 88797.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88797.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 88797.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 88797.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88797.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 88797.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 88797.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88797.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 88797.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 88797.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88797.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072220]
>[ 88797.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072220] width 1920 pitch 7680 (/4 1920)
>[ 88797.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88797.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88798.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d4a0]
>[ 88798.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d4a0] width 1920 pitch 7680 (/4 1920)
>[ 88798.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac070]
>[ 88798.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac070] width 1920 pitch 7680 (/4 1920)
>[ 88798.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d4a0]
>[ 88798.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d4a0] width 1920 pitch 7680 (/4 1920)
>[ 88798.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebfde0]
>[ 88798.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebfde0] width 1920 pitch 7680 (/4 1920)
>[ 88798.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8eb20]
>[ 88798.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8eb20] width 1920 pitch 7680 (/4 1920)
>[ 88798.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebfde0]
>[ 88798.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebfde0] width 1920 pitch 7680 (/4 1920)
>[ 88798.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8eb20]
>[ 88798.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8eb20] width 1920 pitch 7680 (/4 1920)
>[ 88798.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecb980]
>[ 88798.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecb980] width 1920 pitch 7680 (/4 1920)
>[ 88798.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff1f0]
>[ 88798.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff1f0] width 1920 pitch 7680 (/4 1920)
>[ 88798.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b027d0]
>[ 88798.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b027d0] width 1920 pitch 7680 (/4 1920)
>[ 88798.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff1f0]
>[ 88798.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff1f0] width 1920 pitch 7680 (/4 1920)
>[ 88798.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b027d0]
>[ 88798.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b027d0] width 1920 pitch 7680 (/4 1920)
>[ 88799.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4390]
>[ 88799.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4390] width 1920 pitch 7680 (/4 1920)
>[ 88799.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef54b0]
>[ 88799.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef54b0] width 1920 pitch 7680 (/4 1920)
>[ 88799.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321d0]
>[ 88799.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321d0] width 1920 pitch 7680 (/4 1920)
>[ 88800.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50891b0]
>[ 88800.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50891b0] width 1920 pitch 7680 (/4 1920)
>[ 88800.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40321d0]
>[ 88800.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40321d0] width 1920 pitch 7680 (/4 1920)
>[ 88801.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50891b0]
>[ 88801.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50891b0] width 1920 pitch 7680 (/4 1920)
>[ 88850.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50891b0]
>[ 88850.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50891b0] width 1920 pitch 7680 (/4 1920)
>[ 88850.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 88850.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 88851.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 88851.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 88851.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 88851.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 88851.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 88851.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 88856.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de1170]
>[ 88856.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de1170] width 1920 pitch 7680 (/4 1920)
>[ 88856.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88856.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88856.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1100]
>[ 88856.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1100] width 1920 pitch 7680 (/4 1920)
>[ 88857.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063f80]
>[ 88857.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063f80] width 1920 pitch 7680 (/4 1920)
>[ 88857.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 88857.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 88863.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 88863.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 88863.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88863.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88863.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88863.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88863.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca770]
>[ 88863.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca770] width 1920 pitch 7680 (/4 1920)
>[ 88863.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f37f90]
>[ 88864.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f37f90] width 1920 pitch 7680 (/4 1920)
>[ 88864.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca770]
>[ 88864.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca770] width 1920 pitch 7680 (/4 1920)
>[ 88865.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7070]
>[ 88866.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7070] width 1920 pitch 7680 (/4 1920)
>[ 88866.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 88866.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 88866.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88866.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88866.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88866.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88867.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d6420]
>[ 88867.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d6420] width 1920 pitch 7680 (/4 1920)
>[ 88867.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdbb0]
>[ 88867.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdbb0] width 1920 pitch 7680 (/4 1920)
>[ 88868.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de1170]
>[ 88868.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de1170] width 1920 pitch 7680 (/4 1920)
>[ 89244.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 89244.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 89244.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89244.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89245.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89245.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89245.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4100]
>[ 89245.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4100] width 1920 pitch 7680 (/4 1920)
>[ 89262.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87cf0]
>[ 89262.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87cf0] width 1920 pitch 7680 (/4 1920)
>[ 89262.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c87cf0]
>[ 89262.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c87cf0] width 1920 pitch 7680 (/4 1920)
>[ 89263.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1200]
>[ 89263.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1200] width 1920 pitch 7680 (/4 1920)
>[ 89263.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1200]
>[ 89263.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1200] width 1920 pitch 7680 (/4 1920)
>[ 89264.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f36fe0]
>[ 89264.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f36fe0] width 1920 pitch 7680 (/4 1920)
>[ 89264.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 89264.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 89265.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 89265.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 89270.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89270.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89270.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 89270.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 89270.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de88a0]
>[ 89270.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de88a0] width 1920 pitch 7680 (/4 1920)
>[ 89270.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89270.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89271.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28270a0]
>[ 89271.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28270a0] width 1920 pitch 7680 (/4 1920)
>[ 89271.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28270a0]
>[ 89271.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28270a0] width 1920 pitch 7680 (/4 1920)
>[ 89272.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 89272.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 89273.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4100]
>[ 89273.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4100] width 1920 pitch 7680 (/4 1920)
>[ 89295.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 89295.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 89295.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e9e30]
>[ 89295.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e9e30] width 1920 pitch 7680 (/4 1920)
>[ 89296.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d5e0]
>[ 89296.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d5e0] width 1920 pitch 7680 (/4 1920)
>[ 89296.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de88a0]
>[ 89296.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de88a0] width 1920 pitch 7680 (/4 1920)
>[ 89296.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11110]
>[ 89296.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11110] width 1920 pitch 7680 (/4 1920)
>[ 89296.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ab40]
>[ 89296.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ab40] width 1920 pitch 7680 (/4 1920)
>[ 89297.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8aae0]
>[ 89297.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8aae0] width 1920 pitch 7680 (/4 1920)
>[ 89399.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c58bb0]
>[ 89399.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c58bb0] width 1920 pitch 7680 (/4 1920)
>[ 89400.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5caf0]
>[ 89400.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5caf0] width 1920 pitch 7680 (/4 1920)
>[ 89400.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c3f0]
>[ 89400.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c3f0] width 1920 pitch 7680 (/4 1920)
>[ 89400.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de88a0]
>[ 89400.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de88a0] width 1920 pitch 7680 (/4 1920)
>[ 89401.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bc10]
>[ 89401.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bc10] width 1920 pitch 7680 (/4 1920)
>[ 89401.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f65530]
>[ 89401.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f65530] width 1920 pitch 7680 (/4 1920)
>[ 89401.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4bf20]
>[ 89401.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4bf20] width 1920 pitch 7680 (/4 1920)
>[ 89402.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1200]
>[ 89402.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1200] width 1920 pitch 7680 (/4 1920)
>[ 89410.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1200]
>[ 89410.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1200] width 1920 pitch 7680 (/4 1920)
>[ 89410.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecad0]
>[ 89410.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecad0] width 1920 pitch 7680 (/4 1920)
>[ 89410.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb3190]
>[ 89410.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb3190] width 1920 pitch 7680 (/4 1920)
>[ 89411.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e430]
>[ 89411.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e430] width 1920 pitch 7680 (/4 1920)
>[ 89413.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d97480]
>[ 89413.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d97480] width 1920 pitch 7680 (/4 1920)
>[ 89413.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18830]
>[ 89413.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18830] width 1920 pitch 7680 (/4 1920)
>[ 89413.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507f100]
>[ 89413.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507f100] width 1920 pitch 7680 (/4 1920)
>[ 89414.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270510]
>[ 89414.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270510] width 1920 pitch 7680 (/4 1920)
>[ 89456.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e350]
>[ 89456.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e350] width 1920 pitch 7680 (/4 1920)
>[ 89456.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca920]
>[ 89456.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca920] width 1920 pitch 7680 (/4 1920)
>[ 89456.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d97440]
>[ 89456.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d97440] width 1920 pitch 7680 (/4 1920)
>[ 89456.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bc10]
>[ 89456.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bc10] width 1920 pitch 7680 (/4 1920)
>[ 89456.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2862400]
>[ 89456.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2862400] width 1920 pitch 7680 (/4 1920)
>[ 89457.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bc10]
>[ 89457.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bc10] width 1920 pitch 7680 (/4 1920)
>[ 89461.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4bc10]
>[ 89461.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4bc10] width 1920 pitch 7680 (/4 1920)
>[ 89461.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 89461.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 89462.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[ 89462.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1920 pitch 7680 (/4 1920)
>[ 89506.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 89506.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 89506.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 89506.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 89507.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 89507.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 89507.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2cf0]
>[ 89507.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2cf0] width 1920 pitch 7680 (/4 1920)
>[ 89507.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b8b0]
>[ 89507.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b8b0] width 1920 pitch 7680 (/4 1920)
>[ 89508.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7b8b0]
>[ 89508.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7b8b0] width 1920 pitch 7680 (/4 1920)
>[ 89586.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30370]
>[ 89586.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30370] width 1920 pitch 7680 (/4 1920)
>[ 89589.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b51b50]
>[ 89589.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b51b50] width 1920 pitch 7680 (/4 1920)
>[ 89589.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b830]
>[ 89589.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b830] width 1920 pitch 7680 (/4 1920)
>[ 89589.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863740]
>[ 89589.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863740] width 1920 pitch 7680 (/4 1920)
>[ 89589.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b000]
>[ 89589.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b000] width 1920 pitch 7680 (/4 1920)
>[ 89591.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7150]
>[ 89591.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7150] width 1920 pitch 7680 (/4 1920)
>[ 89604.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5020060]
>[ 89604.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5020060] width 1920 pitch 7680 (/4 1920)
>[ 89604.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1330]
>[ 89604.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1330] width 1920 pitch 7680 (/4 1920)
>[ 89604.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4009720]
>[ 89604.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4009720] width 1920 pitch 7680 (/4 1920)
>[ 89605.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84b00]
>[ 89605.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84b00] width 1920 pitch 7680 (/4 1920)
>[ 89605.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89605.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89605.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53050]
>[ 89605.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53050] width 1920 pitch 7680 (/4 1920)
>[ 89606.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1330]
>[ 89606.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1330] width 1920 pitch 7680 (/4 1920)
>[ 89606.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c531a0]
>[ 89606.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c531a0] width 1920 pitch 7680 (/4 1920)
>[ 89607.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c531a0]
>[ 89607.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c531a0] width 1920 pitch 7680 (/4 1920)
>[ 89607.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89607.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89607.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53200]
>[ 89608.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53200] width 1920 pitch 7680 (/4 1920)
>[ 89608.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067be0]
>[ 89608.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067be0] width 1920 pitch 7680 (/4 1920)
>[ 89608.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89608.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89608.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 89608.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 89609.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89609.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89610.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061160]
>[ 89610.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061160] width 1920 pitch 7680 (/4 1920)
>[ 89610.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091430]
>[ 89610.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091430] width 1920 pitch 7680 (/4 1920)
>[ 89610.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89610.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89610.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89610.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89610.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89610.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89610.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89610.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89610.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89610.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89610.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89610.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89610.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89610.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89610.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89610.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89610.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89610.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89610.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89610.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89611.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89611.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89611.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89611.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89611.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75d80]
>[ 89611.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75d80] width 1920 pitch 7680 (/4 1920)
>[ 89611.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89611.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89611.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 89611.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 89611.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89611.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89611.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 89611.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 89611.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89611.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89611.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 89611.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 89611.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89611.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89611.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 89611.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 89611.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89611.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89611.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06f40]
>[ 89611.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06f40] width 1920 pitch 7680 (/4 1920)
>[ 89611.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43960]
>[ 89611.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43960] width 1920 pitch 7680 (/4 1920)
>[ 89612.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9ed60]
>[ 89612.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9ed60] width 1920 pitch 7680 (/4 1920)
>[ 89612.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9ed60]
>[ 89612.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9ed60] width 1920 pitch 7680 (/4 1920)
>[ 89615.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edeb80]
>[ 89615.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edeb80] width 1920 pitch 7680 (/4 1920)
>[ 89615.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba3a80]
>[ 89615.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba3a80] width 1920 pitch 7680 (/4 1920)
>[ 89615.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba3a80]
>[ 89615.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba3a80] width 1920 pitch 7680 (/4 1920)
>[ 89616.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b03fd0]
>[ 89616.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b03fd0] width 1920 pitch 7680 (/4 1920)
>[ 89616.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e581d0]
>[ 89616.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e581d0] width 1920 pitch 7680 (/4 1920)
>[ 89616.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edebd0]
>[ 89616.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edebd0] width 1920 pitch 7680 (/4 1920)
>[ 89617.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43960]
>[ 89617.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43960] width 1920 pitch 7680 (/4 1920)
>[ 89617.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43960]
>[ 89617.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43960] width 1920 pitch 7680 (/4 1920)
>[ 89618.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43960]
>[ 89618.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43960] width 1920 pitch 7680 (/4 1920)
>[ 89618.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08be0]
>[ 89618.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08be0] width 1920 pitch 7680 (/4 1920)
>[ 89618.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89618.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc30]
>[ 89619.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc30] width 1920 pitch 7680 (/4 1920)
>[ 89619.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94920]
>[ 89619.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94920] width 1920 pitch 7680 (/4 1920)
>[ 89619.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89619.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89619.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89619.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89619.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89619.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89619.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89619.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89619.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89619.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f502d0]
>[ 89619.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f502d0] width 1920 pitch 7680 (/4 1920)
>[ 89619.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285f4f0]
>[ 89619.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285f4f0] width 1920 pitch 7680 (/4 1920)
>[ 89620.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89620.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89620.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 89620.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 89620.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c52f30]
>[ 89620.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c52f30] width 1920 pitch 7680 (/4 1920)
>[ 89620.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1190]
>[ 89620.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1190] width 1920 pitch 7680 (/4 1920)
>[ 89620.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecf440]
>[ 89620.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecf440] width 1920 pitch 7680 (/4 1920)
>[ 89620.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9b530]
>[ 89620.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9b530] width 1920 pitch 7680 (/4 1920)
>[ 89620.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc30]
>[ 89620.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc30] width 1920 pitch 7680 (/4 1920)
>[ 89620.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061160]
>[ 89620.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061160] width 1920 pitch 7680 (/4 1920)
>[ 89620.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9b530]
>[ 89620.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9b530] width 1920 pitch 7680 (/4 1920)
>[ 89620.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9b530]
>[ 89620.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9b530] width 1920 pitch 7680 (/4 1920)
>[ 89620.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecf440]
>[ 89620.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecf440] width 1920 pitch 7680 (/4 1920)
>[ 89620.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9b530]
>[ 89620.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9b530] width 1920 pitch 7680 (/4 1920)
>[ 89620.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecf440]
>[ 89620.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecf440] width 1920 pitch 7680 (/4 1920)
>[ 89620.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 89620.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 89620.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 89620.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 89620.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94920]
>[ 89620.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94920] width 1920 pitch 7680 (/4 1920)
>[ 89620.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 89620.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 89621.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89621.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89621.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94920]
>[ 89621.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94920] width 1920 pitch 7680 (/4 1920)
>[ 89621.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4410]
>[ 89621.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4410] width 1920 pitch 7680 (/4 1920)
>[ 89621.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061160]
>[ 89621.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061160] width 1920 pitch 7680 (/4 1920)
>[ 89621.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[ 89621.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1920 pitch 7680 (/4 1920)
>[ 89622.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 89622.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 89638.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc30]
>[ 89638.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc30] width 1920 pitch 7680 (/4 1920)
>[ 89638.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1f7b0]
>[ 89638.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1f7b0] width 1920 pitch 7680 (/4 1920)
>[ 89639.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1f7b0]
>[ 89639.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1f7b0] width 1920 pitch 7680 (/4 1920)
>[ 89642.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2a10]
>[ 89642.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2a10] width 1920 pitch 7680 (/4 1920)
>[ 89642.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c57630]
>[ 89642.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c57630] width 1920 pitch 7680 (/4 1920)
>[ 89643.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01c40]
>[ 89643.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01c40] width 1920 pitch 7680 (/4 1920)
>[ 89645.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9dc30]
>[ 89645.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9dc30] width 1920 pitch 7680 (/4 1920)
>[ 89645.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b53780]
>[ 89645.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b53780] width 1920 pitch 7680 (/4 1920)
>[ 89645.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edead0]
>[ 89645.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edead0] width 1920 pitch 7680 (/4 1920)
>[ 89645.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b53780]
>[ 89645.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b53780] width 1920 pitch 7680 (/4 1920)
>[ 89646.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0810]
>[ 89646.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0810] width 1920 pitch 7680 (/4 1920)
>[ 89646.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 89646.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 89646.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89646.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89646.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89646.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89646.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89646.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89646.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89646.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89646.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89646.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89646.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 89646.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 89646.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44d20]
>[ 89646.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44d20] width 1920 pitch 7680 (/4 1920)
>[ 89646.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052310]
>[ 89646.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052310] width 1920 pitch 7680 (/4 1920)
>[ 89677.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 89677.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 89678.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97270]
>[ 89678.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97270] width 1920 pitch 7680 (/4 1920)
>[ 89678.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[ 89678.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[ 89678.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 89678.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 89678.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[ 89678.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[ 89692.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 89692.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 89693.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a550]
>[ 89693.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a550] width 1920 pitch 7680 (/4 1920)
>[ 89693.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 89693.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 89693.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 89693.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 89693.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89693.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89694.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 89694.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 89694.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 89694.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 89695.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1a260]
>[ 89695.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1a260] width 1920 pitch 7680 (/4 1920)
>[ 89695.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 89695.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 89695.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 89695.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 89696.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac09f0]
>[ 89696.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac09f0] width 1920 pitch 7680 (/4 1920)
>[ 89703.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57e50]
>[ 89703.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57e50] width 1920 pitch 7680 (/4 1920)
>[ 89703.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114d80]
>[ 89703.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c8c0]
>[ 89703.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c8c0] width 1920 pitch 7680 (/4 1920)
>[ 89703.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08d80]
>[ 89703.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08d80] width 1920 pitch 7680 (/4 1920)
>[ 89703.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[ 89703.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1920 pitch 7680 (/4 1920)
>[ 89703.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 89703.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 89703.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28516f0]
>[ 89703.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28516f0] width 1920 pitch 7680 (/4 1920)
>[ 89703.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6e90]
>[ 89703.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6e90] width 1920 pitch 7680 (/4 1920)
>[ 89704.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 89704.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 89704.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 89704.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 89704.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[ 89704.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1920 pitch 7680 (/4 1920)
>[ 89704.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 89704.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 89704.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[ 89704.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1920 pitch 7680 (/4 1920)
>[ 89704.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50476b0]
>[ 89704.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50476b0] width 1920 pitch 7680 (/4 1920)
>[ 89704.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 89704.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 89704.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 89704.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 89704.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 89704.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 89704.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 89704.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 89704.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 89704.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 89704.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 89704.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 89704.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896d80]
>[ 89704.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896d80] width 1920 pitch 7680 (/4 1920)
>[ 89705.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50748a0]
>[ 89705.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50748a0] width 1920 pitch 7680 (/4 1920)
>[ 89705.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de80f0]
>[ 89705.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de80f0] width 1920 pitch 7680 (/4 1920)
>[ 89705.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd8d0]
>[ 89705.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd8d0] width 1920 pitch 7680 (/4 1920)
>[ 89706.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c29950]
>[ 89706.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c29950] width 1920 pitch 7680 (/4 1920)
>[ 89706.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3ba70]
>[ 89706.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3ba70] width 1920 pitch 7680 (/4 1920)
>[ 89706.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 89706.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 89706.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b53720]
>[ 89707.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b53720] width 1920 pitch 7680 (/4 1920)
>[ 89707.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf4d00]
>[ 89707.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf4d00] width 1920 pitch 7680 (/4 1920)
>[ 89707.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 89707.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 89708.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 89708.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 89709.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076fb0]
>[ 89709.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076fb0] width 1920 pitch 7680 (/4 1920)
>[ 89709.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 89709.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 89710.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 89710.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 89711.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb7a0]
>[ 89711.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb7a0] width 1920 pitch 7680 (/4 1920)
>[ 89711.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 89711.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 89711.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e32800]
>[ 89711.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e32800] width 1920 pitch 7680 (/4 1920)
>[ 89711.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd8d0]
>[ 89711.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd8d0] width 1920 pitch 7680 (/4 1920)
>[ 89712.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5450]
>[ 89712.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5450] width 1920 pitch 7680 (/4 1920)
>[ 89712.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073950]
>[ 89712.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073950] width 1920 pitch 7680 (/4 1920)
>[ 89713.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8cc80]
>[ 89713.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8cc80] width 1920 pitch 7680 (/4 1920)
>[ 89713.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 89713.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 89770.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30240]
>[ 89770.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30240] width 1920 pitch 7680 (/4 1920)
>[ 89770.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd8d0]
>[ 89770.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd8d0] width 1920 pitch 7680 (/4 1920)
>[ 89771.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea68d0]
>[ 89771.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea68d0] width 1920 pitch 7680 (/4 1920)
>[ 89771.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 89771.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 89776.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b03c60]
>[ 89776.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b03c60] width 1920 pitch 7680 (/4 1920)
>[ 89792.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b51cf0]
>[ 89792.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b51cf0] width 1920 pitch 7680 (/4 1920)
>[ 89792.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acde00]
>[ 89792.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acde00] width 1920 pitch 7680 (/4 1920)
>[ 89793.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501e8e0]
>[ 89793.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501e8e0] width 1920 pitch 7680 (/4 1920)
>[ 89794.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa6f40]
>[ 89794.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa6f40] width 1920 pitch 7680 (/4 1920)
>[ 89863.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f108f0]
>[ 89863.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f108f0] width 1920 pitch 7680 (/4 1920)
>[ 89863.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc6800]
>[ 89863.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc6800] width 1920 pitch 7680 (/4 1920)
>[ 89863.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eca230]
>[ 89863.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eca230] width 1920 pitch 7680 (/4 1920)
>[ 89864.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 89864.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 89864.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 89864.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 89864.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 89864.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 89920.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca8e0]
>[ 89920.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca8e0] width 1920 pitch 7680 (/4 1920)
>[ 90058.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc9410]
>[ 90058.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc9410] width 1920 pitch 7680 (/4 1920)
>[ 90059.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bbf90]
>[ 90059.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bbf90] width 1920 pitch 7680 (/4 1920)
>[ 90060.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0f1c0]
>[ 90060.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0f1c0] width 1920 pitch 7680 (/4 1920)
>[ 90060.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90060.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90061.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90061.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90061.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90061.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90061.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90061.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90061.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a362b0]
>[ 90061.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a362b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90061.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a362b0]
>[ 90061.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a362b0] width 1920 pitch 7680 (/4 1920)
>[ 90061.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90061.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90061.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90062.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90062.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f010]
>[ 90062.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f010] width 1920 pitch 7680 (/4 1920)
>[ 90062.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975650]
>[ 90062.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975650] width 1920 pitch 7680 (/4 1920)
>[ 90062.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0f1c0]
>[ 90062.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0f1c0] width 1920 pitch 7680 (/4 1920)
>[ 90062.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a362b0]
>[ 90062.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a362b0] width 1920 pitch 7680 (/4 1920)
>[ 90062.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0f1c0]
>[ 90062.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0f1c0] width 1920 pitch 7680 (/4 1920)
>[ 90160.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efaa00]
>[ 90160.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efaa00] width 1920 pitch 7680 (/4 1920)
>[ 90160.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf4d00]
>[ 90160.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf4d00] width 1920 pitch 7680 (/4 1920)
>[ 90160.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 90160.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 90185.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90185.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90185.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3859560]
>[ 90185.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3859560] width 1920 pitch 7680 (/4 1920)
>[ 90185.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90185.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90185.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51323e0]
>[ 90185.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51323e0] width 1920 pitch 7680 (/4 1920)
>[ 90208.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b07df0]
>[ 90208.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b07df0] width 1920 pitch 7680 (/4 1920)
>[ 90208.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90208.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90209.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 90209.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 90209.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fca8e0]
>[ 90209.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fca8e0] width 1920 pitch 7680 (/4 1920)
>[ 90209.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42e20]
>[ 90209.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42e20] width 1920 pitch 7680 (/4 1920)
>[ 90210.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90210.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90210.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f15e80]
>[ 90210.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f15e80] width 1920 pitch 7680 (/4 1920)
>[ 90226.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2819280]
>[ 90226.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2819280] width 1920 pitch 7680 (/4 1920)
>[ 90226.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 90226.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 90226.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 90226.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 90226.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 90226.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 90227.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 90227.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 90227.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bad360]
>[ 90227.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bad360] width 1920 pitch 7680 (/4 1920)
>[ 90228.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d877b0]
>[ 90228.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d877b0] width 1920 pitch 7680 (/4 1920)
>[ 90228.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90228.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90228.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5091c00]
>[ 90228.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5091c00] width 1920 pitch 7680 (/4 1920)
>[ 90229.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3859560]
>[ 90229.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3859560] width 1920 pitch 7680 (/4 1920)
>[ 90354.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 90354.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 90354.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90354.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 90354.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 90354.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90354.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 90354.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 90354.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90354.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 90354.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 90354.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90354.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 90354.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 90354.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90354.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[ 90354.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1920 pitch 7680 (/4 1920)
>[ 90354.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90354.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90357.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bc50]
>[ 90357.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bc50] width 1920 pitch 7680 (/4 1920)
>[ 90359.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281f910]
>[ 90359.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281f910] width 1920 pitch 7680 (/4 1920)
>[ 90374.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90374.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90374.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90374.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90375.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 90375.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 90375.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90375.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90375.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90375.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90375.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90375.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90375.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90375.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90375.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90375.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90375.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90375.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90375.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90375.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90375.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90375.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90375.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90375.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90376.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90376.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90376.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90376.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90376.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90376.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90411.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90411.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90411.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90411.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90411.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90411.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90411.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90411.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90411.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90411.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90411.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90411.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90411.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90411.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90414.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 90414.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 90414.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90414.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90414.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90414.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90414.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073950]
>[ 90414.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073950] width 1920 pitch 7680 (/4 1920)
>[ 90414.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90414.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90414.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90414.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90414.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90414.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90414.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90414.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90414.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 90414.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 90414.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90414.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90415.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90415.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90415.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90415.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90415.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf4d00]
>[ 90415.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf4d00] width 1920 pitch 7680 (/4 1920)
>[ 90415.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26940]
>[ 90415.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26940] width 1920 pitch 7680 (/4 1920)
>[ 90415.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf4d00]
>[ 90415.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf4d00] width 1920 pitch 7680 (/4 1920)
>[ 90415.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67cd0]
>[ 90415.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67cd0] width 1920 pitch 7680 (/4 1920)
>[ 90415.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90415.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90415.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90415.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90415.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90415.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90415.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca020]
>[ 90415.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca020] width 1920 pitch 7680 (/4 1920)
>[ 90415.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 90415.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 90415.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e1c0]
>[ 90415.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e1c0] width 1920 pitch 7680 (/4 1920)
>[ 90415.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50479c0]
>[ 90415.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50479c0] width 1920 pitch 7680 (/4 1920)
>[ 90415.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90415.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90415.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90415.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90415.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90415.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90415.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90415.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90416.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90416.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90416.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90416.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90416.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90416.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90416.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b460]
>[ 90416.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b460] width 1920 pitch 7680 (/4 1920)
>[ 90416.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90416.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90416.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90416.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90416.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 90416.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 90416.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90416.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90416.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90416.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90416.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90416.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90416.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90416.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90416.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 90416.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 90416.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90416.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90416.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 90416.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 90418.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90418.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90419.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90419.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90420.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd7b60]
>[ 90420.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 90420.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 90420.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 90420.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13030]
>[ 90420.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13030] width 1920 pitch 7680 (/4 1920)
>[ 90420.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 90420.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 90420.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 90420.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 90421.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896d80]
>[ 90421.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896d80] width 1920 pitch 7680 (/4 1920)
>[ 90421.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90421.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90421.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896d80]
>[ 90421.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896d80] width 1920 pitch 7680 (/4 1920)
>[ 90438.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3974bb0]
>[ 90438.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3974bb0] width 1920 pitch 7680 (/4 1920)
>[ 90438.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896d80]
>[ 90438.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896d80] width 1920 pitch 7680 (/4 1920)
>[ 90438.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96b60]
>[ 90438.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96b60] width 1920 pitch 7680 (/4 1920)
>[ 90439.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 90439.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 90445.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90445.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90445.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51323e0]
>[ 90445.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51323e0] width 1920 pitch 7680 (/4 1920)
>[ 90445.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6aed0]
>[ 90446.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6aed0] width 1920 pitch 7680 (/4 1920)
>[ 90446.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 90446.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 90446.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab6c0]
>[ 90446.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab6c0] width 1920 pitch 7680 (/4 1920)
>[ 90447.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90447.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90447.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a000]
>[ 90447.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a000] width 1920 pitch 7680 (/4 1920)
>[ 90448.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[ 90448.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1920 pitch 7680 (/4 1920)
>[ 90449.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90449.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90452.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1500]
>[ 90452.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1500] width 1920 pitch 7680 (/4 1920)
>[ 90452.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9d80]
>[ 90452.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9d80] width 1920 pitch 7680 (/4 1920)
>[ 90452.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 90452.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 90452.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40234b0]
>[ 90452.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40234b0] width 1920 pitch 7680 (/4 1920)
>[ 90453.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90453.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90454.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e76d60]
>[ 90454.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e76d60] width 1920 pitch 7680 (/4 1920)
>[ 90458.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90458.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90458.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9d80]
>[ 90458.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9d80] width 1920 pitch 7680 (/4 1920)
>[ 90459.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e76d60]
>[ 90459.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e76d60] width 1920 pitch 7680 (/4 1920)
>[ 90459.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[ 90459.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[ 90459.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4660]
>[ 90459.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4660] width 1920 pitch 7680 (/4 1920)
>[ 90460.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066c50]
>[ 90460.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066c50] width 1920 pitch 7680 (/4 1920)
>[ 90470.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066c50]
>[ 90470.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066c50] width 1920 pitch 7680 (/4 1920)
>[ 90471.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 90471.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 90471.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efaa00]
>[ 90471.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efaa00] width 1920 pitch 7680 (/4 1920)
>[ 90471.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 90471.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 90471.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97600]
>[ 90471.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97600] width 1920 pitch 7680 (/4 1920)
>[ 90472.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90472.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90477.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e76d60]
>[ 90477.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e76d60] width 1920 pitch 7680 (/4 1920)
>[ 90501.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 90501.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 90501.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90501.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90502.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[ 90502.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[ 90502.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efaa00]
>[ 90502.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efaa00] width 1920 pitch 7680 (/4 1920)
>[ 90502.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[ 90502.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1920 pitch 7680 (/4 1920)
>[ 90503.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdf5f0]
>[ 90503.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdf5f0] width 1920 pitch 7680 (/4 1920)
>[ 90515.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5e830]
>[ 90515.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5e830] width 1920 pitch 7680 (/4 1920)
>[ 90515.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 90515.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 90516.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5bb30]
>[ 90516.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5bb30] width 1920 pitch 7680 (/4 1920)
>[ 90516.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90516.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90517.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 90517.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 90517.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 90517.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 90518.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90518.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90518.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5e830]
>[ 90518.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5e830] width 1920 pitch 7680 (/4 1920)
>[ 90599.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69762f0]
>[ 90599.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69762f0] width 1920 pitch 7680 (/4 1920)
>[ 90599.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90599.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90600.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97600]
>[ 90600.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97600] width 1920 pitch 7680 (/4 1920)
>[ 90600.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90600.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90600.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90600.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90601.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90601.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90602.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90602.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90602.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf1ba0]
>[ 90602.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf1ba0] width 1920 pitch 7680 (/4 1920)
>[ 90602.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28327b0]
>[ 90602.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28327b0] width 1920 pitch 7680 (/4 1920)
>[ 90602.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f920]
>[ 90602.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f920] width 1920 pitch 7680 (/4 1920)
>[ 90602.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58f10]
>[ 90602.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58f10] width 1920 pitch 7680 (/4 1920)
>[ 90602.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90602.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90604.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bc50]
>[ 90604.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bc50] width 1920 pitch 7680 (/4 1920)
>[ 90604.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90604.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90604.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea0ac0]
>[ 90604.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea0ac0] width 1920 pitch 7680 (/4 1920)
>[ 90604.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90604.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90604.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90604.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90604.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90604.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90604.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90604.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90604.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90604.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90604.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90605.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90605.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90605.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90605.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90605.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90605.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90605.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90605.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90605.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90605.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90605.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90605.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90605.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90605.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90605.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90605.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90605.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90605.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90605.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90605.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90605.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90605.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90605.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90605.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90605.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90605.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90605.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90605.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90605.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90605.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90605.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90605.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90606.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90606.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90606.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea0ac0]
>[ 90606.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea0ac0] width 1920 pitch 7680 (/4 1920)
>[ 90606.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa6f70]
>[ 90606.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa6f70] width 1920 pitch 7680 (/4 1920)
>[ 90606.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90606.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90607.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f920]
>[ 90607.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f920] width 1920 pitch 7680 (/4 1920)
>[ 90620.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90620.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90620.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90620.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90620.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90620.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90620.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90620.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90620.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90620.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90620.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90620.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90620.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90620.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90620.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90620.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90620.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90620.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90620.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90620.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90621.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90621.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90621.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90621.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90621.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90621.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90621.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90621.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90622.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04290]
>[ 90622.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04290] width 1920 pitch 7680 (/4 1920)
>[ 90622.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90622.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90622.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90622.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90622.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90622.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90622.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90622.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90622.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90622.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90622.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90622.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90622.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90622.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90622.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90622.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90622.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90622.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90622.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90622.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90622.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90623.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90623.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90623.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90623.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90623.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90623.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90623.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90623.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90623.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90654.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90654.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90654.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90654.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90654.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90654.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90654.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90654.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90654.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90654.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90654.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90654.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90654.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90654.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90654.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90654.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90654.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90654.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90654.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90654.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90655.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90655.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90655.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90655.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90655.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90655.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90655.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90655.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90659.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90659.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90659.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ddf530]
>[ 90659.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ddf530] width 1920 pitch 7680 (/4 1920)
>[ 90662.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce48f0]
>[ 90662.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce48f0] width 1920 pitch 7680 (/4 1920)
>[ 90662.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90662.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90662.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90662.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90662.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90662.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90662.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90662.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90662.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90662.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90662.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9d930]
>[ 90662.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9d930] width 1920 pitch 7680 (/4 1920)
>[ 90662.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90662.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90662.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9d930]
>[ 90663.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9d930] width 1920 pitch 7680 (/4 1920)
>[ 90663.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90663.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90663.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9d930]
>[ 90663.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9d930] width 1920 pitch 7680 (/4 1920)
>[ 90663.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[ 90663.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1920 pitch 7680 (/4 1920)
>[ 90663.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9d930]
>[ 90663.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9d930] width 1920 pitch 7680 (/4 1920)
>[ 90663.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90663.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90663.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 90663.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 90663.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90663.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90663.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90664.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90664.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90664.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90664.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90664.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90664.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90664.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90664.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90664.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90664.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90664.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90664.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90664.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90664.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90664.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90664.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90664.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90664.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53670]
>[ 90665.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53670] width 1920 pitch 7680 (/4 1920)
>[ 90665.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90665.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90665.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90665.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90665.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90665.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90665.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90665.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90665.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90665.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90665.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90665.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90665.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a000]
>[ 90665.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a000] width 1920 pitch 7680 (/4 1920)
>[ 90665.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa2b10]
>[ 90665.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa2b10] width 1920 pitch 7680 (/4 1920)
>[ 90694.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 90694.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 90694.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90694.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90694.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa2b10]
>[ 90694.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa2b10] width 1920 pitch 7680 (/4 1920)
>[ 90694.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18530]
>[ 90694.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18530] width 1920 pitch 7680 (/4 1920)
>[ 90694.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c52680]
>[ 90694.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c52680] width 1920 pitch 7680 (/4 1920)
>[ 90694.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90694.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90694.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90694.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90694.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90694.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90694.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90694.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90694.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90694.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90694.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90694.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90694.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90694.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90695.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90695.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90695.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90695.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90695.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90695.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90698.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90698.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90698.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90698.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90698.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90698.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90698.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90698.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90698.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90698.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90698.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90698.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90698.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90698.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90698.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 90698.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 90698.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e4810]
>[ 90698.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e4810] width 1920 pitch 7680 (/4 1920)
>[ 90699.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99380]
>[ 90699.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99380] width 1920 pitch 7680 (/4 1920)
>[ 90699.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6f0a0]
>[ 90699.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6f0a0] width 1920 pitch 7680 (/4 1920)
>[ 90699.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147270]
>[ 90699.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147270] width 1920 pitch 7680 (/4 1920)
>[ 90699.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c703d0]
>[ 90699.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c703d0] width 1920 pitch 7680 (/4 1920)
>[ 90699.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30cc0]
>[ 90699.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30cc0] width 1920 pitch 7680 (/4 1920)
>[ 90699.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[ 90699.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1920 pitch 7680 (/4 1920)
>[ 90699.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90699.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90699.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[ 90699.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1920 pitch 7680 (/4 1920)
>[ 90699.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90699.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90699.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[ 90699.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1920 pitch 7680 (/4 1920)
>[ 90699.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90699.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90700.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[ 90700.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1920 pitch 7680 (/4 1920)
>[ 90700.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90700.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90700.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[ 90700.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1920 pitch 7680 (/4 1920)
>[ 90700.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90700.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90700.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa2b10]
>[ 90700.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa2b10] width 1920 pitch 7680 (/4 1920)
>[ 90700.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c703d0]
>[ 90700.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c703d0] width 1920 pitch 7680 (/4 1920)
>[ 90700.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147270]
>[ 90700.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147270] width 1920 pitch 7680 (/4 1920)
>[ 90700.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30cc0]
>[ 90700.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30cc0] width 1920 pitch 7680 (/4 1920)
>[ 90700.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebf370]
>[ 90700.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebf370] width 1920 pitch 7680 (/4 1920)
>[ 90700.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3e150]
>[ 90700.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3e150] width 1920 pitch 7680 (/4 1920)
>[ 90700.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90701.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90701.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90701.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90701.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90701.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5c80]
>[ 90701.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5c80] width 1920 pitch 7680 (/4 1920)
>[ 90701.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90701.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90703.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90703.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90703.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90703.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90703.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90703.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90703.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90703.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90703.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90703.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90703.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90703.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90703.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90703.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90703.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90703.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90704.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90704.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90704.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90704.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90704.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90704.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef7270]
>[ 90704.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef7270] width 1920 pitch 7680 (/4 1920)
>[ 90704.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebef90]
>[ 90705.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebef90] width 1920 pitch 7680 (/4 1920)
>[ 90705.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 90705.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 90705.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 90705.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 90705.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 90705.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 90705.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 90705.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 90705.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99090]
>[ 90705.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99090] width 1920 pitch 7680 (/4 1920)
>[ 90705.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2aff0]
>[ 90705.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2aff0] width 1920 pitch 7680 (/4 1920)
>[ 90705.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2aff0]
>[ 90705.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2aff0] width 1920 pitch 7680 (/4 1920)
>[ 90705.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90705.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90705.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2aff0]
>[ 90705.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2aff0] width 1920 pitch 7680 (/4 1920)
>[ 90705.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281a120]
>[ 90706.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281a120] width 1920 pitch 7680 (/4 1920)
>[ 90706.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2aff0]
>[ 90706.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2aff0] width 1920 pitch 7680 (/4 1920)
>[ 90706.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90706.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90706.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90706.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90706.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90706.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90706.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90706.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90706.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90706.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90706.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90706.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90706.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90706.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90706.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90706.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90706.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90706.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90706.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90706.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90707.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90707.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90707.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282c0f0]
>[ 90707.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282c0f0] width 1920 pitch 7680 (/4 1920)
>[ 90707.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90707.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 90707.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 90707.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90707.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 90707.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 90707.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 90707.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 90707.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 90707.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90707.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90707.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90707.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90707.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90707.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90768.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90768.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90768.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90768.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90768.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90768.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90768.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90768.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90768.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90768.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90768.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90768.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90768.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90768.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90769.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90769.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90769.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90769.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90769.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90769.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90769.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90769.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90769.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90769.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90769.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90769.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90769.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90769.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90769.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90769.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90769.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90769.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90769.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90769.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90769.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90769.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90770.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90770.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90770.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90770.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90770.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90770.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90770.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90770.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90770.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90770.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90770.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5015bc0]
>[ 90770.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5015bc0] width 1920 pitch 7680 (/4 1920)
>[ 90796.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90796.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90835.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90835.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90835.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90835.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90836.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90836.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90855.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3e0d0]
>[ 90855.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3e0d0] width 1920 pitch 7680 (/4 1920)
>[ 90855.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5096230]
>[ 90856.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5096230] width 1920 pitch 7680 (/4 1920)
>[ 90856.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b2c0]
>[ 90856.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b2c0] width 1920 pitch 7680 (/4 1920)
>[ 90880.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59320]
>[ 90880.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59320] width 1920 pitch 7680 (/4 1920)
>[ 90880.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59320]
>[ 90880.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59320] width 1920 pitch 7680 (/4 1920)
>[ 90880.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59320]
>[ 90880.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59320] width 1920 pitch 7680 (/4 1920)
>[ 90881.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 90881.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 90881.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea5550]
>[ 90881.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea5550] width 1920 pitch 7680 (/4 1920)
>[ 90882.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90882.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90888.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[ 90888.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[ 90888.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[ 90888.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[ 90888.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90888.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90889.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[ 90889.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[ 90889.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90889.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90889.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90889.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90890.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90890.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90890.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc2fc0]
>[ 90890.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc2fc0] width 1920 pitch 7680 (/4 1920)
>[ 90890.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59320]
>[ 90890.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59320] width 1920 pitch 7680 (/4 1920)
>[ 90891.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 90891.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 90891.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5ab0]
>[ 90891.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5ab0] width 1920 pitch 7680 (/4 1920)
>[ 90892.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2d1c0]
>[ 90892.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2d1c0] width 1920 pitch 7680 (/4 1920)
>[ 90892.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6abc0]
>[ 90892.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6abc0] width 1920 pitch 7680 (/4 1920)
>[ 90892.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fea2a0]
>[ 90892.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fea2a0] width 1920 pitch 7680 (/4 1920)
>[ 90893.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90893.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90893.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90893.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90893.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5130570]
>[ 90893.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5130570] width 1920 pitch 7680 (/4 1920)
>[ 90894.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5bb30]
>[ 90894.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5bb30] width 1920 pitch 7680 (/4 1920)
>[ 90894.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90894.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90894.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90894.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 90895.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90895.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90896.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43b80]
>[ 90896.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43b80] width 1920 pitch 7680 (/4 1920)
>[ 90901.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b740]
>[ 90901.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b740] width 1920 pitch 7680 (/4 1920)
>[ 90902.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 90902.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 90902.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[ 90902.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[ 90946.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c7a0]
>[ 90946.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c7a0] width 1920 pitch 7680 (/4 1920)
>[ 90947.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 90947.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 90947.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[ 90947.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[ 91001.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0e300]
>[ 91001.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0e300] width 1920 pitch 7680 (/4 1920)
>[ 91001.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a780]
>[ 91002.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a780] width 1920 pitch 7680 (/4 1920)
>[ 91002.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9e70]
>[ 91002.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9e70] width 1920 pitch 7680 (/4 1920)
>[ 91002.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51323e0]
>[ 91002.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51323e0] width 1920 pitch 7680 (/4 1920)
>[ 91003.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51323e0]
>[ 91003.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51323e0] width 1920 pitch 7680 (/4 1920)
>[ 91003.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[ 91003.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[ 91003.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea6170]
>[ 91003.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea6170] width 1920 pitch 7680 (/4 1920)
>[ 91003.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2de0]
>[ 91003.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2de0] width 1920 pitch 7680 (/4 1920)
>[ 91004.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 91004.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 91005.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 91005.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 91005.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b120]
>[ 91005.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b120] width 1920 pitch 7680 (/4 1920)
>[ 91005.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91005.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91005.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91005.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91005.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 91005.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 91005.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 91005.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 91005.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 91005.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 91005.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e03560]
>[ 91005.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e03560] width 1920 pitch 7680 (/4 1920)
>[ 91005.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdef60]
>[ 91005.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdef60] width 1920 pitch 7680 (/4 1920)
>[ 91005.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2de0]
>[ 91005.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2de0] width 1920 pitch 7680 (/4 1920)
>[ 91005.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91005.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91005.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2de0]
>[ 91005.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2de0] width 1920 pitch 7680 (/4 1920)
>[ 91005.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91006.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91006.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd2de0]
>[ 91006.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd2de0] width 1920 pitch 7680 (/4 1920)
>[ 91006.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91006.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91006.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91006.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91058.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95b60]
>[ 91059.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95b60] width 1920 pitch 7680 (/4 1920)
>[ 91059.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050a70]
>[ 91059.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050a70] width 1920 pitch 7680 (/4 1920)
>[ 91059.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[ 91059.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[ 91059.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91059.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91059.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91059.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91059.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91059.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91059.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91060.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91060.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91060.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91060.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91060.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91060.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91060.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91060.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91060.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91060.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91060.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91060.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91060.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91060.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb4950]
>[ 91060.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb4950] width 1920 pitch 7680 (/4 1920)
>[ 91060.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 91060.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 91060.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b15810]
>[ 91060.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b15810] width 1920 pitch 7680 (/4 1920)
>[ 91060.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91060.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91060.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[ 91060.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[ 91060.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec54d0]
>[ 91060.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec54d0] width 1920 pitch 7680 (/4 1920)
>[ 91060.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[ 91060.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[ 91060.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[ 91060.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[ 91060.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 91060.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 91060.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[ 91060.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[ 91060.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 91060.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 91060.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fa590]
>[ 91060.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fa590] width 1920 pitch 7680 (/4 1920)
>[ 91060.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[ 91060.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[ 91060.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fa590]
>[ 91060.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fa590] width 1920 pitch 7680 (/4 1920)
>[ 91060.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9e70]
>[ 91060.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9e70] width 1920 pitch 7680 (/4 1920)
>[ 91060.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095a20]
>[ 91060.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095a20] width 1920 pitch 7680 (/4 1920)
>[ 91061.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 91061.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 91061.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982490]
>[ 91061.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982490] width 1920 pitch 7680 (/4 1920)
>[ 91077.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9ffe0]
>[ 91077.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9ffe0] width 1920 pitch 7680 (/4 1920)
>[ 91077.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839230]
>[ 91077.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839230] width 1920 pitch 7680 (/4 1920)
>[ 91078.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873c20]
>[ 91078.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873c20] width 1920 pitch 7680 (/4 1920)
>[ 91113.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b5d20]
>[ 91113.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b5d20] width 1920 pitch 7680 (/4 1920)
>[ 91113.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 91113.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 91114.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 91114.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 91115.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[ 91115.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[ 91115.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91115.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91115.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9d00]
>[ 91115.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9d00] width 1920 pitch 7680 (/4 1920)
>[ 91116.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e61c20]
>[ 91116.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e61c20] width 1920 pitch 7680 (/4 1920)
>[ 91117.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcc70]
>[ 91117.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcc70] width 1920 pitch 7680 (/4 1920)
>[ 91118.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec91a0]
>[ 91118.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec91a0] width 1920 pitch 7680 (/4 1920)
>[ 91118.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 91118.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 91119.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e61c20]
>[ 91119.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e61c20] width 1920 pitch 7680 (/4 1920)
>[ 91120.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b256f0]
>[ 91120.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b256f0] width 1920 pitch 7680 (/4 1920)
>[ 91231.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e244d0]
>[ 91231.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e244d0] width 1920 pitch 7680 (/4 1920)
>[ 91231.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e242d0]
>[ 91231.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e242d0] width 1920 pitch 7680 (/4 1920)
>[ 91232.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5680]
>[ 91232.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5680] width 1920 pitch 7680 (/4 1920)
>[ 91233.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24290]
>[ 91233.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24290] width 1920 pitch 7680 (/4 1920)
>[ 91339.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea49a0]
>[ 91339.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea49a0] width 1920 pitch 7680 (/4 1920)
>[ 91339.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 91339.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 91340.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 91340.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 91340.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcc70]
>[ 91340.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcc70] width 1920 pitch 7680 (/4 1920)
>[ 91409.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcc70]
>[ 91409.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcc70] width 1920 pitch 7680 (/4 1920)
>[ 91409.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 91409.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 91410.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcc70]
>[ 91410.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcc70] width 1920 pitch 7680 (/4 1920)
>[ 91415.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a98de0]
>[ 91415.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a98de0] width 1920 pitch 7680 (/4 1920)
>[ 91415.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91415.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91416.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdb6c0]
>[ 91416.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdb6c0] width 1920 pitch 7680 (/4 1920)
>[ 91417.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 91417.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 91417.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 91417.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 91419.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 91419.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 91419.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095a20]
>[ 91419.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095a20] width 1920 pitch 7680 (/4 1920)
>[ 91419.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dee600]
>[ 91419.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dee600] width 1920 pitch 7680 (/4 1920)
>[ 91420.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1e350]
>[ 91420.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1e350] width 1920 pitch 7680 (/4 1920)
>[ 91420.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1e350]
>[ 91420.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1e350] width 1920 pitch 7680 (/4 1920)
>[ 91420.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51044d0]
>[ 91420.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51044d0] width 1920 pitch 7680 (/4 1920)
>[ 91421.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51044d0]
>[ 91421.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51044d0] width 1920 pitch 7680 (/4 1920)
>[ 91434.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a780]
>[ 91434.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a780] width 1920 pitch 7680 (/4 1920)
>[ 91434.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a780]
>[ 91434.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a780] width 1920 pitch 7680 (/4 1920)
>[ 91435.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[ 91435.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1920 pitch 7680 (/4 1920)
>[ 91515.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb1530]
>[ 91515.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb1530] width 1920 pitch 7680 (/4 1920)
>[ 91515.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91516.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91516.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb1530]
>[ 91516.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb1530] width 1920 pitch 7680 (/4 1920)
>[ 91532.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d922d0]
>[ 91532.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d922d0] width 1920 pitch 7680 (/4 1920)
>[ 91532.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 91532.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 91533.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[ 91533.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1920 pitch 7680 (/4 1920)
>[ 91533.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bc50]
>[ 91533.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bc50] width 1920 pitch 7680 (/4 1920)
>[ 91534.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9f10]
>[ 91534.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9f10] width 1920 pitch 7680 (/4 1920)
>[ 91542.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[ 91542.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1920 pitch 7680 (/4 1920)
>[ 91542.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bc50]
>[ 91542.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bc50] width 1920 pitch 7680 (/4 1920)
>[ 91543.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f200]
>[ 91543.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f200] width 1920 pitch 7680 (/4 1920)
>[ 91545.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[ 91545.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[ 91545.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[ 91545.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[ 91546.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bc50]
>[ 91546.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bc50] width 1920 pitch 7680 (/4 1920)
>[ 91546.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4e6a0]
>[ 91546.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4e6a0] width 1920 pitch 7680 (/4 1920)
>[ 91546.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1cb60]
>[ 91546.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1cb60] width 1920 pitch 7680 (/4 1920)
>[ 91547.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f489f0]
>[ 91547.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f489f0] width 1920 pitch 7680 (/4 1920)
>[ 91548.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[ 91548.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1920 pitch 7680 (/4 1920)
>[ 91548.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b640]
>[ 91548.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b640] width 1920 pitch 7680 (/4 1920)
>[ 91548.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb0580]
>[ 91548.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb0580] width 1920 pitch 7680 (/4 1920)
>[ 91548.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c530]
>[ 91548.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c530] width 1920 pitch 7680 (/4 1920)
>[ 91548.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[ 91548.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1920 pitch 7680 (/4 1920)
>[ 91549.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c299b0]
>[ 91549.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c299b0] width 1920 pitch 7680 (/4 1920)
>[ 91549.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[ 91549.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[ 91550.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[ 91550.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[ 91591.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d400]
>[ 91591.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d400] width 1920 pitch 7680 (/4 1920)
>[ 91591.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1efd0]
>[ 91591.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1efd0] width 1920 pitch 7680 (/4 1920)
>[ 91592.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e59e30]
>[ 91592.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e59e30] width 1920 pitch 7680 (/4 1920)
>[ 91592.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f5e0]
>[ 91592.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f5e0] width 1920 pitch 7680 (/4 1920)
>[ 91592.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d400]
>[ 91592.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d400] width 1920 pitch 7680 (/4 1920)
>[ 91627.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6c10]
>[ 91627.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6c10] width 1920 pitch 7680 (/4 1920)
>[ 91627.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea5470]
>[ 91627.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea5470] width 1920 pitch 7680 (/4 1920)
>[ 91628.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80b10]
>[ 91628.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80b10] width 1920 pitch 7680 (/4 1920)
>[ 91638.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4044c40]
>[ 91638.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4044c40] width 1920 pitch 7680 (/4 1920)
>[ 91639.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4044c40]
>[ 91639.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4044c40] width 1920 pitch 7680 (/4 1920)
>[ 91639.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 91639.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 91670.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 91670.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 91670.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f61ea0]
>[ 91670.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f61ea0] width 1920 pitch 7680 (/4 1920)
>[ 91670.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d400]
>[ 91671.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d400] width 1920 pitch 7680 (/4 1920)
>[ 91674.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[ 91674.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1920 pitch 7680 (/4 1920)
>[ 91674.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404aee0]
>[ 91674.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404aee0] width 1920 pitch 7680 (/4 1920)
>[ 91674.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91674.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91675.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[ 91675.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1920 pitch 7680 (/4 1920)
>[ 91675.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 91675.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 91675.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[ 91675.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[ 91675.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efc4c0]
>[ 91675.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efc4c0] width 1920 pitch 7680 (/4 1920)
>[ 91676.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 91676.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 91691.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f5e0]
>[ 91691.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f5e0] width 1920 pitch 7680 (/4 1920)
>[ 91691.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 91691.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 91691.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873670]
>[ 91691.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873670] width 1920 pitch 7680 (/4 1920)
>[ 91692.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95270]
>[ 91692.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95270] width 1920 pitch 7680 (/4 1920)
>[ 91724.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b324a0]
>[ 91724.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b324a0] width 1920 pitch 7680 (/4 1920)
>[ 91725.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36cc0]
>[ 91725.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36cc0] width 1920 pitch 7680 (/4 1920)
>[ 91725.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04e90]
>[ 91725.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04e90] width 1920 pitch 7680 (/4 1920)
>[ 91783.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[ 91783.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[ 91785.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be18b0]
>[ 91785.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be18b0] width 1920 pitch 7680 (/4 1920)
>[ 91818.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114b30]
>[ 91818.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114b30] width 1920 pitch 7680 (/4 1920)
>[ 91856.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb7ac0]
>[ 91856.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb7ac0] width 1920 pitch 7680 (/4 1920)
>[ 91856.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8270]
>[ 91856.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8270] width 1920 pitch 7680 (/4 1920)
>[ 91857.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6c10]
>[ 91857.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6c10] width 1920 pitch 7680 (/4 1920)
>[ 91857.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f098b0]
>[ 91857.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f098b0] width 1920 pitch 7680 (/4 1920)
>[ 91858.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8270]
>[ 91858.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8270] width 1920 pitch 7680 (/4 1920)
>[ 91858.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be18b0]
>[ 91858.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be18b0] width 1920 pitch 7680 (/4 1920)
>[ 91859.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873670]
>[ 91859.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873670] width 1920 pitch 7680 (/4 1920)
>[ 91859.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 91859.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 91861.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48600]
>[ 91861.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48600] width 1920 pitch 7680 (/4 1920)
>[ 91861.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6c10]
>[ 91861.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6c10] width 1920 pitch 7680 (/4 1920)
>[ 91863.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6bbd0]
>[ 91863.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6bbd0] width 1920 pitch 7680 (/4 1920)
>[ 91865.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873670]
>[ 91865.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873670] width 1920 pitch 7680 (/4 1920)
>[ 91865.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9860]
>[ 91865.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9860] width 1920 pitch 7680 (/4 1920)
>[ 91865.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a07750]
>[ 91865.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a07750] width 1920 pitch 7680 (/4 1920)
>[ 91866.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb0580]
>[ 91866.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb0580] width 1920 pitch 7680 (/4 1920)
>[ 91867.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91867.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91867.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dee600]
>[ 91867.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dee600] width 1920 pitch 7680 (/4 1920)
>[ 91867.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91867.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91929.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91929.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91930.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece720]
>[ 91930.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece720] width 1920 pitch 7680 (/4 1920)
>[ 91930.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91930.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91930.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 91930.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 91931.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dee600]
>[ 91931.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dee600] width 1920 pitch 7680 (/4 1920)
>[ 91932.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dee600]
>[ 91932.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dee600] width 1920 pitch 7680 (/4 1920)
>[ 91932.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dee600]
>[ 91932.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dee600] width 1920 pitch 7680 (/4 1920)
>[ 91932.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99960]
>[ 91932.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99960] width 1920 pitch 7680 (/4 1920)
>[ 91932.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[ 91932.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[ 91933.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3c00]
>[ 91933.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3c00] width 1920 pitch 7680 (/4 1920)
>[ 91933.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2f010]
>[ 91933.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2f010] width 1920 pitch 7680 (/4 1920)
>[ 91933.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99960]
>[ 91933.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99960] width 1920 pitch 7680 (/4 1920)
>[ 91933.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[ 91933.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[ 91934.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[ 91934.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1920 pitch 7680 (/4 1920)
>[ 91934.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0f780]
>[ 91934.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0f780] width 1920 pitch 7680 (/4 1920)
>[ 91934.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c530]
>[ 91934.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c530] width 1920 pitch 7680 (/4 1920)
>[ 91935.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1b640]
>[ 91935.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1b640] width 1920 pitch 7680 (/4 1920)
>[ 91943.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d400]
>[ 91943.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d400] width 1920 pitch 7680 (/4 1920)
>[ 91943.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51044d0]
>[ 91943.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51044d0] width 1920 pitch 7680 (/4 1920)
>[ 91943.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5114b30]
>[ 91943.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5114b30] width 1920 pitch 7680 (/4 1920)
>[ 91944.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6c10]
>[ 91944.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6c10] width 1920 pitch 7680 (/4 1920)
>[ 91944.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 91944.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 91945.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f081c0]
>[ 91945.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f081c0] width 1920 pitch 7680 (/4 1920)
>[ 91945.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be18b0]
>[ 91945.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be18b0] width 1920 pitch 7680 (/4 1920)
>[ 92210.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[ 92211.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[ 92211.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f14140]
>[ 92211.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f14140] width 1920 pitch 7680 (/4 1920)
>[ 92211.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d60f20]
>[ 92211.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d60f20] width 1920 pitch 7680 (/4 1920)
>[ 92218.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f530]
>[ 92218.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f530] width 1920 pitch 7680 (/4 1920)
>[ 92218.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11550]
>[ 92218.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11550] width 1920 pitch 7680 (/4 1920)
>[ 92219.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e950]
>[ 92219.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e950] width 1920 pitch 7680 (/4 1920)
>[ 92219.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed73d0]
>[ 92219.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed73d0] width 1920 pitch 7680 (/4 1920)
>[ 92219.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[ 92219.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[ 92219.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059c80]
>[ 92219.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059c80] width 1920 pitch 7680 (/4 1920)
>[ 92219.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[ 92219.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1920 pitch 7680 (/4 1920)
>[ 92220.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c7a0]
>[ 92220.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c7a0] width 1920 pitch 7680 (/4 1920)
>[ 92259.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec9860]
>[ 92259.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec9860] width 1920 pitch 7680 (/4 1920)
>[ 92261.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00cc0]
>[ 92261.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00cc0] width 1920 pitch 7680 (/4 1920)
>[ 92272.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873670]
>[ 92272.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873670] width 1920 pitch 7680 (/4 1920)
>[ 92272.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00cc0]
>[ 92272.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00cc0] width 1920 pitch 7680 (/4 1920)
>[ 92272.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e950]
>[ 92272.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e950] width 1920 pitch 7680 (/4 1920)
>[ 92272.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[ 92272.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[ 92273.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404d5d0]
>[ 92273.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404d5d0] width 1920 pitch 7680 (/4 1920)
>[ 92274.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835da0]
>[ 92274.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835da0] width 1920 pitch 7680 (/4 1920)
>[ 92275.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[ 92275.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1920 pitch 7680 (/4 1920)
>[ 92275.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[ 92275.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1920 pitch 7680 (/4 1920)
>[ 92275.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf47d0]
>[ 92275.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf47d0] width 1920 pitch 7680 (/4 1920)
>[ 92275.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2ad50]
>[ 92275.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2ad50] width 1920 pitch 7680 (/4 1920)
>[ 92275.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf47d0]
>[ 92276.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf47d0] width 1920 pitch 7680 (/4 1920)
>[ 92276.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 92276.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 92276.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be1300]
>[ 92276.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be1300] width 1920 pitch 7680 (/4 1920)
>[ 92276.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 92276.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 92276.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be1300]
>[ 92276.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be1300] width 1920 pitch 7680 (/4 1920)
>[ 92276.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 92276.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 92276.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be1300]
>[ 92276.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be1300] width 1920 pitch 7680 (/4 1920)
>[ 92276.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 92276.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 92276.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be1300]
>[ 92276.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be1300] width 1920 pitch 7680 (/4 1920)
>[ 92276.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1b330]
>[ 92276.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1b330] width 1920 pitch 7680 (/4 1920)
>[ 92276.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[ 92276.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[ 92278.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcbcf0]
>[ 92278.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcbcf0] width 1920 pitch 7680 (/4 1920)
>[ 92278.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f3200]
>[ 92278.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f3200] width 1920 pitch 7680 (/4 1920)
>[ 92278.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859c30]
>[ 92278.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859c30] width 1920 pitch 7680 (/4 1920)
>[ 92278.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[ 92278.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1920 pitch 7680 (/4 1920)
>[ 92279.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059c80]
>[ 92279.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059c80] width 1920 pitch 7680 (/4 1920)
>[ 92283.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fec0]
>[ 92283.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fec0] width 1920 pitch 7680 (/4 1920)
>[ 92284.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f18c80]
>[ 92284.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f18c80] width 1920 pitch 7680 (/4 1920)
>[ 92285.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01a30]
>[ 92285.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01a30] width 1920 pitch 7680 (/4 1920)
>[ 92285.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[ 92285.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[ 92285.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[ 92285.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[ 92285.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[ 92285.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[ 92285.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[ 92285.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[ 92285.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023450]
>[ 92285.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023450] width 1920 pitch 7680 (/4 1920)
>[ 92286.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28353e0]
>[ 92286.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28353e0] width 1920 pitch 7680 (/4 1920)
>[ 92286.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6db20]
>[ 92286.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6db20] width 1920 pitch 7680 (/4 1920)
>[ 92286.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[ 92286.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[ 92286.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[ 92286.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[ 92287.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80a60]
>[ 92287.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80a60] width 1920 pitch 7680 (/4 1920)
>[ 92287.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[ 92287.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[ 92310.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[ 92310.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1920 pitch 7680 (/4 1920)
>[ 92311.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9f10]
>[ 92311.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9f10] width 1920 pitch 7680 (/4 1920)
>[ 92311.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[ 92311.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[ 92311.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7b60]
>[ 92311.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7b60] width 1920 pitch 7680 (/4 1920)
>[ 92312.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec130]
>[ 92312.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec130] width 1920 pitch 7680 (/4 1920)
>[ 92312.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f14140]
>[ 92312.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f14140] width 1920 pitch 7680 (/4 1920)
>[ 92330.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d950]
>[ 92330.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d950] width 1920 pitch 7680 (/4 1920)
>[ 92330.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eecc70]
>[ 92330.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eecc70] width 1920 pitch 7680 (/4 1920)
>[ 92331.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea33d0]
>[ 92331.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea33d0] width 1920 pitch 7680 (/4 1920)
>[ 92331.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831560]
>[ 92331.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831560] width 1920 pitch 7680 (/4 1920)
>[ 92350.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fda0]
>[ 92350.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fda0] width 1920 pitch 7680 (/4 1920)
>[ 92350.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fae0]
>[ 92350.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fae0] width 1920 pitch 7680 (/4 1920)
>[ 92350.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e51d20]
>[ 92350.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e51d20] width 1920 pitch 7680 (/4 1920)
>[ 92350.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404fb10]
>[ 92350.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404fb10] width 1920 pitch 7680 (/4 1920)
>[ 92351.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f31160]
>[ 92351.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f31160] width 1920 pitch 7680 (/4 1920)
>[ 92701.512] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[ 92701.513] (II) RADEON(0): Using hsync ranges from config file
>[ 92701.513] (II) RADEON(0): Using vrefresh ranges from config file
>[ 92701.513] (II) RADEON(0): Printing DDC gathered Modelines:
>[ 92701.513] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[ 92701.513] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[ 92701.513] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[ 92791.749] (II) RADEON(0): RADEONSaveScreen(2)
>[ 92791.749] (II) RADEON(0): RADEONSaveScreen(0)
>[124526.234] (II) RADEON(0): RADEONSaveScreen(1)
>[124539.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3cf00]
>[124539.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3cf00] width 1920 pitch 7680 (/4 1920)
>[124546.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb23d0]
>[124546.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb23d0] width 1920 pitch 7680 (/4 1920)
>[124546.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3cf00]
>[124546.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3cf00] width 1920 pitch 7680 (/4 1920)
>[124546.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb23d0]
>[124546.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb23d0] width 1920 pitch 7680 (/4 1920)
>[124578.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6bb0]
>[124578.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6bb0] width 1920 pitch 7680 (/4 1920)
>[124585.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92fe0]
>[124585.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92fe0] width 1920 pitch 7680 (/4 1920)
>[124585.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2bd00]
>[124586.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2bd00] width 1920 pitch 7680 (/4 1920)
>[124586.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2be00]
>[124586.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2be00] width 1920 pitch 7680 (/4 1920)
>[124587.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092f20]
>[124587.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092f20] width 1920 pitch 7680 (/4 1920)
>[124588.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092f20]
>[124588.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092f20] width 1920 pitch 7680 (/4 1920)
>[124588.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124588.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124588.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124589.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124589.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b129b0]
>[124589.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b129b0] width 1920 pitch 7680 (/4 1920)
>[124589.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4fcb0]
>[124589.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4fcb0] width 1920 pitch 7680 (/4 1920)
>[124589.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b129b0]
>[124589.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b129b0] width 1920 pitch 7680 (/4 1920)
>[124589.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b131e0]
>[124589.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b131e0] width 1920 pitch 7680 (/4 1920)
>[124589.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b129b0]
>[124589.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b129b0] width 1920 pitch 7680 (/4 1920)
>[124589.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b131e0]
>[124589.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b131e0] width 1920 pitch 7680 (/4 1920)
>[124589.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b129b0]
>[124589.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b129b0] width 1920 pitch 7680 (/4 1920)
>[124589.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124589.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124591.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124591.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124595.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124595.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124595.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124595.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124595.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124595.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124595.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124595.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124595.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124595.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124596.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124596.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124596.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124596.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124596.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124596.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124596.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124596.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124596.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124596.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124596.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124596.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124596.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124596.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124596.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124596.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124596.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c79280]
>[124596.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c79280] width 1920 pitch 7680 (/4 1920)
>[124596.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e620]
>[124596.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e620] width 1920 pitch 7680 (/4 1920)
>[124596.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[124596.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1920 pitch 7680 (/4 1920)
>[124596.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124596.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124596.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[124596.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1920 pitch 7680 (/4 1920)
>[124596.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124596.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124596.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[124596.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1920 pitch 7680 (/4 1920)
>[124596.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e620]
>[124596.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e620] width 1920 pitch 7680 (/4 1920)
>[124596.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a8c00]
>[124596.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a8c00] width 1920 pitch 7680 (/4 1920)
>[124596.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124596.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124596.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e620]
>[124596.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e620] width 1920 pitch 7680 (/4 1920)
>[124596.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124596.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124598.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4640]
>[124598.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4640] width 1920 pitch 7680 (/4 1920)
>[124605.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[124605.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1920 pitch 7680 (/4 1920)
>[124608.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be46a0]
>[124608.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be46a0] width 1920 pitch 7680 (/4 1920)
>[124641.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124641.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124641.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124641.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124641.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124641.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124641.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124641.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124641.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124641.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124641.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124641.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124641.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124641.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124641.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124642.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124642.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124642.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124642.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124642.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124642.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124642.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124642.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124642.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124642.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124642.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124642.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124642.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124642.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124644.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124644.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124644.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124644.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124644.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124644.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124644.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124644.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124644.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124644.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124644.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124645.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124645.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124645.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124645.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124645.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124645.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124645.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124645.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c50]
>[124645.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c50] width 1920 pitch 7680 (/4 1920)
>[124645.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94d00]
>[124645.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94d00] width 1920 pitch 7680 (/4 1920)
>[124645.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f30f70]
>[124645.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f30f70] width 1920 pitch 7680 (/4 1920)
>[124661.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[124661.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1920 pitch 7680 (/4 1920)
>[124672.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124672.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124672.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124672.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124672.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[124672.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1920 pitch 7680 (/4 1920)
>[124672.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a1380]
>[124672.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a1380] width 1920 pitch 7680 (/4 1920)
>[124672.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6df10]
>[124672.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6df10] width 1920 pitch 7680 (/4 1920)
>[124672.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124672.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124672.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8cc60]
>[124672.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8cc60] width 1920 pitch 7680 (/4 1920)
>[124672.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124672.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124672.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3edd0]
>[124672.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3edd0] width 1920 pitch 7680 (/4 1920)
>[124673.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124673.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124674.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124674.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124675.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124675.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124675.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124675.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124675.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124675.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124675.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124675.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124675.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124675.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124675.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[124675.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1920 pitch 7680 (/4 1920)
>[124676.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124676.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124676.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124676.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124677.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[124677.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1920 pitch 7680 (/4 1920)
>[124677.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6df10]
>[124677.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6df10] width 1920 pitch 7680 (/4 1920)
>[124677.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3edd0]
>[124677.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3edd0] width 1920 pitch 7680 (/4 1920)
>[124679.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124679.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124679.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124679.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124680.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6df10]
>[124680.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6df10] width 1920 pitch 7680 (/4 1920)
>[124680.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124680.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124680.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3edd0]
>[124680.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3edd0] width 1920 pitch 7680 (/4 1920)
>[124680.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124680.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124680.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124680.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124680.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124680.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124680.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124680.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124681.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124681.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124681.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124681.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124682.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124682.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124682.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[124682.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1920 pitch 7680 (/4 1920)
>[124682.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124682.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124683.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[124683.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1920 pitch 7680 (/4 1920)
>[124683.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124683.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124683.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[124683.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[124684.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124684.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124684.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[124684.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[124684.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124684.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124685.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[124685.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[124685.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124685.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124686.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63900]
>[124686.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63900] width 1920 pitch 7680 (/4 1920)
>[124686.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[124686.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[124687.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124687.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124687.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124687.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124688.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124688.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124688.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124688.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124688.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124688.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124688.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124688.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124688.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124688.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124688.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124688.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124689.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124689.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124689.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124689.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124689.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124689.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124689.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124689.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124689.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124690.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124690.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[124690.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1920 pitch 7680 (/4 1920)
>[124691.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124691.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124692.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63900]
>[124692.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63900] width 1920 pitch 7680 (/4 1920)
>[124693.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[124693.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[124696.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6df10]
>[124696.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6df10] width 1920 pitch 7680 (/4 1920)
>[124697.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124697.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124697.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124697.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124697.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124697.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124697.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124697.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124698.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124698.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124698.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124698.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124699.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124699.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124699.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124699.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124700.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124700.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124701.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124701.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124701.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124701.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124701.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124701.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124701.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124701.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124702.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124702.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124702.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124702.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124702.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124702.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124702.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124702.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124702.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124702.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124702.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124702.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124703.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124703.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124703.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124703.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124704.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124704.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124704.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124704.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124705.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124705.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124705.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124705.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124705.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124705.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124705.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124705.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124705.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124705.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124705.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124705.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124705.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[124705.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[124705.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124705.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124705.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124705.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124705.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[124705.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1920 pitch 7680 (/4 1920)
>[124706.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c614a0]
>[124706.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c614a0] width 1920 pitch 7680 (/4 1920)
>[124707.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4c30]
>[124707.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4c30] width 1920 pitch 7680 (/4 1920)
>[124707.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[124707.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1920 pitch 7680 (/4 1920)
>[124707.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4c30]
>[124707.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4c30] width 1920 pitch 7680 (/4 1920)
>[124708.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[124708.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1920 pitch 7680 (/4 1920)
>[124708.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec5500]
>[124708.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec5500] width 1920 pitch 7680 (/4 1920)
>[124708.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124708.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124708.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec5500]
>[124708.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec5500] width 1920 pitch 7680 (/4 1920)
>[124709.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124709.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124709.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124709.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124709.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124710.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47900]
>[124710.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47900] width 1920 pitch 7680 (/4 1920)
>[124710.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124710.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124711.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3edd0]
>[124711.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3edd0] width 1920 pitch 7680 (/4 1920)
>[124712.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[124712.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[124713.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124713.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124713.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124713.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124714.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124714.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124714.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124714.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124715.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124715.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124715.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124715.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124716.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124716.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124716.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124716.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124716.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124716.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124716.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a244f0]
>[124716.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a244f0] width 1920 pitch 7680 (/4 1920)
>[124716.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[124716.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[124717.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[124718.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1920 pitch 7680 (/4 1920)
>[124718.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[124718.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[124718.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124718.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124718.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124718.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124718.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124718.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124718.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124718.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124718.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124718.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124718.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124718.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124719.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124719.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124719.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124719.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124719.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124719.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124719.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124719.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124719.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124719.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124719.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124719.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124719.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124719.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124719.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826590]
>[124719.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826590] width 1920 pitch 7680 (/4 1920)
>[124720.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124720.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124720.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124720.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124721.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124721.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124721.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124721.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124721.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124721.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124721.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124721.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124721.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124721.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124721.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124721.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124721.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124721.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124721.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124721.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124721.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e388c0]
>[124721.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e388c0] width 1920 pitch 7680 (/4 1920)
>[124722.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124722.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124722.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124722.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124722.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124722.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124722.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124722.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124722.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124722.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124722.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124722.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124722.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124722.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124722.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124722.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124722.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124722.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124723.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124723.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edbed0]
>[124723.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edbed0] width 1920 pitch 7680 (/4 1920)
>[124723.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124723.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51162c0]
>[124723.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51162c0] width 1920 pitch 7680 (/4 1920)
>[124723.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124723.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124723.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124723.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124723.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124723.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124723.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124723.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124723.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124723.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124723.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124724.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124724.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124724.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124724.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124724.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124724.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124724.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124724.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124724.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124724.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124724.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124724.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124724.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124724.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124724.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124724.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124724.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124724.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124724.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ea2c0]
>[124724.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ea2c0] width 1920 pitch 7680 (/4 1920)
>[124822.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4170]
>[124822.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4170] width 1920 pitch 7680 (/4 1920)
>[124824.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124824.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124824.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396d940]
>[124824.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396d940] width 1920 pitch 7680 (/4 1920)
>[124824.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[124824.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[124824.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124824.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124824.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7c40]
>[124824.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7c40] width 1920 pitch 7680 (/4 1920)
>[124824.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124824.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124824.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391cca0]
>[124824.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391cca0] width 1920 pitch 7680 (/4 1920)
>[124824.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[124824.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[124824.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e05b0]
>[124824.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e05b0] width 1920 pitch 7680 (/4 1920)
>[124824.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc22a0]
>[124824.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc22a0] width 1920 pitch 7680 (/4 1920)
>[124825.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[124825.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[124838.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124838.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124838.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a90000]
>[124838.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a90000] width 1920 pitch 7680 (/4 1920)
>[124838.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124838.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124838.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124838.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124838.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124838.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124838.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6a230]
>[124839.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6a230] width 1920 pitch 7680 (/4 1920)
>[124839.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124839.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124839.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a90000]
>[124839.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a90000] width 1920 pitch 7680 (/4 1920)
>[124839.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124839.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124839.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc22a0]
>[124839.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc22a0] width 1920 pitch 7680 (/4 1920)
>[124839.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124839.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124839.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[124839.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1920 pitch 7680 (/4 1920)
>[124845.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[124845.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[124845.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[124845.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[124845.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391cca0]
>[124845.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391cca0] width 1920 pitch 7680 (/4 1920)
>[124845.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124845.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124845.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[124845.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[124845.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[124845.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1920 pitch 7680 (/4 1920)
>[124845.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831950]
>[124845.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831950] width 1920 pitch 7680 (/4 1920)
>[124845.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50930c0]
>[124845.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50930c0] width 1920 pitch 7680 (/4 1920)
>[124845.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124845.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124846.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391f730]
>[124846.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391f730] width 1920 pitch 7680 (/4 1920)
>[124846.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e05b0]
>[124846.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e05b0] width 1920 pitch 7680 (/4 1920)
>[124846.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124846.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124846.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc22a0]
>[124846.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc22a0] width 1920 pitch 7680 (/4 1920)
>[124846.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124846.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124846.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[124846.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[124846.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124846.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124846.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f780]
>[124846.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f780] width 1920 pitch 7680 (/4 1920)
>[124846.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124846.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124846.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e05b0]
>[124846.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e05b0] width 1920 pitch 7680 (/4 1920)
>[124846.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc22a0]
>[124846.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc22a0] width 1920 pitch 7680 (/4 1920)
>[124846.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54b50]
>[124847.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54b50] width 1920 pitch 7680 (/4 1920)
>[124847.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6a230]
>[124847.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6a230] width 1920 pitch 7680 (/4 1920)
>[124847.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124847.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124847.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[124847.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1920 pitch 7680 (/4 1920)
>[124847.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[124847.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[124847.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24c80]
>[124847.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24c80] width 1920 pitch 7680 (/4 1920)
>[124847.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[124847.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[124902.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7cb0]
>[124902.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7cb0] width 1920 pitch 7680 (/4 1920)
>[124902.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8c50]
>[124902.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8c50] width 1920 pitch 7680 (/4 1920)
>[124902.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[124902.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1920 pitch 7680 (/4 1920)
>[124902.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124902.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124902.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[124902.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[124902.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[124902.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1920 pitch 7680 (/4 1920)
>[124902.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7c40]
>[124902.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7c40] width 1920 pitch 7680 (/4 1920)
>[124902.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124902.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124902.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[124902.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[124902.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4f90]
>[124902.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4f90] width 1920 pitch 7680 (/4 1920)
>[124902.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831950]
>[124902.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831950] width 1920 pitch 7680 (/4 1920)
>[124902.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[124902.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[124903.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[124903.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1920 pitch 7680 (/4 1920)
>[124903.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391cca0]
>[124903.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391cca0] width 1920 pitch 7680 (/4 1920)
>[124903.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124903.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124903.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54b50]
>[124903.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54b50] width 1920 pitch 7680 (/4 1920)
>[124903.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[124903.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[124903.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124903.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124903.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaacf0]
>[124903.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaacf0] width 1920 pitch 7680 (/4 1920)
>[124903.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826680]
>[124903.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826680] width 1920 pitch 7680 (/4 1920)
>[124903.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8c50]
>[124903.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8c50] width 1920 pitch 7680 (/4 1920)
>[124903.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f780]
>[124903.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f780] width 1920 pitch 7680 (/4 1920)
>[124903.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[124903.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1920 pitch 7680 (/4 1920)
>[124903.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[124903.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[124903.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[124903.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[124903.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[124903.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1920 pitch 7680 (/4 1920)
>[124903.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7c40]
>[124903.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7c40] width 1920 pitch 7680 (/4 1920)
>[124903.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[124903.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[124903.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[124903.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[124903.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb4f90]
>[124903.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb4f90] width 1920 pitch 7680 (/4 1920)
>[124903.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831950]
>[124903.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831950] width 1920 pitch 7680 (/4 1920)
>[124903.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[124903.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[124903.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[124903.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1920 pitch 7680 (/4 1920)
>[124903.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391cca0]
>[124903.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391cca0] width 1920 pitch 7680 (/4 1920)
>[124908.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[124908.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[124908.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124908.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124908.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[124908.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[124908.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[124908.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[124908.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab5ee0]
>[124908.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab5ee0] width 1920 pitch 7680 (/4 1920)
>[124908.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[124908.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[124908.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3edd0]
>[124908.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3edd0] width 1920 pitch 7680 (/4 1920)
>[124908.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405fdf0]
>[124908.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405fdf0] width 1920 pitch 7680 (/4 1920)
>[124908.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a1280]
>[124909.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a1280] width 1920 pitch 7680 (/4 1920)
>[124909.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[124909.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1920 pitch 7680 (/4 1920)
>[124909.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[124909.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[124909.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[124909.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1920 pitch 7680 (/4 1920)
>[124909.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[124909.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[124909.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[124909.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[124909.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2831950]
>[124909.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2831950] width 1920 pitch 7680 (/4 1920)
>[124909.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8c50]
>[124909.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8c50] width 1920 pitch 7680 (/4 1920)
>[124909.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ee10]
>[124909.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ee10] width 1920 pitch 7680 (/4 1920)
>[124909.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[124909.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1920 pitch 7680 (/4 1920)
>[124909.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[124909.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[124909.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826680]
>[124909.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826680] width 1920 pitch 7680 (/4 1920)
>[124909.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b54b50]
>[124909.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b54b50] width 1920 pitch 7680 (/4 1920)
>[124909.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[124909.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1920 pitch 7680 (/4 1920)
>[124909.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfda20]
>[124909.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfda20] width 1920 pitch 7680 (/4 1920)
>[124909.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd730]
>[124909.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd730] width 1920 pitch 7680 (/4 1920)
>[124909.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6d8d0]
>[124909.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6d8d0] width 1920 pitch 7680 (/4 1920)
>[124909.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[124909.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[124938.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ce70]
>[124938.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ce70] width 1920 pitch 7680 (/4 1920)
>[124949.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[124949.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1920 pitch 7680 (/4 1920)
>[124949.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c561a0]
>[124949.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c561a0] width 1920 pitch 7680 (/4 1920)
>[124949.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76110]
>[124949.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76110] width 1920 pitch 7680 (/4 1920)
>[124949.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[124949.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1920 pitch 7680 (/4 1920)
>[124949.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db28b0]
>[124949.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db28b0] width 1920 pitch 7680 (/4 1920)
>[124949.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09fc0]
>[124949.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09fc0] width 1920 pitch 7680 (/4 1920)
>[125038.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30f70]
>[125038.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30f70] width 1920 pitch 7680 (/4 1920)
>[125039.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e880]
>[125039.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e880] width 1920 pitch 7680 (/4 1920)
>[125040.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125040.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125040.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e83ec0]
>[125041.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e83ec0] width 1920 pitch 7680 (/4 1920)
>[125041.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[125041.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1920 pitch 7680 (/4 1920)
>[125041.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[125041.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[125041.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125041.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125041.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125041.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125041.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125041.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125041.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125041.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125041.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125041.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125041.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125041.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125041.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125041.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125041.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125041.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125046.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125046.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125046.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[125046.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[125047.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecb470]
>[125047.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecb470] width 1920 pitch 7680 (/4 1920)
>[125048.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[125048.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1920 pitch 7680 (/4 1920)
>[125048.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[125048.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[125048.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125049.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125068.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecca90]
>[125068.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecca90] width 1920 pitch 7680 (/4 1920)
>[125068.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392f2e0]
>[125068.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392f2e0] width 1920 pitch 7680 (/4 1920)
>[125068.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125068.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125068.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[125068.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[125068.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125068.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125068.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[125068.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[125068.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125069.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125069.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[125069.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[125069.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125069.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125069.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[125069.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[125069.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125069.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125069.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[125069.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[125071.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125071.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125071.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125071.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125071.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125071.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125071.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125071.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125071.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125071.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125071.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125071.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125071.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125071.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125071.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125071.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125071.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125071.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125071.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125071.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125072.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125072.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125072.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125072.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125072.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125072.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125072.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125072.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125072.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125072.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125072.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125072.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125072.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125072.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125072.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125072.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125072.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125072.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125072.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[125072.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[125073.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125074.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[125074.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[125074.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125074.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[125074.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[125074.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125074.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[125074.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[125074.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125074.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[125074.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[125074.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125074.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[125074.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[125074.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125074.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125075.038] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[125075.038] (II) RADEON(0): Using hsync ranges from config file
>[125075.038] (II) RADEON(0): Using vrefresh ranges from config file
>[125075.038] (II) RADEON(0): Printing DDC gathered Modelines:
>[125075.038] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[125075.038] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[125075.038] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[125075.038] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[125075.038] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[125075.038] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[125075.038] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[125075.038] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[125075.038] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[125075.038] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[125075.038] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[125078.762] (II) AIGLX: Suspending AIGLX clients for VT switch
>[125078.779] (II) RADEON(0): RADEONLeaveVT_KMS
>[125078.799] (II) RADEON(0): Ok, leaving now...
>[125084.906] (II) AIGLX: Resuming AIGLX clients after VT switch
>[125084.906] (II) RADEON(0): RADEONEnterVT_KMS
>[125085.606] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[125085.606] (II) RADEON(0): Using hsync ranges from config file
>[125085.606] (II) RADEON(0): Using vrefresh ranges from config file
>[125085.606] (II) RADEON(0): Printing DDC gathered Modelines:
>[125085.606] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[125085.606] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[125085.606] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[125085.606] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[125085.606] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[125085.606] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[125085.606] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[125085.606] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[125085.606] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[125085.606] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[125085.606] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[125085.610] (II) RADEON(0): RADEONSaveScreen(2)
>[125085.648] (**) Option "Device" "/dev/input/event5"
>[125085.657] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[125095.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[125095.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1920 pitch 7680 (/4 1920)
>[125095.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[125095.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[125095.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125095.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125095.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[125095.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[125095.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125095.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125095.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e73ca0]
>[125095.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e73ca0] width 1920 pitch 7680 (/4 1920)
>[125095.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125095.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125095.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[125095.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1920 pitch 7680 (/4 1920)
>[125095.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125095.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125095.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125095.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125095.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125095.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125095.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de33c0]
>[125095.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de33c0] width 1920 pitch 7680 (/4 1920)
>[125095.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125095.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125095.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[125095.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[125096.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[125096.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[125097.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125097.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125097.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7c40]
>[125097.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7c40] width 1920 pitch 7680 (/4 1920)
>[125097.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[125097.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1920 pitch 7680 (/4 1920)
>[125097.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[125097.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1920 pitch 7680 (/4 1920)
>[125097.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[125097.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[125097.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092090]
>[125097.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092090] width 1920 pitch 7680 (/4 1920)
>[125097.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125097.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125098.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[125098.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[125098.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3951e10]
>[125098.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3951e10] width 1920 pitch 7680 (/4 1920)
>[125098.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[125098.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[125098.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3a60]
>[125098.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3a60] width 1920 pitch 7680 (/4 1920)
>[125098.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc6800]
>[125098.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc6800] width 1920 pitch 7680 (/4 1920)
>[125098.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[125098.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[125098.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[125098.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[125098.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[125098.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[125098.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125098.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125098.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023450]
>[125098.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023450] width 1920 pitch 7680 (/4 1920)
>[125098.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125098.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125098.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125098.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125098.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[125098.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1920 pitch 7680 (/4 1920)
>[125098.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2bfc0]
>[125098.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2bfc0] width 1920 pitch 7680 (/4 1920)
>[125098.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504dce0]
>[125098.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504dce0] width 1920 pitch 7680 (/4 1920)
>[125099.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6f2b0]
>[125099.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6f2b0] width 1920 pitch 7680 (/4 1920)
>[125099.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505ed30]
>[125099.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505ed30] width 1920 pitch 7680 (/4 1920)
>[125099.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125099.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125099.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[125099.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[125099.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861880]
>[125099.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861880] width 1920 pitch 7680 (/4 1920)
>[125099.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[125099.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1920 pitch 7680 (/4 1920)
>[125099.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[125099.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1920 pitch 7680 (/4 1920)
>[125099.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[125099.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1920 pitch 7680 (/4 1920)
>[125099.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392f2e0]
>[125099.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392f2e0] width 1920 pitch 7680 (/4 1920)
>[125099.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125099.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125099.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[125099.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1920 pitch 7680 (/4 1920)
>[125099.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[125099.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1920 pitch 7680 (/4 1920)
>[125099.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391cca0]
>[125099.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391cca0] width 1920 pitch 7680 (/4 1920)
>[125099.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125099.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125099.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[125099.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[125099.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[125099.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[125099.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125099.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125099.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e73ca0]
>[125099.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e73ca0] width 1920 pitch 7680 (/4 1920)
>[125099.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125099.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125099.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125099.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125099.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[125099.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[125099.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40392b0]
>[125099.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40392b0] width 1920 pitch 7680 (/4 1920)
>[125099.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059c80]
>[125099.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059c80] width 1920 pitch 7680 (/4 1920)
>[125099.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a4a20]
>[125099.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a4a20] width 1920 pitch 7680 (/4 1920)
>[125099.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc16a0]
>[125099.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc16a0] width 1920 pitch 7680 (/4 1920)
>[125099.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[125099.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[125099.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[125099.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[125099.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed73d0]
>[125099.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed73d0] width 1920 pitch 7680 (/4 1920)
>[125099.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[125099.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1920 pitch 7680 (/4 1920)
>[125099.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063fc0]
>[125099.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063fc0] width 1920 pitch 7680 (/4 1920)
>[125100.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[125100.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1920 pitch 7680 (/4 1920)
>[125100.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb2780]
>[125100.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb2780] width 1920 pitch 7680 (/4 1920)
>[125100.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[125100.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1920 pitch 7680 (/4 1920)
>[125100.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[125100.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1920 pitch 7680 (/4 1920)
>[125100.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[125100.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1920 pitch 7680 (/4 1920)
>[125100.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f098b0]
>[125100.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f098b0] width 1920 pitch 7680 (/4 1920)
>[125100.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fd730]
>[125100.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fd730] width 1920 pitch 7680 (/4 1920)
>[125100.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125100.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125100.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[125100.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1920 pitch 7680 (/4 1920)
>[125100.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[125100.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1920 pitch 7680 (/4 1920)
>[125100.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f216a0]
>[125100.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f216a0] width 1920 pitch 7680 (/4 1920)
>[125100.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125100.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125100.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89230]
>[125100.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89230] width 1920 pitch 7680 (/4 1920)
>[125100.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a1280]
>[125100.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a1280] width 1920 pitch 7680 (/4 1920)
>[125100.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6df10]
>[125100.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6df10] width 1920 pitch 7680 (/4 1920)
>[125100.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a1380]
>[125100.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a1380] width 1920 pitch 7680 (/4 1920)
>[125100.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[125100.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1920 pitch 7680 (/4 1920)
>[125100.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[125100.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[125100.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[125100.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1920 pitch 7680 (/4 1920)
>[125100.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[125100.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[125100.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[125100.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[125100.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[125100.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1920 pitch 7680 (/4 1920)
>[125100.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092090]
>[125100.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092090] width 1920 pitch 7680 (/4 1920)
>[125100.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125100.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125100.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125100.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125100.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125100.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125100.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[125100.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[125100.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[125100.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[125100.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7e90]
>[125100.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7e90] width 1920 pitch 7680 (/4 1920)
>[125100.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cec520]
>[125100.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cec520] width 1920 pitch 7680 (/4 1920)
>[125101.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125101.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125101.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[125101.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1920 pitch 7680 (/4 1920)
>[125101.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8c50]
>[125101.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8c50] width 1920 pitch 7680 (/4 1920)
>[125101.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[125101.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[125101.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb7f0]
>[125101.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb7f0] width 1920 pitch 7680 (/4 1920)
>[125101.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[125101.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[125101.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b3a60]
>[125101.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b3a60] width 1920 pitch 7680 (/4 1920)
>[125101.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc6800]
>[125101.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc6800] width 1920 pitch 7680 (/4 1920)
>[125101.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4264f60]
>[125101.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4264f60] width 1920 pitch 7680 (/4 1920)
>[125101.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[125101.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[125101.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50aa300]
>[125101.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50aa300] width 1920 pitch 7680 (/4 1920)
>[125101.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125101.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125101.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023450]
>[125101.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023450] width 1920 pitch 7680 (/4 1920)
>[125101.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28160]
>[125101.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28160] width 1920 pitch 7680 (/4 1920)
>[125101.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125101.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125101.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[125101.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1920 pitch 7680 (/4 1920)
>[125101.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2bfc0]
>[125101.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2bfc0] width 1920 pitch 7680 (/4 1920)
>[125101.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504dce0]
>[125101.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504dce0] width 1920 pitch 7680 (/4 1920)
>[125101.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6f2b0]
>[125101.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6f2b0] width 1920 pitch 7680 (/4 1920)
>[125101.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505ed30]
>[125101.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505ed30] width 1920 pitch 7680 (/4 1920)
>[125101.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125101.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125101.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[125101.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1920 pitch 7680 (/4 1920)
>[125101.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6fe00]
>[125101.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6fe00] width 1920 pitch 7680 (/4 1920)
>[125101.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861880]
>[125101.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861880] width 1920 pitch 7680 (/4 1920)
>[125101.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[125101.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1920 pitch 7680 (/4 1920)
>[125101.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[125101.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1920 pitch 7680 (/4 1920)
>[125101.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[125101.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1920 pitch 7680 (/4 1920)
>[125101.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x392f2e0]
>[125101.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x392f2e0] width 1920 pitch 7680 (/4 1920)
>[125101.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc8e0]
>[125101.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc8e0] width 1920 pitch 7680 (/4 1920)
>[125101.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f904b0]
>[125101.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f904b0] width 1920 pitch 7680 (/4 1920)
>[125102.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f183c0]
>[125102.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f183c0] width 1920 pitch 7680 (/4 1920)
>[125102.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[125102.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1920 pitch 7680 (/4 1920)
>[125102.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[125102.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1920 pitch 7680 (/4 1920)
>[125102.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d997b0]
>[125102.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d997b0] width 1920 pitch 7680 (/4 1920)
>[125102.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[125102.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1920 pitch 7680 (/4 1920)
>[125102.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[125102.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1920 pitch 7680 (/4 1920)
>[125102.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125102.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125102.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[125102.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[125102.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125102.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125102.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de33c0]
>[125102.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de33c0] width 1920 pitch 7680 (/4 1920)
>[125102.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125102.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125102.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[125102.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[125102.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[125102.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[125102.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40392b0]
>[125102.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40392b0] width 1920 pitch 7680 (/4 1920)
>[125102.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[125102.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[125102.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5059c80]
>[125102.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5059c80] width 1920 pitch 7680 (/4 1920)
>[125102.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[125102.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1920 pitch 7680 (/4 1920)
>[125102.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f4b70]
>[125102.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f4b70] width 1920 pitch 7680 (/4 1920)
>[125102.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[125103.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[125103.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed73d0]
>[125103.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed73d0] width 1920 pitch 7680 (/4 1920)
>[125103.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[125103.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1920 pitch 7680 (/4 1920)
>[125103.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[125103.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[125103.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[125103.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1920 pitch 7680 (/4 1920)
>[125103.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[125103.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[125103.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125103.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125103.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[125103.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1920 pitch 7680 (/4 1920)
>[125103.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c50260]
>[125103.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c50260] width 1920 pitch 7680 (/4 1920)
>[125104.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6e750]
>[125104.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6e750] width 1920 pitch 7680 (/4 1920)
>[125104.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2cf10]
>[125104.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2cf10] width 1920 pitch 7680 (/4 1920)
>[125104.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a1380]
>[125104.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a1380] width 1920 pitch 7680 (/4 1920)
>[125104.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[125104.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[125104.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[125104.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1920 pitch 7680 (/4 1920)
>[125104.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[125104.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1920 pitch 7680 (/4 1920)
>[125104.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50757a0]
>[125104.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50757a0] width 1920 pitch 7680 (/4 1920)
>[125104.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[125104.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1920 pitch 7680 (/4 1920)
>[125104.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[125104.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1920 pitch 7680 (/4 1920)
>[125104.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[125104.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1920 pitch 7680 (/4 1920)
>[125104.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[125104.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[125104.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c44820]
>[125104.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c44820] width 1920 pitch 7680 (/4 1920)
>[125104.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50451f0]
>[125104.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50451f0] width 1920 pitch 7680 (/4 1920)
>[125104.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ffda0]
>[125104.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ffda0] width 1920 pitch 7680 (/4 1920)
>[125104.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[125104.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1920 pitch 7680 (/4 1920)
>[125104.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ece720]
>[125104.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ece720] width 1920 pitch 7680 (/4 1920)
>[125104.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[125104.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1920 pitch 7680 (/4 1920)
>[125104.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34bd0]
>[125104.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34bd0] width 1920 pitch 7680 (/4 1920)
>[125104.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[125104.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[125104.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5092090]
>[125104.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5092090] width 1920 pitch 7680 (/4 1920)
>[125104.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[125104.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[125104.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125104.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125104.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125104.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125104.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125104.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125104.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125104.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125104.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125104.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125104.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125104.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125104.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125104.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125104.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125104.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125104.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125105.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125105.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75780]
>[125105.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75780] width 1920 pitch 7680 (/4 1920)
>[125105.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125105.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125105.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125105.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125105.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125105.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125105.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125105.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[125106.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[125106.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6780]
>[125106.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6780] width 1920 pitch 7680 (/4 1920)
>[125106.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ed2b0]
>[125106.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ed2b0] width 1920 pitch 7680 (/4 1920)
>[125106.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42736c0]
>[125106.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42736c0] width 1920 pitch 7680 (/4 1920)
>[125106.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[125106.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1920 pitch 7680 (/4 1920)
>[125107.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x42736c0]
>[125107.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x42736c0] width 1920 pitch 7680 (/4 1920)
>[125107.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[125107.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1920 pitch 7680 (/4 1920)
>[125107.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125107.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125107.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cec520]
>[125107.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cec520] width 1920 pitch 7680 (/4 1920)
>[125107.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125107.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125107.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125107.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125107.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125107.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125107.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125107.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125108.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[125108.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1920 pitch 7680 (/4 1920)
>[125108.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125108.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125108.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[125108.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1920 pitch 7680 (/4 1920)
>[125108.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125108.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125108.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[125108.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1920 pitch 7680 (/4 1920)
>[125108.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125108.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125108.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[125108.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1920 pitch 7680 (/4 1920)
>[125108.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[125108.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1920 pitch 7680 (/4 1920)
>[125108.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[125108.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1920 pitch 7680 (/4 1920)
>[125108.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[125108.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1920 pitch 7680 (/4 1920)
>[125108.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80890]
>[125108.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80890] width 1920 pitch 7680 (/4 1920)
>[125108.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[125108.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1920 pitch 7680 (/4 1920)
>[125108.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80890]
>[125108.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80890] width 1920 pitch 7680 (/4 1920)
>[125108.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[125108.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1920 pitch 7680 (/4 1920)
>[125108.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80890]
>[125108.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80890] width 1920 pitch 7680 (/4 1920)
>[125108.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[125108.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[125108.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80890]
>[125108.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80890] width 1920 pitch 7680 (/4 1920)
>[125108.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[125108.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[125108.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e80890]
>[125108.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e80890] width 1920 pitch 7680 (/4 1920)
>[125108.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[125108.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1920 pitch 7680 (/4 1920)
>[125108.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb7f0]
>[125108.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb7f0] width 1920 pitch 7680 (/4 1920)
>[125108.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c320]
>[125108.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c320] width 1920 pitch 7680 (/4 1920)
>[125108.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23350]
>[125108.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23350] width 1920 pitch 7680 (/4 1920)
>[125108.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4c180]
>[125108.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4c180] width 1920 pitch 7680 (/4 1920)
>[125108.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba920]
>[125108.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba920] width 1920 pitch 7680 (/4 1920)
>[125108.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4c180]
>[125108.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4c180] width 1920 pitch 7680 (/4 1920)
>[125108.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba920]
>[125108.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba920] width 1920 pitch 7680 (/4 1920)
>[125108.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45e00]
>[125108.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45e00] width 1920 pitch 7680 (/4 1920)
>[125108.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125108.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125108.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7e10]
>[125108.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7e10] width 1920 pitch 7680 (/4 1920)
>[125108.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125108.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125108.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7e10]
>[125108.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7e10] width 1920 pitch 7680 (/4 1920)
>[125108.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125108.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125108.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7e10]
>[125108.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7e10] width 1920 pitch 7680 (/4 1920)
>[125108.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125108.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125109.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7e10]
>[125109.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7e10] width 1920 pitch 7680 (/4 1920)
>[125109.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125109.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125109.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7e10]
>[125109.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7e10] width 1920 pitch 7680 (/4 1920)
>[125109.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b350f0]
>[125109.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b350f0] width 1920 pitch 7680 (/4 1920)
>[125109.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db64d0]
>[125109.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db64d0] width 1920 pitch 7680 (/4 1920)
>[125110.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e61ff0]
>[125110.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e61ff0] width 1920 pitch 7680 (/4 1920)
>[125110.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3de0]
>[125110.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3de0] width 1920 pitch 7680 (/4 1920)
>[125110.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10640]
>[125110.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10640] width 1920 pitch 7680 (/4 1920)
>[125110.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[125110.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[125110.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cee8c0]
>[125110.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cee8c0] width 1920 pitch 7680 (/4 1920)
>[125110.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125110.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4059670]
>[125110.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4059670] width 1920 pitch 7680 (/4 1920)
>[125110.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125110.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf030]
>[125110.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf030] width 1920 pitch 7680 (/4 1920)
>[125110.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125110.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf030]
>[125110.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf030] width 1920 pitch 7680 (/4 1920)
>[125110.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125110.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf030]
>[125110.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf030] width 1920 pitch 7680 (/4 1920)
>[125110.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125110.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcf030]
>[125110.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcf030] width 1920 pitch 7680 (/4 1920)
>[125110.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60650]
>[125110.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60650] width 1920 pitch 7680 (/4 1920)
>[125111.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[125111.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1920 pitch 7680 (/4 1920)
>[125111.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f183c0]
>[125111.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f183c0] width 1920 pitch 7680 (/4 1920)
>[125111.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[125111.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1920 pitch 7680 (/4 1920)
>[125111.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef66d0]
>[125111.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef66d0] width 1920 pitch 7680 (/4 1920)
>[125111.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[125111.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1920 pitch 7680 (/4 1920)
>[125111.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[125111.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1920 pitch 7680 (/4 1920)
>[125111.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[125111.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1920 pitch 7680 (/4 1920)
>[125111.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125111.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125111.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125111.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125111.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125111.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125111.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125111.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125111.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[125111.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[125112.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95210]
>[125112.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95210] width 1920 pitch 7680 (/4 1920)
>[125112.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[125112.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1920 pitch 7680 (/4 1920)
>[125113.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[125113.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1920 pitch 7680 (/4 1920)
>[125113.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[125113.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1920 pitch 7680 (/4 1920)
>[125113.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[125113.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1920 pitch 7680 (/4 1920)
>[125113.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125113.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125113.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[125113.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[125113.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125113.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125113.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[125113.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[125113.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125113.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125113.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[125113.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[125113.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125113.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125113.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[125113.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[125113.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[125113.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[125121.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125121.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[125121.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[125121.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea7f0]
>[125121.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea7f0] width 1920 pitch 7680 (/4 1920)
>[125124.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125124.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125124.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125124.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125124.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125124.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125124.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125124.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125124.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125124.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125124.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125124.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125124.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125124.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125124.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125124.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125124.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125124.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125125.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125125.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125125.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125125.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125125.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125125.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125125.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125125.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125125.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125126.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125126.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25160]
>[125126.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25160] width 1920 pitch 7680 (/4 1920)
>[125127.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f530]
>[125127.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f530] width 1920 pitch 7680 (/4 1920)
>[125129.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125129.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125129.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125129.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125129.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125129.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125129.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125129.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125129.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125129.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125129.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125130.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125130.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125130.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125130.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125130.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125130.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125130.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125130.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125130.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125130.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125130.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125130.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125130.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125130.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125130.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125130.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125130.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125131.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125131.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125132.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125132.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125132.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125132.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125132.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125132.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125132.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125132.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125132.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125132.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125132.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125132.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125132.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125132.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125132.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046950]
>[125132.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046950] width 1920 pitch 7680 (/4 1920)
>[125132.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33920]
>[125132.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33920] width 1920 pitch 7680 (/4 1920)
>[125133.375] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[125133.375] (II) RADEON(0): Using hsync ranges from config file
>[125133.375] (II) RADEON(0): Using vrefresh ranges from config file
>[125133.375] (II) RADEON(0): Printing DDC gathered Modelines:
>[125133.375] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[125133.375] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[125133.375] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[125133.375] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[125133.375] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[125133.375] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[125133.375] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[125133.375] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[125133.375] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[125133.375] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[125133.375] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[125133.375] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[125133.375] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[125133.376] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[125133.376] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[125133.376] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[125135.594] (II) AIGLX: Suspending AIGLX clients for VT switch
>[125135.594] (II) RADEON(0): RADEONLeaveVT_KMS
>[125135.594] (II) RADEON(0): Ok, leaving now...
>[125139.889] (II) AIGLX: Resuming AIGLX clients after VT switch
>[125139.889] (II) RADEON(0): RADEONEnterVT_KMS
>[125140.796] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[125140.796] (II) RADEON(0): Using hsync ranges from config file
>[125140.796] (II) RADEON(0): Using vrefresh ranges from config file
>[125140.797] (II) RADEON(0): Printing DDC gathered Modelines:
>[125140.797] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[125140.797] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[125140.797] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[125140.797] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[125140.797] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[125140.797] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[125140.797] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[125140.797] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[125140.797] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[125140.797] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[125140.797] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[125140.804] (II) RADEON(0): RADEONSaveScreen(2)
>[125140.806] (**) Option "Device" "/dev/input/event5"
>[125140.806] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[125530.743] (II) RADEON(0): RADEONSaveScreen(2)
>[125530.743] (II) RADEON(0): RADEONSaveScreen(0)
>[127943.103] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event18)
>[127943.116] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[127943.116] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127943.116] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[127943.116] 	Option "XkbRules" "evdev"
>[127943.116] 	Option "XkbModel" "pc105+inet"
>[127943.116] 	Option "XkbLayout" "us"
>[127943.116] 	Option "_source" "server/udev"
>[127943.116] 	Option "name" "VISENTA V1 "
>[127943.116] 	Option "path" "/dev/input/event18"
>[127943.116] 	Option "device" "/dev/input/event18"
>[127943.116] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input18/event18"
>[127943.116] 	Option "driver" "evdev"
>[127943.116] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[127943.116] (**) VISENTA V1 : always reports core events
>[127943.116] (**) evdev: VISENTA V1 : Device: "/dev/input/event18"
>[127943.116] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[127943.116] (--) evdev: VISENTA V1 : Found keys
>[127943.116] (II) evdev: VISENTA V1 : Configuring as keyboard
>[127943.116] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input18/event18"
>[127943.116] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 17)
>[127943.116] (**) Option "xkb_rules" "evdev"
>[127943.116] (**) Option "xkb_model" "pc105+inet"
>[127943.116] (**) Option "xkb_layout" "us"
>[127943.116] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[127943.116] (II) XKB: Reusing cached keymap
>[127943.126] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse3)
>[127943.126] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127943.126] (II) No input driver specified, ignoring this device.
>[127943.126] (II) This device may have been added with another device file.
>[127943.126] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event19)
>[127943.126] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[127943.126] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[127943.126] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127943.126] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[127943.126] 	Option "XkbRules" "evdev"
>[127943.126] 	Option "XkbModel" "pc105+inet"
>[127943.126] 	Option "XkbLayout" "us"
>[127943.126] 	Option "_source" "server/udev"
>[127943.126] 	Option "name" "VISENTA V1 "
>[127943.126] 	Option "path" "/dev/input/event19"
>[127943.126] 	Option "device" "/dev/input/event19"
>[127943.126] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input19/event19"
>[127943.126] 	Option "driver" "evdev"
>[127943.126] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[127943.126] (**) VISENTA V1 : always reports core events
>[127943.126] (**) evdev: VISENTA V1 : Device: "/dev/input/event19"
>[127943.126] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[127943.126] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[127943.126] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[127943.126] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[127943.126] (--) evdev: VISENTA V1 : Found relative axes
>[127943.126] (--) evdev: VISENTA V1 : Found x and y relative axes
>[127943.126] (--) evdev: VISENTA V1 : Found absolute axes
>[127943.126] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[127943.126] (--) evdev: VISENTA V1 : Found keys
>[127943.127] (II) evdev: VISENTA V1 : Configuring as mouse
>[127943.127] (II) evdev: VISENTA V1 : Configuring as keyboard
>[127943.127] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[127943.127] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[127943.127] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[127943.127] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input19/event19"
>[127943.127] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 18)
>[127943.127] (**) Option "xkb_rules" "evdev"
>[127943.127] (**) Option "xkb_model" "pc105+inet"
>[127943.127] (**) Option "xkb_layout" "us"
>[127943.127] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[127943.127] (II) XKB: Reusing cached keymap
>[127943.127] (II) evdev: VISENTA V1 : initialized for relative axes.
>[127943.127] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[127943.127] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[127943.127] (**) VISENTA V1 : (accel) acceleration profile 0
>[127943.127] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[127943.127] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[127988.827] (II) config/udev: removing device VISENTA V1 
>[127988.827] (II) evdev: VISENTA V1 : Close
>[127988.827] (II) UnloadModule: "evdev"
>[127988.846] (II) config/udev: removing device VISENTA V1 
>[127988.847] (II) evdev: VISENTA V1 : Close
>[127988.847] (II) UnloadModule: "evdev"
>[127995.039] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event18)
>[127995.039] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[127995.039] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127995.039] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[127995.039] 	Option "XkbRules" "evdev"
>[127995.039] 	Option "XkbModel" "pc105+inet"
>[127995.039] 	Option "XkbLayout" "us"
>[127995.039] 	Option "_source" "server/udev"
>[127995.039] 	Option "name" "VISENTA V1 "
>[127995.039] 	Option "path" "/dev/input/event18"
>[127995.039] 	Option "device" "/dev/input/event18"
>[127995.039] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input20/event18"
>[127995.039] 	Option "driver" "evdev"
>[127995.039] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[127995.039] (**) VISENTA V1 : always reports core events
>[127995.039] (**) evdev: VISENTA V1 : Device: "/dev/input/event18"
>[127995.039] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[127995.039] (--) evdev: VISENTA V1 : Found keys
>[127995.039] (II) evdev: VISENTA V1 : Configuring as keyboard
>[127995.039] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input20/event18"
>[127995.039] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 17)
>[127995.039] (**) Option "xkb_rules" "evdev"
>[127995.039] (**) Option "xkb_model" "pc105+inet"
>[127995.039] (**) Option "xkb_layout" "us"
>[127995.039] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[127995.039] (II) XKB: Reusing cached keymap
>[127995.040] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse3)
>[127995.040] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127995.040] (II) No input driver specified, ignoring this device.
>[127995.040] (II) This device may have been added with another device file.
>[127995.042] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event19)
>[127995.042] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[127995.042] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[127995.042] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[127995.043] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[127995.043] 	Option "XkbRules" "evdev"
>[127995.043] 	Option "XkbModel" "pc105+inet"
>[127995.043] 	Option "XkbLayout" "us"
>[127995.043] 	Option "_source" "server/udev"
>[127995.043] 	Option "name" "VISENTA V1 "
>[127995.043] 	Option "path" "/dev/input/event19"
>[127995.043] 	Option "device" "/dev/input/event19"
>[127995.043] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input21/event19"
>[127995.043] 	Option "driver" "evdev"
>[127995.043] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[127995.043] (**) VISENTA V1 : always reports core events
>[127995.043] (**) evdev: VISENTA V1 : Device: "/dev/input/event19"
>[127995.043] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[127995.043] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[127995.043] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[127995.043] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[127995.043] (--) evdev: VISENTA V1 : Found relative axes
>[127995.043] (--) evdev: VISENTA V1 : Found x and y relative axes
>[127995.043] (--) evdev: VISENTA V1 : Found absolute axes
>[127995.043] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[127995.043] (--) evdev: VISENTA V1 : Found keys
>[127995.043] (II) evdev: VISENTA V1 : Configuring as mouse
>[127995.043] (II) evdev: VISENTA V1 : Configuring as keyboard
>[127995.043] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[127995.043] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[127995.043] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[127995.043] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input21/event19"
>[127995.043] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 18)
>[127995.043] (**) Option "xkb_rules" "evdev"
>[127995.043] (**) Option "xkb_model" "pc105+inet"
>[127995.043] (**) Option "xkb_layout" "us"
>[127995.043] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[127995.043] (II) XKB: Reusing cached keymap
>[127995.043] (II) evdev: VISENTA V1 : initialized for relative axes.
>[127995.043] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[127995.044] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[127995.044] (**) VISENTA V1 : (accel) acceleration profile 0
>[127995.044] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[127995.044] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[128010.207] (II) RADEON(0): RADEONSaveScreen(1)
>[128400.768] (II) RADEON(0): RADEONSaveScreen(2)
>[128400.769] (II) RADEON(0): RADEONSaveScreen(0)
>[158932.988] (II) RADEON(0): RADEONSaveScreen(1)
>[158951.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[158951.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1920 pitch 7680 (/4 1920)
>[158953.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[158953.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[158953.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f45570]
>[158953.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f45570] width 1920 pitch 7680 (/4 1920)
>[158953.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[158953.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1920 pitch 7680 (/4 1920)
>[158953.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[158953.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1920 pitch 7680 (/4 1920)
>[158953.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2c10]
>[158953.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2c10] width 1920 pitch 7680 (/4 1920)
>[158953.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40392b0]
>[158953.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40392b0] width 1920 pitch 7680 (/4 1920)
>[158953.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f4b70]
>[158953.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f4b70] width 1920 pitch 7680 (/4 1920)
>[158953.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3951e10]
>[158953.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3951e10] width 1920 pitch 7680 (/4 1920)
>[158953.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fab6c0]
>[158953.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fab6c0] width 1920 pitch 7680 (/4 1920)
>[158953.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a31f0]
>[158954.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a31f0] width 1920 pitch 7680 (/4 1920)
>[158954.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[158954.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[158954.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cec520]
>[158954.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cec520] width 1920 pitch 7680 (/4 1920)
>[158954.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[158954.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1920 pitch 7680 (/4 1920)
>[158954.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[158954.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1920 pitch 7680 (/4 1920)
>[158960.023] (II) config/udev: removing device VISENTA V1 
>[158960.023] (II) evdev: VISENTA V1 : Close
>[158960.023] (II) UnloadModule: "evdev"
>[158960.039] (II) config/udev: removing device VISENTA V1 
>[158960.039] (II) evdev: VISENTA V1 : Close
>[158960.039] (II) UnloadModule: "evdev"
>[158964.436] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse3)
>[158964.436] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[158964.436] (II) No input driver specified, ignoring this device.
>[158964.436] (II) This device may have been added with another device file.
>[158964.437] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event19)
>[158964.437] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[158964.437] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[158964.437] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[158964.437] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[158964.437] 	Option "XkbRules" "evdev"
>[158964.437] 	Option "XkbModel" "pc105+inet"
>[158964.437] 	Option "XkbLayout" "us"
>[158964.437] 	Option "_source" "server/udev"
>[158964.437] 	Option "name" "VISENTA V1 "
>[158964.437] 	Option "path" "/dev/input/event19"
>[158964.437] 	Option "device" "/dev/input/event19"
>[158964.437] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input23/event19"
>[158964.437] 	Option "driver" "evdev"
>[158964.437] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[158964.437] (**) VISENTA V1 : always reports core events
>[158964.437] (**) evdev: VISENTA V1 : Device: "/dev/input/event19"
>[158964.437] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[158964.437] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[158964.437] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[158964.437] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[158964.437] (--) evdev: VISENTA V1 : Found relative axes
>[158964.437] (--) evdev: VISENTA V1 : Found x and y relative axes
>[158964.437] (--) evdev: VISENTA V1 : Found absolute axes
>[158964.437] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[158964.437] (--) evdev: VISENTA V1 : Found keys
>[158964.437] (II) evdev: VISENTA V1 : Configuring as mouse
>[158964.437] (II) evdev: VISENTA V1 : Configuring as keyboard
>[158964.437] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[158964.437] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[158964.437] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[158964.437] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input23/event19"
>[158964.437] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 17)
>[158964.437] (**) Option "xkb_rules" "evdev"
>[158964.437] (**) Option "xkb_model" "pc105+inet"
>[158964.437] (**) Option "xkb_layout" "us"
>[158964.437] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[158964.437] (II) XKB: Reusing cached keymap
>[158964.437] (II) evdev: VISENTA V1 : initialized for relative axes.
>[158964.437] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[158964.438] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[158964.438] (**) VISENTA V1 : (accel) acceleration profile 0
>[158964.438] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[158964.438] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[158964.440] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event18)
>[158964.440] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[158964.440] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[158964.440] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[158964.440] 	Option "XkbRules" "evdev"
>[158964.440] 	Option "XkbModel" "pc105+inet"
>[158964.440] 	Option "XkbLayout" "us"
>[158964.440] 	Option "_source" "server/udev"
>[158964.440] 	Option "name" "VISENTA V1 "
>[158964.440] 	Option "path" "/dev/input/event18"
>[158964.440] 	Option "device" "/dev/input/event18"
>[158964.440] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input22/event18"
>[158964.440] 	Option "driver" "evdev"
>[158964.440] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[158964.440] (**) VISENTA V1 : always reports core events
>[158964.440] (**) evdev: VISENTA V1 : Device: "/dev/input/event18"
>[158964.440] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[158964.440] (--) evdev: VISENTA V1 : Found keys
>[158964.440] (II) evdev: VISENTA V1 : Configuring as keyboard
>[158964.440] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input22/event18"
>[158964.440] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 18)
>[158964.440] (**) Option "xkb_rules" "evdev"
>[158964.440] (**) Option "xkb_model" "pc105+inet"
>[158964.440] (**) Option "xkb_layout" "us"
>[158964.440] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[158964.441] (II) XKB: Reusing cached keymap
>[158964.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[158964.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1920 pitch 7680 (/4 1920)
>[158965.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[158965.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1920 pitch 7680 (/4 1920)
>[158971.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063fc0]
>[158972.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063fc0] width 1920 pitch 7680 (/4 1920)
>[158976.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[158976.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1920 pitch 7680 (/4 1920)
>[158976.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef66d0]
>[158976.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef66d0] width 1920 pitch 7680 (/4 1920)
>[158987.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24d60]
>[158987.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24d60] width 1920 pitch 7680 (/4 1920)
>[159000.469] (II) config/udev: removing device VISENTA V1 
>[159000.469] (II) evdev: VISENTA V1 : Close
>[159000.469] (II) UnloadModule: "evdev"
>[159000.485] (II) config/udev: removing device VISENTA V1 
>[159000.486] (II) evdev: VISENTA V1 : Close
>[159000.486] (II) UnloadModule: "evdev"
>[159003.602] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse3)
>[159003.602] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[159003.602] (II) No input driver specified, ignoring this device.
>[159003.602] (II) This device may have been added with another device file.
>[159003.603] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event18)
>[159003.603] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[159003.603] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[159003.603] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[159003.603] 	Option "XkbRules" "evdev"
>[159003.603] 	Option "XkbModel" "pc105+inet"
>[159003.603] 	Option "XkbLayout" "us"
>[159003.603] 	Option "_source" "server/udev"
>[159003.603] 	Option "name" "VISENTA V1 "
>[159003.603] 	Option "path" "/dev/input/event18"
>[159003.603] 	Option "device" "/dev/input/event18"
>[159003.603] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input24/event18"
>[159003.603] 	Option "driver" "evdev"
>[159003.603] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[159003.603] (**) VISENTA V1 : always reports core events
>[159003.603] (**) evdev: VISENTA V1 : Device: "/dev/input/event18"
>[159003.603] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[159003.603] (--) evdev: VISENTA V1 : Found keys
>[159003.603] (II) evdev: VISENTA V1 : Configuring as keyboard
>[159003.603] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input24/event18"
>[159003.603] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 17)
>[159003.603] (**) Option "xkb_rules" "evdev"
>[159003.603] (**) Option "xkb_model" "pc105+inet"
>[159003.603] (**) Option "xkb_layout" "us"
>[159003.603] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[159003.603] (II) XKB: Reusing cached keymap
>[159003.604] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event19)
>[159003.604] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[159003.604] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[159003.604] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[159003.604] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[159003.604] 	Option "XkbRules" "evdev"
>[159003.604] 	Option "XkbModel" "pc105+inet"
>[159003.604] 	Option "XkbLayout" "us"
>[159003.604] 	Option "_source" "server/udev"
>[159003.604] 	Option "name" "VISENTA V1 "
>[159003.604] 	Option "path" "/dev/input/event19"
>[159003.604] 	Option "device" "/dev/input/event19"
>[159003.604] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input25/event19"
>[159003.604] 	Option "driver" "evdev"
>[159003.604] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[159003.604] (**) VISENTA V1 : always reports core events
>[159003.604] (**) evdev: VISENTA V1 : Device: "/dev/input/event19"
>[159003.604] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[159003.604] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[159003.604] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[159003.604] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[159003.604] (--) evdev: VISENTA V1 : Found relative axes
>[159003.604] (--) evdev: VISENTA V1 : Found x and y relative axes
>[159003.604] (--) evdev: VISENTA V1 : Found absolute axes
>[159003.604] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[159003.604] (--) evdev: VISENTA V1 : Found keys
>[159003.604] (II) evdev: VISENTA V1 : Configuring as mouse
>[159003.604] (II) evdev: VISENTA V1 : Configuring as keyboard
>[159003.604] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[159003.604] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[159003.604] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[159003.604] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input25/event19"
>[159003.604] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 18)
>[159003.604] (**) Option "xkb_rules" "evdev"
>[159003.604] (**) Option "xkb_model" "pc105+inet"
>[159003.604] (**) Option "xkb_layout" "us"
>[159003.604] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[159003.604] (II) XKB: Reusing cached keymap
>[159003.604] (II) evdev: VISENTA V1 : initialized for relative axes.
>[159003.604] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[159003.604] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[159003.604] (**) VISENTA V1 : (accel) acceleration profile 0
>[159003.604] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[159003.604] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[159004.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba2f0]
>[159004.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba2f0] width 1920 pitch 7680 (/4 1920)
>[159045.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f6a0]
>[159045.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f6a0] width 1920 pitch 7680 (/4 1920)
>[159045.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[159045.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[159051.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159051.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1920 pitch 7680 (/4 1920)
>[159051.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159051.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1920 pitch 7680 (/4 1920)
>[159052.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[159052.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[159052.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[159052.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1920 pitch 7680 (/4 1920)
>[159057.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b4b0]
>[159057.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b4b0] width 1920 pitch 7680 (/4 1920)
>[159057.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a99230]
>[159057.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a99230] width 1920 pitch 7680 (/4 1920)
>[159057.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f2e0]
>[159057.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f2e0] width 1920 pitch 7680 (/4 1920)
>[159058.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[159058.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1920 pitch 7680 (/4 1920)
>[159058.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[159058.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1920 pitch 7680 (/4 1920)
>[159058.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40455c0]
>[159058.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40455c0] width 1920 pitch 7680 (/4 1920)
>[159102.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[159102.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1920 pitch 7680 (/4 1920)
>[159102.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f51980]
>[159102.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f51980] width 1920 pitch 7680 (/4 1920)
>[159103.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee460]
>[159103.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee460] width 1920 pitch 7680 (/4 1920)
>[159104.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[159104.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1920 pitch 7680 (/4 1920)
>[159104.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159104.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1920 pitch 7680 (/4 1920)
>[159104.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c7a0]
>[159104.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c7a0] width 1920 pitch 7680 (/4 1920)
>[159108.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6c1f0]
>[159108.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6c1f0] width 1920 pitch 7680 (/4 1920)
>[159108.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[159108.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1920 pitch 7680 (/4 1920)
>[159109.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f145a0]
>[159109.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f145a0] width 1920 pitch 7680 (/4 1920)
>[159109.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[159109.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1920 pitch 7680 (/4 1920)
>[159109.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159109.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159110.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159110.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159110.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159110.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1920 pitch 7680 (/4 1920)
>[159111.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[159111.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1920 pitch 7680 (/4 1920)
>[159111.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[159111.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1920 pitch 7680 (/4 1920)
>[159127.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7db40]
>[159127.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7db40] width 1920 pitch 7680 (/4 1920)
>[159132.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159132.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159132.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159132.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159132.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159132.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159132.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159132.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159132.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159132.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159132.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159132.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159132.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159132.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159132.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159132.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159132.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159132.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159132.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159132.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159133.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1920 pitch 7680 (/4 1920)
>[159133.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3f770]
>[159133.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3f770] width 1920 pitch 7680 (/4 1920)
>[159133.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[159133.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[159134.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159134.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159134.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[159134.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[159134.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159134.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159134.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[159134.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[159134.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159134.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159134.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[159134.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[159134.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159134.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159134.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da5fb0]
>[159134.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da5fb0] width 1920 pitch 7680 (/4 1920)
>[159134.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9110]
>[159134.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9110] width 1920 pitch 7680 (/4 1920)
>[159135.023] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[159135.023] (II) RADEON(0): Using hsync ranges from config file
>[159135.023] (II) RADEON(0): Using vrefresh ranges from config file
>[159135.023] (II) RADEON(0): Printing DDC gathered Modelines:
>[159135.023] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[159135.023] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[159135.023] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[159135.023] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[159135.023] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[159135.023] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[159135.023] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[159135.023] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[159135.023] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[159135.023] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[159135.023] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[159137.290] (II) AIGLX: Suspending AIGLX clients for VT switch
>[159137.290] (II) RADEON(0): RADEONLeaveVT_KMS
>[159137.290] (II) RADEON(0): Ok, leaving now...
>[159141.672] (II) AIGLX: Resuming AIGLX clients after VT switch
>[159141.672] (II) RADEON(0): RADEONEnterVT_KMS
>[159142.601] (II) RADEON(0): EDID vendor "HWP", prod id 9968
>[159142.601] (II) RADEON(0): Using hsync ranges from config file
>[159142.602] (II) RADEON(0): Using vrefresh ranges from config file
>[159142.602] (II) RADEON(0): Printing DDC gathered Modelines:
>[159142.602] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz eP)
>[159142.602] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[159142.602] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[159142.602] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[159142.602] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[159142.602] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[159142.602] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1152x720"x60.0   67.32  1152 1208 1328 1504  720 721 724 746 -hsync +vsync (44.8 kHz e)
>[159142.602] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[159142.607] (II) RADEON(0): RADEONSaveScreen(2)
>[159142.633] (EE) evdev: USB USB Keykoard: Unable to open evdev device "/dev/input/event6".
>[159142.649] [dix] couldn't enable device 9
>[159142.649] (EE) evdev: USB USB Keykoard: Unable to open evdev device "/dev/input/event7".
>[159142.649] [dix] couldn't enable device 10
>[159142.649] (EE) evdev: Logitech USB Optical Mouse: Unable to open evdev device "/dev/input/event8".
>[159142.649] [dix] couldn't enable device 11
>[159142.649] (**) Option "Device" "/dev/input/event5"
>[159142.649] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[159142.649] (EE) evdev: VISENTA V1 : Unable to open evdev device "/dev/input/event18".
>[159142.649] [dix] couldn't enable device 17
>[159142.649] (EE) evdev: VISENTA V1 : Unable to open evdev device "/dev/input/event19".
>[159142.649] [dix] couldn't enable device 18
>[159142.650] (II) config/udev: removing device USB USB Keykoard
>[159142.650] (II) evdev: USB USB Keykoard: Close
>[159142.650] (II) UnloadModule: "evdev"
>[159142.651] (II) config/udev: removing device USB USB Keykoard
>[159142.652] (II) evdev: USB USB Keykoard: Close
>[159142.652] (II) UnloadModule: "evdev"
>[159142.676] (II) config/udev: removing device Logitech USB Optical Mouse
>[159142.677] (II) evdev: Logitech USB Optical Mouse: Close
>[159142.677] (II) UnloadModule: "evdev"
>[159142.686] (II) config/udev: removing device VISENTA V1 
>[159142.686] (II) evdev: VISENTA V1 : Close
>[159142.686] (II) UnloadModule: "evdev"
>[159142.687] (II) config/udev: removing device VISENTA V1 
>[159142.687] (II) evdev: VISENTA V1 : Close
>[159142.687] (II) UnloadModule: "evdev"
>[159142.908] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[159142.909] (II) RADEON(0): VRAM usage limit set to 223324K
>[159143.813] (II) RADEON(0): EDID vendor "HWP", prod id 9968
>[159143.813] (II) RADEON(0): Using hsync ranges from config file
>[159143.813] (II) RADEON(0): Using vrefresh ranges from config file
>[159143.813] (II) RADEON(0): Printing DDC gathered Modelines:
>[159143.813] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz eP)
>[159143.813] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[159143.813] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[159143.813] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[159143.813] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[159143.813] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[159143.813] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1152x720"x60.0   67.32  1152 1208 1328 1504  720 721 724 746 -hsync +vsync (44.8 kHz e)
>[159143.813] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[159143.822] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[159143.825] (II) RADEON(0): VRAM usage limit set to 223324K
>[159156.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159156.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159158.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28626f0]
>[159158.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28626f0] width 1600 pitch 6400 (/4 1600)
>[159158.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28626f0]
>[159158.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28626f0] width 1600 pitch 6400 (/4 1600)
>[159158.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28626f0]
>[159158.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28626f0] width 1600 pitch 6400 (/4 1600)
>[159158.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28626f0]
>[159158.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28626f0] width 1600 pitch 6400 (/4 1600)
>[159158.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28626f0]
>[159158.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28626f0] width 1600 pitch 6400 (/4 1600)
>[159158.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[159158.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1600 pitch 6400 (/4 1600)
>[159158.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d54d20]
>[159158.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d54d20] width 1600 pitch 6400 (/4 1600)
>[159158.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[159158.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1600 pitch 6400 (/4 1600)
>[159160.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159160.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159160.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159160.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159160.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159160.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159160.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159160.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159160.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159160.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159160.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159160.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159160.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159160.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159160.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159160.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159160.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159160.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159160.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159160.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159160.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159160.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159160.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159160.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159161.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159161.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159161.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159161.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159161.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159161.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159161.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159161.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159161.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159161.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159161.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159161.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159161.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159161.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159161.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159161.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159161.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159161.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159162.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159162.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159162.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159162.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159162.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159162.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159162.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159162.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159162.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159162.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159162.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159162.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159162.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159162.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159163.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159163.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159163.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159163.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159164.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159164.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159164.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159164.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159164.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159166.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159166.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159166.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159166.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[159166.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159166.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159166.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159166.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[159166.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159166.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159166.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159166.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[159166.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159166.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159166.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159166.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[159166.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159166.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159166.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[159166.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[159166.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159166.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159172.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[159173.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[159173.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca9a0]
>[159173.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca9a0] width 1600 pitch 6400 (/4 1600)
>[159173.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159173.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159175.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159175.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159175.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159175.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159175.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159175.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159175.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[159175.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1600 pitch 6400 (/4 1600)
>[159175.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[159175.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1600 pitch 6400 (/4 1600)
>[159175.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[159175.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1600 pitch 6400 (/4 1600)
>[159175.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159175.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[159175.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1600 pitch 6400 (/4 1600)
>[159175.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159175.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159179.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aea0]
>[159179.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aea0] width 1600 pitch 6400 (/4 1600)
>[159179.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[159179.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[159179.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159179.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159179.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159179.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159205.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159205.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159205.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f6a0]
>[159205.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f6a0] width 1600 pitch 6400 (/4 1600)
>[159205.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f6a0]
>[159205.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f6a0] width 1600 pitch 6400 (/4 1600)
>[159205.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4058c00]
>[159205.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4058c00] width 1600 pitch 6400 (/4 1600)
>[159205.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca9a0]
>[159205.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca9a0] width 1600 pitch 6400 (/4 1600)
>[159205.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159205.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159205.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159205.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159205.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159205.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159205.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159205.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159205.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159205.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159205.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[159205.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1600 pitch 6400 (/4 1600)
>[159205.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159205.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159205.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159205.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159205.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[159205.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[159205.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159205.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159205.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21940]
>[159205.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21940] width 1600 pitch 6400 (/4 1600)
>[159205.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f58070]
>[159205.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f58070] width 1600 pitch 6400 (/4 1600)
>[159206.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159206.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159207.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[159207.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1600 pitch 6400 (/4 1600)
>[159208.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca9a0]
>[159208.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca9a0] width 1600 pitch 6400 (/4 1600)
>[159208.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40222b0]
>[159208.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40222b0] width 1600 pitch 6400 (/4 1600)
>[159208.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159208.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159208.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[159208.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1600 pitch 6400 (/4 1600)
>[159208.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0afe0]
>[159208.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0afe0] width 1600 pitch 6400 (/4 1600)
>[159208.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159208.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159208.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159209.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159209.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[159209.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1600 pitch 6400 (/4 1600)
>[159209.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159209.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159209.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159209.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159209.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159209.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159209.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159209.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159209.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159209.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159209.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[159209.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[159209.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[159209.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[159220.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f098b0]
>[159220.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f098b0] width 1600 pitch 6400 (/4 1600)
>[159220.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea04e0]
>[159220.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea04e0] width 1600 pitch 6400 (/4 1600)
>[159220.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f21340]
>[159220.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f21340] width 1600 pitch 6400 (/4 1600)
>[159221.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[159221.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1600 pitch 6400 (/4 1600)
>[159221.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef15f0]
>[159221.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef15f0] width 1600 pitch 6400 (/4 1600)
>[159221.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[159221.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1600 pitch 6400 (/4 1600)
>[159222.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159222.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159259.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240c410]
>[159259.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240c410] width 1600 pitch 6400 (/4 1600)
>[159259.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[159259.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[159260.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861880]
>[159260.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861880] width 1600 pitch 6400 (/4 1600)
>[159264.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159264.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159264.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159264.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159264.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159264.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159264.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159264.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159264.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159265.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159265.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159265.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d060]
>[159265.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d060] width 1600 pitch 6400 (/4 1600)
>[159266.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[159266.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[159266.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[159266.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1600 pitch 6400 (/4 1600)
>[159266.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159266.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159266.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055240]
>[159266.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055240] width 1600 pitch 6400 (/4 1600)
>[159266.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3956410]
>[159266.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3956410] width 1600 pitch 6400 (/4 1600)
>[159266.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159266.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159266.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd360]
>[159266.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd360] width 1600 pitch 6400 (/4 1600)
>[159266.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159266.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159271.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[159271.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[159271.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[159271.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1600 pitch 6400 (/4 1600)
>[159272.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[159272.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1600 pitch 6400 (/4 1600)
>[159272.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055240]
>[159272.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055240] width 1600 pitch 6400 (/4 1600)
>[159272.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[159272.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[159272.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f6a0]
>[159272.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f6a0] width 1600 pitch 6400 (/4 1600)
>[159272.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159272.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1600 pitch 6400 (/4 1600)
>[159272.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7530]
>[159272.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7530] width 1600 pitch 6400 (/4 1600)
>[159272.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159272.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1600 pitch 6400 (/4 1600)
>[159272.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[159272.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1600 pitch 6400 (/4 1600)
>[159272.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159272.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1600 pitch 6400 (/4 1600)
>[159272.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159272.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1600 pitch 6400 (/4 1600)
>[159272.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159272.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1600 pitch 6400 (/4 1600)
>[159272.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159272.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1600 pitch 6400 (/4 1600)
>[159272.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54e00]
>[159272.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54e00] width 1600 pitch 6400 (/4 1600)
>[159272.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262c00]
>[159272.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262c00] width 1600 pitch 6400 (/4 1600)
>[159273.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240c410]
>[159273.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240c410] width 1600 pitch 6400 (/4 1600)
>[159274.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159274.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159327.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c70]
>[159327.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c70] width 1600 pitch 6400 (/4 1600)
>[159327.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[159327.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[159327.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[159327.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1600 pitch 6400 (/4 1600)
>[159327.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159328.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159328.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159328.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159328.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159328.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159328.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159328.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159328.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159328.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159328.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159328.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159328.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159328.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159328.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159328.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159328.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6aad0]
>[159328.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6aad0] width 1600 pitch 6400 (/4 1600)
>[159328.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159328.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159385.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[159385.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1600 pitch 6400 (/4 1600)
>[159385.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbb5c0]
>[159385.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbb5c0] width 1600 pitch 6400 (/4 1600)
>[159385.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[159385.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1600 pitch 6400 (/4 1600)
>[159385.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f6a0]
>[159385.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f6a0] width 1600 pitch 6400 (/4 1600)
>[159385.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc16a0]
>[159386.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc16a0] width 1600 pitch 6400 (/4 1600)
>[159386.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[159386.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[159386.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[159386.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1600 pitch 6400 (/4 1600)
>[159386.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7a780]
>[159386.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7a780] width 1600 pitch 6400 (/4 1600)
>[159386.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[159386.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[159386.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[159386.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[159386.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811a30]
>[159386.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811a30] width 1600 pitch 6400 (/4 1600)
>[159386.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6bee0]
>[159386.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6bee0] width 1600 pitch 6400 (/4 1600)
>[159387.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159387.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159388.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[159388.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[159388.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50857c0]
>[159388.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50857c0] width 1600 pitch 6400 (/4 1600)
>[159388.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159388.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159388.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[159388.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[159388.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0c30]
>[159388.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0c30] width 1600 pitch 6400 (/4 1600)
>[159388.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f098b0]
>[159388.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f098b0] width 1600 pitch 6400 (/4 1600)
>[159388.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[159388.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[159388.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9aa20]
>[159388.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9aa20] width 1600 pitch 6400 (/4 1600)
>[159388.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecd360]
>[159388.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecd360] width 1600 pitch 6400 (/4 1600)
>[159388.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159388.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159388.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[159388.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[159388.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[159388.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1600 pitch 6400 (/4 1600)
>[159392.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159392.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fba0e0]
>[159392.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fba0e0] width 1600 pitch 6400 (/4 1600)
>[159392.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adfa00]
>[159392.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adfa00] width 1600 pitch 6400 (/4 1600)
>[159446.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5c90]
>[159446.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5c90] width 1600 pitch 6400 (/4 1600)
>[159446.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ae00]
>[159446.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ae00] width 1600 pitch 6400 (/4 1600)
>[159447.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159447.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159451.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[159451.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[159451.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[159451.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[159452.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[159452.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[159452.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[159452.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[159452.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[159452.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1600 pitch 6400 (/4 1600)
>[159453.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[159453.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[159584.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159584.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159584.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c5620]
>[159584.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c5620] width 1600 pitch 6400 (/4 1600)
>[159585.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3b1b0]
>[159585.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3b1b0] width 1600 pitch 6400 (/4 1600)
>[159585.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159585.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159594.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f20b30]
>[159594.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f20b30] width 1600 pitch 6400 (/4 1600)
>[159595.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159595.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159595.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb2b70]
>[159595.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb2b70] width 1600 pitch 6400 (/4 1600)
>[159595.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159595.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159601.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159601.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159601.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159601.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159601.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159601.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159601.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f064a0]
>[159601.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f064a0] width 1600 pitch 6400 (/4 1600)
>[159601.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f064a0]
>[159601.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f064a0] width 1600 pitch 6400 (/4 1600)
>[159601.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f064a0]
>[159601.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f064a0] width 1600 pitch 6400 (/4 1600)
>[159601.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f064a0]
>[159601.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f064a0] width 1600 pitch 6400 (/4 1600)
>[159601.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24b80]
>[159601.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24b80] width 1600 pitch 6400 (/4 1600)
>[159601.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24b80]
>[159601.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24b80] width 1600 pitch 6400 (/4 1600)
>[159601.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159601.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159601.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159601.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[159601.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[159603.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24ca0]
>[159603.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24ca0] width 1600 pitch 6400 (/4 1600)
>[159605.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159605.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159605.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df67c0]
>[159605.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df67c0] width 1600 pitch 6400 (/4 1600)
>[159606.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159606.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb9b0]
>[159606.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb9b0] width 1600 pitch 6400 (/4 1600)
>[159606.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159606.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159659.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecbc70]
>[159659.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecbc70] width 1600 pitch 6400 (/4 1600)
>[159660.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159660.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159661.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[159661.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[159688.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a7d0]
>[159688.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a7d0] width 1600 pitch 6400 (/4 1600)
>[159688.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f06ff0]
>[159688.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f06ff0] width 1600 pitch 6400 (/4 1600)
>[159689.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea57b0]
>[159689.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea57b0] width 1600 pitch 6400 (/4 1600)
>[159828.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159828.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159828.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159828.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159828.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159828.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159828.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159828.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159828.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159828.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159828.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159828.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159828.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159828.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159828.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159828.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159828.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159829.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159829.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159829.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159829.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159829.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159829.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159829.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159829.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159829.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159829.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159829.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159829.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159831.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159831.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159831.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159831.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159833.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159833.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159833.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159833.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159833.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159833.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159833.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159833.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159833.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159833.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159833.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159833.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159833.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159833.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159833.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159833.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159833.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159833.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159833.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159833.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159833.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159833.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159833.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159833.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159833.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159833.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159835.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159835.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159838.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159838.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159838.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159838.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159838.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159838.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159838.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159838.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159838.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159838.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159838.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159838.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159838.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159838.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159838.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[159838.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[159838.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159838.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159838.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159838.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159838.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159838.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159838.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159838.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159838.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159894.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159894.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159894.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159894.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159895.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159895.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159895.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159895.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159895.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159895.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159895.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159895.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159895.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159895.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159895.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159895.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159895.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159895.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159896.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159896.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159896.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159896.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159896.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159897.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159897.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159897.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159897.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159897.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159897.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159897.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159897.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159897.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159898.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159898.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159898.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159898.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159898.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[159898.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[159899.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159899.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159899.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159899.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159899.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159917.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159917.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[159917.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bee2e0]
>[159917.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bee2e0] width 1600 pitch 6400 (/4 1600)
>[159918.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[159918.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[159919.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ded5e0]
>[159919.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ded5e0] width 1600 pitch 6400 (/4 1600)
>[160049.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160049.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160049.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160049.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160050.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160050.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160050.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160050.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160050.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[160050.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1600 pitch 6400 (/4 1600)
>[160051.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160051.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160051.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160052.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160052.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160052.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160053.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff22c0]
>[160053.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff22c0] width 1600 pitch 6400 (/4 1600)
>[160053.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160054.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160054.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0140]
>[160054.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0140] width 1600 pitch 6400 (/4 1600)
>[160054.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160054.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160055.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160055.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160055.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160055.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160055.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce310]
>[160055.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce310] width 1600 pitch 6400 (/4 1600)
>[160056.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[160056.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1600 pitch 6400 (/4 1600)
>[160104.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[160104.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1600 pitch 6400 (/4 1600)
>[160104.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160104.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160105.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbf2f0]
>[160105.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbf2f0] width 1600 pitch 6400 (/4 1600)
>[160122.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0140]
>[160122.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0140] width 1600 pitch 6400 (/4 1600)
>[160122.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80580]
>[160122.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80580] width 1600 pitch 6400 (/4 1600)
>[160122.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db2f60]
>[160122.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db2f60] width 1600 pitch 6400 (/4 1600)
>[160122.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160122.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160122.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160122.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160122.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160122.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160122.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[160122.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1600 pitch 6400 (/4 1600)
>[160122.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160122.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160122.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160122.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160122.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160122.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160122.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce310]
>[160122.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce310] width 1600 pitch 6400 (/4 1600)
>[160122.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160122.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160122.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[160122.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1600 pitch 6400 (/4 1600)
>[160122.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160122.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160122.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160122.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160122.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160122.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160122.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160126.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160126.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160126.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160126.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160126.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160126.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160126.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160126.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160126.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160126.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160126.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160126.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160126.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160127.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160127.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160127.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160127.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160127.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160127.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160127.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160127.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160127.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160127.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160127.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160127.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160127.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160127.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160127.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160128.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160128.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160128.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160128.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160128.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160128.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160128.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[160128.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[160128.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160128.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160129.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160129.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160129.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80580]
>[160129.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80580] width 1600 pitch 6400 (/4 1600)
>[160129.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160129.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160129.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80580]
>[160129.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80580] width 1600 pitch 6400 (/4 1600)
>[160129.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160129.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160129.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80580]
>[160129.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80580] width 1600 pitch 6400 (/4 1600)
>[160129.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160129.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160129.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f80580]
>[160129.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f80580] width 1600 pitch 6400 (/4 1600)
>[160129.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160129.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160129.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160129.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160129.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160129.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160129.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160129.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160129.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[160129.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[160129.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160129.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160129.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160129.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160129.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160129.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160129.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160129.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160129.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160129.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160129.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160130.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160130.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f335b0]
>[160130.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f335b0] width 1600 pitch 6400 (/4 1600)
>[160130.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160130.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160130.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbf2f0]
>[160130.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbf2f0] width 1600 pitch 6400 (/4 1600)
>[160130.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160130.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160130.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160130.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160130.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160131.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[160131.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[160131.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160131.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160175.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160175.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160175.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160175.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160175.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160175.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160175.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160175.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160175.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160175.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160175.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160175.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160176.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160176.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160176.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160176.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160176.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160176.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160176.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160176.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160176.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160176.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160176.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160176.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160176.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160176.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160176.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160176.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160176.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160176.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160176.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160176.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160176.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160176.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160176.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[160176.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[160180.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160180.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160180.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160180.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160180.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160180.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160180.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160180.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160180.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c310]
>[160180.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c310] width 1600 pitch 6400 (/4 1600)
>[160180.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160180.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160180.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[160180.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[160180.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160180.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160180.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea7e50]
>[160180.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea7e50] width 1600 pitch 6400 (/4 1600)
>[160180.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242d210]
>[160180.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242d210] width 1600 pitch 6400 (/4 1600)
>[160180.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6b020]
>[160180.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6b020] width 1600 pitch 6400 (/4 1600)
>[160180.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db2f60]
>[160180.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db2f60] width 1600 pitch 6400 (/4 1600)
>[160322.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160322.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160322.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160322.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160322.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160322.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160322.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160322.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160322.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160322.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160322.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160322.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160322.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160322.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160322.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160322.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160322.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160322.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160322.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160322.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160322.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160322.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160322.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160322.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160322.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160322.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160322.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160322.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160322.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160322.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160322.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160322.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160322.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160322.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160322.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160322.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160322.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160322.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160323.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160323.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160323.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160323.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160323.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160323.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160323.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160323.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160323.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160323.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160323.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160323.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160323.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160323.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160323.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160323.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160323.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160323.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160323.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160323.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160323.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160323.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160323.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160323.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160323.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160323.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160323.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160323.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160323.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160323.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160323.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160323.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160323.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160323.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160323.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160323.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160323.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160323.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160323.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160323.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160323.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160323.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160323.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160323.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160323.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160323.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160323.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160324.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160324.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160324.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160324.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160324.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160324.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160324.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160324.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160324.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160324.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160324.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160324.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160324.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160324.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160324.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160324.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160324.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160324.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160324.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160324.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160324.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160324.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160324.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160324.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160343.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160343.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160343.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160343.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160343.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160343.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160343.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160343.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160343.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160343.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160343.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160343.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160343.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160343.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160343.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160343.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160343.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160343.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160343.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160343.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160343.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160343.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160343.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160343.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160343.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160343.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160343.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[160343.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[160343.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160343.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160344.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160344.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160344.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160344.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160344.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160344.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160344.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160344.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160344.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160344.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160345.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160345.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160348.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[160348.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[160348.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160348.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160348.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160348.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160348.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160348.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160348.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160348.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160348.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160348.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160348.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160348.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160348.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160348.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160348.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160348.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160348.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160348.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160348.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160348.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160348.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160348.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160348.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[160348.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[160348.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b31b40]
>[160348.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b31b40] width 1600 pitch 6400 (/4 1600)
>[160348.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89270]
>[160348.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89270] width 1600 pitch 6400 (/4 1600)
>[160348.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[160348.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[160348.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160348.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160348.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[160348.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[160348.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160348.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160348.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[160348.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[160348.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160348.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160348.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393c1d0]
>[160348.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393c1d0] width 1600 pitch 6400 (/4 1600)
>[160348.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160348.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160348.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[160348.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[160348.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[160348.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[160352.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9dc0]
>[160352.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9dc0] width 1600 pitch 6400 (/4 1600)
>[160352.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[160352.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[160400.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[160400.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[160400.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[160400.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[160401.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7970]
>[160401.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7970] width 1600 pitch 6400 (/4 1600)
>[160401.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a23140]
>[160401.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a23140] width 1600 pitch 6400 (/4 1600)
>[160402.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a23140]
>[160402.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a23140] width 1600 pitch 6400 (/4 1600)
>[160403.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a46150]
>[160403.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a46150] width 1600 pitch 6400 (/4 1600)
>[160469.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c55380]
>[160469.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c55380] width 1600 pitch 6400 (/4 1600)
>[160470.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508c850]
>[160470.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508c850] width 1600 pitch 6400 (/4 1600)
>[160470.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b360]
>[160470.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b360] width 1600 pitch 6400 (/4 1600)
>[160470.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd410]
>[160470.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd410] width 1600 pitch 6400 (/4 1600)
>[160470.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b360]
>[160470.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b360] width 1600 pitch 6400 (/4 1600)
>[160470.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd410]
>[160470.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd410] width 1600 pitch 6400 (/4 1600)
>[160470.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160470.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160470.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd410]
>[160470.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd410] width 1600 pitch 6400 (/4 1600)
>[160470.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160470.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160470.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd410]
>[160470.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd410] width 1600 pitch 6400 (/4 1600)
>[160470.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160470.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160470.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40fd410]
>[160470.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40fd410] width 1600 pitch 6400 (/4 1600)
>[160472.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3936cb0]
>[160472.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3936cb0] width 1600 pitch 6400 (/4 1600)
>[160472.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55070]
>[160472.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55070] width 1600 pitch 6400 (/4 1600)
>[160477.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55070]
>[160477.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55070] width 1600 pitch 6400 (/4 1600)
>[160478.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0e50]
>[160478.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0e50] width 1600 pitch 6400 (/4 1600)
>[160492.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55070]
>[160492.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55070] width 1600 pitch 6400 (/4 1600)
>[160492.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160492.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160492.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55070]
>[160492.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55070] width 1600 pitch 6400 (/4 1600)
>[160512.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60af0]
>[160512.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60af0] width 1600 pitch 6400 (/4 1600)
>[160512.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508c850]
>[160512.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508c850] width 1600 pitch 6400 (/4 1600)
>[160512.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b310]
>[160512.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b310] width 1600 pitch 6400 (/4 1600)
>[160512.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aced00]
>[160512.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aced00] width 1600 pitch 6400 (/4 1600)
>[160512.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b310]
>[160512.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b310] width 1600 pitch 6400 (/4 1600)
>[160512.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035c30]
>[160512.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035c30] width 1600 pitch 6400 (/4 1600)
>[160512.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b310]
>[160512.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b310] width 1600 pitch 6400 (/4 1600)
>[160512.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035c30]
>[160512.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035c30] width 1600 pitch 6400 (/4 1600)
>[160512.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b310]
>[160512.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b310] width 1600 pitch 6400 (/4 1600)
>[160512.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035c30]
>[160512.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035c30] width 1600 pitch 6400 (/4 1600)
>[160512.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b310]
>[160512.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b310] width 1600 pitch 6400 (/4 1600)
>[160512.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035c30]
>[160512.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035c30] width 1600 pitch 6400 (/4 1600)
>[160512.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075390]
>[160512.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075390] width 1600 pitch 6400 (/4 1600)
>[160512.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4035c30]
>[160512.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4035c30] width 1600 pitch 6400 (/4 1600)
>[160528.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a909c0]
>[160528.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a909c0] width 1600 pitch 6400 (/4 1600)
>[160528.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160528.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160528.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160528.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160528.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160528.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160528.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160528.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160528.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160528.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160528.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160528.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160528.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160529.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160529.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160529.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160529.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160529.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160529.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160529.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160529.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160529.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160529.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160529.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160529.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db33a0]
>[160529.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db33a0] width 1600 pitch 6400 (/4 1600)
>[160529.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c63490]
>[160529.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c63490] width 1600 pitch 6400 (/4 1600)
>[160533.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160533.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160533.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160533.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160533.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160538.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160538.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160538.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160538.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160539.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160539.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160539.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160539.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160539.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160539.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160539.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160539.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160539.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160539.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160539.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160539.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160539.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877890]
>[160539.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877890] width 1600 pitch 6400 (/4 1600)
>[160539.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12400]
>[160539.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12400] width 1600 pitch 6400 (/4 1600)
>[160540.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160540.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160540.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12400]
>[160540.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12400] width 1600 pitch 6400 (/4 1600)
>[160590.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12400]
>[160590.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12400] width 1600 pitch 6400 (/4 1600)
>[160590.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160590.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160590.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12400]
>[160590.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12400] width 1600 pitch 6400 (/4 1600)
>[160590.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160590.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160674.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160674.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160674.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160675.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8220]
>[160675.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8220] width 1600 pitch 6400 (/4 1600)
>[160675.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160675.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160707.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160707.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160707.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160707.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160707.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160707.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160707.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160708.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160708.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160708.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61240]
>[160708.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61240] width 1600 pitch 6400 (/4 1600)
>[160712.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160712.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160712.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160712.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160712.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064d30]
>[160712.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064d30] width 1600 pitch 6400 (/4 1600)
>[160712.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160712.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160712.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160712.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160712.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064cd0]
>[160713.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064cd0] width 1600 pitch 6400 (/4 1600)
>[160713.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f50f0]
>[160713.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f50f0] width 1600 pitch 6400 (/4 1600)
>[160713.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a909c0]
>[160713.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a909c0] width 1600 pitch 6400 (/4 1600)
>[160713.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160713.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160713.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160713.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160713.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160713.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160713.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f5090]
>[160713.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f5090] width 1600 pitch 6400 (/4 1600)
>[160713.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf4a0]
>[160713.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf4a0] width 1600 pitch 6400 (/4 1600)
>[160713.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160713.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160713.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160713.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160713.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160713.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160713.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160713.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160713.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160713.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160713.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcdcd0]
>[160714.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcdcd0] width 1600 pitch 6400 (/4 1600)
>[160714.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d863c0]
>[160714.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d863c0] width 1600 pitch 6400 (/4 1600)
>[160714.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b51830]
>[160714.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b51830] width 1600 pitch 6400 (/4 1600)
>[160715.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160715.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160737.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9e370]
>[160737.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9e370] width 1600 pitch 6400 (/4 1600)
>[160737.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2f2b0]
>[160737.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2f2b0] width 1600 pitch 6400 (/4 1600)
>[160737.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160737.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160738.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160738.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160738.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b220]
>[160738.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b220] width 1600 pitch 6400 (/4 1600)
>[160780.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5b720]
>[160780.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5b720] width 1600 pitch 6400 (/4 1600)
>[160780.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5b720]
>[160780.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5b720] width 1600 pitch 6400 (/4 1600)
>[160780.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28117e0]
>[160780.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28117e0] width 1600 pitch 6400 (/4 1600)
>[160781.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811780]
>[160781.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811780] width 1600 pitch 6400 (/4 1600)
>[160781.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34ad0]
>[160781.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34ad0] width 1600 pitch 6400 (/4 1600)
>[160781.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835d80]
>[160781.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835d80] width 1600 pitch 6400 (/4 1600)
>[160781.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34ad0]
>[160781.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34ad0] width 1600 pitch 6400 (/4 1600)
>[160781.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811780]
>[160781.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811780] width 1600 pitch 6400 (/4 1600)
>[160781.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34ad0]
>[160781.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34ad0] width 1600 pitch 6400 (/4 1600)
>[160781.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8c2d0]
>[160781.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8c2d0] width 1600 pitch 6400 (/4 1600)
>[160781.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a116a0]
>[160781.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a116a0] width 1600 pitch 6400 (/4 1600)
>[160781.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34ad0]
>[160781.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34ad0] width 1600 pitch 6400 (/4 1600)
>[160781.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a116a0]
>[160781.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a116a0] width 1600 pitch 6400 (/4 1600)
>[160781.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34ad0]
>[160781.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34ad0] width 1600 pitch 6400 (/4 1600)
>[160781.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a116a0]
>[160781.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a116a0] width 1600 pitch 6400 (/4 1600)
>[160785.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160785.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca8660]
>[160785.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca8660] width 1600 pitch 6400 (/4 1600)
>[160785.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5cd20]
>[160785.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5cd20] width 1600 pitch 6400 (/4 1600)
>[160820.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160820.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[160820.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[160820.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160820.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160822.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816940]
>[160822.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816940] width 1600 pitch 6400 (/4 1600)
>[160822.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[160822.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[160823.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069480]
>[160823.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069480] width 1600 pitch 6400 (/4 1600)
>[160823.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[160823.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[160856.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8c190]
>[160856.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8c190] width 1600 pitch 6400 (/4 1600)
>[160856.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[160856.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[160896.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[160896.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[160896.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[160896.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[160896.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[160896.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[160896.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[160896.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[160896.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[160896.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161072.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161072.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161073.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161073.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161075.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161075.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161075.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161075.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161101.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2816bf0]
>[161101.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2816bf0] width 1600 pitch 6400 (/4 1600)
>[161101.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161101.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161101.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161101.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161102.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161102.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161152.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161152.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161152.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161152.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161154.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161154.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161154.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161154.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161169.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161169.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161169.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161169.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161169.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161169.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161169.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161169.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161169.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161169.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161169.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161169.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161169.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161169.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161169.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161173.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161173.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161173.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161173.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161173.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161173.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161173.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161173.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161173.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161173.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161173.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161173.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161173.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161173.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161173.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161173.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161173.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161173.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161173.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7300]
>[161173.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7300] width 1600 pitch 6400 (/4 1600)
>[161181.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161181.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161181.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161181.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161182.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161182.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161182.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161182.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161186.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161186.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161186.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161186.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161199.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161199.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161199.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40aa5b0]
>[161199.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40aa5b0] width 1600 pitch 6400 (/4 1600)
>[161199.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8600]
>[161199.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8600] width 1600 pitch 6400 (/4 1600)
>[161199.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161199.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161214.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161214.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161214.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161214.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161214.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161214.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161214.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161214.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161215.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161215.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161215.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161215.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161215.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161215.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161215.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161215.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161220.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161220.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161220.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161220.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161220.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161220.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161220.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161220.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161220.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161220.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161226.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161226.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161230.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161230.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161230.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161230.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161230.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161230.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161230.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161230.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161230.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161230.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161230.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161234.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b401d0]
>[161234.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b401d0] width 1600 pitch 6400 (/4 1600)
>[161234.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9f0d0]
>[161234.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9f0d0] width 1600 pitch 6400 (/4 1600)
>[161234.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[161234.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[161234.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[161234.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[161234.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[161234.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[161234.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[161234.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[161234.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161234.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161234.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[161234.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[161236.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fed0]
>[161236.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fed0] width 1600 pitch 6400 (/4 1600)
>[161237.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161237.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161237.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161237.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161237.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[161237.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1600 pitch 6400 (/4 1600)
>[161237.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161237.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161237.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[161237.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1600 pitch 6400 (/4 1600)
>[161239.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161240.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161249.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161249.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161253.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d4a0]
>[161253.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d4a0] width 1600 pitch 6400 (/4 1600)
>[161253.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1caa0]
>[161253.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1caa0] width 1600 pitch 6400 (/4 1600)
>[161264.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161264.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161264.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd740]
>[161264.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd740] width 1600 pitch 6400 (/4 1600)
>[161264.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161264.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161265.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161265.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161276.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161276.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161277.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07970]
>[161277.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07970] width 1600 pitch 6400 (/4 1600)
>[161278.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07970]
>[161278.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07970] width 1600 pitch 6400 (/4 1600)
>[161278.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161278.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161280.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161281.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161281.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161281.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161281.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb5d0]
>[161281.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb5d0] width 1600 pitch 6400 (/4 1600)
>[161281.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161281.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161286.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161286.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161287.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161287.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161288.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161288.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161288.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161288.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161314.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd7e0]
>[161314.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd7e0] width 1600 pitch 6400 (/4 1600)
>[161314.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161314.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161314.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161314.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161314.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3f90]
>[161314.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3f90] width 1600 pitch 6400 (/4 1600)
>[161314.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161314.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161314.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3f90]
>[161314.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3f90] width 1600 pitch 6400 (/4 1600)
>[161314.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161314.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161314.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3f90]
>[161314.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3f90] width 1600 pitch 6400 (/4 1600)
>[161314.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161314.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161314.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3f90]
>[161314.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3f90] width 1600 pitch 6400 (/4 1600)
>[161314.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e890]
>[161314.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e890] width 1600 pitch 6400 (/4 1600)
>[161315.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161315.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161315.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161315.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161316.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161316.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161319.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161319.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161319.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161319.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161320.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161320.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161320.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161320.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161320.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161320.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161321.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df5660]
>[161321.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df5660] width 1600 pitch 6400 (/4 1600)
>[161327.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1260]
>[161327.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1260] width 1600 pitch 6400 (/4 1600)
>[161327.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161327.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161330.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7970]
>[161330.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7970] width 1600 pitch 6400 (/4 1600)
>[161330.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e92e60]
>[161330.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e92e60] width 1600 pitch 6400 (/4 1600)
>[161330.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2f510]
>[161330.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2f510] width 1600 pitch 6400 (/4 1600)
>[161330.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfeb70]
>[161330.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfeb70] width 1600 pitch 6400 (/4 1600)
>[161330.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df37f0]
>[161330.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df37f0] width 1600 pitch 6400 (/4 1600)
>[161330.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfeb70]
>[161330.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfeb70] width 1600 pitch 6400 (/4 1600)
>[161330.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df37f0]
>[161330.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df37f0] width 1600 pitch 6400 (/4 1600)
>[161330.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfeb70]
>[161330.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfeb70] width 1600 pitch 6400 (/4 1600)
>[161330.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df37f0]
>[161330.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df37f0] width 1600 pitch 6400 (/4 1600)
>[161330.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161330.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc59d0]
>[161330.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc59d0] width 1600 pitch 6400 (/4 1600)
>[161330.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d098e0]
>[161330.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d098e0] width 1600 pitch 6400 (/4 1600)
>[161334.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09890]
>[161334.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09890] width 1600 pitch 6400 (/4 1600)
>[161334.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bf3d0]
>[161334.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bf3d0] width 1600 pitch 6400 (/4 1600)
>[161335.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161335.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161337.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161337.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161337.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c240]
>[161337.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c240] width 1600 pitch 6400 (/4 1600)
>[161337.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c240]
>[161337.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c240] width 1600 pitch 6400 (/4 1600)
>[161337.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c240]
>[161338.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c240] width 1600 pitch 6400 (/4 1600)
>[161338.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161338.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161338.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x396c1c0]
>[161338.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x396c1c0] width 1600 pitch 6400 (/4 1600)
>[161340.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c4e80]
>[161340.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c4e80] width 1600 pitch 6400 (/4 1600)
>[161340.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505a570]
>[161340.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505a570] width 1600 pitch 6400 (/4 1600)
>[161340.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[161340.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[161340.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21d10]
>[161340.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21d10] width 1600 pitch 6400 (/4 1600)
>[161340.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec2420]
>[161340.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec2420] width 1600 pitch 6400 (/4 1600)
>[161340.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a21d10]
>[161340.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a21d10] width 1600 pitch 6400 (/4 1600)
>[161340.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec2420]
>[161340.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec2420] width 1600 pitch 6400 (/4 1600)
>[161340.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ea150]
>[161340.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ea150] width 1600 pitch 6400 (/4 1600)
>[161340.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec2420]
>[161340.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec2420] width 1600 pitch 6400 (/4 1600)
>[161345.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161345.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161345.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161345.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161345.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161346.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161346.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161346.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161346.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161349.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161349.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161350.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43f60]
>[161350.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43f60] width 1600 pitch 6400 (/4 1600)
>[161410.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161410.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161410.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161410.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161410.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[161410.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[161410.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161410.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[161410.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[161410.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161410.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[161410.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[161410.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161410.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[161410.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[161410.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161410.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161411.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[161411.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[161411.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161411.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161412.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a8650]
>[161412.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a8650] width 1600 pitch 6400 (/4 1600)
>[161412.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161412.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161412.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161412.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161425.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161425.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161425.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc25c0]
>[161425.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc25c0] width 1600 pitch 6400 (/4 1600)
>[161425.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ff30]
>[161425.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ff30] width 1600 pitch 6400 (/4 1600)
>[161426.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ff30]
>[161426.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ff30] width 1600 pitch 6400 (/4 1600)
>[161426.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[161426.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[161427.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4d330]
>[161427.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4d330] width 1600 pitch 6400 (/4 1600)
>[161428.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c890]
>[161428.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c890] width 1600 pitch 6400 (/4 1600)
>[161428.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161428.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161428.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[161428.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[161428.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[161428.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[161428.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161428.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161428.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ff30]
>[161428.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ff30] width 1600 pitch 6400 (/4 1600)
>[161429.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161429.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161429.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac11f0]
>[161429.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac11f0] width 1600 pitch 6400 (/4 1600)
>[161430.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac11f0]
>[161430.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac11f0] width 1600 pitch 6400 (/4 1600)
>[161431.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac11f0]
>[161431.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac11f0] width 1600 pitch 6400 (/4 1600)
>[161431.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[161431.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[161432.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa2770]
>[161432.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa2770] width 1600 pitch 6400 (/4 1600)
>[161542.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161542.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161542.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[161542.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[161542.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161542.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161542.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[161542.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[161542.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069620]
>[161542.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069620] width 1600 pitch 6400 (/4 1600)
>[161542.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161542.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161542.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069620]
>[161542.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069620] width 1600 pitch 6400 (/4 1600)
>[161542.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161542.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161542.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069620]
>[161542.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069620] width 1600 pitch 6400 (/4 1600)
>[161542.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161542.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161542.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069620]
>[161542.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069620] width 1600 pitch 6400 (/4 1600)
>[161542.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161542.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161542.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069620]
>[161542.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069620] width 1600 pitch 6400 (/4 1600)
>[161544.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[161544.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[161544.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[161544.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[161578.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061b70]
>[161578.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061b70] width 1600 pitch 6400 (/4 1600)
>[161578.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8dc20]
>[161578.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8dc20] width 1600 pitch 6400 (/4 1600)
>[161578.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a248d0]
>[161578.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a248d0] width 1600 pitch 6400 (/4 1600)
>[161578.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8dc20]
>[161578.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8dc20] width 1600 pitch 6400 (/4 1600)
>[161578.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a248d0]
>[161578.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a248d0] width 1600 pitch 6400 (/4 1600)
>[161578.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9060]
>[161578.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9060] width 1600 pitch 6400 (/4 1600)
>[161588.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9060]
>[161588.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9060] width 1600 pitch 6400 (/4 1600)
>[161588.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[161588.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[161589.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161589.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161589.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[161589.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[161592.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[161592.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[161593.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161593.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161593.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161593.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161593.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161593.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9d0]
>[161593.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9d0] width 1600 pitch 6400 (/4 1600)
>[161593.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71950]
>[161593.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71950] width 1600 pitch 6400 (/4 1600)
>[161641.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e99cd0]
>[161641.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e99cd0] width 1600 pitch 6400 (/4 1600)
>[161641.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161641.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161642.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[161642.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[161642.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89270]
>[161642.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89270] width 1600 pitch 6400 (/4 1600)
>[161642.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161642.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161643.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89270]
>[161643.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89270] width 1600 pitch 6400 (/4 1600)
>[161648.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80690]
>[161648.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80690] width 1600 pitch 6400 (/4 1600)
>[161648.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a11390]
>[161648.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a11390] width 1600 pitch 6400 (/4 1600)
>[161649.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a24670]
>[161649.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a24670] width 1600 pitch 6400 (/4 1600)
>[161649.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161649.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161659.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5104060]
>[161659.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5104060] width 1600 pitch 6400 (/4 1600)
>[161659.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161659.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161659.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161659.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161659.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24930]
>[161659.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24930] width 1600 pitch 6400 (/4 1600)
>[161659.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161659.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161659.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161659.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[161659.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[161659.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161659.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161663.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161663.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161663.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161663.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161663.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161663.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161663.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161663.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161663.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161663.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161663.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161663.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161663.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161663.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161663.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161663.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161663.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161664.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161664.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161664.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161664.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161664.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161664.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161664.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161664.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[161664.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[161664.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea9040]
>[161664.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea9040] width 1600 pitch 6400 (/4 1600)
>[161680.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161680.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161680.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161680.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161680.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161681.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161681.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161681.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161681.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161735.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161735.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161735.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161735.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161735.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161735.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161735.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161735.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161751.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161751.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161751.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161751.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161751.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161751.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161751.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161751.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161751.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161751.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161751.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161751.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161751.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161751.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161756.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161756.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161756.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161756.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161756.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161756.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161756.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161756.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161756.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161756.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161756.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161756.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161756.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161756.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161756.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161756.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161756.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161756.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161756.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161756.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161756.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161756.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161756.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161756.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161756.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161756.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161756.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161756.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161756.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161756.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161756.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161756.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161756.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161756.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161756.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161756.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161756.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161756.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161756.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161756.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161756.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161757.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161757.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161757.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161792.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161792.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161792.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161792.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161792.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[161792.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[161792.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161792.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161792.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161792.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161792.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161792.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161792.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161792.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161792.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161792.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[161792.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[161792.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[161792.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[161792.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161792.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161792.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161792.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161792.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161792.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161792.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161792.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161793.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161793.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161793.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161793.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161793.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161793.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161793.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161793.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161793.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161793.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161793.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161793.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161793.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[161793.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[161794.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf10]
>[161794.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf10] width 1600 pitch 6400 (/4 1600)
>[161794.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf10]
>[161794.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf10] width 1600 pitch 6400 (/4 1600)
>[161794.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161794.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161794.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161794.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161794.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf20]
>[161794.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf20] width 1600 pitch 6400 (/4 1600)
>[161794.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf20]
>[161795.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf20] width 1600 pitch 6400 (/4 1600)
>[161795.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161795.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161795.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[161795.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[161795.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161795.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161795.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf20]
>[161795.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf20] width 1600 pitch 6400 (/4 1600)
>[161795.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161795.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161795.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[161795.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[161795.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[161795.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[161795.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf20]
>[161795.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf20] width 1600 pitch 6400 (/4 1600)
>[161795.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161795.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161795.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381bf20]
>[161795.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381bf20] width 1600 pitch 6400 (/4 1600)
>[161795.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3df80]
>[161795.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3df80] width 1600 pitch 6400 (/4 1600)
>[161795.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161795.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161795.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3df80]
>[161795.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3df80] width 1600 pitch 6400 (/4 1600)
>[161850.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161850.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161850.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069820]
>[161850.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069820] width 1600 pitch 6400 (/4 1600)
>[161850.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161850.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161850.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eda040]
>[161850.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eda040] width 1600 pitch 6400 (/4 1600)
>[161850.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[161850.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[161850.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[161850.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[161850.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161850.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161878.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161878.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161878.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[161878.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[161878.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[161878.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[161879.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[161879.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[161879.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2e0]
>[161879.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2e0] width 1600 pitch 6400 (/4 1600)
>[161879.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[161879.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1600 pitch 6400 (/4 1600)
>[161879.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069820]
>[161879.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069820] width 1600 pitch 6400 (/4 1600)
>[161881.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[161881.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[161881.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069820]
>[161881.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069820] width 1600 pitch 6400 (/4 1600)
>[161889.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[161889.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[161927.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161927.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161927.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[161927.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[161927.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[161927.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[161927.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[161927.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[161927.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f376e0]
>[161927.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f376e0] width 1600 pitch 6400 (/4 1600)
>[161927.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f376e0]
>[161927.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f376e0] width 1600 pitch 6400 (/4 1600)
>[161927.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1740]
>[161927.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1740] width 1600 pitch 6400 (/4 1600)
>[161927.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161927.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161927.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1740]
>[161928.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1740] width 1600 pitch 6400 (/4 1600)
>[161928.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161928.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161928.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1740]
>[161928.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1740] width 1600 pitch 6400 (/4 1600)
>[161928.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161928.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161928.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1740]
>[161928.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1740] width 1600 pitch 6400 (/4 1600)
>[161928.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161928.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161928.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849600]
>[161928.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849600] width 1600 pitch 6400 (/4 1600)
>[161928.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161928.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161928.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849600]
>[161928.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849600] width 1600 pitch 6400 (/4 1600)
>[161928.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161928.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161928.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849600]
>[161928.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849600] width 1600 pitch 6400 (/4 1600)
>[161930.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[161930.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[161961.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0820]
>[161961.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0820] width 1600 pitch 6400 (/4 1600)
>[161961.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efbb70]
>[161961.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efbb70] width 1600 pitch 6400 (/4 1600)
>[161961.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[161961.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[161961.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efbb70]
>[161961.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efbb70] width 1600 pitch 6400 (/4 1600)
>[161961.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501d0f0]
>[161961.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501d0f0] width 1600 pitch 6400 (/4 1600)
>[161961.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc500]
>[161961.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc500] width 1600 pitch 6400 (/4 1600)
>[161961.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ee70]
>[161961.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ee70] width 1600 pitch 6400 (/4 1600)
>[161961.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[161961.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[161961.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ee70]
>[161961.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ee70] width 1600 pitch 6400 (/4 1600)
>[161961.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1b120]
>[161961.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1b120] width 1600 pitch 6400 (/4 1600)
>[161961.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[161961.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[161961.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c310]
>[161961.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c310] width 1600 pitch 6400 (/4 1600)
>[161961.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[161961.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[161961.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403d0c0]
>[161961.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403d0c0] width 1600 pitch 6400 (/4 1600)
>[161961.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[161961.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[161961.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161961.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161961.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161962.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[161962.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[161962.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[161962.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[161964.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6830]
>[161964.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6830] width 1600 pitch 6400 (/4 1600)
>[161964.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0fd0]
>[161964.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0fd0] width 1600 pitch 6400 (/4 1600)
>[161964.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6830]
>[161964.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6830] width 1600 pitch 6400 (/4 1600)
>[161964.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161964.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161966.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10330]
>[161966.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10330] width 1600 pitch 6400 (/4 1600)
>[161966.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[161966.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[161973.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[161973.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[161979.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161979.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161979.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161979.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161979.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161979.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161980.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[161980.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[161980.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[161980.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[161981.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[161981.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[161981.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0fd0]
>[161981.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0fd0] width 1600 pitch 6400 (/4 1600)
>[162013.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0820]
>[162013.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0820] width 1600 pitch 6400 (/4 1600)
>[162013.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c2c0]
>[162013.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c2c0] width 1600 pitch 6400 (/4 1600)
>[162013.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c340]
>[162013.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c340] width 1600 pitch 6400 (/4 1600)
>[162013.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b85b0]
>[162013.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b85b0] width 1600 pitch 6400 (/4 1600)
>[162013.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[162013.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[162014.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b85b0]
>[162014.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b85b0] width 1600 pitch 6400 (/4 1600)
>[162014.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[162014.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[162014.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b85b0]
>[162014.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b85b0] width 1600 pitch 6400 (/4 1600)
>[162014.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[162014.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[162014.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b85b0]
>[162014.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b85b0] width 1600 pitch 6400 (/4 1600)
>[162014.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[162014.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[162014.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b85b0]
>[162014.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b85b0] width 1600 pitch 6400 (/4 1600)
>[162016.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162016.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162016.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162016.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162017.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b360]
>[162017.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b360] width 1600 pitch 6400 (/4 1600)
>[162018.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc500]
>[162018.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc500] width 1600 pitch 6400 (/4 1600)
>[162018.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[162018.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[162018.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc500]
>[162018.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc500] width 1600 pitch 6400 (/4 1600)
>[162018.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[162018.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[162018.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc500]
>[162018.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc500] width 1600 pitch 6400 (/4 1600)
>[162018.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[162018.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[162018.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162018.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162018.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162018.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162018.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162018.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162018.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162018.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162018.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162018.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162018.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162018.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162018.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162018.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162018.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162018.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162019.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[162019.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[162081.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0820]
>[162081.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0820] width 1600 pitch 6400 (/4 1600)
>[162081.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[162081.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[162081.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4fb20]
>[162081.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4fb20] width 1600 pitch 6400 (/4 1600)
>[162083.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f214e0]
>[162083.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f214e0] width 1600 pitch 6400 (/4 1600)
>[162084.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[162084.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[162086.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501d0f0]
>[162086.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501d0f0] width 1600 pitch 6400 (/4 1600)
>[162087.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[162087.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[162089.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e940]
>[162089.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e940] width 1600 pitch 6400 (/4 1600)
>[162090.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[162090.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[162092.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5e960]
>[162092.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5e960] width 1600 pitch 6400 (/4 1600)
>[162093.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506d020]
>[162093.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506d020] width 1600 pitch 6400 (/4 1600)
>[162095.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[162095.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[162097.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6c310]
>[162097.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6c310] width 1600 pitch 6400 (/4 1600)
>[162098.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c340]
>[162098.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c340] width 1600 pitch 6400 (/4 1600)
>[162100.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6f8d0]
>[162100.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6f8d0] width 1600 pitch 6400 (/4 1600)
>[162100.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[162100.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[162101.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71090]
>[162101.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71090] width 1600 pitch 6400 (/4 1600)
>[162103.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[162103.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[162104.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[162104.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[162106.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4041890]
>[162106.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4041890] width 1600 pitch 6400 (/4 1600)
>[162169.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162169.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162169.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069820]
>[162169.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069820] width 1600 pitch 6400 (/4 1600)
>[162170.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162170.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162171.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efbb70]
>[162171.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efbb70] width 1600 pitch 6400 (/4 1600)
>[162171.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162171.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162171.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[162171.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[162171.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162171.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162211.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162211.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162211.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[162211.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1600 pitch 6400 (/4 1600)
>[162211.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162211.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162212.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162212.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162213.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162213.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162215.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162215.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162215.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162215.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162216.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162216.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162218.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162218.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162218.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162218.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162218.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162218.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162220.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[162220.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[162221.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162221.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162223.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9bea0]
>[162223.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9bea0] width 1600 pitch 6400 (/4 1600)
>[162224.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162224.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162226.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162226.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162243.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162243.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162243.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162243.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162243.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162243.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162243.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162243.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162244.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162244.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162244.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162244.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162244.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162245.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[162245.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1600 pitch 6400 (/4 1600)
>[162245.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162245.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162246.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162246.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162246.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162246.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162248.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162248.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162249.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40389e0]
>[162249.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40389e0] width 1600 pitch 6400 (/4 1600)
>[162250.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162250.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162250.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162250.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162250.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162250.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162251.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25c70]
>[162251.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25c70] width 1600 pitch 6400 (/4 1600)
>[162251.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162251.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162251.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162251.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162251.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162251.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162251.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162251.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162251.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162251.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162251.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162251.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162251.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162251.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162251.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162251.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162251.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162251.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162251.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162251.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162251.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162251.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162251.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162251.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162251.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162251.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162251.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162251.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162251.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162251.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162252.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162252.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162253.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04a50]
>[162253.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04a50] width 1600 pitch 6400 (/4 1600)
>[162253.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162253.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162253.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40389e0]
>[162253.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40389e0] width 1600 pitch 6400 (/4 1600)
>[162254.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[162254.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1600 pitch 6400 (/4 1600)
>[162254.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162254.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162255.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162255.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162255.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162255.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162256.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162256.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162257.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162257.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162257.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162257.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162257.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162257.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162257.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162257.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162257.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162257.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162257.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162257.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162257.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162257.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162257.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162257.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162257.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162257.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162257.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f25c70]
>[162257.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f25c70] width 1600 pitch 6400 (/4 1600)
>[162257.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162257.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162257.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162257.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162260.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162260.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162260.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162260.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162260.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162260.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162261.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c777e0]
>[162261.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c777e0] width 1600 pitch 6400 (/4 1600)
>[162261.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162261.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162261.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162261.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162261.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162261.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162261.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162261.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162261.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162261.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162261.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162261.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162261.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162261.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162261.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162261.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162261.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162290.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162290.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162290.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162290.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162291.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162291.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162292.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162292.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162292.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162292.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162292.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162292.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162305.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162305.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162305.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162305.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162306.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162306.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162306.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162306.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162306.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162306.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162306.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162306.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162306.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162306.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162306.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162306.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162306.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162306.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162306.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162306.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162306.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162306.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162306.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162306.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162306.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162306.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162306.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162306.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162306.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbad20]
>[162307.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbad20] width 1600 pitch 6400 (/4 1600)
>[162307.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162307.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162308.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8e0]
>[162308.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8e0] width 1600 pitch 6400 (/4 1600)
>[162309.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162309.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162309.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162309.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162311.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162311.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162311.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8e0]
>[162311.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8e0] width 1600 pitch 6400 (/4 1600)
>[162311.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162311.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162311.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[162311.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1600 pitch 6400 (/4 1600)
>[162312.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162312.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162312.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162312.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162312.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162312.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162312.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162312.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162312.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162312.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162312.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162312.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162312.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162312.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162312.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162312.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162312.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162312.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162312.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162315.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162315.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162315.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162315.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162315.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505e2f0]
>[162315.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505e2f0] width 1600 pitch 6400 (/4 1600)
>[162316.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162316.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162316.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162316.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162316.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162316.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162317.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162317.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162322.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162322.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162322.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162322.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162322.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162322.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162323.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162323.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162323.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162323.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162343.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162343.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162343.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162343.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162343.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162343.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162343.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162343.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162343.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162343.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162343.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162343.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162343.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162343.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162343.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162343.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162343.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162343.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162343.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162343.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162343.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162344.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162344.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162344.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162344.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd7e0]
>[162344.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd7e0] width 1600 pitch 6400 (/4 1600)
>[162348.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8e0]
>[162348.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8e0] width 1600 pitch 6400 (/4 1600)
>[162348.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162348.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162361.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162361.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162361.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[162361.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[162361.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162361.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162361.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162361.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162361.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162361.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162361.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162361.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162361.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162361.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162361.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162361.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162361.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162361.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162361.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162361.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162361.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162365.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162365.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162365.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162365.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162365.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162365.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162365.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162366.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162366.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162366.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162366.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb62a0]
>[162366.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb62a0] width 1600 pitch 6400 (/4 1600)
>[162366.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162366.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162366.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[162366.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[162366.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162366.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162366.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[162366.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[162366.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162366.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162366.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8960]
>[162366.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8960] width 1600 pitch 6400 (/4 1600)
>[162366.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162366.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162395.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162395.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162395.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162395.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162396.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162396.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162396.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162396.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162396.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162396.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162396.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162396.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162397.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162397.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162397.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162397.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162398.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162398.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162407.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8e0]
>[162407.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8e0] width 1600 pitch 6400 (/4 1600)
>[162407.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162407.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162408.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162408.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162419.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162419.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162419.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162419.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162420.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162420.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162420.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb1580]
>[162420.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb1580] width 1600 pitch 6400 (/4 1600)
>[162420.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162420.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162420.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162420.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162420.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162420.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162420.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162420.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162420.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162420.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162420.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162420.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162420.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162420.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162420.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162420.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162420.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162420.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162420.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162422.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162422.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162423.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28830]
>[162423.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28830] width 1600 pitch 6400 (/4 1600)
>[162423.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162423.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162423.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50be170]
>[162423.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50be170] width 1600 pitch 6400 (/4 1600)
>[162423.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f9f40]
>[162423.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f9f40] width 1600 pitch 6400 (/4 1600)
>[162424.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162424.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162424.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162424.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162424.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162424.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162425.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162425.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162425.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162425.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162425.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162425.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[162425.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[162425.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162425.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162426.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162426.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162429.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162429.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162429.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51070a0]
>[162429.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51070a0] width 1600 pitch 6400 (/4 1600)
>[162429.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[162429.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[162430.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509dc90]
>[162430.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509dc90] width 1600 pitch 6400 (/4 1600)
>[162430.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efd5d0]
>[162430.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efd5d0] width 1600 pitch 6400 (/4 1600)
>[162431.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19390]
>[162431.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19390] width 1600 pitch 6400 (/4 1600)
>[162454.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162454.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162454.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162454.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162454.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4032b20]
>[162454.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4032b20] width 1600 pitch 6400 (/4 1600)
>[162455.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162455.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162456.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ba8e0]
>[162456.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ba8e0] width 1600 pitch 6400 (/4 1600)
>[162456.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c28db0]
>[162456.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c28db0] width 1600 pitch 6400 (/4 1600)
>[162456.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162456.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162457.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb7af0]
>[162457.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb7af0] width 1600 pitch 6400 (/4 1600)
>[162501.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[162501.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[162501.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162501.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162501.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162501.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162501.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162501.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162501.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162501.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162501.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162501.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162501.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162501.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162501.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162501.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162501.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[162501.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[162501.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162501.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162501.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162501.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162501.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162501.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162501.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162501.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162501.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162502.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[162502.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[162502.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162502.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162503.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162503.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162503.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[162503.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[162550.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c20]
>[162550.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c20] width 1600 pitch 6400 (/4 1600)
>[162550.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162550.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e480]
>[162550.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e480] width 1600 pitch 6400 (/4 1600)
>[162550.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162550.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e480]
>[162550.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e480] width 1600 pitch 6400 (/4 1600)
>[162550.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162550.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e480]
>[162550.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e480] width 1600 pitch 6400 (/4 1600)
>[162550.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162550.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e480]
>[162550.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e480] width 1600 pitch 6400 (/4 1600)
>[162550.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162550.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282e480]
>[162550.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282e480] width 1600 pitch 6400 (/4 1600)
>[162550.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10470]
>[162550.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10470] width 1600 pitch 6400 (/4 1600)
>[162683.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162683.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162683.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403cf70]
>[162683.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403cf70] width 1600 pitch 6400 (/4 1600)
>[162683.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faddb0]
>[162683.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faddb0] width 1600 pitch 6400 (/4 1600)
>[162683.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d697f0]
>[162683.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d697f0] width 1600 pitch 6400 (/4 1600)
>[162683.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faddb0]
>[162683.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faddb0] width 1600 pitch 6400 (/4 1600)
>[162683.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faddb0]
>[162683.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faddb0] width 1600 pitch 6400 (/4 1600)
>[162683.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9cae0]
>[162683.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9cae0] width 1600 pitch 6400 (/4 1600)
>[162683.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faddb0]
>[162683.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faddb0] width 1600 pitch 6400 (/4 1600)
>[162683.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162683.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162683.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162683.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3975320]
>[162683.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3975320] width 1600 pitch 6400 (/4 1600)
>[162684.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed1970]
>[162684.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed1970] width 1600 pitch 6400 (/4 1600)
>[162685.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162685.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162685.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[162685.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1600 pitch 6400 (/4 1600)
>[162685.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14ae0]
>[162685.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14ae0] width 1600 pitch 6400 (/4 1600)
>[162688.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[162688.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[162688.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[162688.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[162688.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fd10]
>[162688.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fd10] width 1600 pitch 6400 (/4 1600)
>[162688.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[162688.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[162688.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162688.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162688.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[162688.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1600 pitch 6400 (/4 1600)
>[162688.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fd10]
>[162688.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fd10] width 1600 pitch 6400 (/4 1600)
>[162688.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[162688.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1600 pitch 6400 (/4 1600)
>[162688.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fd10]
>[162688.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fd10] width 1600 pitch 6400 (/4 1600)
>[162688.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[162688.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1600 pitch 6400 (/4 1600)
>[162688.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fd10]
>[162688.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fd10] width 1600 pitch 6400 (/4 1600)
>[162688.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a405d0]
>[162688.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a405d0] width 1600 pitch 6400 (/4 1600)
>[162692.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162692.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162692.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162692.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162692.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162692.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162692.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162692.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162692.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162693.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162693.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162693.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e807b0]
>[162693.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e807b0] width 1600 pitch 6400 (/4 1600)
>[162695.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef4b0]
>[162695.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef4b0] width 1600 pitch 6400 (/4 1600)
>[162695.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6b90]
>[162695.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6b90] width 1600 pitch 6400 (/4 1600)
>[162696.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5073430]
>[162696.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5073430] width 1600 pitch 6400 (/4 1600)
>[162831.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162831.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162831.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faddb0]
>[162831.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faddb0] width 1600 pitch 6400 (/4 1600)
>[162831.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162831.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162832.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162832.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162832.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162832.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162832.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162832.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162832.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162832.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162832.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162832.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162832.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162832.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162832.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162832.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162832.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162832.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162833.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162833.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162851.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162851.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162851.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162851.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162852.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162852.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162852.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162852.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162852.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162852.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162852.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162852.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162852.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162852.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162852.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162852.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162852.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162852.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162852.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162852.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162852.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162852.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162852.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162852.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[162852.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[162852.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162852.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162852.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162852.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162852.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162852.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162852.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162852.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162852.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162852.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162852.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162853.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162853.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162853.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[162853.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[162853.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162853.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162853.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162853.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162853.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162853.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162853.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162853.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162853.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[162853.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[162853.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4cae0]
>[162853.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4cae0] width 1600 pitch 6400 (/4 1600)
>[162853.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[162853.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[162853.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f370f0]
>[162853.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f370f0] width 1600 pitch 6400 (/4 1600)
>[162854.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd70d0]
>[162854.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd70d0] width 1600 pitch 6400 (/4 1600)
>[162854.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e16bf0]
>[162854.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e16bf0] width 1600 pitch 6400 (/4 1600)
>[162865.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eec470]
>[162865.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eec470] width 1600 pitch 6400 (/4 1600)
>[162874.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7d3b0]
>[162874.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7d3b0] width 1600 pitch 6400 (/4 1600)
>[163039.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d567d0]
>[163039.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d567d0] width 1600 pitch 6400 (/4 1600)
>[163041.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3dc40]
>[163041.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3dc40] width 1600 pitch 6400 (/4 1600)
>[163041.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28ea0]
>[163041.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28ea0] width 1600 pitch 6400 (/4 1600)
>[163041.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3dc40]
>[163041.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3dc40] width 1600 pitch 6400 (/4 1600)
>[163041.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3dc40]
>[163041.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3dc40] width 1600 pitch 6400 (/4 1600)
>[163103.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a8a0]
>[163103.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a8a0] width 1600 pitch 6400 (/4 1600)
>[163104.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a470]
>[163104.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a470] width 1600 pitch 6400 (/4 1600)
>[163104.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6300]
>[163104.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6300] width 1600 pitch 6400 (/4 1600)
>[163104.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a8a0]
>[163104.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a8a0] width 1600 pitch 6400 (/4 1600)
>[163104.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163104.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163105.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f95610]
>[163105.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f95610] width 1600 pitch 6400 (/4 1600)
>[163105.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3fde0]
>[163105.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3fde0] width 1600 pitch 6400 (/4 1600)
>[163149.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163149.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163149.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163149.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163149.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163149.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163149.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163149.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163150.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163150.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163150.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163150.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163151.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163151.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163151.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163151.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163160.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163160.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163160.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163160.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163160.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163160.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163161.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163161.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163161.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163161.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163163.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163163.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163163.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163163.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163163.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163163.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163163.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7290]
>[163163.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7290] width 1600 pitch 6400 (/4 1600)
>[163166.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163166.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163167.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163167.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163167.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163167.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163167.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163167.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163167.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163167.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163167.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163167.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163167.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163167.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163168.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163168.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[163168.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[163168.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163168.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163168.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163168.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163168.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163169.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f59650]
>[163169.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f59650] width 1600 pitch 6400 (/4 1600)
>[163169.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbcf90]
>[163169.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbcf90] width 1600 pitch 6400 (/4 1600)
>[163203.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4d070]
>[163203.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4d070] width 1600 pitch 6400 (/4 1600)
>[163203.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49ef0]
>[163203.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49ef0] width 1600 pitch 6400 (/4 1600)
>[163203.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c2fce0]
>[163203.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c2fce0] width 1600 pitch 6400 (/4 1600)
>[163204.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cad9a0]
>[163204.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cad9a0] width 1600 pitch 6400 (/4 1600)
>[163204.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cad9a0]
>[163204.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cad9a0] width 1600 pitch 6400 (/4 1600)
>[163312.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163312.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163312.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[163312.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1600 pitch 6400 (/4 1600)
>[163312.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163312.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163312.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[163312.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[163314.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f990d0]
>[163314.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f990d0] width 1600 pitch 6400 (/4 1600)
>[163316.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[163316.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[163316.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[163316.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1600 pitch 6400 (/4 1600)
>[163316.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163316.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163316.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163316.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163316.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163316.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adf710]
>[163316.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adf710] width 1600 pitch 6400 (/4 1600)
>[163316.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163316.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163317.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[163317.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1600 pitch 6400 (/4 1600)
>[163317.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163317.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163317.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163318.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163318.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163318.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163318.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c41dd0]
>[163318.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c41dd0] width 1600 pitch 6400 (/4 1600)
>[163318.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163318.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163318.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163318.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163318.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163318.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163318.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163318.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163318.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163318.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163318.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163318.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163318.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163318.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163318.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[163318.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[163318.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163318.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163318.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca9a0]
>[163318.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca9a0] width 1600 pitch 6400 (/4 1600)
>[163318.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[163318.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[163318.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eca9a0]
>[163318.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eca9a0] width 1600 pitch 6400 (/4 1600)
>[163318.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[163318.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[163318.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[163318.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[163318.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[163318.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[163318.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[163318.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[163318.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4b990]
>[163318.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4b990] width 1600 pitch 6400 (/4 1600)
>[163318.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[163318.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[163318.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163318.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163318.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[163318.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[163319.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163319.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163319.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee9a0]
>[163319.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee9a0] width 1600 pitch 6400 (/4 1600)
>[163325.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[163325.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[163325.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[163325.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1600 pitch 6400 (/4 1600)
>[163325.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4036570]
>[163325.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4036570] width 1600 pitch 6400 (/4 1600)
>[163357.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd3a0]
>[163357.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd3a0] width 1600 pitch 6400 (/4 1600)
>[163357.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163357.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163357.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[163357.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[163357.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[163357.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1600 pitch 6400 (/4 1600)
>[163357.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9c3f0]
>[163357.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9c3f0] width 1600 pitch 6400 (/4 1600)
>[163357.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[163357.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[163357.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163358.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163358.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f904b0]
>[163358.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f904b0] width 1600 pitch 6400 (/4 1600)
>[163358.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c480]
>[163358.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c480] width 1600 pitch 6400 (/4 1600)
>[163358.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163358.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163358.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f901f0]
>[163358.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f901f0] width 1600 pitch 6400 (/4 1600)
>[163358.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163358.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163358.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163358.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163358.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163358.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163358.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[163358.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[163358.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ca0]
>[163358.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ca0] width 1600 pitch 6400 (/4 1600)
>[163358.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[163358.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1600 pitch 6400 (/4 1600)
>[163358.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[163358.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1600 pitch 6400 (/4 1600)
>[163358.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[163358.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[163358.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fe10]
>[163358.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fe10] width 1600 pitch 6400 (/4 1600)
>[163358.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[163358.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[163358.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163358.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c6530]
>[163358.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c6530] width 1600 pitch 6400 (/4 1600)
>[163358.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163358.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163359.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163359.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163362.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[163362.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[163362.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163362.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163391.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163391.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163391.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163391.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163391.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163395.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[163395.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[163395.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163395.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163405.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163405.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163405.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163405.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163406.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163406.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163406.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163406.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163406.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163406.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163406.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163406.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163406.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163406.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[163406.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[163406.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163406.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163406.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[163406.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[163406.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163406.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163406.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163406.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163406.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163406.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163406.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163406.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163406.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163407.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163407.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163407.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163407.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163408.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163408.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163408.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163408.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163408.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163408.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9c3f0]
>[163408.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9c3f0] width 1600 pitch 6400 (/4 1600)
>[163408.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163408.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163411.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4c20]
>[163411.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4c20] width 1600 pitch 6400 (/4 1600)
>[163411.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[163411.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[163415.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4c20]
>[163415.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4c20] width 1600 pitch 6400 (/4 1600)
>[163417.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[163417.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[163417.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163417.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163417.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[163417.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[163422.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[163422.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1600 pitch 6400 (/4 1600)
>[163422.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[163422.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[163422.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eed130]
>[163422.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eed130] width 1600 pitch 6400 (/4 1600)
>[163422.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163422.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163422.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[163422.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[163422.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163422.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163422.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[163422.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[163422.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f20]
>[163422.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f20] width 1600 pitch 6400 (/4 1600)
>[163422.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[163422.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[163422.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163422.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163422.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[163422.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[163422.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[163422.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[163422.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[163423.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[163423.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[163423.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[163423.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[163423.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[163423.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[163423.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[163424.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[163424.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[163426.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[163426.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[163427.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163427.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163427.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163427.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163427.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163427.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea1ac0]
>[163427.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea1ac0] width 1600 pitch 6400 (/4 1600)
>[163427.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[163427.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[163451.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df8370]
>[163452.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df8370] width 1600 pitch 6400 (/4 1600)
>[163452.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[163452.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[163452.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[163452.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[163453.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[163453.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1600 pitch 6400 (/4 1600)
>[163453.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3dc0]
>[163453.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3dc0] width 1600 pitch 6400 (/4 1600)
>[163455.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bce310]
>[163455.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bce310] width 1600 pitch 6400 (/4 1600)
>[163455.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[163455.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[163456.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163456.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163456.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1c480]
>[163456.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1c480] width 1600 pitch 6400 (/4 1600)
>[163456.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4036570]
>[163456.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4036570] width 1600 pitch 6400 (/4 1600)
>[163457.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[163457.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[163458.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[163458.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[163458.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0140]
>[163458.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0140] width 1600 pitch 6400 (/4 1600)
>[163459.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163459.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163459.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163459.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163459.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163459.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163460.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[163460.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1600 pitch 6400 (/4 1600)
>[163460.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[163460.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[163460.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2407340]
>[163460.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2407340] width 1600 pitch 6400 (/4 1600)
>[163461.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[163461.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1600 pitch 6400 (/4 1600)
>[163461.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163461.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163501.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e173c0]
>[163501.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e173c0] width 1600 pitch 6400 (/4 1600)
>[163502.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bd0]
>[163502.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bd0] width 1600 pitch 6400 (/4 1600)
>[163503.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c960]
>[163503.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c960] width 1600 pitch 6400 (/4 1600)
>[163503.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[163503.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1600 pitch 6400 (/4 1600)
>[163503.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0140]
>[163503.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0140] width 1600 pitch 6400 (/4 1600)
>[163503.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca15b0]
>[163503.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca15b0] width 1600 pitch 6400 (/4 1600)
>[163506.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043250]
>[163506.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043250] width 1600 pitch 6400 (/4 1600)
>[163506.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe590]
>[163506.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe590] width 1600 pitch 6400 (/4 1600)
>[163507.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823f30]
>[163507.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823f30] width 1600 pitch 6400 (/4 1600)
>[163516.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509c250]
>[163516.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509c250] width 1600 pitch 6400 (/4 1600)
>[163516.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c54730]
>[163516.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c54730] width 1600 pitch 6400 (/4 1600)
>[163516.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebc720]
>[163517.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebc720] width 1600 pitch 6400 (/4 1600)
>[163517.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc6090]
>[163517.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc6090] width 1600 pitch 6400 (/4 1600)
>[163517.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50102b0]
>[163517.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50102b0] width 1600 pitch 6400 (/4 1600)
>[163520.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270fd0]
>[163520.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270fd0] width 1600 pitch 6400 (/4 1600)
>[163524.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be3580]
>[163524.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be3580] width 1600 pitch 6400 (/4 1600)
>[163526.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29070]
>[163526.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29070] width 1600 pitch 6400 (/4 1600)
>[163529.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163529.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163529.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39424e0]
>[163529.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39424e0] width 1600 pitch 6400 (/4 1600)
>[163530.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163530.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163530.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163530.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163530.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39424e0]
>[163530.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39424e0] width 1600 pitch 6400 (/4 1600)
>[163530.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163530.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163530.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163530.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163530.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39424e0]
>[163530.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39424e0] width 1600 pitch 6400 (/4 1600)
>[163530.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163530.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163530.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163530.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163530.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163530.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163530.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39424e0]
>[163530.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39424e0] width 1600 pitch 6400 (/4 1600)
>[163530.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163530.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163530.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163530.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163530.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[163530.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[163530.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda9c0]
>[163530.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda9c0] width 1600 pitch 6400 (/4 1600)
>[163530.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c140]
>[163530.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c140] width 1600 pitch 6400 (/4 1600)
>[163530.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[163530.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[163530.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39424e0]
>[163530.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39424e0] width 1600 pitch 6400 (/4 1600)
>[163530.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3954900]
>[163530.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3954900] width 1600 pitch 6400 (/4 1600)
>[163531.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28e40]
>[163531.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28e40] width 1600 pitch 6400 (/4 1600)
>[163532.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[163532.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[163532.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[163532.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[163533.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5051660]
>[163533.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5051660] width 1600 pitch 6400 (/4 1600)
>[163533.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a7d0]
>[163533.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a7d0] width 1600 pitch 6400 (/4 1600)
>[163533.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a986e0]
>[163533.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a986e0] width 1600 pitch 6400 (/4 1600)
>[163533.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f901f0]
>[163533.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f901f0] width 1600 pitch 6400 (/4 1600)
>[163533.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2856960]
>[163533.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2856960] width 1600 pitch 6400 (/4 1600)
>[163533.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5b310]
>[163533.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5b310] width 1600 pitch 6400 (/4 1600)
>[163533.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163533.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163533.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163533.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163533.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163533.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163533.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163533.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163533.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163533.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163533.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163533.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163533.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163533.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[163533.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[163533.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859960]
>[163533.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859960] width 1600 pitch 6400 (/4 1600)
>[163542.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26050]
>[163542.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26050] width 1600 pitch 6400 (/4 1600)
>[163542.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4056dd0]
>[163542.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4056dd0] width 1600 pitch 6400 (/4 1600)
>[163543.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[163543.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[163647.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df3210]
>[163647.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df3210] width 1600 pitch 6400 (/4 1600)
>[163647.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[163647.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[163647.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bf00d0]
>[163647.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bf00d0] width 1600 pitch 6400 (/4 1600)
>[163648.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64740]
>[163648.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64740] width 1600 pitch 6400 (/4 1600)
>[163650.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea0140]
>[163650.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea0140] width 1600 pitch 6400 (/4 1600)
>[163650.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20a10]
>[163650.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20a10] width 1600 pitch 6400 (/4 1600)
>[163650.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14ec0]
>[163650.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14ec0] width 1600 pitch 6400 (/4 1600)
>[163651.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eef730]
>[163651.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eef730] width 1600 pitch 6400 (/4 1600)
>[163657.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f2f0]
>[163657.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f2f0] width 1600 pitch 6400 (/4 1600)
>[163657.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f2f0]
>[163657.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f2f0] width 1600 pitch 6400 (/4 1600)
>[163657.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f2f0]
>[163657.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f2f0] width 1600 pitch 6400 (/4 1600)
>[163680.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286a6b0]
>[163680.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286a6b0] width 1600 pitch 6400 (/4 1600)
>[163685.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40420e0]
>[163685.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40420e0] width 1600 pitch 6400 (/4 1600)
>[163723.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[163723.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[163724.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40420e0]
>[163725.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40420e0] width 1600 pitch 6400 (/4 1600)
>[163999.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2510cc0]
>[163999.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2510cc0] width 1600 pitch 6400 (/4 1600)
>[163999.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eecc70]
>[163999.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eecc70] width 1600 pitch 6400 (/4 1600)
>[163999.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df3210]
>[163999.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df3210] width 1600 pitch 6400 (/4 1600)
>[164000.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75580]
>[164000.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75580] width 1600 pitch 6400 (/4 1600)
>[164000.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75580]
>[164000.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75580] width 1600 pitch 6400 (/4 1600)
>[164003.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df3210]
>[164003.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df3210] width 1600 pitch 6400 (/4 1600)
>[164197.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[164197.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1600 pitch 6400 (/4 1600)
>[164197.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc60]
>[164197.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc60] width 1600 pitch 6400 (/4 1600)
>[164198.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30bf0]
>[164198.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30bf0] width 1600 pitch 6400 (/4 1600)
>[164198.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eeec70]
>[164198.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eeec70] width 1600 pitch 6400 (/4 1600)
>[164199.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebdfc0]
>[164199.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebdfc0] width 1600 pitch 6400 (/4 1600)
>[164384.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d730]
>[164384.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d730] width 1600 pitch 6400 (/4 1600)
>[164384.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3899c70]
>[164384.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3899c70] width 1600 pitch 6400 (/4 1600)
>[164385.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98410]
>[164385.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98410] width 1600 pitch 6400 (/4 1600)
>[164387.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f030]
>[164387.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f030] width 1600 pitch 6400 (/4 1600)
>[164387.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f9380]
>[164387.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f9380] width 1600 pitch 6400 (/4 1600)
>[164388.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1f030]
>[164388.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1f030] width 1600 pitch 6400 (/4 1600)
>[164394.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a11500]
>[164394.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a11500] width 1600 pitch 6400 (/4 1600)
>[164414.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[164414.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1600 pitch 6400 (/4 1600)
>[164415.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f96c0]
>[164415.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f96c0] width 1600 pitch 6400 (/4 1600)
>[164415.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264a980]
>[164415.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264a980] width 1600 pitch 6400 (/4 1600)
>[164415.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6e20]
>[164415.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6e20] width 1600 pitch 6400 (/4 1600)
>[164415.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9f610]
>[164415.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9f610] width 1600 pitch 6400 (/4 1600)
>[164415.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f96c0]
>[164415.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f96c0] width 1600 pitch 6400 (/4 1600)
>[164415.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264a980]
>[164415.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264a980] width 1600 pitch 6400 (/4 1600)
>[164415.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6e20]
>[164415.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6e20] width 1600 pitch 6400 (/4 1600)
>[164415.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9f610]
>[164415.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9f610] width 1600 pitch 6400 (/4 1600)
>[164415.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9f610]
>[164415.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9f610] width 1600 pitch 6400 (/4 1600)
>[164415.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084390]
>[164415.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084390] width 1600 pitch 6400 (/4 1600)
>[164415.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084390]
>[164415.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084390] width 1600 pitch 6400 (/4 1600)
>[164415.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14ec0]
>[164415.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14ec0] width 1600 pitch 6400 (/4 1600)
>[164415.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084390]
>[164415.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084390] width 1600 pitch 6400 (/4 1600)
>[164415.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14ec0]
>[164415.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14ec0] width 1600 pitch 6400 (/4 1600)
>[164415.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084390]
>[164415.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084390] width 1600 pitch 6400 (/4 1600)
>[164415.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f14ec0]
>[164415.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f14ec0] width 1600 pitch 6400 (/4 1600)
>[164416.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f66730]
>[164416.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f66730] width 1600 pitch 6400 (/4 1600)
>[164416.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[164416.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[164416.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[164416.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[164416.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0ec0]
>[164416.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0ec0] width 1600 pitch 6400 (/4 1600)
>[164416.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[164416.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[164416.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[164416.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[164416.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[164416.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1600 pitch 6400 (/4 1600)
>[164416.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[164416.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[164416.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[164416.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1600 pitch 6400 (/4 1600)
>[164416.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[164416.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[164416.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284b000]
>[164416.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284b000] width 1600 pitch 6400 (/4 1600)
>[164416.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0a690]
>[164416.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0a690] width 1600 pitch 6400 (/4 1600)
>[164417.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b400]
>[164417.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b400] width 1600 pitch 6400 (/4 1600)
>[164417.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53370]
>[164417.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53370] width 1600 pitch 6400 (/4 1600)
>[164417.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[164417.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[164417.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb17c0]
>[164417.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb17c0] width 1600 pitch 6400 (/4 1600)
>[164417.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b400]
>[164417.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b400] width 1600 pitch 6400 (/4 1600)
>[164417.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebfe50]
>[164417.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebfe50] width 1600 pitch 6400 (/4 1600)
>[164417.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084390]
>[164417.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084390] width 1600 pitch 6400 (/4 1600)
>[164417.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebfe50]
>[164417.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebfe50] width 1600 pitch 6400 (/4 1600)
>[164417.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[164417.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1600 pitch 6400 (/4 1600)
>[164417.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a6e20]
>[164417.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a6e20] width 1600 pitch 6400 (/4 1600)
>[164417.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[164417.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1600 pitch 6400 (/4 1600)
>[164417.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a800d0]
>[164417.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a800d0] width 1600 pitch 6400 (/4 1600)
>[164417.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270510]
>[164417.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270510] width 1600 pitch 6400 (/4 1600)
>[164417.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2cd0]
>[164417.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2cd0] width 1600 pitch 6400 (/4 1600)
>[164417.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebd10]
>[164417.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebd10] width 1600 pitch 6400 (/4 1600)
>[164417.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f100]
>[164417.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f100] width 1600 pitch 6400 (/4 1600)
>[164419.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7450]
>[164419.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7450] width 1600 pitch 6400 (/4 1600)
>[164421.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[164421.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[164421.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[164421.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[164421.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116940]
>[164421.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116940] width 1600 pitch 6400 (/4 1600)
>[164421.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ebd10]
>[164421.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ebd10] width 1600 pitch 6400 (/4 1600)
>[164421.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be46a0]
>[164421.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be46a0] width 1600 pitch 6400 (/4 1600)
>[164421.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f634b0]
>[164421.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f634b0] width 1600 pitch 6400 (/4 1600)
>[164421.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92bf0]
>[164421.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92bf0] width 1600 pitch 6400 (/4 1600)
>[164421.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[164421.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[164421.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bb000]
>[164421.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bb000] width 1600 pitch 6400 (/4 1600)
>[164421.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[164421.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[164421.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3c990]
>[164421.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3c990] width 1600 pitch 6400 (/4 1600)
>[164421.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506e750]
>[164421.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506e750] width 1600 pitch 6400 (/4 1600)
>[164421.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9c80]
>[164421.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9c80] width 1600 pitch 6400 (/4 1600)
>[164421.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506e750]
>[164421.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506e750] width 1600 pitch 6400 (/4 1600)
>[164421.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[164421.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[164421.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7660]
>[164421.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7660] width 1600 pitch 6400 (/4 1600)
>[164421.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb17c0]
>[164421.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb17c0] width 1600 pitch 6400 (/4 1600)
>[164421.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402f2f0]
>[164421.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402f2f0] width 1600 pitch 6400 (/4 1600)
>[164421.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[164421.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[164421.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e57ae0]
>[164421.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e57ae0] width 1600 pitch 6400 (/4 1600)
>[164421.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb2fb0]
>[164421.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb2fb0] width 1600 pitch 6400 (/4 1600)
>[164421.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef78a0]
>[164421.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef78a0] width 1600 pitch 6400 (/4 1600)
>[164422.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a7450]
>[164422.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a7450] width 1600 pitch 6400 (/4 1600)
>[164422.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c56330]
>[164422.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c56330] width 1600 pitch 6400 (/4 1600)
>[164422.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5370]
>[164422.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5370] width 1600 pitch 6400 (/4 1600)
>[164422.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeb1d0]
>[164422.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeb1d0] width 1600 pitch 6400 (/4 1600)
>[164422.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7bcc0]
>[164422.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7bcc0] width 1600 pitch 6400 (/4 1600)
>[164422.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efb260]
>[164422.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efb260] width 1600 pitch 6400 (/4 1600)
>[164422.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd840]
>[164422.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd840] width 1600 pitch 6400 (/4 1600)
>[164422.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[164422.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[164422.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[164422.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[164422.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f634b0]
>[164422.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f634b0] width 1600 pitch 6400 (/4 1600)
>[164422.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9490]
>[164422.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9490] width 1600 pitch 6400 (/4 1600)
>[164422.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[164422.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1600 pitch 6400 (/4 1600)
>[164422.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d150]
>[164422.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d150] width 1600 pitch 6400 (/4 1600)
>[164422.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[164422.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[164422.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c53370]
>[164422.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c53370] width 1600 pitch 6400 (/4 1600)
>[164422.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[164422.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[164422.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c71090]
>[164422.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c71090] width 1600 pitch 6400 (/4 1600)
>[164422.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b2880]
>[164422.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b2880] width 1600 pitch 6400 (/4 1600)
>[164422.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164422.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164422.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[164422.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[164422.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501d0f0]
>[164422.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501d0f0] width 1600 pitch 6400 (/4 1600)
>[164422.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ad50]
>[164422.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ad50] width 1600 pitch 6400 (/4 1600)
>[164422.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506e750]
>[164423.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506e750] width 1600 pitch 6400 (/4 1600)
>[164423.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb17c0]
>[164423.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb17c0] width 1600 pitch 6400 (/4 1600)
>[164423.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2b690]
>[164423.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2b690] width 1600 pitch 6400 (/4 1600)
>[164423.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164423.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164423.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[164423.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[164423.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164423.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164423.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164423.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164423.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164423.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164423.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164423.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164423.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164423.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[164423.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[164423.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164423.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[164423.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[164423.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164423.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed9e60]
>[164423.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed9e60] width 1600 pitch 6400 (/4 1600)
>[164423.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14300]
>[164423.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14300] width 1600 pitch 6400 (/4 1600)
>[164464.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057840]
>[164464.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057840] width 1600 pitch 6400 (/4 1600)
>[164464.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6b6a0]
>[164464.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6b6a0] width 1600 pitch 6400 (/4 1600)
>[164465.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4aff0]
>[164465.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4aff0] width 1600 pitch 6400 (/4 1600)
>[164481.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[164481.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[164481.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea1f0]
>[164481.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea1f0] width 1600 pitch 6400 (/4 1600)
>[164481.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[164481.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[164482.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[164482.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[164482.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebfe50]
>[164482.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebfe50] width 1600 pitch 6400 (/4 1600)
>[164482.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[164482.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[164483.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dff0d0]
>[164483.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dff0d0] width 1600 pitch 6400 (/4 1600)
>[164832.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[164832.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[164832.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdce80]
>[164832.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdce80] width 1600 pitch 6400 (/4 1600)
>[164833.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634840]
>[164833.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634840] width 1600 pitch 6400 (/4 1600)
>[165146.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4041890]
>[165146.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4041890] width 1600 pitch 6400 (/4 1600)
>[165146.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165146.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165146.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4fb20]
>[165146.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4fb20] width 1600 pitch 6400 (/4 1600)
>[165324.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[165324.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[165324.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[165324.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[165324.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[165324.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[165324.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[165324.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[165324.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165324.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165324.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165324.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165324.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165324.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165324.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165324.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165324.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165328.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165328.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165328.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165328.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165329.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165329.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165329.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165341.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165341.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165341.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165341.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165341.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165341.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165341.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165341.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165341.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165341.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165341.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165341.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165341.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165341.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165341.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[165341.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[165341.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bc00]
>[165341.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bc00] width 1600 pitch 6400 (/4 1600)
>[165341.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[165341.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[165341.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[165341.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[165341.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[165341.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[165341.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[165341.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[165345.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165345.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6030]
>[165345.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6030] width 1600 pitch 6400 (/4 1600)
>[165345.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[165345.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[165387.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165387.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165387.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165387.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165387.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165387.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165411.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165411.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165411.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165411.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165412.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[165412.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[165415.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[165415.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[165415.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165415.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165415.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165415.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165415.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165415.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165416.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165416.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165416.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165416.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165416.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165416.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165430.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b03d30]
>[165430.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b03d30] width 1600 pitch 6400 (/4 1600)
>[165446.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a040]
>[165446.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a040] width 1600 pitch 6400 (/4 1600)
>[165446.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42460]
>[165446.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42460] width 1600 pitch 6400 (/4 1600)
>[165447.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a040]
>[165447.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a040] width 1600 pitch 6400 (/4 1600)
>[165485.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e04fc0]
>[165485.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e04fc0] width 1600 pitch 6400 (/4 1600)
>[165485.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5980]
>[165485.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5980] width 1600 pitch 6400 (/4 1600)
>[165486.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01330]
>[165486.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01330] width 1600 pitch 6400 (/4 1600)
>[165512.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbbb80]
>[165512.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbbb80] width 1600 pitch 6400 (/4 1600)
>[165514.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5baf0]
>[165514.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5baf0] width 1600 pitch 6400 (/4 1600)
>[165518.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165518.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165518.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[165518.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[165518.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75870]
>[165518.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75870] width 1600 pitch 6400 (/4 1600)
>[165518.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165518.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165518.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165518.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165518.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca1a0]
>[165518.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca1a0] width 1600 pitch 6400 (/4 1600)
>[165518.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165518.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165518.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165518.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165518.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165518.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165518.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165518.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165518.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165518.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165518.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165518.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165518.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165518.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165524.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165524.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165524.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[165524.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[165525.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165525.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165525.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165525.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165525.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a0a0]
>[165525.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a0a0] width 1600 pitch 6400 (/4 1600)
>[165548.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165548.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165548.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97b60]
>[165548.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97b60] width 1600 pitch 6400 (/4 1600)
>[165548.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a0a0]
>[165548.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a0a0] width 1600 pitch 6400 (/4 1600)
>[165549.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8fa10]
>[165549.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8fa10] width 1600 pitch 6400 (/4 1600)
>[165563.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165563.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165563.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165563.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165564.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165564.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165564.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2e70]
>[165564.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2e70] width 1600 pitch 6400 (/4 1600)
>[165564.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165564.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165565.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bca1a0]
>[165565.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bca1a0] width 1600 pitch 6400 (/4 1600)
>[165565.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165565.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165565.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165565.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165566.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165566.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165566.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165566.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165566.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165566.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165567.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165567.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165567.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f2bd0]
>[165567.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f2bd0] width 1600 pitch 6400 (/4 1600)
>[165567.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165567.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165567.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165567.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165567.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165567.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165567.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165567.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165567.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165567.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165567.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165567.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165567.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165567.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165567.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165568.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165568.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165568.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165568.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165568.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165568.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165568.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165568.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165568.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165568.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165568.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165568.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165568.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165568.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea5c40]
>[165568.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea5c40] width 1600 pitch 6400 (/4 1600)
>[165568.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165568.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165568.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0c5c0]
>[165568.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0c5c0] width 1600 pitch 6400 (/4 1600)
>[165568.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165568.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165569.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165569.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165570.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[165570.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[165577.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a0a0]
>[165577.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a0a0] width 1600 pitch 6400 (/4 1600)
>[165577.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[165577.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[165578.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27730]
>[165578.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27730] width 1600 pitch 6400 (/4 1600)
>[165604.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a0a0]
>[165604.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a0a0] width 1600 pitch 6400 (/4 1600)
>[165604.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd660]
>[165604.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd660] width 1600 pitch 6400 (/4 1600)
>[165605.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699a0a0]
>[165605.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699a0a0] width 1600 pitch 6400 (/4 1600)
>[165608.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[165608.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[165608.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba9410]
>[165608.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba9410] width 1600 pitch 6400 (/4 1600)
>[165608.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a33da0]
>[165608.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a33da0] width 1600 pitch 6400 (/4 1600)
>[165609.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7d30]
>[165609.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7d30] width 1600 pitch 6400 (/4 1600)
>[165637.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2817ea0]
>[165637.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2817ea0] width 1600 pitch 6400 (/4 1600)
>[165637.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa16f0]
>[165637.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa16f0] width 1600 pitch 6400 (/4 1600)
>[165637.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a580]
>[165637.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a580] width 1600 pitch 6400 (/4 1600)
>[165638.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f231a0]
>[165638.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f231a0] width 1600 pitch 6400 (/4 1600)
>[165638.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50755b0]
>[165638.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50755b0] width 1600 pitch 6400 (/4 1600)
>[165638.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501d0c0]
>[165638.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501d0c0] width 1600 pitch 6400 (/4 1600)
>[165638.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[165638.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[165638.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d880]
>[165639.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d880] width 1600 pitch 6400 (/4 1600)
>[165639.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0b390]
>[165639.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0b390] width 1600 pitch 6400 (/4 1600)
>[165639.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c8e0]
>[165639.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c8e0] width 1600 pitch 6400 (/4 1600)
>[165912.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a84560]
>[165912.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a84560] width 1600 pitch 6400 (/4 1600)
>[165912.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb5650]
>[165912.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb5650] width 1600 pitch 6400 (/4 1600)
>[165913.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[165913.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[165913.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[165913.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[165925.604] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[165925.604] (II) RADEON(0): Printing DDC gathered Modelines:
>[165925.604] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[165925.604] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[166315.744] (II) RADEON(0): RADEONSaveScreen(2)
>[166315.744] (II) RADEON(0): RADEONSaveScreen(0)
>[166480.012] (II) RADEON(0): RADEONSaveScreen(1)
>[166484.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[166484.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[166490.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f100]
>[166490.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f100] width 1600 pitch 6400 (/4 1600)
>[166490.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eecc70]
>[166490.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eecc70] width 1600 pitch 6400 (/4 1600)
>[166491.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[166491.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[166501.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[166501.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[166501.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2817ea0]
>[166501.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2817ea0] width 1600 pitch 6400 (/4 1600)
>[166502.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b1d360]
>[166502.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b1d360] width 1600 pitch 6400 (/4 1600)
>[166502.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99370]
>[166502.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99370] width 1600 pitch 6400 (/4 1600)
>[166503.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace450]
>[166503.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace450] width 1600 pitch 6400 (/4 1600)
>[166503.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef0770]
>[166503.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef0770] width 1600 pitch 6400 (/4 1600)
>[166503.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[166503.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[166525.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00070]
>[166525.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00070] width 1600 pitch 6400 (/4 1600)
>[166678.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166678.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166678.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166678.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166678.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166682.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166682.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166682.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166683.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166683.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166683.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166683.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166683.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea290]
>[166683.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea290] width 1600 pitch 6400 (/4 1600)
>[166683.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d49f0]
>[166683.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d49f0] width 1600 pitch 6400 (/4 1600)
>[166691.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166691.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[166691.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[166691.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166691.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166692.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a84560]
>[166692.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a84560] width 1600 pitch 6400 (/4 1600)
>[166692.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[166692.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[166692.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b1f100]
>[166692.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b1f100] width 1600 pitch 6400 (/4 1600)
>[166694.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2817ea0]
>[166694.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2817ea0] width 1600 pitch 6400 (/4 1600)
>[166694.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[166694.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[166695.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[166695.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[166695.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e576d0]
>[166695.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e576d0] width 1600 pitch 6400 (/4 1600)
>[166695.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[166695.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[166695.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d96400]
>[166695.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d96400] width 1600 pitch 6400 (/4 1600)
>[166695.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eed130]
>[166695.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eed130] width 1600 pitch 6400 (/4 1600)
>[166696.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a84560]
>[166696.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a84560] width 1600 pitch 6400 (/4 1600)
>[166696.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eed130]
>[166696.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eed130] width 1600 pitch 6400 (/4 1600)
>[166696.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[166696.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[166696.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eed130]
>[166696.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eed130] width 1600 pitch 6400 (/4 1600)
>[166696.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[166696.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[166696.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f57510]
>[166696.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f57510] width 1600 pitch 6400 (/4 1600)
>[166696.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[166696.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1600 pitch 6400 (/4 1600)
>[166696.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eecc70]
>[166696.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eecc70] width 1600 pitch 6400 (/4 1600)
>[166697.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d06b0]
>[166697.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d06b0] width 1600 pitch 6400 (/4 1600)
>[166799.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2618e20]
>[166799.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2618e20] width 1600 pitch 6400 (/4 1600)
>[166799.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d99370]
>[166800.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d99370] width 1600 pitch 6400 (/4 1600)
>[166800.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2ce0]
>[166800.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2ce0] width 1600 pitch 6400 (/4 1600)
>[166800.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[166800.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[166800.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[166800.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[166801.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f23210]
>[166801.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f23210] width 1600 pitch 6400 (/4 1600)
>[166825.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb8e10]
>[166825.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb8e10] width 1600 pitch 6400 (/4 1600)
>[166825.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[166825.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[166826.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[166826.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[166877.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a40]
>[166877.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a40] width 1600 pitch 6400 (/4 1600)
>[166877.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2817ea0]
>[166877.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2817ea0] width 1600 pitch 6400 (/4 1600)
>[166878.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a90150]
>[166878.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a90150] width 1600 pitch 6400 (/4 1600)
>[166879.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[166879.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[166879.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[166879.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[166879.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f06ff0]
>[166879.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f06ff0] width 1600 pitch 6400 (/4 1600)
>[166880.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[166880.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[166975.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[166975.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[167095.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[167095.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[167095.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167095.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167096.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167096.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167096.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167096.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167096.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167097.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167097.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167097.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167097.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167098.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167098.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167098.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167098.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167099.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167099.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167099.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167099.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167100.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167100.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167100.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167100.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167101.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167101.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167101.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167101.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167102.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167102.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167102.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167102.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167102.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[167102.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[167102.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167102.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167102.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[167102.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[167103.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5580]
>[167103.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5580] width 1600 pitch 6400 (/4 1600)
>[167103.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504d1a0]
>[167103.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504d1a0] width 1600 pitch 6400 (/4 1600)
>[167103.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f006d0]
>[167103.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f006d0] width 1600 pitch 6400 (/4 1600)
>[167103.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6beb0]
>[167103.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6beb0] width 1600 pitch 6400 (/4 1600)
>[167103.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0acc0]
>[167103.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0acc0] width 1600 pitch 6400 (/4 1600)
>[167103.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdf8a0]
>[167103.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdf8a0] width 1600 pitch 6400 (/4 1600)
>[167103.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5076860]
>[167103.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5076860] width 1600 pitch 6400 (/4 1600)
>[167103.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0ad70]
>[167103.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0ad70] width 1600 pitch 6400 (/4 1600)
>[167103.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea8c60]
>[167103.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea8c60] width 1600 pitch 6400 (/4 1600)
>[167103.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b32740]
>[167103.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b32740] width 1600 pitch 6400 (/4 1600)
>[167103.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fc80]
>[167103.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fc80] width 1600 pitch 6400 (/4 1600)
>[167103.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a640]
>[167103.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a640] width 1600 pitch 6400 (/4 1600)
>[167103.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2160]
>[167103.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2160] width 1600 pitch 6400 (/4 1600)
>[167103.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24240]
>[167103.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24240] width 1600 pitch 6400 (/4 1600)
>[167103.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa4b20]
>[167103.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa4b20] width 1600 pitch 6400 (/4 1600)
>[167103.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb27c0]
>[167103.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb27c0] width 1600 pitch 6400 (/4 1600)
>[167103.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef87a0]
>[167103.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef87a0] width 1600 pitch 6400 (/4 1600)
>[167103.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12790]
>[167103.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12790] width 1600 pitch 6400 (/4 1600)
>[167103.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc3340]
>[167103.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc3340] width 1600 pitch 6400 (/4 1600)
>[167103.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17400]
>[167103.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17400] width 1600 pitch 6400 (/4 1600)
>[167103.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f24b60]
>[167103.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f24b60] width 1600 pitch 6400 (/4 1600)
>[167103.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f0960]
>[167103.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f0960] width 1600 pitch 6400 (/4 1600)
>[167103.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d3ed0]
>[167103.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d3ed0] width 1600 pitch 6400 (/4 1600)
>[167103.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f07cd0]
>[167103.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f07cd0] width 1600 pitch 6400 (/4 1600)
>[167103.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f152a0]
>[167103.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f152a0] width 1600 pitch 6400 (/4 1600)
>[167103.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[167103.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[167103.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167103.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167103.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167103.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167103.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167103.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167103.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[167103.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[167103.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167103.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167103.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6f30]
>[167103.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6f30] width 1600 pitch 6400 (/4 1600)
>[167103.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167103.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167103.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167103.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167103.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167103.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167103.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167103.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167103.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402eed0]
>[167103.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402eed0] width 1600 pitch 6400 (/4 1600)
>[167103.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[167104.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[167104.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167104.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167104.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[167104.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[167104.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167104.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167104.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[167104.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[167104.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167104.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167104.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167104.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167104.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167104.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167105.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f152a0]
>[167105.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f152a0] width 1600 pitch 6400 (/4 1600)
>[167116.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c050]
>[167116.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c050] width 1600 pitch 6400 (/4 1600)
>[167121.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167121.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167134.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9e60]
>[167134.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9e60] width 1600 pitch 6400 (/4 1600)
>[167142.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101e10]
>[167142.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101e10] width 1600 pitch 6400 (/4 1600)
>[167142.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167142.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167143.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[167143.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[167143.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[167143.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[167146.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[167147.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[167161.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167161.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6b390]
>[167161.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6b390] width 1600 pitch 6400 (/4 1600)
>[167161.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26f40]
>[167161.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26f40] width 1600 pitch 6400 (/4 1600)
>[167161.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ca90]
>[167161.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ca90] width 1600 pitch 6400 (/4 1600)
>[167161.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167161.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ca90]
>[167161.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ca90] width 1600 pitch 6400 (/4 1600)
>[167161.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167161.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ca90]
>[167161.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ca90] width 1600 pitch 6400 (/4 1600)
>[167161.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167161.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ca90]
>[167161.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ca90] width 1600 pitch 6400 (/4 1600)
>[167161.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167161.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9ca90]
>[167161.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9ca90] width 1600 pitch 6400 (/4 1600)
>[167161.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6d80]
>[167161.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6d80] width 1600 pitch 6400 (/4 1600)
>[167163.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcae40]
>[167163.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcae40] width 1600 pitch 6400 (/4 1600)
>[167163.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cf250]
>[167163.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cf250] width 1600 pitch 6400 (/4 1600)
>[167170.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcae40]
>[167170.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcae40] width 1600 pitch 6400 (/4 1600)
>[167176.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c41da0]
>[167176.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c41da0] width 1600 pitch 6400 (/4 1600)
>[167176.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f210]
>[167176.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f210] width 1600 pitch 6400 (/4 1600)
>[167176.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167176.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d902e0]
>[167176.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d902e0] width 1600 pitch 6400 (/4 1600)
>[167176.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167176.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d902e0]
>[167176.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d902e0] width 1600 pitch 6400 (/4 1600)
>[167176.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167176.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d902e0]
>[167176.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d902e0] width 1600 pitch 6400 (/4 1600)
>[167176.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167176.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d902e0]
>[167176.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d902e0] width 1600 pitch 6400 (/4 1600)
>[167176.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167176.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d902e0]
>[167176.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d902e0] width 1600 pitch 6400 (/4 1600)
>[167176.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b252c0]
>[167176.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b252c0] width 1600 pitch 6400 (/4 1600)
>[167182.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8bf0]
>[167182.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8bf0] width 1600 pitch 6400 (/4 1600)
>[167182.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef58b0]
>[167182.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef58b0] width 1600 pitch 6400 (/4 1600)
>[167182.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcae40]
>[167182.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcae40] width 1600 pitch 6400 (/4 1600)
>[167183.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ee0]
>[167183.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ee0] width 1600 pitch 6400 (/4 1600)
>[167184.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ee0]
>[167184.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ee0] width 1600 pitch 6400 (/4 1600)
>[167184.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ee0]
>[167184.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ee0] width 1600 pitch 6400 (/4 1600)
>[167184.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286b540]
>[167184.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286b540] width 1600 pitch 6400 (/4 1600)
>[167185.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35e90]
>[167185.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35e90] width 1600 pitch 6400 (/4 1600)
>[167192.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46d50]
>[167192.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46d50] width 1600 pitch 6400 (/4 1600)
>[167192.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46d50]
>[167192.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46d50] width 1600 pitch 6400 (/4 1600)
>[167193.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8b240]
>[167193.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8b240] width 1600 pitch 6400 (/4 1600)
>[167193.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167193.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167193.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e93d90]
>[167193.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e93d90] width 1600 pitch 6400 (/4 1600)
>[167194.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e93d90]
>[167194.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e93d90] width 1600 pitch 6400 (/4 1600)
>[167230.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167230.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167230.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8b240]
>[167230.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8b240] width 1600 pitch 6400 (/4 1600)
>[167231.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46d50]
>[167231.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46d50] width 1600 pitch 6400 (/4 1600)
>[167231.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46d50]
>[167231.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46d50] width 1600 pitch 6400 (/4 1600)
>[167234.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdfa90]
>[167234.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdfa90] width 1600 pitch 6400 (/4 1600)
>[167234.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167234.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835e00]
>[167234.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835e00] width 1600 pitch 6400 (/4 1600)
>[167234.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be2470]
>[167234.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be2470] width 1600 pitch 6400 (/4 1600)
>[167236.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff10]
>[167236.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff10] width 1600 pitch 6400 (/4 1600)
>[167236.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2861e20]
>[167236.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2861e20] width 1600 pitch 6400 (/4 1600)
>[167291.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4920]
>[167291.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4920] width 1600 pitch 6400 (/4 1600)
>[167291.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42460]
>[167291.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42460] width 1600 pitch 6400 (/4 1600)
>[167291.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a910]
>[167291.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a910] width 1600 pitch 6400 (/4 1600)
>[167291.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42460]
>[167291.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42460] width 1600 pitch 6400 (/4 1600)
>[167291.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[167291.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[167292.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[167292.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[167292.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[167292.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[167292.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[167292.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[167292.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[167292.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[167292.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a910]
>[167292.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a910] width 1600 pitch 6400 (/4 1600)
>[167292.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a910]
>[167292.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a910] width 1600 pitch 6400 (/4 1600)
>[167292.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167292.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a910]
>[167292.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a910] width 1600 pitch 6400 (/4 1600)
>[167292.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[167292.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[167403.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[167403.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1600 pitch 6400 (/4 1600)
>[167403.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[167403.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[167404.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[167404.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[167405.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed73d0]
>[167405.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed73d0] width 1600 pitch 6400 (/4 1600)
>[167456.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2bcb0]
>[167456.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2bcb0] width 1600 pitch 6400 (/4 1600)
>[167456.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[167456.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[167456.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e29f50]
>[167456.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e29f50] width 1600 pitch 6400 (/4 1600)
>[167457.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3939ba0]
>[167457.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3939ba0] width 1600 pitch 6400 (/4 1600)
>[167559.182] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[167559.182] (II) RADEON(0): Printing DDC gathered Modelines:
>[167559.182] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[167559.182] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[167949.742] (II) RADEON(0): RADEONSaveScreen(2)
>[167949.742] (II) RADEON(0): RADEONSaveScreen(0)
>[171698.757] (II) RADEON(0): RADEONSaveScreen(1)
>[171703.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171703.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171703.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171703.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171703.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171703.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171703.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171703.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171703.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171703.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171703.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171703.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171703.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171703.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171703.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171703.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171703.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171703.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171703.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171704.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171704.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171704.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171704.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171705.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171705.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171705.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171705.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171706.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171706.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171706.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171706.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171706.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171706.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171706.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171706.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171706.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171706.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171706.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171706.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171706.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171706.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171706.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171706.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171706.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171706.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171707.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171707.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171707.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171707.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171707.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171707.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171726.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171726.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171726.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171726.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171726.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171726.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171726.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171726.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171831.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac11f0]
>[171831.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac11f0] width 1600 pitch 6400 (/4 1600)
>[171831.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171831.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171831.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac11f0]
>[171831.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac11f0] width 1600 pitch 6400 (/4 1600)
>[171831.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171831.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171894.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171894.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171894.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171894.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171895.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171895.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171895.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171911.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171911.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171911.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171911.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171915.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171915.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171915.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171915.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171915.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171915.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171915.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171916.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171916.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171916.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171916.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171916.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171916.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171916.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171916.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171916.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171916.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171916.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171916.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171916.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171916.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171916.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171916.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[171920.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e90270]
>[171920.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e90270] width 1600 pitch 6400 (/4 1600)
>[171920.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4abe0]
>[171920.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4abe0] width 1600 pitch 6400 (/4 1600)
>[172102.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[172102.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[172102.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[172102.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[172103.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2bcb0]
>[172103.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2bcb0] width 1600 pitch 6400 (/4 1600)
>[172149.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4d4b0]
>[172149.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4d4b0] width 1600 pitch 6400 (/4 1600)
>[172151.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd5900]
>[172151.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd5900] width 1600 pitch 6400 (/4 1600)
>[172152.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b317f0]
>[172152.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b317f0] width 1600 pitch 6400 (/4 1600)
>[172152.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5136220]
>[172152.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5136220] width 1600 pitch 6400 (/4 1600)
>[172152.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e840]
>[172152.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e840] width 1600 pitch 6400 (/4 1600)
>[172152.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5136220]
>[172152.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5136220] width 1600 pitch 6400 (/4 1600)
>[172154.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2bcb0]
>[172154.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2bcb0] width 1600 pitch 6400 (/4 1600)
>[172154.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f82b0]
>[172154.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f82b0] width 1600 pitch 6400 (/4 1600)
>[172154.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[172154.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[172155.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172155.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172189.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3800]
>[172189.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3800] width 1600 pitch 6400 (/4 1600)
>[172189.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172189.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172189.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172189.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172191.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[172191.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[172200.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[172200.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[172200.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172200.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172200.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[172200.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[172201.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[172201.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1600 pitch 6400 (/4 1600)
>[172322.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5bc70]
>[172322.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5bc70] width 1600 pitch 6400 (/4 1600)
>[172322.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172322.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172323.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[172323.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[172324.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[172324.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[172324.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[172324.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[172324.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172324.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172329.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405b440]
>[172329.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405b440] width 1600 pitch 6400 (/4 1600)
>[172329.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[172329.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[172329.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172329.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172330.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172330.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172389.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023450]
>[172389.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023450] width 1600 pitch 6400 (/4 1600)
>[172389.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[172389.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1600 pitch 6400 (/4 1600)
>[172389.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172389.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172390.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172390.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172397.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172397.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172398.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4023450]
>[172398.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4023450] width 1600 pitch 6400 (/4 1600)
>[172398.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9c3f0]
>[172398.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9c3f0] width 1600 pitch 6400 (/4 1600)
>[172398.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c97e0]
>[172398.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c97e0] width 1600 pitch 6400 (/4 1600)
>[172398.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172398.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172398.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c97e0]
>[172398.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c97e0] width 1600 pitch 6400 (/4 1600)
>[172398.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[172398.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[172398.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[172398.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[172398.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[172398.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[172398.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc640]
>[172398.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc640] width 1600 pitch 6400 (/4 1600)
>[172398.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172398.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172398.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[172398.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1600 pitch 6400 (/4 1600)
>[172398.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172398.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172398.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172398.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172398.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172398.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172398.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172398.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172398.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172398.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172398.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172398.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172398.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172398.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172398.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172398.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172398.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172398.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172398.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172398.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172398.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172398.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172402.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd59f0]
>[172402.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd59f0] width 1600 pitch 6400 (/4 1600)
>[172402.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd59f0]
>[172402.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd59f0] width 1600 pitch 6400 (/4 1600)
>[172402.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172402.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172402.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172402.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172402.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172402.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172402.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172402.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172402.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172402.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172402.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[172403.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[172403.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506c520]
>[172403.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506c520] width 1600 pitch 6400 (/4 1600)
>[172404.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e42f0]
>[172404.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e42f0] width 1600 pitch 6400 (/4 1600)
>[172404.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397cbc0]
>[172404.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397cbc0] width 1600 pitch 6400 (/4 1600)
>[172404.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e42f0]
>[172404.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e42f0] width 1600 pitch 6400 (/4 1600)
>[172404.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397cbc0]
>[172404.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397cbc0] width 1600 pitch 6400 (/4 1600)
>[172404.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e42f0]
>[172404.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e42f0] width 1600 pitch 6400 (/4 1600)
>[172404.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397cbc0]
>[172404.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397cbc0] width 1600 pitch 6400 (/4 1600)
>[172404.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e42f0]
>[172404.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e42f0] width 1600 pitch 6400 (/4 1600)
>[172404.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397cbc0]
>[172404.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397cbc0] width 1600 pitch 6400 (/4 1600)
>[172404.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ad30]
>[172404.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ad30] width 1600 pitch 6400 (/4 1600)
>[172404.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x397cbc0]
>[172404.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x397cbc0] width 1600 pitch 6400 (/4 1600)
>[172404.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172404.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172404.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172404.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172404.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[172404.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[172404.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172404.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172404.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[172404.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[172404.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172404.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172404.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[172404.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[172404.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172404.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172404.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[172404.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[172404.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fbfcf0]
>[172404.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fbfcf0] width 1600 pitch 6400 (/4 1600)
>[172404.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3c340]
>[172404.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3c340] width 1600 pitch 6400 (/4 1600)
>[172404.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e42f0]
>[172404.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e42f0] width 1600 pitch 6400 (/4 1600)
>[172404.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172404.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172404.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172404.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172404.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172404.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172404.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172404.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172404.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172404.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172404.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172404.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172404.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172404.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172404.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172404.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172404.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172405.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172405.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172405.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172405.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172405.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172405.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172405.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1140]
>[172405.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1140] width 1600 pitch 6400 (/4 1600)
>[172405.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172405.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172405.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f12e00]
>[172405.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f12e00] width 1600 pitch 6400 (/4 1600)
>[172405.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172405.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172430.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172430.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172430.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172430.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172436.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172436.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172436.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172436.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172436.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172436.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172436.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172436.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172436.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a36670]
>[172436.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a36670] width 1600 pitch 6400 (/4 1600)
>[172436.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172436.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172436.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172436.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172436.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172436.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172436.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172436.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172436.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[172436.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[172436.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[172436.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[172436.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172436.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[172436.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[172436.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172436.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172468.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[172468.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[172468.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172468.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172469.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5131cd0]
>[172469.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5131cd0] width 1600 pitch 6400 (/4 1600)
>[172469.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068300]
>[172469.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068300] width 1600 pitch 6400 (/4 1600)
>[172470.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051eb0]
>[172470.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051eb0] width 1600 pitch 6400 (/4 1600)
>[172470.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172470.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172471.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[172471.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[172471.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ccf0]
>[172471.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ccf0] width 1600 pitch 6400 (/4 1600)
>[172473.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[172473.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[172473.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172473.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172473.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93480]
>[172473.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93480] width 1600 pitch 6400 (/4 1600)
>[172473.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[172473.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[172473.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172473.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172473.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add610]
>[172473.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add610] width 1600 pitch 6400 (/4 1600)
>[172473.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172473.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172473.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[172473.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[172473.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172473.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172473.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c97e0]
>[172473.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c97e0] width 1600 pitch 6400 (/4 1600)
>[172473.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172473.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172473.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6acc5a0]
>[172473.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6acc5a0] width 1600 pitch 6400 (/4 1600)
>[172473.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a8d0]
>[172473.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a8d0] width 1600 pitch 6400 (/4 1600)
>[172473.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5079290]
>[172473.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5079290] width 1600 pitch 6400 (/4 1600)
>[172473.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ad30]
>[172473.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ad30] width 1600 pitch 6400 (/4 1600)
>[172473.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5bc70]
>[172473.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5bc70] width 1600 pitch 6400 (/4 1600)
>[172473.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bb30]
>[172473.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bb30] width 1600 pitch 6400 (/4 1600)
>[172473.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172473.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172473.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[172473.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[172473.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172473.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172473.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172473.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172473.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172473.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172473.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172473.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172473.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172473.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172473.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172473.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172473.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172473.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172473.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172473.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172473.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172474.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172474.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172474.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172474.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[172474.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[172474.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[172474.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[172475.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172475.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172475.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[172475.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[172475.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172476.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172476.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172476.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172476.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172476.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172480.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[172480.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[172480.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d91c50]
>[172480.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d91c50] width 1600 pitch 6400 (/4 1600)
>[172480.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d91c50]
>[172480.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d91c50] width 1600 pitch 6400 (/4 1600)
>[172480.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[172480.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[172480.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[172480.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[172480.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172480.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172480.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[172480.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[172480.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172480.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172481.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[172481.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[172481.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172481.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172482.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[172482.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[172482.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[172482.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1600 pitch 6400 (/4 1600)
>[172482.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[172482.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[172482.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[172482.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[172482.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[172482.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[172482.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[172482.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[172482.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[172482.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[172482.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[172482.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[172524.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c70]
>[172524.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c70] width 1600 pitch 6400 (/4 1600)
>[172524.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[172524.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[172524.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[172524.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1600 pitch 6400 (/4 1600)
>[172525.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[172525.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1600 pitch 6400 (/4 1600)
>[172536.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172536.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172536.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[172536.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[172537.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5bc70]
>[172537.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5bc70] width 1600 pitch 6400 (/4 1600)
>[172537.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[172537.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[172537.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4147110]
>[172537.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4147110] width 1600 pitch 6400 (/4 1600)
>[172538.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[172538.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[172554.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40daae0]
>[172554.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40daae0] width 1600 pitch 6400 (/4 1600)
>[172554.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[172554.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[172554.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068300]
>[172554.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068300] width 1600 pitch 6400 (/4 1600)
>[172554.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f06ff0]
>[172554.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f06ff0] width 1600 pitch 6400 (/4 1600)
>[172555.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068300]
>[172555.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068300] width 1600 pitch 6400 (/4 1600)
>[172556.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe140]
>[172556.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe140] width 1600 pitch 6400 (/4 1600)
>[172560.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501bcc0]
>[172560.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501bcc0] width 1600 pitch 6400 (/4 1600)
>[172560.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c70]
>[172560.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c70] width 1600 pitch 6400 (/4 1600)
>[172560.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[172560.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[172561.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fbb0]
>[172561.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fbb0] width 1600 pitch 6400 (/4 1600)
>[172636.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee54a0]
>[172636.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee54a0] width 1600 pitch 6400 (/4 1600)
>[172636.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e87230]
>[172636.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e87230] width 1600 pitch 6400 (/4 1600)
>[172637.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c70]
>[172637.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c70] width 1600 pitch 6400 (/4 1600)
>[172937.001] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[172937.001] (II) RADEON(0): Printing DDC gathered Modelines:
>[172937.001] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[172937.001] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[173027.743] (II) RADEON(0): RADEONSaveScreen(2)
>[173027.743] (II) RADEON(0): RADEONSaveScreen(0)
>[181978.531] (II) RADEON(0): RADEONSaveScreen(1)
>[181986.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[181986.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[181986.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[181986.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[181987.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181987.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181992.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181992.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181992.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[181992.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[181997.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[181997.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[181997.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[181997.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[181997.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[182052.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2634570]
>[182052.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2634570] width 1600 pitch 6400 (/4 1600)
>[182058.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a810]
>[182058.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a810] width 1600 pitch 6400 (/4 1600)
>[182429.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7ee0]
>[182429.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7ee0] width 1600 pitch 6400 (/4 1600)
>[182431.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[182431.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[182431.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51052b0]
>[182431.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51052b0] width 1600 pitch 6400 (/4 1600)
>[182431.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51052b0]
>[182431.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51052b0] width 1600 pitch 6400 (/4 1600)
>[182431.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eec4d0]
>[182431.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eec4d0] width 1600 pitch 6400 (/4 1600)
>[182431.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1490]
>[182431.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1490] width 1600 pitch 6400 (/4 1600)
>[182431.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eec4d0]
>[182431.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eec4d0] width 1600 pitch 6400 (/4 1600)
>[182431.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[182431.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[182431.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eec4d0]
>[182431.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eec4d0] width 1600 pitch 6400 (/4 1600)
>[182431.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51052b0]
>[182431.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51052b0] width 1600 pitch 6400 (/4 1600)
>[182431.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7390]
>[182431.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7390] width 1600 pitch 6400 (/4 1600)
>[182431.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51052b0]
>[182431.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51052b0] width 1600 pitch 6400 (/4 1600)
>[182431.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a7390]
>[182431.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a7390] width 1600 pitch 6400 (/4 1600)
>[182431.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[182431.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[182431.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50477c0]
>[182431.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50477c0] width 1600 pitch 6400 (/4 1600)
>[182431.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[182431.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[182431.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50477c0]
>[182431.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50477c0] width 1600 pitch 6400 (/4 1600)
>[182431.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[182431.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[182431.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[182431.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[182431.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[182431.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[182431.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[182431.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[182431.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a59d70]
>[182431.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a59d70] width 1600 pitch 6400 (/4 1600)
>[182431.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[182431.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[182431.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182431.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182431.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edf790]
>[182431.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edf790] width 1600 pitch 6400 (/4 1600)
>[182431.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182431.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182431.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50477c0]
>[182431.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50477c0] width 1600 pitch 6400 (/4 1600)
>[182439.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dff30]
>[182439.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dff30] width 1600 pitch 6400 (/4 1600)
>[182439.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[182439.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[182439.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50767e0]
>[182439.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50767e0] width 1600 pitch 6400 (/4 1600)
>[182442.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c115e0]
>[182442.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c115e0] width 1600 pitch 6400 (/4 1600)
>[182475.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef94a0]
>[182476.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef94a0] width 1600 pitch 6400 (/4 1600)
>[182476.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182476.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182476.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef88c0]
>[182476.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef88c0] width 1600 pitch 6400 (/4 1600)
>[182480.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f47be0]
>[182480.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f47be0] width 1600 pitch 6400 (/4 1600)
>[182482.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3c670]
>[182482.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3c670] width 1600 pitch 6400 (/4 1600)
>[182618.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2360]
>[182618.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2360] width 1600 pitch 6400 (/4 1600)
>[182620.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a44ae0]
>[182620.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a44ae0] width 1600 pitch 6400 (/4 1600)
>[182620.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2a60]
>[182620.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2a60] width 1600 pitch 6400 (/4 1600)
>[182620.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de7660]
>[182620.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de7660] width 1600 pitch 6400 (/4 1600)
>[182620.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2a60]
>[182620.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2a60] width 1600 pitch 6400 (/4 1600)
>[182620.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e10520]
>[182620.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e10520] width 1600 pitch 6400 (/4 1600)
>[182620.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182620.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182620.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182620.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182620.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182620.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[182620.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[182620.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea4900]
>[182620.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea4900] width 1600 pitch 6400 (/4 1600)
>[182653.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6440]
>[182653.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6440] width 1600 pitch 6400 (/4 1600)
>[182655.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7a210]
>[182655.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7a210] width 1600 pitch 6400 (/4 1600)
>[182655.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de61a0]
>[182655.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de61a0] width 1600 pitch 6400 (/4 1600)
>[182675.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec23b0]
>[182675.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec23b0] width 1600 pitch 6400 (/4 1600)
>[182827.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182827.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182827.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182827.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182827.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182827.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182827.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182828.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd530]
>[182828.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd530] width 1600 pitch 6400 (/4 1600)
>[182828.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182828.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182832.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40512d0]
>[182832.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40512d0] width 1600 pitch 6400 (/4 1600)
>[182832.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11e30]
>[182832.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11e30] width 1600 pitch 6400 (/4 1600)
>[182973.459] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[182973.459] (II) RADEON(0): Printing DDC gathered Modelines:
>[182973.459] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[182973.460] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[183063.750] (II) RADEON(0): RADEONSaveScreen(2)
>[183063.750] (II) RADEON(0): RADEONSaveScreen(0)
>[183192.951] (II) RADEON(0): RADEONSaveScreen(1)
>[183200.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eecd20]
>[183200.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eecd20] width 1600 pitch 6400 (/4 1600)
>[183203.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1ff50]
>[183203.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1ff50] width 1600 pitch 6400 (/4 1600)
>[183342.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7540]
>[183343.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7540] width 1600 pitch 6400 (/4 1600)
>[183343.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd590]
>[183343.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd590] width 1600 pitch 6400 (/4 1600)
>[183343.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cadc80]
>[183343.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cadc80] width 1600 pitch 6400 (/4 1600)
>[183343.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[183343.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[183343.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cadc80]
>[183343.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cadc80] width 1600 pitch 6400 (/4 1600)
>[183343.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[183343.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[183343.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd590]
>[183343.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd590] width 1600 pitch 6400 (/4 1600)
>[183343.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb02f0]
>[183343.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb02f0] width 1600 pitch 6400 (/4 1600)
>[183343.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[183343.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[183343.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdd590]
>[183343.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdd590] width 1600 pitch 6400 (/4 1600)
>[183343.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee3d40]
>[183343.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee3d40] width 1600 pitch 6400 (/4 1600)
>[183343.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb02f0]
>[183343.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb02f0] width 1600 pitch 6400 (/4 1600)
>[183343.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee3d40]
>[183343.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee3d40] width 1600 pitch 6400 (/4 1600)
>[183343.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[183343.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[183343.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb0300]
>[183343.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb0300] width 1600 pitch 6400 (/4 1600)
>[183344.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cadc80]
>[183344.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cadc80] width 1600 pitch 6400 (/4 1600)
>[183344.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183344.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183344.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183344.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183344.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183344.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183344.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183344.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183344.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183344.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183344.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183344.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183345.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183345.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183345.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183345.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183346.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183346.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183346.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183346.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183346.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183346.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0420]
>[183346.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0420] width 1600 pitch 6400 (/4 1600)
>[183346.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183346.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183347.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183347.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183347.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183347.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183348.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba50b0]
>[183348.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba50b0] width 1600 pitch 6400 (/4 1600)
>[183348.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183348.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183349.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183349.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183349.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183349.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183357.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183357.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183357.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fafe80]
>[183357.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fafe80] width 1600 pitch 6400 (/4 1600)
>[183452.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183452.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183452.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183452.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183452.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183452.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183452.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183452.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183455.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183455.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183458.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183458.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183458.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183458.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183458.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183458.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183458.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183458.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183459.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183459.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183464.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183464.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183464.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183464.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183464.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183464.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183464.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183464.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183464.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183464.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183467.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183467.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183467.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860720]
>[183467.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860720] width 1600 pitch 6400 (/4 1600)
>[183467.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe9480]
>[183467.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe9480] width 1600 pitch 6400 (/4 1600)
>[183689.267] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[183689.268] (II) RADEON(0): Printing DDC gathered Modelines:
>[183689.268] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[183689.268] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[183690.893] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[183690.893] (II) RADEON(0): Printing DDC gathered Modelines:
>[183690.893] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[183690.893] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[183691.005] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[183691.005] (II) RADEON(0): Printing DDC gathered Modelines:
>[183691.005] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[183691.005] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[183739.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183739.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183739.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3a80]
>[183739.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3a80] width 1600 pitch 6400 (/4 1600)
>[183739.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3a80]
>[183739.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3a80] width 1600 pitch 6400 (/4 1600)
>[183739.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183739.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183739.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3a80]
>[183739.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3a80] width 1600 pitch 6400 (/4 1600)
>[183740.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82de0]
>[183740.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82de0] width 1600 pitch 6400 (/4 1600)
>[183740.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183740.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183741.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183741.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183741.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183741.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183742.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183742.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183742.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183742.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183742.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183742.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183742.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183742.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395aa30]
>[183742.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395aa30] width 1600 pitch 6400 (/4 1600)
>[183742.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183742.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183742.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f079f0]
>[183742.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f079f0] width 1600 pitch 6400 (/4 1600)
>[183742.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece9a0]
>[183742.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece9a0] width 1600 pitch 6400 (/4 1600)
>[183742.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa2890]
>[183742.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa2890] width 1600 pitch 6400 (/4 1600)
>[183742.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f079f0]
>[183742.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f079f0] width 1600 pitch 6400 (/4 1600)
>[183742.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f970]
>[183742.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f970] width 1600 pitch 6400 (/4 1600)
>[183742.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece9a0]
>[183742.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece9a0] width 1600 pitch 6400 (/4 1600)
>[183742.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f970]
>[183742.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f970] width 1600 pitch 6400 (/4 1600)
>[183742.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f970]
>[183742.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f970] width 1600 pitch 6400 (/4 1600)
>[183742.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[183742.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1600 pitch 6400 (/4 1600)
>[183742.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c17ef0]
>[183742.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c17ef0] width 1600 pitch 6400 (/4 1600)
>[183743.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2667260]
>[183743.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2667260] width 1600 pitch 6400 (/4 1600)
>[183743.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f970]
>[183743.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f970] width 1600 pitch 6400 (/4 1600)
>[183744.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b25490]
>[183744.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b25490] width 1600 pitch 6400 (/4 1600)
>[183744.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece9a0]
>[183744.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece9a0] width 1600 pitch 6400 (/4 1600)
>[183744.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183744.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183745.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f12b10]
>[183745.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f12b10] width 1600 pitch 6400 (/4 1600)
>[183746.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183746.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183746.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183746.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183747.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183747.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183747.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183747.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183747.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183747.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183747.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183747.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183747.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183747.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183747.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183747.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183747.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183747.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183747.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183747.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183747.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183747.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183747.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183747.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183747.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183747.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183748.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183748.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183749.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b08910]
>[183749.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b08910] width 1600 pitch 6400 (/4 1600)
>[183749.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183749.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183749.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183749.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183749.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183749.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183749.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183749.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183749.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[183749.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1600 pitch 6400 (/4 1600)
>[183749.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183749.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183749.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183749.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183749.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183749.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183749.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183749.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183749.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d082b0]
>[183749.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d082b0] width 1600 pitch 6400 (/4 1600)
>[183749.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca3b10]
>[183749.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca3b10] width 1600 pitch 6400 (/4 1600)
>[183750.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb100]
>[183750.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb100] width 1600 pitch 6400 (/4 1600)
>[183750.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da0300]
>[183750.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da0300] width 1600 pitch 6400 (/4 1600)
>[183750.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5a080]
>[183750.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5a080] width 1600 pitch 6400 (/4 1600)
>[183787.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3988a80]
>[183787.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3988a80] width 1600 pitch 6400 (/4 1600)
>[183787.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3846580]
>[183788.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3846580] width 1600 pitch 6400 (/4 1600)
>[183799.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbf1e0]
>[183799.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbf1e0] width 1600 pitch 6400 (/4 1600)
>[183799.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3848ad0]
>[183799.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3848ad0] width 1600 pitch 6400 (/4 1600)
>[183799.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183799.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183799.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3848ad0]
>[183799.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3848ad0] width 1600 pitch 6400 (/4 1600)
>[183799.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183799.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183799.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183800.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183800.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183800.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183800.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183800.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183800.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183800.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183800.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183800.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183800.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183800.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183800.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183800.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183800.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183800.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183800.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaedf0]
>[183800.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaedf0] width 1600 pitch 6400 (/4 1600)
>[183801.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509b100]
>[183801.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509b100] width 1600 pitch 6400 (/4 1600)
>[183801.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509b100]
>[183801.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509b100] width 1600 pitch 6400 (/4 1600)
>[183801.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3988b20]
>[183801.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3988b20] width 1600 pitch 6400 (/4 1600)
>[183801.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183801.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183801.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183801.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183801.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183801.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183801.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183801.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183801.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183802.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183802.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183802.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183802.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183802.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183802.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183802.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183802.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183802.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183802.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183802.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183802.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183802.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f129f0]
>[183802.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f129f0] width 1600 pitch 6400 (/4 1600)
>[183802.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[183802.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[183802.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183802.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183802.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d45b0]
>[183802.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d45b0] width 1600 pitch 6400 (/4 1600)
>[183802.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[183802.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[183802.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c940]
>[183802.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c940] width 1600 pitch 6400 (/4 1600)
>[183802.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d45b0]
>[183802.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d45b0] width 1600 pitch 6400 (/4 1600)
>[183802.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27560]
>[183802.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27560] width 1600 pitch 6400 (/4 1600)
>[183802.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d45b0]
>[183802.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d45b0] width 1600 pitch 6400 (/4 1600)
>[183826.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27980]
>[183827.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27980] width 1600 pitch 6400 (/4 1600)
>[183827.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a29ee0]
>[183827.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a29ee0] width 1600 pitch 6400 (/4 1600)
>[183827.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f273d0]
>[183827.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f273d0] width 1600 pitch 6400 (/4 1600)
>[183828.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfef50]
>[183828.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfef50] width 1600 pitch 6400 (/4 1600)
>[183828.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a308f0]
>[183828.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a308f0] width 1600 pitch 6400 (/4 1600)
>[183864.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8370]
>[183864.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8370] width 1600 pitch 6400 (/4 1600)
>[183864.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed6bc0]
>[183864.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed6bc0] width 1600 pitch 6400 (/4 1600)
>[183865.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[183865.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[183866.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab990]
>[183866.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab990] width 1600 pitch 6400 (/4 1600)
>[183866.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d7400]
>[183866.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d7400] width 1600 pitch 6400 (/4 1600)
>[183866.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c940]
>[183866.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c940] width 1600 pitch 6400 (/4 1600)
>[183867.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea8d0]
>[183867.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea8d0] width 1600 pitch 6400 (/4 1600)
>[183873.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bae410]
>[183873.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bae410] width 1600 pitch 6400 (/4 1600)
>[183873.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea8d0]
>[183873.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea8d0] width 1600 pitch 6400 (/4 1600)
>[183874.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0de0]
>[183874.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0de0] width 1600 pitch 6400 (/4 1600)
>[183971.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0de0]
>[183971.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0de0] width 1600 pitch 6400 (/4 1600)
>[184077.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b56eb0]
>[184077.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b56eb0] width 1600 pitch 6400 (/4 1600)
>[184077.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b56eb0]
>[184077.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b56eb0] width 1600 pitch 6400 (/4 1600)
>[184078.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2699540]
>[184078.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2699540] width 1600 pitch 6400 (/4 1600)
>[184319.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2e60]
>[184319.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2e60] width 1600 pitch 6400 (/4 1600)
>[184319.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184319.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184319.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc2e60]
>[184319.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc2e60] width 1600 pitch 6400 (/4 1600)
>[184539.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270270]
>[184539.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270270] width 1600 pitch 6400 (/4 1600)
>[184539.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4920]
>[184539.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4920] width 1600 pitch 6400 (/4 1600)
>[184540.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[184540.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[184540.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[184540.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[184540.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4facee0]
>[184540.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4facee0] width 1600 pitch 6400 (/4 1600)
>[184540.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef28a0]
>[184540.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef28a0] width 1600 pitch 6400 (/4 1600)
>[184541.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f8580]
>[184541.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f8580] width 1600 pitch 6400 (/4 1600)
>[184602.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184603.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184603.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184603.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184603.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184607.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184607.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184607.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184607.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184650.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184650.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184650.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184650.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184650.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184650.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184650.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184650.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184650.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184650.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184650.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184650.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184650.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a43620]
>[184650.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a43620] width 1600 pitch 6400 (/4 1600)
>[184651.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3f60]
>[184651.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3f60] width 1600 pitch 6400 (/4 1600)
>[184651.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d93a10]
>[184651.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d93a10] width 1600 pitch 6400 (/4 1600)
>[184651.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041c60]
>[184651.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041c60] width 1600 pitch 6400 (/4 1600)
>[184651.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0de0]
>[184651.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0de0] width 1600 pitch 6400 (/4 1600)
>[184651.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184652.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184652.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c877d0]
>[184652.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c877d0] width 1600 pitch 6400 (/4 1600)
>[184652.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4facee0]
>[184652.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4facee0] width 1600 pitch 6400 (/4 1600)
>[184654.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[184655.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e7de0]
>[184655.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e7de0] width 1600 pitch 6400 (/4 1600)
>[184655.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa44c0]
>[184655.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa44c0] width 1600 pitch 6400 (/4 1600)
>[185177.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a120e0]
>[185177.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a120e0] width 1600 pitch 6400 (/4 1600)
>[185496.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f781a0]
>[185496.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f781a0] width 1600 pitch 6400 (/4 1600)
>[185496.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106d40]
>[185496.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106d40] width 1600 pitch 6400 (/4 1600)
>[185496.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01420]
>[185496.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01420] width 1600 pitch 6400 (/4 1600)
>[185497.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106d40]
>[185497.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106d40] width 1600 pitch 6400 (/4 1600)
>[185505.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01420]
>[185506.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01420] width 1600 pitch 6400 (/4 1600)
>[185661.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df0670]
>[185661.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df0670] width 1600 pitch 6400 (/4 1600)
>[185661.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e820]
>[185661.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e820] width 1600 pitch 6400 (/4 1600)
>[185662.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185662.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185662.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1e820]
>[185662.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1e820] width 1600 pitch 6400 (/4 1600)
>[185662.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185662.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185663.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185663.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185663.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185663.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185664.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185664.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185664.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185664.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185664.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185664.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185664.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185664.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185664.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185664.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b390]
>[185664.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b390] width 1600 pitch 6400 (/4 1600)
>[185665.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5aa70]
>[185665.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5aa70] width 1600 pitch 6400 (/4 1600)
>[185665.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185665.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185665.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185665.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185667.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185667.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185667.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185667.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185667.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185667.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185667.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185667.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185667.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185667.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185667.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3857dd0]
>[185667.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3857dd0] width 1600 pitch 6400 (/4 1600)
>[185667.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185667.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185667.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185667.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185668.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185668.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185668.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185668.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185668.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185668.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185668.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad81d0]
>[185668.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad81d0] width 1600 pitch 6400 (/4 1600)
>[185668.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad81d0]
>[185668.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad81d0] width 1600 pitch 6400 (/4 1600)
>[185668.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad81d0]
>[185668.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad81d0] width 1600 pitch 6400 (/4 1600)
>[185668.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad81d0]
>[185668.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad81d0] width 1600 pitch 6400 (/4 1600)
>[185668.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad81d0]
>[185668.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad81d0] width 1600 pitch 6400 (/4 1600)
>[185668.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185668.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185668.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185668.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185669.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185669.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185669.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185669.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185670.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185670.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185672.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185672.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185672.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185672.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185673.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185673.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185674.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2dbc0]
>[185674.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2dbc0] width 1600 pitch 6400 (/4 1600)
>[185674.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185674.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185674.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185674.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185675.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185675.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185675.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185675.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185676.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185676.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185678.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185678.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185678.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185678.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185678.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185678.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185678.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185678.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185678.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185678.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185678.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185678.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185678.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185678.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185678.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185678.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185678.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185678.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185678.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185678.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185679.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185679.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185679.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185679.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185680.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185680.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185680.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185680.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185680.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185680.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185680.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185680.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185680.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185680.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185680.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185680.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185680.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185680.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185680.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185680.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185681.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185681.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185681.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185681.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185681.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185681.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185681.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185681.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185681.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185681.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185681.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185681.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185681.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185681.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185681.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185681.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185681.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185681.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185681.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185681.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185681.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185681.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185681.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185681.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185681.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185681.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185681.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185681.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185681.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185682.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185682.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185682.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185682.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185683.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185683.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185683.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185683.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185683.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185683.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2b450]
>[185683.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2b450] width 1600 pitch 6400 (/4 1600)
>[185683.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb9e60]
>[185683.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb9e60] width 1600 pitch 6400 (/4 1600)
>[185683.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185683.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185683.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185683.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185684.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185684.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185684.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185684.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185684.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185684.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185684.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185684.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185684.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185684.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185684.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185684.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185685.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185685.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185685.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185685.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185685.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185685.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185685.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185685.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185685.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185685.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185685.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185685.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185685.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185685.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185685.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185685.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185693.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185693.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185693.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185693.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185693.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185693.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185693.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185693.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185693.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185693.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185693.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185693.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185693.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185693.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185694.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185694.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185694.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185694.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185695.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185695.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185695.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185695.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185696.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185696.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185726.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185726.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185726.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185726.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185727.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185727.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185727.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185727.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185727.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185727.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185727.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185727.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185727.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185727.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185727.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185727.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185727.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185727.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185727.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185727.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185727.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185727.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185736.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185736.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185736.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185736.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185736.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df0670]
>[185736.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df0670] width 1600 pitch 6400 (/4 1600)
>[185736.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94ac0]
>[185736.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94ac0] width 1600 pitch 6400 (/4 1600)
>[185736.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185736.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac22a0]
>[185736.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac22a0] width 1600 pitch 6400 (/4 1600)
>[185736.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185736.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185737.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df0670]
>[185737.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df0670] width 1600 pitch 6400 (/4 1600)
>[185737.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185737.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185737.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185737.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185737.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185737.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185737.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185737.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185737.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f209b0]
>[185737.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f209b0] width 1600 pitch 6400 (/4 1600)
>[185737.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6d80]
>[185737.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6d80] width 1600 pitch 6400 (/4 1600)
>[185737.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b8240]
>[185737.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b8240] width 1600 pitch 6400 (/4 1600)
>[185737.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185737.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185737.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185737.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185737.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185737.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185737.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185737.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185737.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185737.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185737.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185737.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185737.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185737.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185737.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185737.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501efa0]
>[185738.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501efa0] width 1600 pitch 6400 (/4 1600)
>[185738.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f27f50]
>[185738.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f27f50] width 1600 pitch 6400 (/4 1600)
>[185738.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df0670]
>[185738.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df0670] width 1600 pitch 6400 (/4 1600)
>[185738.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185738.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185738.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185738.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185738.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185738.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185738.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185738.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185738.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185738.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[185738.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1600 pitch 6400 (/4 1600)
>[185738.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6d740]
>[185738.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6d740] width 1600 pitch 6400 (/4 1600)
>[185756.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa2910]
>[185756.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa2910] width 1600 pitch 6400 (/4 1600)
>[185756.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa2e40]
>[185756.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa2e40] width 1600 pitch 6400 (/4 1600)
>[185757.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185757.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509aec0]
>[185757.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509aec0] width 1600 pitch 6400 (/4 1600)
>[185757.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185757.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185762.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[185762.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[185762.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcbc0]
>[185762.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcbc0] width 1600 pitch 6400 (/4 1600)
>[185763.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da0270]
>[185763.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da0270] width 1600 pitch 6400 (/4 1600)
>[185764.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcc10]
>[185764.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcc10] width 1600 pitch 6400 (/4 1600)
>[185764.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeab30]
>[185764.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeab30] width 1600 pitch 6400 (/4 1600)
>[185764.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7020]
>[185764.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7020] width 1600 pitch 6400 (/4 1600)
>[185764.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7020]
>[185764.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7020] width 1600 pitch 6400 (/4 1600)
>[185764.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7020]
>[185764.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7020] width 1600 pitch 6400 (/4 1600)
>[185764.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7020]
>[185764.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7020] width 1600 pitch 6400 (/4 1600)
>[185764.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185764.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185764.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f7020]
>[185764.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f7020] width 1600 pitch 6400 (/4 1600)
>[185765.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185765.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185765.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185765.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185765.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185766.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185766.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5160]
>[185766.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5160] width 1600 pitch 6400 (/4 1600)
>[185766.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185766.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185766.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185766.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185766.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185767.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54010]
>[185767.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54010] width 1600 pitch 6400 (/4 1600)
>[185767.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185767.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185767.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185767.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185767.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185767.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185767.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185767.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185767.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185767.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185767.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185767.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185767.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185767.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185767.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185767.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185767.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2682fe0]
>[185767.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2682fe0] width 1600 pitch 6400 (/4 1600)
>[185767.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185767.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185768.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683270]
>[185768.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683270] width 1600 pitch 6400 (/4 1600)
>[185768.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185768.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185799.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2170]
>[185799.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2170] width 1600 pitch 6400 (/4 1600)
>[185799.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185799.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185803.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98960]
>[185803.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98960] width 1600 pitch 6400 (/4 1600)
>[185803.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2170]
>[185803.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2170] width 1600 pitch 6400 (/4 1600)
>[185803.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98960]
>[185803.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98960] width 1600 pitch 6400 (/4 1600)
>[185803.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2170]
>[185803.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2170] width 1600 pitch 6400 (/4 1600)
>[185803.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3a4a0]
>[185803.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3a4a0] width 1600 pitch 6400 (/4 1600)
>[185803.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185803.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185803.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26830b0]
>[185803.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26830b0] width 1600 pitch 6400 (/4 1600)
>[185803.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26830b0]
>[185803.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26830b0] width 1600 pitch 6400 (/4 1600)
>[185803.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26830b0]
>[185803.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26830b0] width 1600 pitch 6400 (/4 1600)
>[185803.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26830b0]
>[185803.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26830b0] width 1600 pitch 6400 (/4 1600)
>[185803.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26830b0]
>[185803.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26830b0] width 1600 pitch 6400 (/4 1600)
>[185803.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185803.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185803.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185803.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185803.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185803.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185803.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185803.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185803.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185803.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185803.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185804.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185804.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185804.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185804.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73b10]
>[185804.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73b10] width 1600 pitch 6400 (/4 1600)
>[185804.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388d3d0]
>[185804.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388d3d0] width 1600 pitch 6400 (/4 1600)
>[185804.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185804.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185804.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185804.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185804.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185805.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185805.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185805.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185805.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f41150]
>[185806.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f41150] width 1600 pitch 6400 (/4 1600)
>[185806.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992480]
>[185806.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992480] width 1600 pitch 6400 (/4 1600)
>[185806.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185806.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185806.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185806.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185806.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185807.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259c0]
>[185807.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259c0] width 1600 pitch 6400 (/4 1600)
>[185807.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185807.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185808.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72f10]
>[185808.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72f10] width 1600 pitch 6400 (/4 1600)
>[185808.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405b210]
>[185808.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405b210] width 1600 pitch 6400 (/4 1600)
>[185808.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae8b0]
>[185808.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae8b0] width 1600 pitch 6400 (/4 1600)
>[185808.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185808.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb8650]
>[185808.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb8650] width 1600 pitch 6400 (/4 1600)
>[185808.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7ea50]
>[185808.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7ea50] width 1600 pitch 6400 (/4 1600)
>[185809.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185809.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185809.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185809.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185809.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdcae0]
>[185809.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdcae0] width 1600 pitch 6400 (/4 1600)
>[185833.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185833.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185833.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185833.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185833.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185833.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185833.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185833.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185833.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185834.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185834.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185834.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40ec0]
>[185834.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40ec0] width 1600 pitch 6400 (/4 1600)
>[185855.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185855.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185855.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185855.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185855.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185855.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185855.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185855.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185861.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185861.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185861.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185861.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185861.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185861.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185861.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185862.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185862.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185862.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185862.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185862.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185862.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185862.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185862.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185862.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185862.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185862.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185862.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185862.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185862.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9380]
>[185862.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9380] width 1600 pitch 6400 (/4 1600)
>[185862.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e85ac0]
>[185862.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e85ac0] width 1600 pitch 6400 (/4 1600)
>[185863.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185863.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185863.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185863.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185871.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185871.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185871.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3930]
>[185871.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3930] width 1600 pitch 6400 (/4 1600)
>[185871.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386d4d0]
>[185871.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386d4d0] width 1600 pitch 6400 (/4 1600)
>[185871.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9d90]
>[185871.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9d90] width 1600 pitch 6400 (/4 1600)
>[185871.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9d90]
>[185871.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9d90] width 1600 pitch 6400 (/4 1600)
>[185871.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9d90]
>[185871.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9d90] width 1600 pitch 6400 (/4 1600)
>[185871.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9d90]
>[185871.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9d90] width 1600 pitch 6400 (/4 1600)
>[185871.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebc40]
>[185871.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebc40] width 1600 pitch 6400 (/4 1600)
>[185871.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebc40]
>[185871.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebc40] width 1600 pitch 6400 (/4 1600)
>[185871.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebc40]
>[185871.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebc40] width 1600 pitch 6400 (/4 1600)
>[185871.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994750]
>[185871.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994750] width 1600 pitch 6400 (/4 1600)
>[185871.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebc40]
>[185871.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebc40] width 1600 pitch 6400 (/4 1600)
>[185875.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185875.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185875.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185875.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185875.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185875.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185875.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185875.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185875.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185875.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185875.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185875.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185875.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185875.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185875.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185876.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185876.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185876.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185876.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185876.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185876.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185876.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185876.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185876.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185876.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa100]
>[185876.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa100] width 1600 pitch 6400 (/4 1600)
>[185876.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f30d0]
>[185876.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f30d0] width 1600 pitch 6400 (/4 1600)
>[185892.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eed0a0]
>[185892.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eed0a0] width 1600 pitch 6400 (/4 1600)
>[185892.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185892.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185892.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd630]
>[185892.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd630] width 1600 pitch 6400 (/4 1600)
>[185912.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185912.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185912.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185912.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185912.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8010]
>[185912.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8010] width 1600 pitch 6400 (/4 1600)
>[185912.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185912.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185912.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185912.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185912.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185912.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185912.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185912.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[185912.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[185912.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f189b0]
>[185912.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f189b0] width 1600 pitch 6400 (/4 1600)
>[185915.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185915.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185915.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185915.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185917.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185917.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185918.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185918.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185918.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df04c0]
>[185918.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df04c0] width 1600 pitch 6400 (/4 1600)
>[185918.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185918.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185918.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df04c0]
>[185918.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df04c0] width 1600 pitch 6400 (/4 1600)
>[185918.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185918.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942220]
>[185924.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942220] width 1600 pitch 6400 (/4 1600)
>[185924.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185924.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df04c0]
>[185924.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df04c0] width 1600 pitch 6400 (/4 1600)
>[185924.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3f00]
>[185924.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3f00] width 1600 pitch 6400 (/4 1600)
>[185924.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185924.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185924.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185924.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185924.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185924.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185924.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185924.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185924.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3790]
>[185924.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3790] width 1600 pitch 6400 (/4 1600)
>[185924.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185924.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185958.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185958.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185958.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[185958.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[185958.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[185958.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[185963.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[185963.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[185963.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[185963.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[185963.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e0a0]
>[185963.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e0a0] width 1600 pitch 6400 (/4 1600)
>[185963.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba4880]
>[185963.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba4880] width 1600 pitch 6400 (/4 1600)
>[185963.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c550b0]
>[185963.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c550b0] width 1600 pitch 6400 (/4 1600)
>[185963.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185963.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185963.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[185963.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[185963.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185963.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185963.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[185963.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[185963.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba4880]
>[185963.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba4880] width 1600 pitch 6400 (/4 1600)
>[185963.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185963.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185963.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[185963.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[185963.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba4880]
>[185963.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba4880] width 1600 pitch 6400 (/4 1600)
>[185963.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185963.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185963.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba4880]
>[185963.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba4880] width 1600 pitch 6400 (/4 1600)
>[185963.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[185963.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[185963.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185963.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185963.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[185963.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[185963.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185963.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185963.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[185964.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[185964.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185964.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a977b0]
>[185965.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a977b0] width 1600 pitch 6400 (/4 1600)
>[185965.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[185965.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[185965.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[185965.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[185965.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[185965.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[185965.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[185965.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e5620]
>[185965.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e5620] width 1600 pitch 6400 (/4 1600)
>[185965.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[185965.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[186026.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[186026.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[186026.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2852af0]
>[186026.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2852af0] width 1600 pitch 6400 (/4 1600)
>[186027.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd630]
>[186027.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd630] width 1600 pitch 6400 (/4 1600)
>[186027.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27220]
>[186027.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27220] width 1600 pitch 6400 (/4 1600)
>[186027.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e53f0]
>[186027.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e53f0] width 1600 pitch 6400 (/4 1600)
>[186028.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300b390]
>[186028.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300b390] width 1600 pitch 6400 (/4 1600)
>[186028.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[186028.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[186029.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2852af0]
>[186029.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2852af0] width 1600 pitch 6400 (/4 1600)
>[186029.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2852af0]
>[186029.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2852af0] width 1600 pitch 6400 (/4 1600)
>[186029.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2852af0]
>[186029.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2852af0] width 1600 pitch 6400 (/4 1600)
>[186030.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075050]
>[186030.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075050] width 1600 pitch 6400 (/4 1600)
>[186030.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13a60]
>[186030.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13a60] width 1600 pitch 6400 (/4 1600)
>[186030.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2852af0]
>[186030.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2852af0] width 1600 pitch 6400 (/4 1600)
>[186031.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd630]
>[186031.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd630] width 1600 pitch 6400 (/4 1600)
>[186043.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bd630]
>[186043.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bd630] width 1600 pitch 6400 (/4 1600)
>[186044.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[186044.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[186044.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9ee0]
>[186044.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9ee0] width 1600 pitch 6400 (/4 1600)
>[186044.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9f10]
>[186044.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9f10] width 1600 pitch 6400 (/4 1600)
>[186044.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecb8c0]
>[186044.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecb8c0] width 1600 pitch 6400 (/4 1600)
>[186045.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecb8c0]
>[186045.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecb8c0] width 1600 pitch 6400 (/4 1600)
>[186045.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efa370]
>[186045.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efa370] width 1600 pitch 6400 (/4 1600)
>[186045.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28200d0]
>[186045.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28200d0] width 1600 pitch 6400 (/4 1600)
>[186045.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa29e0]
>[186045.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa29e0] width 1600 pitch 6400 (/4 1600)
>[186046.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a90150]
>[186046.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a90150] width 1600 pitch 6400 (/4 1600)
>[186047.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b45b50]
>[186047.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b45b50] width 1600 pitch 6400 (/4 1600)
>[186047.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bf40]
>[186047.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bf40] width 1600 pitch 6400 (/4 1600)
>[186048.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[186048.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[186048.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9ee0]
>[186048.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9ee0] width 1600 pitch 6400 (/4 1600)
>[186071.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0ec0]
>[186071.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0ec0] width 1600 pitch 6400 (/4 1600)
>[186071.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e07410]
>[186071.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e07410] width 1600 pitch 6400 (/4 1600)
>[186071.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c370]
>[186072.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c370] width 1600 pitch 6400 (/4 1600)
>[186072.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f259a0]
>[186072.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f259a0] width 1600 pitch 6400 (/4 1600)
>[186073.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5063da0]
>[186073.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5063da0] width 1600 pitch 6400 (/4 1600)
>[186073.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f051f0]
>[186073.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f051f0] width 1600 pitch 6400 (/4 1600)
>[186074.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3bf40]
>[186074.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3bf40] width 1600 pitch 6400 (/4 1600)
>[186084.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0bda0]
>[186084.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0bda0] width 1600 pitch 6400 (/4 1600)
>[186097.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91df0]
>[186097.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91df0] width 1600 pitch 6400 (/4 1600)
>[186097.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3edd7c0]
>[186097.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3edd7c0] width 1600 pitch 6400 (/4 1600)
>[186097.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd19e0]
>[186097.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd19e0] width 1600 pitch 6400 (/4 1600)
>[186098.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f88fe0]
>[186098.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f88fe0] width 1600 pitch 6400 (/4 1600)
>[186171.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186171.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186171.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186171.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186172.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186172.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186172.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186172.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186174.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7f80]
>[186174.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7f80] width 1600 pitch 6400 (/4 1600)
>[186174.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186174.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186175.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186175.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186175.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec1140]
>[186175.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec1140] width 1600 pitch 6400 (/4 1600)
>[186176.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d61e70]
>[186176.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d61e70] width 1600 pitch 6400 (/4 1600)
>[186176.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23140]
>[186176.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23140] width 1600 pitch 6400 (/4 1600)
>[186176.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4630]
>[186176.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4630] width 1600 pitch 6400 (/4 1600)
>[186176.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4630]
>[186176.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4630] width 1600 pitch 6400 (/4 1600)
>[186176.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4630]
>[186176.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4630] width 1600 pitch 6400 (/4 1600)
>[186176.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186176.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186176.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186176.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186176.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186176.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186176.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186176.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186176.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186176.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186176.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e0f0]
>[186176.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e0f0] width 1600 pitch 6400 (/4 1600)
>[186176.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73e80]
>[186176.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73e80] width 1600 pitch 6400 (/4 1600)
>[186177.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186177.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186177.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc7f80]
>[186177.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc7f80] width 1600 pitch 6400 (/4 1600)
>[186178.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51062b0]
>[186178.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51062b0] width 1600 pitch 6400 (/4 1600)
>[186178.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5079130]
>[186178.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5079130] width 1600 pitch 6400 (/4 1600)
>[186179.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5019d60]
>[186179.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5019d60] width 1600 pitch 6400 (/4 1600)
>[186179.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2e810]
>[186179.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2e810] width 1600 pitch 6400 (/4 1600)
>[186179.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c73e80]
>[186179.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c73e80] width 1600 pitch 6400 (/4 1600)
>[186180.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc8460]
>[186180.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc8460] width 1600 pitch 6400 (/4 1600)
>[186180.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a31070]
>[186180.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a31070] width 1600 pitch 6400 (/4 1600)
>[186180.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebc70]
>[186180.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebc70] width 1600 pitch 6400 (/4 1600)
>[186181.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a85d0]
>[186181.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a85d0] width 1600 pitch 6400 (/4 1600)
>[186181.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186181.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186182.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9180]
>[186182.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9180] width 1600 pitch 6400 (/4 1600)
>[186182.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9180]
>[186182.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9180] width 1600 pitch 6400 (/4 1600)
>[186182.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186182.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186183.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186183.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186184.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9180]
>[186184.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9180] width 1600 pitch 6400 (/4 1600)
>[186185.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186185.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186186.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59860]
>[186186.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59860] width 1600 pitch 6400 (/4 1600)
>[186186.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186186.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186188.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5b0]
>[186188.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5b0] width 1600 pitch 6400 (/4 1600)
>[186188.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c27730]
>[186188.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c27730] width 1600 pitch 6400 (/4 1600)
>[186188.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9180]
>[186188.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9180] width 1600 pitch 6400 (/4 1600)
>[186211.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50afdb0]
>[186211.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50afdb0] width 1600 pitch 6400 (/4 1600)
>[186211.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada7e0]
>[186211.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada7e0] width 1600 pitch 6400 (/4 1600)
>[186212.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada7e0]
>[186212.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada7e0] width 1600 pitch 6400 (/4 1600)
>[186213.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa52e0]
>[186213.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa52e0] width 1600 pitch 6400 (/4 1600)
>[186213.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[186213.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[186213.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa52e0]
>[186213.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa52e0] width 1600 pitch 6400 (/4 1600)
>[186214.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[186214.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[186387.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada7e0]
>[186388.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada7e0] width 1600 pitch 6400 (/4 1600)
>[186388.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2bcb0]
>[186388.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2bcb0] width 1600 pitch 6400 (/4 1600)
>[186388.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[186388.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[186388.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[186388.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[186388.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[186388.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[186388.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186388.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[186388.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[186388.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186388.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[186388.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[186388.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186388.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[186388.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[186388.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186388.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[186388.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[186388.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186388.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[186388.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[186388.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186388.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186390.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa52e0]
>[186390.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa52e0] width 1600 pitch 6400 (/4 1600)
>[186390.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[186390.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[186391.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[186391.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[186391.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[186391.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[186391.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[186391.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[186391.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[186392.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[186392.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[186392.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[186392.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27efe40]
>[186392.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27efe40] width 1600 pitch 6400 (/4 1600)
>[186392.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50afdb0]
>[186392.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50afdb0] width 1600 pitch 6400 (/4 1600)
>[186392.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[186392.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1600 pitch 6400 (/4 1600)
>[186392.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[186392.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1600 pitch 6400 (/4 1600)
>[186392.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[186392.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[186392.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2bcb0]
>[186392.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2bcb0] width 1600 pitch 6400 (/4 1600)
>[186392.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f14010]
>[186392.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f14010] width 1600 pitch 6400 (/4 1600)
>[186392.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ada7e0]
>[186392.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ada7e0] width 1600 pitch 6400 (/4 1600)
>[186392.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5075050]
>[186392.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5075050] width 1600 pitch 6400 (/4 1600)
>[186392.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[186392.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1600 pitch 6400 (/4 1600)
>[186392.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[186392.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[186392.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[186392.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[186392.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[186392.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[186392.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522ed80]
>[186392.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522ed80] width 1600 pitch 6400 (/4 1600)
>[186392.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[186392.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[186392.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[186392.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[186392.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[186392.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[186392.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[186392.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[186392.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f14010]
>[186392.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f14010] width 1600 pitch 6400 (/4 1600)
>[186392.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[186392.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[186392.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[186392.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[186392.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f684e0]
>[186392.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f684e0] width 1600 pitch 6400 (/4 1600)
>[186392.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64510]
>[186392.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64510] width 1600 pitch 6400 (/4 1600)
>[186392.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64510]
>[186392.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64510] width 1600 pitch 6400 (/4 1600)
>[186392.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[186393.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[186393.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f684e0]
>[186393.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f684e0] width 1600 pitch 6400 (/4 1600)
>[186393.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb76f0]
>[186393.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb76f0] width 1600 pitch 6400 (/4 1600)
>[186393.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f303b0]
>[186393.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f303b0] width 1600 pitch 6400 (/4 1600)
>[186393.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f303b0]
>[186393.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f303b0] width 1600 pitch 6400 (/4 1600)
>[186393.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb76f0]
>[186393.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb76f0] width 1600 pitch 6400 (/4 1600)
>[186393.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[186393.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[186393.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9ee0]
>[186393.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9ee0] width 1600 pitch 6400 (/4 1600)
>[186393.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd460]
>[186393.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd460] width 1600 pitch 6400 (/4 1600)
>[186393.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9ee0]
>[186393.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9ee0] width 1600 pitch 6400 (/4 1600)
>[186393.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f1c40]
>[186393.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f1c40] width 1600 pitch 6400 (/4 1600)
>[186393.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3eb0]
>[186393.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3eb0] width 1600 pitch 6400 (/4 1600)
>[186393.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39720b0]
>[186393.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39720b0] width 1600 pitch 6400 (/4 1600)
>[186393.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39720b0]
>[186393.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39720b0] width 1600 pitch 6400 (/4 1600)
>[186407.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec87c0]
>[186407.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec87c0] width 1600 pitch 6400 (/4 1600)
>[186407.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[186407.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[186408.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[186408.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[186433.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08940]
>[186433.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08940] width 1600 pitch 6400 (/4 1600)
>[186435.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08940]
>[186435.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08940] width 1600 pitch 6400 (/4 1600)
>[186435.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82020]
>[186435.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82020] width 1600 pitch 6400 (/4 1600)
>[186435.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a5f0]
>[186435.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a5f0] width 1600 pitch 6400 (/4 1600)
>[186435.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[186435.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[186950.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efef60]
>[186950.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efef60] width 1600 pitch 6400 (/4 1600)
>[187031.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506b240]
>[187031.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506b240] width 1600 pitch 6400 (/4 1600)
>[187032.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc85a0]
>[187032.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc85a0] width 1600 pitch 6400 (/4 1600)
>[187032.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187032.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187032.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187032.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187032.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187032.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece600]
>[187033.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece600] width 1600 pitch 6400 (/4 1600)
>[187033.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5068b50]
>[187033.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5068b50] width 1600 pitch 6400 (/4 1600)
>[187033.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14cf0]
>[187033.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14cf0] width 1600 pitch 6400 (/4 1600)
>[187033.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3da07c0]
>[187033.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3da07c0] width 1600 pitch 6400 (/4 1600)
>[187033.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26181b0]
>[187033.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26181b0] width 1600 pitch 6400 (/4 1600)
>[187033.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08940]
>[187033.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08940] width 1600 pitch 6400 (/4 1600)
>[187033.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5fbb0]
>[187033.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5fbb0] width 1600 pitch 6400 (/4 1600)
>[187033.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbd30]
>[187033.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbd30] width 1600 pitch 6400 (/4 1600)
>[187033.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[187033.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[187033.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbd30]
>[187033.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbd30] width 1600 pitch 6400 (/4 1600)
>[187033.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[187033.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[187033.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbd30]
>[187033.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbd30] width 1600 pitch 6400 (/4 1600)
>[187033.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[187033.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[187033.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbd30]
>[187033.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbd30] width 1600 pitch 6400 (/4 1600)
>[187033.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[187033.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[187033.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbd30]
>[187033.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbd30] width 1600 pitch 6400 (/4 1600)
>[187033.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[187033.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[187034.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187034.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187034.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187034.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187034.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187035.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187035.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187035.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187035.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187036.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab16a0]
>[187036.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab16a0] width 1600 pitch 6400 (/4 1600)
>[187036.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f931e0]
>[187036.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f931e0] width 1600 pitch 6400 (/4 1600)
>[187036.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec5f30]
>[187036.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec5f30] width 1600 pitch 6400 (/4 1600)
>[187036.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc85a0]
>[187036.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc85a0] width 1600 pitch 6400 (/4 1600)
>[187037.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a500f0]
>[187037.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a500f0] width 1600 pitch 6400 (/4 1600)
>[187037.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ca30]
>[187037.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ca30] width 1600 pitch 6400 (/4 1600)
>[187037.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187037.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[187037.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[187037.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[187037.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[187038.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26181b0]
>[187039.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26181b0] width 1600 pitch 6400 (/4 1600)
>[187039.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26181b0]
>[187039.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26181b0] width 1600 pitch 6400 (/4 1600)
>[187039.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a500f0]
>[187039.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a500f0] width 1600 pitch 6400 (/4 1600)
>[187343.491] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[187343.491] (II) RADEON(0): Printing DDC gathered Modelines:
>[187343.491] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[187343.491] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[187345.252] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[187345.253] (II) RADEON(0): Printing DDC gathered Modelines:
>[187345.253] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[187345.253] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[187345.370] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[187345.370] (II) RADEON(0): Printing DDC gathered Modelines:
>[187345.370] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[187345.370] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[187433.742] (II) RADEON(0): RADEONSaveScreen(2)
>[187433.742] (II) RADEON(0): RADEONSaveScreen(0)
>[188232.084] (II) RADEON(0): RADEONSaveScreen(1)
>[188235.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188235.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188245.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab240]
>[188245.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab240] width 1600 pitch 6400 (/4 1600)
>[188245.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[188245.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[188246.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[188246.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[188246.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[188246.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[188247.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[188247.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[188247.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[188247.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[188247.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[188247.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[188248.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5bc70]
>[188248.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5bc70] width 1600 pitch 6400 (/4 1600)
>[188248.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb91d0]
>[188248.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb91d0] width 1600 pitch 6400 (/4 1600)
>[188249.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c100]
>[188249.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c100] width 1600 pitch 6400 (/4 1600)
>[188251.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f850]
>[188251.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f850] width 1600 pitch 6400 (/4 1600)
>[188254.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11870]
>[188254.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11870] width 1600 pitch 6400 (/4 1600)
>[188254.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[188254.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[188254.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[188254.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[188254.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188254.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188254.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[188254.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[188255.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188255.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188255.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[188255.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[188255.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188255.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188255.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[188255.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[188255.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188255.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188255.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044690]
>[188255.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044690] width 1600 pitch 6400 (/4 1600)
>[188283.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4780]
>[188283.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4780] width 1600 pitch 6400 (/4 1600)
>[188283.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2821b70]
>[188283.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2821b70] width 1600 pitch 6400 (/4 1600)
>[188284.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5bc70]
>[188284.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5bc70] width 1600 pitch 6400 (/4 1600)
>[188285.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188285.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188285.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ace6e0]
>[188285.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ace6e0] width 1600 pitch 6400 (/4 1600)
>[188286.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188286.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188297.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5072a00]
>[188297.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5072a00] width 1600 pitch 6400 (/4 1600)
>[188299.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49be0]
>[188299.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49be0] width 1600 pitch 6400 (/4 1600)
>[188299.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35d20]
>[188299.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35d20] width 1600 pitch 6400 (/4 1600)
>[188319.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea8e60]
>[188319.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea8e60] width 1600 pitch 6400 (/4 1600)
>[188319.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0a30]
>[188319.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0a30] width 1600 pitch 6400 (/4 1600)
>[188319.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbc7a0]
>[188319.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbc7a0] width 1600 pitch 6400 (/4 1600)
>[188339.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c32a90]
>[188339.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c32a90] width 1600 pitch 6400 (/4 1600)
>[188364.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb9c0]
>[188364.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb9c0] width 1600 pitch 6400 (/4 1600)
>[188366.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188366.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188366.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188366.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188366.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188366.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188366.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188366.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188367.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed1880]
>[188367.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed1880] width 1600 pitch 6400 (/4 1600)
>[188367.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188367.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188368.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188368.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188368.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188368.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188368.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188368.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188405.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14030]
>[188405.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14030] width 1600 pitch 6400 (/4 1600)
>[188408.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa1340]
>[188408.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa1340] width 1600 pitch 6400 (/4 1600)
>[188408.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6abd320]
>[188408.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6abd320] width 1600 pitch 6400 (/4 1600)
>[188421.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbc1b0]
>[188421.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbc1b0] width 1600 pitch 6400 (/4 1600)
>[188421.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce6d60]
>[188421.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce6d60] width 1600 pitch 6400 (/4 1600)
>[188428.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbc1b0]
>[188428.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbc1b0] width 1600 pitch 6400 (/4 1600)
>[188431.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c31d30]
>[188431.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c31d30] width 1600 pitch 6400 (/4 1600)
>[188557.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c346f0]
>[188557.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c346f0] width 1600 pitch 6400 (/4 1600)
>[188557.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a259e0]
>[188557.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a259e0] width 1600 pitch 6400 (/4 1600)
>[188558.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188558.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188558.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[188558.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[188559.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[188559.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[188560.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f1ef40]
>[188560.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f1ef40] width 1600 pitch 6400 (/4 1600)
>[188577.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[188577.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[188577.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2cf50]
>[188577.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2cf50] width 1600 pitch 6400 (/4 1600)
>[188578.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f16b70]
>[188578.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f16b70] width 1600 pitch 6400 (/4 1600)
>[188580.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82e00]
>[188580.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82e00] width 1600 pitch 6400 (/4 1600)
>[188581.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188581.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188581.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188581.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188581.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f74b20]
>[188581.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f74b20] width 1600 pitch 6400 (/4 1600)
>[188581.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9d40]
>[188581.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9d40] width 1600 pitch 6400 (/4 1600)
>[188581.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188581.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188581.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188581.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188581.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188581.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188581.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188581.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188581.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188581.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188581.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188581.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188581.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[188582.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[188582.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecc070]
>[188582.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecc070] width 1600 pitch 6400 (/4 1600)
>[188655.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed25c0]
>[188655.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed25c0] width 1600 pitch 6400 (/4 1600)
>[188655.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188655.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188656.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[188656.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[188673.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[188673.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[188673.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188673.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188673.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4053030]
>[188673.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4053030] width 1600 pitch 6400 (/4 1600)
>[188679.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[188679.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[188679.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188679.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188680.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188680.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188680.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f48cb0]
>[188680.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f48cb0] width 1600 pitch 6400 (/4 1600)
>[188680.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[188680.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[188681.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[188681.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1600 pitch 6400 (/4 1600)
>[188681.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f38fa0]
>[188681.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f38fa0] width 1600 pitch 6400 (/4 1600)
>[188682.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188682.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188682.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188682.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188684.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bd60]
>[188684.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bd60] width 1600 pitch 6400 (/4 1600)
>[188684.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188684.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188684.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec95a0]
>[188684.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec95a0] width 1600 pitch 6400 (/4 1600)
>[188685.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[188685.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[188685.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510f710]
>[188685.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510f710] width 1600 pitch 6400 (/4 1600)
>[188685.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7510]
>[188685.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7510] width 1600 pitch 6400 (/4 1600)
>[188729.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[188729.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[188729.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188729.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188729.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188729.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188730.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188730.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188730.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f356c0]
>[188730.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f356c0] width 1600 pitch 6400 (/4 1600)
>[188731.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188731.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188750.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188750.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188750.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce60]
>[188750.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce60] width 1600 pitch 6400 (/4 1600)
>[188750.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188750.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188763.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188763.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188763.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b220c0]
>[188763.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b220c0] width 1600 pitch 6400 (/4 1600)
>[188764.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[188764.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[188764.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188764.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f7310]
>[188765.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f7310] width 1600 pitch 6400 (/4 1600)
>[188765.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188765.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188765.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188765.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188765.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188766.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188766.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188766.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[188766.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[188766.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188766.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188766.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188766.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188766.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188766.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188766.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188766.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188766.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188766.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188766.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f76ae0]
>[188766.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f76ae0] width 1600 pitch 6400 (/4 1600)
>[188766.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188766.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188766.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38580e0]
>[188766.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38580e0] width 1600 pitch 6400 (/4 1600)
>[188767.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50123e0]
>[188767.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50123e0] width 1600 pitch 6400 (/4 1600)
>[188767.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a0390]
>[188767.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a0390] width 1600 pitch 6400 (/4 1600)
>[188770.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec95a0]
>[188770.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec95a0] width 1600 pitch 6400 (/4 1600)
>[188770.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188770.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188771.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188771.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188771.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188771.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188771.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188771.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188771.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188771.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188771.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188771.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188771.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188771.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188771.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188771.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188771.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188771.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188771.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188771.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188772.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188772.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188772.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188772.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188772.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188772.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188772.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188772.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188772.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188772.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188772.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188772.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188772.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188772.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188773.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188773.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fd30]
>[188773.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fd30] width 1600 pitch 6400 (/4 1600)
>[188773.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fd30]
>[188773.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fd30] width 1600 pitch 6400 (/4 1600)
>[188773.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fd30]
>[188773.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fd30] width 1600 pitch 6400 (/4 1600)
>[188773.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fd30]
>[188773.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fd30] width 1600 pitch 6400 (/4 1600)
>[188773.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188773.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fd30]
>[188773.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fd30] width 1600 pitch 6400 (/4 1600)
>[188773.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188773.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188774.711] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[188774.711] (II) RADEON(0): Printing DDC gathered Modelines:
>[188774.711] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[188774.711] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[188777.387] (II) AIGLX: Suspending AIGLX clients for VT switch
>[188777.387] (II) RADEON(0): RADEONLeaveVT_KMS
>[188777.387] (II) RADEON(0): Ok, leaving now...
>[188782.162] (II) AIGLX: Resuming AIGLX clients after VT switch
>[188782.162] (II) RADEON(0): RADEONEnterVT_KMS
>[188782.197] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[188782.197] (II) RADEON(0): Printing DDC gathered Modelines:
>[188782.198] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[188782.198] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[188782.287] (II) RADEON(0): RADEONSaveScreen(2)
>[188782.289] (**) Option "Device" "/dev/input/event5"
>[188782.289] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[188788.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188788.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188788.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188788.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188788.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188788.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188788.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[188788.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[188789.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19c30]
>[188789.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19c30] width 1600 pitch 6400 (/4 1600)
>[188789.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188789.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188789.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188789.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188789.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188789.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188789.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188789.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188789.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188789.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188789.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188789.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188789.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188789.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188789.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188789.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188789.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188789.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188789.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[188789.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[188789.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188789.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188789.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7260]
>[188789.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7260] width 1600 pitch 6400 (/4 1600)
>[188791.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188791.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188791.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188791.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188791.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188791.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188791.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188791.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188791.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7260]
>[188791.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7260] width 1600 pitch 6400 (/4 1600)
>[188791.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188791.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188791.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188791.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188791.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188791.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188791.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188791.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188791.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188791.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188791.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188791.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188791.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188791.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188791.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188791.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188791.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188791.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188791.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188791.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188791.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19c30]
>[188791.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19c30] width 1600 pitch 6400 (/4 1600)
>[188791.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[188791.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[188791.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188791.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188791.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188791.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188791.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188791.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188791.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7260]
>[188791.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7260] width 1600 pitch 6400 (/4 1600)
>[188791.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188791.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188791.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188791.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188791.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188791.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188791.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188791.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188791.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188791.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188791.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188791.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188791.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188791.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188791.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188792.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188792.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cfc0]
>[188792.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cfc0] width 1600 pitch 6400 (/4 1600)
>[188792.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188792.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188792.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188792.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188792.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188792.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188792.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19c30]
>[188792.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19c30] width 1600 pitch 6400 (/4 1600)
>[188792.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188792.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188792.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7260]
>[188792.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7260] width 1600 pitch 6400 (/4 1600)
>[188792.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188792.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188792.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7260]
>[188792.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7260] width 1600 pitch 6400 (/4 1600)
>[188792.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188792.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188792.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188792.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188792.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188792.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188792.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188792.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188792.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188792.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188792.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188792.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188792.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188792.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188792.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188792.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188792.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cfc0]
>[188792.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cfc0] width 1600 pitch 6400 (/4 1600)
>[188792.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188792.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188792.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188792.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188792.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188792.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188792.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188792.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188792.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188792.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188792.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188792.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188792.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188792.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188792.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cfc0]
>[188792.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cfc0] width 1600 pitch 6400 (/4 1600)
>[188792.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188792.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188792.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188792.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188792.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188792.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188792.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188792.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188792.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188792.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188793.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec95a0]
>[188793.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec95a0] width 1600 pitch 6400 (/4 1600)
>[188793.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188793.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188793.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188793.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188793.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbd2b0]
>[188793.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbd2b0] width 1600 pitch 6400 (/4 1600)
>[188793.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[188793.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[188793.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1cfc0]
>[188793.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1cfc0] width 1600 pitch 6400 (/4 1600)
>[188793.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188793.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188793.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188793.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188793.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188793.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188793.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188793.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188793.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[188793.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[188793.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188793.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188794.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188794.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188794.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188794.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188794.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188794.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188794.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188794.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188794.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188794.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188794.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188794.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188794.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188794.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188794.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188794.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188794.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[188794.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[188794.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188794.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188794.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188794.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188794.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[188794.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[188796.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188796.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188796.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188796.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188796.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188796.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188796.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188796.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188796.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188796.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188796.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188796.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188796.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188796.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188796.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188796.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188796.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188796.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188796.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188796.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188796.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188796.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188797.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188797.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188797.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188797.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188797.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188797.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188797.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188797.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188797.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188797.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188797.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188797.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188797.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188797.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188797.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188797.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188797.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188797.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188797.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188797.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188797.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188797.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188797.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188798.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0ea90]
>[188798.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0ea90] width 1600 pitch 6400 (/4 1600)
>[188798.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19c30]
>[188798.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19c30] width 1600 pitch 6400 (/4 1600)
>[188800.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188801.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188801.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188801.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188801.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188801.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188801.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188801.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188801.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[188801.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[188801.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188801.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188801.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188801.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188801.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188801.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188801.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188802.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188802.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188802.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188802.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188804.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[188804.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[188804.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188804.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188804.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188804.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188804.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188804.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188804.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188804.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188804.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188804.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188804.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188804.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188804.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188804.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188804.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[188804.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[188804.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[188804.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[188806.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa3610]
>[188806.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa3610] width 1600 pitch 6400 (/4 1600)
>[188806.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfdd40]
>[188806.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfdd40] width 1600 pitch 6400 (/4 1600)
>[188807.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfdd40]
>[188807.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfdd40] width 1600 pitch 6400 (/4 1600)
>[188807.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e17b90]
>[188807.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e17b90] width 1600 pitch 6400 (/4 1600)
>[188826.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efebc0]
>[188826.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efebc0] width 1600 pitch 6400 (/4 1600)
>[188870.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[188870.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[188870.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fe450]
>[188870.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fe450] width 1600 pitch 6400 (/4 1600)
>[188870.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188870.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188870.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188870.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188870.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188870.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188870.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188870.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188870.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188870.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188870.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188870.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188870.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188870.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188870.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188870.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[188870.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[188871.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[188871.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[188871.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[188871.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[188872.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6add1b0]
>[188872.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6add1b0] width 1600 pitch 6400 (/4 1600)
>[188873.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[188873.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[188873.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188873.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188873.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[188873.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[188874.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188874.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[188874.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[188874.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[188874.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300b4d0]
>[188874.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300b4d0] width 1600 pitch 6400 (/4 1600)
>[188888.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[188888.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[188888.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5f5d0]
>[188888.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5f5d0] width 1600 pitch 6400 (/4 1600)
>[188888.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c546d0]
>[188888.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c546d0] width 1600 pitch 6400 (/4 1600)
>[188889.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee52c0]
>[188889.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee52c0] width 1600 pitch 6400 (/4 1600)
>[189068.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[189068.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[189068.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405f200]
>[189068.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405f200] width 1600 pitch 6400 (/4 1600)
>[189068.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42880]
>[189068.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42880] width 1600 pitch 6400 (/4 1600)
>[189101.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[189101.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[189101.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[189101.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[189102.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e90]
>[189102.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e90] width 1600 pitch 6400 (/4 1600)
>[189102.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e22e90]
>[189102.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e22e90] width 1600 pitch 6400 (/4 1600)
>[189102.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[189102.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[189103.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[189103.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[189103.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[189103.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[189104.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f19f80]
>[189104.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f19f80] width 1600 pitch 6400 (/4 1600)
>[189104.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[189104.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[189105.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[189105.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[189105.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82e00]
>[189105.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82e00] width 1600 pitch 6400 (/4 1600)
>[189105.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcd0a0]
>[189105.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcd0a0] width 1600 pitch 6400 (/4 1600)
>[189106.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f44f50]
>[189106.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f44f50] width 1600 pitch 6400 (/4 1600)
>[189110.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82e00]
>[189110.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82e00] width 1600 pitch 6400 (/4 1600)
>[189110.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42880]
>[189110.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42880] width 1600 pitch 6400 (/4 1600)
>[189110.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509e950]
>[189110.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509e950] width 1600 pitch 6400 (/4 1600)
>[189111.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c440]
>[189111.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c440] width 1600 pitch 6400 (/4 1600)
>[189111.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282af50]
>[189111.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282af50] width 1600 pitch 6400 (/4 1600)
>[189111.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[189111.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[189111.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[189111.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[189112.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021150]
>[189112.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021150] width 1600 pitch 6400 (/4 1600)
>[189151.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[189151.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[189154.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38cb120]
>[189154.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38cb120] width 1600 pitch 6400 (/4 1600)
>[189189.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[189189.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[189189.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[189189.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[189189.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a790]
>[189189.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a790] width 1600 pitch 6400 (/4 1600)
>[189190.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bea0]
>[189190.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bea0] width 1600 pitch 6400 (/4 1600)
>[189190.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[189190.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[189190.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[189190.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[189193.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82e00]
>[189193.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82e00] width 1600 pitch 6400 (/4 1600)
>[189206.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189206.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189206.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189206.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189206.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189206.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189206.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189206.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189206.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189206.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189206.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189206.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189206.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189206.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189206.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189206.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189206.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189207.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189207.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189207.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189207.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189207.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189207.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189207.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189207.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13cf0]
>[189207.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13cf0] width 1600 pitch 6400 (/4 1600)
>[189207.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189207.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189208.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba5fc0]
>[189208.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba5fc0] width 1600 pitch 6400 (/4 1600)
>[189208.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189208.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189215.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189215.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189216.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189216.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189216.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189216.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189226.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189226.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189226.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189226.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189226.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189226.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189235.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f17670]
>[189235.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f17670] width 1600 pitch 6400 (/4 1600)
>[189235.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce7a50]
>[189235.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce7a50] width 1600 pitch 6400 (/4 1600)
>[189235.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db6aa0]
>[189235.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db6aa0] width 1600 pitch 6400 (/4 1600)
>[189238.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189238.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189238.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f178f0]
>[189238.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f178f0] width 1600 pitch 6400 (/4 1600)
>[189238.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189238.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189293.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce7a50]
>[189293.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce7a50] width 1600 pitch 6400 (/4 1600)
>[189293.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189293.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189293.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189293.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189293.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189293.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189294.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189294.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189294.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189294.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189294.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189294.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189294.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189294.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189294.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189294.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189294.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189294.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189294.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189294.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189294.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189294.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7ec80]
>[189294.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7ec80] width 1600 pitch 6400 (/4 1600)
>[189296.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189296.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189296.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189296.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189296.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189296.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189297.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189297.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189297.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189297.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189297.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189297.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189298.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189298.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189298.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189298.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189315.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189315.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189315.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189315.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189315.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5cb10]
>[189315.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5cb10] width 1600 pitch 6400 (/4 1600)
>[189315.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189315.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189315.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189315.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189315.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189315.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189315.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189316.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189316.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189316.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189316.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d878f0]
>[189316.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d878f0] width 1600 pitch 6400 (/4 1600)
>[189316.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189316.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189316.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189316.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189316.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189316.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189316.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189316.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189321.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189321.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189321.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189321.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189321.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189321.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189321.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189321.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189321.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7fa0]
>[189321.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7fa0] width 1600 pitch 6400 (/4 1600)
>[189321.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189321.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189321.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189321.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189321.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189321.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189322.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdac90]
>[189322.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdac90] width 1600 pitch 6400 (/4 1600)
>[189322.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00520]
>[189322.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00520] width 1600 pitch 6400 (/4 1600)
>[189328.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dadd40]
>[189328.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dadd40] width 1600 pitch 6400 (/4 1600)
>[189328.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2820ce0]
>[189328.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2820ce0] width 1600 pitch 6400 (/4 1600)
>[189328.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512d750]
>[189328.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512d750] width 1600 pitch 6400 (/4 1600)
>[189328.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5ee0]
>[189328.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5ee0] width 1600 pitch 6400 (/4 1600)
>[189328.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e80]
>[189328.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e80] width 1600 pitch 6400 (/4 1600)
>[189328.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce210]
>[189328.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce210] width 1600 pitch 6400 (/4 1600)
>[189328.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce1b0]
>[189328.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce1b0] width 1600 pitch 6400 (/4 1600)
>[189328.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e29120]
>[189328.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e29120] width 1600 pitch 6400 (/4 1600)
>[189328.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e290c0]
>[189328.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e290c0] width 1600 pitch 6400 (/4 1600)
>[189328.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873190]
>[189328.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873190] width 1600 pitch 6400 (/4 1600)
>[189328.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189328.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2873130]
>[189328.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2873130] width 1600 pitch 6400 (/4 1600)
>[189328.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5e00]
>[189328.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5e00] width 1600 pitch 6400 (/4 1600)
>[189332.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189332.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189332.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189332.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189332.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189332.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189332.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189332.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189332.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189332.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189332.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189332.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189332.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189332.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189332.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189332.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189332.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189332.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189333.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189333.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189333.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189333.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189333.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189333.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189333.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189333.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189333.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189333.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189337.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189337.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189337.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33000]
>[189337.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33000] width 1600 pitch 6400 (/4 1600)
>[189337.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189337.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189337.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33000]
>[189337.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33000] width 1600 pitch 6400 (/4 1600)
>[189337.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189337.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189337.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189337.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189337.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4adb0]
>[189337.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4adb0] width 1600 pitch 6400 (/4 1600)
>[189337.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189337.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189337.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189337.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189337.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189337.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189337.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ab4b0]
>[189337.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ab4b0] width 1600 pitch 6400 (/4 1600)
>[189337.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5bf0]
>[189337.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5bf0] width 1600 pitch 6400 (/4 1600)
>[189337.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b33000]
>[189337.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b33000] width 1600 pitch 6400 (/4 1600)
>[189407.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50a40]
>[189407.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50a40] width 1600 pitch 6400 (/4 1600)
>[189407.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbeba0]
>[189407.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbeba0] width 1600 pitch 6400 (/4 1600)
>[189407.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50be0]
>[189407.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50be0] width 1600 pitch 6400 (/4 1600)
>[189408.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4aaf0]
>[189408.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4aaf0] width 1600 pitch 6400 (/4 1600)
>[189441.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cb390]
>[189441.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cb390] width 1600 pitch 6400 (/4 1600)
>[189443.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0430]
>[189443.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0430] width 1600 pitch 6400 (/4 1600)
>[189447.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c1950]
>[189447.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c1950] width 1600 pitch 6400 (/4 1600)
>[189448.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3990]
>[189448.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3990] width 1600 pitch 6400 (/4 1600)
>[189506.578] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[189506.578] (II) RADEON(0): Printing DDC gathered Modelines:
>[189506.578] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[189506.578] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[189896.742] (II) RADEON(0): RADEONSaveScreen(2)
>[189896.742] (II) RADEON(0): RADEONSaveScreen(0)
>[193678.007] (II) RADEON(0): RADEONSaveScreen(1)
>[193681.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193681.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193683.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193683.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193683.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193683.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193688.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193688.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193689.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193689.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193693.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193693.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193693.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193693.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4aad0]
>[193702.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4aad0] width 1600 pitch 6400 (/4 1600)
>[193702.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dd40]
>[193702.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dd40] width 1600 pitch 6400 (/4 1600)
>[193702.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043d40]
>[193702.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043d40] width 1600 pitch 6400 (/4 1600)
>[193702.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193702.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193702.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043d40]
>[193702.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043d40] width 1600 pitch 6400 (/4 1600)
>[193702.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193702.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193702.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193702.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193702.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5132af0]
>[193702.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5132af0] width 1600 pitch 6400 (/4 1600)
>[193702.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ba9e10]
>[193702.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ba9e10] width 1600 pitch 6400 (/4 1600)
>[193702.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dd40]
>[193702.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dd40] width 1600 pitch 6400 (/4 1600)
>[193704.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[193704.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[193704.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[193704.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[193704.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193704.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193704.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[193704.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[193704.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193705.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[193705.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[193705.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193705.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[193705.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[193705.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaed10]
>[193705.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaed10] width 1600 pitch 6400 (/4 1600)
>[193705.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[193705.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[193705.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaed10]
>[193705.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaed10] width 1600 pitch 6400 (/4 1600)
>[193705.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193705.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaed10]
>[193705.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaed10] width 1600 pitch 6400 (/4 1600)
>[193705.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193705.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaed10]
>[193705.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaed10] width 1600 pitch 6400 (/4 1600)
>[193705.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[193705.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaed10]
>[193705.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaed10] width 1600 pitch 6400 (/4 1600)
>[193705.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f2d0]
>[193705.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f2d0] width 1600 pitch 6400 (/4 1600)
>[194013.834] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[194013.834] (II) RADEON(0): Printing DDC gathered Modelines:
>[194013.834] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[194013.834] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[194047.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[194047.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[194048.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2684160]
>[194048.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2684160] width 1600 pitch 6400 (/4 1600)
>[194048.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f7b0]
>[194048.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f7b0] width 1600 pitch 6400 (/4 1600)
>[194048.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c553d0]
>[194048.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c553d0] width 1600 pitch 6400 (/4 1600)
>[194049.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adac10]
>[194049.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adac10] width 1600 pitch 6400 (/4 1600)
>[194049.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405e310]
>[194049.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405e310] width 1600 pitch 6400 (/4 1600)
>[194080.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[194080.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[194080.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[194080.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[194080.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbb9c0]
>[194080.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbb9c0] width 1600 pitch 6400 (/4 1600)
>[194080.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6ce50]
>[194080.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6ce50] width 1600 pitch 6400 (/4 1600)
>[194080.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd68f0]
>[194080.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd68f0] width 1600 pitch 6400 (/4 1600)
>[194080.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[194080.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[194080.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd68f0]
>[194080.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd68f0] width 1600 pitch 6400 (/4 1600)
>[194080.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6be50]
>[194080.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6be50] width 1600 pitch 6400 (/4 1600)
>[194080.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6ce50]
>[194080.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6ce50] width 1600 pitch 6400 (/4 1600)
>[194080.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[194080.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[194080.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194080.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194080.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[194080.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[194080.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[194080.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[194080.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[194080.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[194080.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194080.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194080.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194080.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194080.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194080.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194080.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194080.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194081.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194081.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194081.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51319c0]
>[194081.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51319c0] width 1600 pitch 6400 (/4 1600)
>[194081.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecfd60]
>[194081.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecfd60] width 1600 pitch 6400 (/4 1600)
>[194081.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506cc10]
>[194081.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506cc10] width 1600 pitch 6400 (/4 1600)
>[194081.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194081.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194081.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194081.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194081.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194081.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ecddb0]
>[194081.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ecddb0] width 1600 pitch 6400 (/4 1600)
>[194082.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c291b0]
>[194082.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c291b0] width 1600 pitch 6400 (/4 1600)
>[194266.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[194266.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1600 pitch 6400 (/4 1600)
>[194266.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194266.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194266.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[194266.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[194266.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[194266.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1600 pitch 6400 (/4 1600)
>[194266.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[194267.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[194267.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[194267.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[194267.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194267.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194269.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194269.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194269.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194269.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194270.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194270.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194270.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[194270.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[194270.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[194270.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[194270.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194270.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194270.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194270.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194270.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194271.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a1b0]
>[194271.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a1b0] width 1600 pitch 6400 (/4 1600)
>[194271.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194271.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194271.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f360]
>[194271.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f360] width 1600 pitch 6400 (/4 1600)
>[194271.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194271.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194271.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f360]
>[194271.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f360] width 1600 pitch 6400 (/4 1600)
>[194271.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194271.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194271.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9e60]
>[194271.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9e60] width 1600 pitch 6400 (/4 1600)
>[194271.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[194271.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[194271.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194271.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194271.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecc6e0]
>[194271.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecc6e0] width 1600 pitch 6400 (/4 1600)
>[194271.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194271.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194271.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd2280]
>[194271.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd2280] width 1600 pitch 6400 (/4 1600)
>[194271.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194271.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194271.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194271.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194271.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194271.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194271.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[194271.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[194271.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194271.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194271.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[194271.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[194271.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[194271.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[194272.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98410]
>[194272.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98410] width 1600 pitch 6400 (/4 1600)
>[194272.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194272.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194272.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[194272.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[194273.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194273.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194273.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a1b0]
>[194273.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a1b0] width 1600 pitch 6400 (/4 1600)
>[194274.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4b20]
>[194274.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4b20] width 1600 pitch 6400 (/4 1600)
>[194274.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194274.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194275.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[194275.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1600 pitch 6400 (/4 1600)
>[194275.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194275.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194275.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194275.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24580]
>[194275.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24580] width 1600 pitch 6400 (/4 1600)
>[194277.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194277.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194277.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194277.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194278.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[194278.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[194278.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a1b0]
>[194278.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a1b0] width 1600 pitch 6400 (/4 1600)
>[194278.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[194278.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[194278.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a1b0]
>[194278.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a1b0] width 1600 pitch 6400 (/4 1600)
>[194339.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194339.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194339.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194339.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194339.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194339.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194339.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194339.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194339.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194339.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194339.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194339.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194339.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194339.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194339.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194339.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194339.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194339.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194339.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194339.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194339.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194339.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194339.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194340.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194340.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e9b0]
>[194340.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e9b0] width 1600 pitch 6400 (/4 1600)
>[194341.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194341.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194341.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[194341.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[194342.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81650]
>[194342.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81650] width 1600 pitch 6400 (/4 1600)
>[194343.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194343.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194343.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de7e0]
>[194343.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de7e0] width 1600 pitch 6400 (/4 1600)
>[194344.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194344.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194352.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194352.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194353.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[194353.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[194353.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194353.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194353.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[194353.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[194353.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194353.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194353.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[194353.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[194353.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194353.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194353.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194353.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194353.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194353.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194353.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[194353.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[194354.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194354.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194354.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[194354.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[194355.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194355.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194357.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d696a0]
>[194357.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d696a0] width 1600 pitch 6400 (/4 1600)
>[194357.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194357.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194357.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a87f0]
>[194357.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a87f0] width 1600 pitch 6400 (/4 1600)
>[194357.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[194358.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[194359.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[194359.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[194359.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194359.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194359.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f98410]
>[194359.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f98410] width 1600 pitch 6400 (/4 1600)
>[194359.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194359.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194359.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de7e0]
>[194359.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de7e0] width 1600 pitch 6400 (/4 1600)
>[194359.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194359.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194359.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc7810]
>[194359.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc7810] width 1600 pitch 6400 (/4 1600)
>[194359.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194359.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194359.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9e60]
>[194359.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9e60] width 1600 pitch 6400 (/4 1600)
>[194359.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194359.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194360.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194360.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[194360.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[194360.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194360.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194361.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f47790]
>[194361.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f47790] width 1600 pitch 6400 (/4 1600)
>[194361.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[194361.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[194370.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2a1b0]
>[194370.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2a1b0] width 1600 pitch 6400 (/4 1600)
>[194370.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08fa0]
>[194370.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08fa0] width 1600 pitch 6400 (/4 1600)
>[194370.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[194370.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[194370.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x508e1e0]
>[194370.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x508e1e0] width 1600 pitch 6400 (/4 1600)
>[194371.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194371.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194371.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09db0]
>[194371.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09db0] width 1600 pitch 6400 (/4 1600)
>[194371.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194371.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194371.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194371.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194371.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194371.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194371.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[194371.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[194371.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194371.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194371.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[194371.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[194372.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194372.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194380.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[194380.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[194381.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28284c0]
>[194381.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28284c0] width 1600 pitch 6400 (/4 1600)
>[194381.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[194381.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[194381.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194381.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194381.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194381.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194382.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194382.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194409.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194409.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194409.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194409.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194409.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194409.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194409.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194410.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194410.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194410.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a845c0]
>[194410.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a845c0] width 1600 pitch 6400 (/4 1600)
>[194410.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[194410.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[194410.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f10b30]
>[194410.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f10b30] width 1600 pitch 6400 (/4 1600)
>[194410.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[194410.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[194410.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[194410.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[194410.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f183b0]
>[194410.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f183b0] width 1600 pitch 6400 (/4 1600)
>[194410.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194410.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194410.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194410.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194410.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194410.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194410.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194410.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194410.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4b20]
>[194410.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4b20] width 1600 pitch 6400 (/4 1600)
>[194410.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194410.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194410.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194410.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194410.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194410.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194410.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194410.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194410.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194410.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194410.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40211a0]
>[194410.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40211a0] width 1600 pitch 6400 (/4 1600)
>[194410.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194410.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194410.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df37f0]
>[194410.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df37f0] width 1600 pitch 6400 (/4 1600)
>[194410.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194410.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194410.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbf110]
>[194410.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbf110] width 1600 pitch 6400 (/4 1600)
>[194411.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[194411.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[194412.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194412.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194412.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ad50]
>[194412.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ad50] width 1600 pitch 6400 (/4 1600)
>[194413.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b09e70]
>[194413.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b09e70] width 1600 pitch 6400 (/4 1600)
>[194413.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[194413.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[194413.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[194413.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[194414.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194414.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194414.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194414.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194414.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[194414.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[194414.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa6f70]
>[194414.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa6f70] width 1600 pitch 6400 (/4 1600)
>[194415.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811db0]
>[194415.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811db0] width 1600 pitch 6400 (/4 1600)
>[194415.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6b10]
>[194415.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6b10] width 1600 pitch 6400 (/4 1600)
>[194416.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1fb90]
>[194416.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1fb90] width 1600 pitch 6400 (/4 1600)
>[194416.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[194416.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[194420.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54010]
>[194420.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54010] width 1600 pitch 6400 (/4 1600)
>[194423.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[194423.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[194423.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b490]
>[194423.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b490] width 1600 pitch 6400 (/4 1600)
>[194423.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f14010]
>[194423.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f14010] width 1600 pitch 6400 (/4 1600)
>[194424.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[194424.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[194467.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[194467.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[194467.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[194467.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[194467.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[194467.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[194467.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[194467.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[194467.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[194467.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[194467.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[194467.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[194467.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b548c0]
>[194467.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b548c0] width 1600 pitch 6400 (/4 1600)
>[194467.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19ed0]
>[194467.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19ed0] width 1600 pitch 6400 (/4 1600)
>[194467.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b490]
>[194467.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b490] width 1600 pitch 6400 (/4 1600)
>[194472.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194472.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194472.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194472.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194472.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194472.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194472.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194472.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194472.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194472.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194472.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194472.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194472.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194472.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194472.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194473.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194473.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194473.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194473.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194473.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194473.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194473.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194473.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501c250]
>[194473.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501c250] width 1600 pitch 6400 (/4 1600)
>[194473.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[194473.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[194477.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19ed0]
>[194477.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19ed0] width 1600 pitch 6400 (/4 1600)
>[194477.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[194477.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[194477.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e19ed0]
>[194477.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e19ed0] width 1600 pitch 6400 (/4 1600)
>[194477.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[194477.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[194477.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ad50]
>[194477.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ad50] width 1600 pitch 6400 (/4 1600)
>[194477.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194477.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194477.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194477.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194477.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e090]
>[194477.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e090] width 1600 pitch 6400 (/4 1600)
>[194477.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194477.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194477.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194477.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194477.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194477.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194477.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194477.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194477.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[194477.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[194477.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194477.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194728.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[194728.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[194728.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194728.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194729.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[194729.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[194738.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194738.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194738.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[194738.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[194738.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[194738.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[194740.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[194740.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[194740.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[194740.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[194740.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[194740.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[194740.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[194740.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[194958.170] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[194958.170] (II) RADEON(0): Printing DDC gathered Modelines:
>[194958.170] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[194958.170] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[195348.749] (II) RADEON(0): RADEONSaveScreen(2)
>[195348.749] (II) RADEON(0): RADEONSaveScreen(0)
>[206615.765] (II) RADEON(0): RADEONSaveScreen(1)
>[206620.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[206620.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1600 pitch 6400 (/4 1600)
>[206621.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206621.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[206621.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[206621.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa87e0]
>[206621.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa87e0] width 1600 pitch 6400 (/4 1600)
>[206622.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206622.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206622.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206622.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206622.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206622.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206622.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206622.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206622.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206622.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206622.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206623.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206623.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206623.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206623.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[206623.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[206623.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[206623.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[206625.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[206625.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[206625.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[206625.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[206626.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206626.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206626.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[206626.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[206626.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[206626.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[206626.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[206626.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[206626.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206626.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206627.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[206627.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[206631.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206631.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206631.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[206631.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[206631.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206631.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206631.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[206631.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[206631.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[206631.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[206631.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[206631.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[206631.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[206631.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[206631.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[206631.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[206631.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[206631.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[206631.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0360]
>[206631.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0360] width 1600 pitch 6400 (/4 1600)
>[206631.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[206631.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[206699.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[206699.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[206699.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[206699.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[206700.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28184d0]
>[206700.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28184d0] width 1600 pitch 6400 (/4 1600)
>[206741.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63900]
>[206741.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63900] width 1600 pitch 6400 (/4 1600)
>[206741.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ad30]
>[206741.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ad30] width 1600 pitch 6400 (/4 1600)
>[206741.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206741.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206762.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206762.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206762.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eccc90]
>[206762.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eccc90] width 1600 pitch 6400 (/4 1600)
>[206762.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[206762.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[206767.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e98d90]
>[206767.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e98d90] width 1600 pitch 6400 (/4 1600)
>[206767.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f900]
>[206767.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f900] width 1600 pitch 6400 (/4 1600)
>[206768.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[206768.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[206768.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206768.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206769.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[206769.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[206769.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[206769.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[206774.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[206774.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[206774.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[206774.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[206775.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206775.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206776.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[206776.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[206776.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[206776.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[206776.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f406f0]
>[206776.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f406f0] width 1600 pitch 6400 (/4 1600)
>[206777.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63900]
>[206777.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63900] width 1600 pitch 6400 (/4 1600)
>[206782.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[206782.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[206782.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[206782.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[206782.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c55b10]
>[206783.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c55b10] width 1600 pitch 6400 (/4 1600)
>[206783.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[206783.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[206783.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206783.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206783.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[206783.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[206783.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206783.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206783.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[206783.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[206783.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206783.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206783.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[206783.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[206783.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[206783.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[206783.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206783.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206783.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[206783.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[206783.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[206783.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[206788.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[206788.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[206789.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206789.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206790.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f900]
>[206790.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f900] width 1600 pitch 6400 (/4 1600)
>[206815.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206815.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206826.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f900]
>[206826.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f900] width 1600 pitch 6400 (/4 1600)
>[206826.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206826.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206826.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f900]
>[206826.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f900] width 1600 pitch 6400 (/4 1600)
>[206850.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206850.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206850.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f900]
>[206850.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f900] width 1600 pitch 6400 (/4 1600)
>[206850.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206850.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206852.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[206852.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[206897.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[206897.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[206897.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2649e40]
>[206897.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2649e40] width 1600 pitch 6400 (/4 1600)
>[206897.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[206897.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[206897.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[206897.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[206897.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09db0]
>[206897.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09db0] width 1600 pitch 6400 (/4 1600)
>[206897.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[206897.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[206897.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09db0]
>[206897.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09db0] width 1600 pitch 6400 (/4 1600)
>[206897.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[206897.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[206897.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09db0]
>[206897.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09db0] width 1600 pitch 6400 (/4 1600)
>[206897.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[206897.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[206897.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09db0]
>[206897.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09db0] width 1600 pitch 6400 (/4 1600)
>[206897.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[206897.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[206898.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[206898.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[206898.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[206898.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[206898.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[206898.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[206898.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[206898.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[206898.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[206898.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[206898.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206898.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206898.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[206898.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[206898.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206898.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206898.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206898.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206898.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206898.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206898.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206898.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206898.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206899.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206899.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206899.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206899.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206899.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206899.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206899.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206899.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206899.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5320]
>[206899.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5320] width 1600 pitch 6400 (/4 1600)
>[206899.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206899.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206900.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[206900.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[206900.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206900.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206900.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[206900.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[206900.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206900.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206900.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[206900.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[206900.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206900.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206900.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[206900.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[206900.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206900.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206900.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[206900.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[206900.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206900.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206900.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206900.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206900.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[206900.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[206900.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[206900.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[206900.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f406f0]
>[206900.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f406f0] width 1600 pitch 6400 (/4 1600)
>[206900.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206900.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206900.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5b310]
>[206900.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5b310] width 1600 pitch 6400 (/4 1600)
>[206900.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eccc90]
>[206900.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eccc90] width 1600 pitch 6400 (/4 1600)
>[206900.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206900.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206900.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[206900.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[206900.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[206900.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[206900.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206900.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206900.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef97d0]
>[206900.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef97d0] width 1600 pitch 6400 (/4 1600)
>[206900.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[206900.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[206900.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef97d0]
>[206900.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef97d0] width 1600 pitch 6400 (/4 1600)
>[206900.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[206900.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[206901.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[206901.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[206901.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206901.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[206901.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[206901.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[206901.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[206902.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206902.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206902.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dade80]
>[206902.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dade80] width 1600 pitch 6400 (/4 1600)
>[206930.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de7e0]
>[206930.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de7e0] width 1600 pitch 6400 (/4 1600)
>[206930.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206930.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206930.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206930.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206931.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206931.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206931.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206931.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206931.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206931.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206931.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206931.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206931.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206931.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[206931.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[206931.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0c710]
>[206931.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0c710] width 1600 pitch 6400 (/4 1600)
>[206931.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[206931.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[206931.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[206932.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[206932.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[206932.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[206965.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e75230]
>[206965.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e75230] width 1600 pitch 6400 (/4 1600)
>[206971.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08810]
>[206971.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08810] width 1600 pitch 6400 (/4 1600)
>[206971.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3ded0]
>[206972.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3ded0] width 1600 pitch 6400 (/4 1600)
>[206972.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[206972.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[206972.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64200]
>[206972.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64200] width 1600 pitch 6400 (/4 1600)
>[206972.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206972.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206972.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f406f0]
>[206972.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f406f0] width 1600 pitch 6400 (/4 1600)
>[206972.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[206972.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[206972.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dade80]
>[206972.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dade80] width 1600 pitch 6400 (/4 1600)
>[206972.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[206972.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[206972.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206972.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206972.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[206972.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[206972.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206972.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206972.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[206972.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[206972.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206972.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206972.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[206972.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[206972.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[206972.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[206972.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[206972.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[206972.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9420]
>[206972.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9420] width 1600 pitch 6400 (/4 1600)
>[206978.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206978.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206978.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206978.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206979.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206979.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206983.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206983.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206983.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206983.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206984.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206984.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206984.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206984.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206985.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206985.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206985.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206985.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206986.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206986.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206986.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206986.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206987.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206987.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206987.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206987.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206991.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206991.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206991.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206991.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206991.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206991.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206991.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206991.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206991.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206991.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206991.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206991.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206991.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206991.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206991.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206991.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206992.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206992.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206992.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206992.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206993.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206993.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206993.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206993.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206993.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206993.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206993.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206993.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206993.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206993.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206993.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206993.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206998.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[206998.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[206998.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206998.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206998.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206998.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206998.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206998.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206998.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206998.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[206998.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[206998.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[206998.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[206998.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206998.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206998.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206998.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206998.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206998.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206998.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206998.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206998.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206998.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[206998.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[206999.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[206999.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[206999.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206999.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206999.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206999.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206999.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[206999.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[206999.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[206999.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[206999.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[207098.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[207098.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[207098.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[207098.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[207115.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f860]
>[207115.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f860] width 1600 pitch 6400 (/4 1600)
>[207116.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e98d90]
>[207116.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e98d90] width 1600 pitch 6400 (/4 1600)
>[207116.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[207116.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[207117.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[207117.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[207117.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207117.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207118.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207118.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207118.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[207118.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[207118.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[207118.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[207118.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207118.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207119.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[207119.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1600 pitch 6400 (/4 1600)
>[207119.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[207119.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[207120.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404bea0]
>[207120.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404bea0] width 1600 pitch 6400 (/4 1600)
>[207120.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[207120.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[207120.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b5990]
>[207120.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b5990] width 1600 pitch 6400 (/4 1600)
>[207121.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a7e890]
>[207121.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a7e890] width 1600 pitch 6400 (/4 1600)
>[207127.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[207127.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[207127.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[207127.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[207127.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef87a0]
>[207127.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef87a0] width 1600 pitch 6400 (/4 1600)
>[207128.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0da70]
>[207128.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0da70] width 1600 pitch 6400 (/4 1600)
>[207129.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404bea0]
>[207129.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404bea0] width 1600 pitch 6400 (/4 1600)
>[207129.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbe500]
>[207129.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbe500] width 1600 pitch 6400 (/4 1600)
>[207130.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300dc60]
>[207130.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300dc60] width 1600 pitch 6400 (/4 1600)
>[207134.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[207134.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[207134.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[207134.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[207134.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[207134.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[207141.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[207141.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[207141.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207141.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207142.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[207142.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1600 pitch 6400 (/4 1600)
>[207142.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207142.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207142.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[207142.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1600 pitch 6400 (/4 1600)
>[207142.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f406f0]
>[207142.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f406f0] width 1600 pitch 6400 (/4 1600)
>[207143.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[207143.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[207143.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[207143.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[207146.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5b350]
>[207146.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5b350] width 1600 pitch 6400 (/4 1600)
>[207146.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[207146.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[207146.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e08980]
>[207146.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e08980] width 1600 pitch 6400 (/4 1600)
>[207147.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40587c0]
>[207147.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40587c0] width 1600 pitch 6400 (/4 1600)
>[207178.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef87a0]
>[207178.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef87a0] width 1600 pitch 6400 (/4 1600)
>[207178.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e98d90]
>[207178.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e98d90] width 1600 pitch 6400 (/4 1600)
>[207178.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401f860]
>[207178.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401f860] width 1600 pitch 6400 (/4 1600)
>[207179.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207179.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207181.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[207181.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[207181.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207181.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207182.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a8f0]
>[207182.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a8f0] width 1600 pitch 6400 (/4 1600)
>[207188.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aba430]
>[207188.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aba430] width 1600 pitch 6400 (/4 1600)
>[207198.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aba430]
>[207198.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aba430] width 1600 pitch 6400 (/4 1600)
>[207244.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398d350]
>[207244.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398d350] width 1600 pitch 6400 (/4 1600)
>[207246.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f10630]
>[207246.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f10630] width 1600 pitch 6400 (/4 1600)
>[207247.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[207247.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1600 pitch 6400 (/4 1600)
>[207247.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a84f0]
>[207247.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a84f0] width 1600 pitch 6400 (/4 1600)
>[207247.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[207247.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1600 pitch 6400 (/4 1600)
>[207247.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a84f0]
>[207247.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a84f0] width 1600 pitch 6400 (/4 1600)
>[207247.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[207247.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1600 pitch 6400 (/4 1600)
>[207247.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6ee10]
>[207247.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6ee10] width 1600 pitch 6400 (/4 1600)
>[207247.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[207247.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[207247.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[207247.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[207247.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207247.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207247.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab49c0]
>[207247.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab49c0] width 1600 pitch 6400 (/4 1600)
>[207247.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207247.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207247.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207247.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207247.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207258.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9420]
>[207258.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9420] width 1600 pitch 6400 (/4 1600)
>[207258.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9420]
>[207258.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9420] width 1600 pitch 6400 (/4 1600)
>[207258.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9420]
>[207258.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9420] width 1600 pitch 6400 (/4 1600)
>[207259.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7ef0]
>[207259.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7ef0] width 1600 pitch 6400 (/4 1600)
>[207259.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93480]
>[207259.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93480] width 1600 pitch 6400 (/4 1600)
>[207260.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d696a0]
>[207260.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d696a0] width 1600 pitch 6400 (/4 1600)
>[207260.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207260.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207263.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[207263.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[207263.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9ad30]
>[207263.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9ad30] width 1600 pitch 6400 (/4 1600)
>[207264.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098480]
>[207264.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098480] width 1600 pitch 6400 (/4 1600)
>[207264.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098480]
>[207264.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098480] width 1600 pitch 6400 (/4 1600)
>[207269.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5098480]
>[207269.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5098480] width 1600 pitch 6400 (/4 1600)
>[207269.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860870]
>[207269.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860870] width 1600 pitch 6400 (/4 1600)
>[207270.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207270.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207333.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[207333.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[207333.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[207333.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[207333.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[207333.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[207333.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[207333.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[207333.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dade80]
>[207333.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dade80] width 1600 pitch 6400 (/4 1600)
>[207333.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[207333.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[207334.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dade80]
>[207334.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dade80] width 1600 pitch 6400 (/4 1600)
>[207337.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f93480]
>[207337.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f93480] width 1600 pitch 6400 (/4 1600)
>[207337.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[207337.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[207338.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[207338.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[207390.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207390.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207390.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207390.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207391.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207391.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207391.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207391.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207391.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207392.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207392.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207392.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207392.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207392.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207392.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207392.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207392.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207392.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207392.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[207392.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[207392.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[207392.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[207392.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[207392.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[207392.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[207392.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[207392.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7f70]
>[207392.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7f70] width 1600 pitch 6400 (/4 1600)
>[207392.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed7f70]
>[207392.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed7f70] width 1600 pitch 6400 (/4 1600)
>[207393.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef97d0]
>[207393.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef97d0] width 1600 pitch 6400 (/4 1600)
>[207393.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ebde90]
>[207393.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ebde90] width 1600 pitch 6400 (/4 1600)
>[207393.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef97d0]
>[207393.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef97d0] width 1600 pitch 6400 (/4 1600)
>[207394.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207394.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207405.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f34220]
>[207405.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f34220] width 1600 pitch 6400 (/4 1600)
>[207406.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec88b0]
>[207406.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec88b0] width 1600 pitch 6400 (/4 1600)
>[207406.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbd990]
>[207406.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbd990] width 1600 pitch 6400 (/4 1600)
>[207406.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[207406.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[207406.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4decd30]
>[207406.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4decd30] width 1600 pitch 6400 (/4 1600)
>[207406.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284f310]
>[207406.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284f310] width 1600 pitch 6400 (/4 1600)
>[207406.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401fc80]
>[207406.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401fc80] width 1600 pitch 6400 (/4 1600)
>[207406.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[207406.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[207406.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2afc0]
>[207406.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2afc0] width 1600 pitch 6400 (/4 1600)
>[207406.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecbc20]
>[207406.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecbc20] width 1600 pitch 6400 (/4 1600)
>[207406.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048f50]
>[207406.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048f50] width 1600 pitch 6400 (/4 1600)
>[207406.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f72830]
>[207406.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f72830] width 1600 pitch 6400 (/4 1600)
>[207406.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f12c80]
>[207406.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f12c80] width 1600 pitch 6400 (/4 1600)
>[207406.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb8f20]
>[207406.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb8f20] width 1600 pitch 6400 (/4 1600)
>[207406.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd9010]
>[207406.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd9010] width 1600 pitch 6400 (/4 1600)
>[207410.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23fe0]
>[207410.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23fe0] width 1600 pitch 6400 (/4 1600)
>[207411.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207411.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c127b0]
>[207422.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c127b0] width 1600 pitch 6400 (/4 1600)
>[207422.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207422.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207422.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207422.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207422.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207422.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207422.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207422.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207422.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207422.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207422.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207422.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207422.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207426.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207426.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207426.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207426.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207426.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207426.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207426.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207427.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207427.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207427.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207427.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207427.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207427.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207427.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207427.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207427.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207427.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207427.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207427.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207427.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207427.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207427.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207427.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207478.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[207478.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[207478.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207478.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207479.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df65e0]
>[207479.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df65e0] width 1600 pitch 6400 (/4 1600)
>[207479.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef3ca0]
>[207479.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef3ca0] width 1600 pitch 6400 (/4 1600)
>[207479.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d5a0]
>[207479.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d5a0] width 1600 pitch 6400 (/4 1600)
>[207480.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512c810]
>[207480.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512c810] width 1600 pitch 6400 (/4 1600)
>[207509.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f406f0]
>[207509.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f406f0] width 1600 pitch 6400 (/4 1600)
>[207509.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698e650]
>[207509.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698e650] width 1600 pitch 6400 (/4 1600)
>[207510.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[207510.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[207510.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[207510.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[207511.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[207511.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1600 pitch 6400 (/4 1600)
>[207551.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[207551.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[207551.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207551.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207551.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207551.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207551.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207551.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207551.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207553.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207553.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207553.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207553.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207553.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207553.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207554.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207554.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207554.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207554.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207554.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207554.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207554.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207554.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207554.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207554.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207554.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207554.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207554.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207554.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207554.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[207554.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[207554.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207554.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207554.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[207554.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[207554.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be8b90]
>[207554.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be8b90] width 1600 pitch 6400 (/4 1600)
>[207554.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[207554.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[207569.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[207569.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[207569.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[207569.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[207569.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb6ca0]
>[207569.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb6ca0] width 1600 pitch 6400 (/4 1600)
>[207571.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[207571.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[207571.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[207571.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[207571.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4460]
>[207571.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4460] width 1600 pitch 6400 (/4 1600)
>[207599.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[207599.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[207599.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[207599.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[207599.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2ec80]
>[207599.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2ec80] width 1600 pitch 6400 (/4 1600)
>[207600.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[207600.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[207605.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[207605.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[207605.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71bb0]
>[207605.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71bb0] width 1600 pitch 6400 (/4 1600)
>[207605.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63900]
>[207605.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63900] width 1600 pitch 6400 (/4 1600)
>[207606.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207606.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207606.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[207606.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[207615.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207615.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207615.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[207615.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[207615.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2833050]
>[207615.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2833050] width 1600 pitch 6400 (/4 1600)
>[207615.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[207615.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[207615.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207615.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207615.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207615.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207615.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[207615.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[207615.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[207615.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[207615.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207615.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207615.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[207615.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[207615.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207615.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207616.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6ce50]
>[207616.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6ce50] width 1600 pitch 6400 (/4 1600)
>[207616.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207616.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207616.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207616.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207616.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207616.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207616.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207616.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207616.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207616.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207616.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207616.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207616.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207616.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207616.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207616.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207616.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[207616.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[207616.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207616.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207616.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[207616.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[207616.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc1760]
>[207616.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc1760] width 1600 pitch 6400 (/4 1600)
>[207616.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207616.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207617.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207617.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207618.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27db450]
>[207618.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27db450] width 1600 pitch 6400 (/4 1600)
>[207618.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207618.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207619.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207619.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207619.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94ba0]
>[207619.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94ba0] width 1600 pitch 6400 (/4 1600)
>[207680.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207680.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207680.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207680.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207680.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207681.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207681.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207681.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207681.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207682.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207682.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207682.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207682.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207683.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207683.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207683.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207683.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207684.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207684.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207684.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207684.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207685.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207685.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207685.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207685.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207685.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207685.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207685.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207685.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207685.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207686.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[207686.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[207686.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[207686.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1600 pitch 6400 (/4 1600)
>[207695.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f640]
>[207695.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f640] width 1600 pitch 6400 (/4 1600)
>[207695.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207695.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207695.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40502f0]
>[207695.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40502f0] width 1600 pitch 6400 (/4 1600)
>[207695.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[207695.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[207696.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207696.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207696.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[207696.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[207697.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40502f0]
>[207697.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40502f0] width 1600 pitch 6400 (/4 1600)
>[207699.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207699.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207699.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207699.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207700.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207700.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207700.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207700.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207700.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207700.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207700.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207700.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207700.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207700.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda730]
>[207701.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda730] width 1600 pitch 6400 (/4 1600)
>[207701.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[207701.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[207701.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207701.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207701.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[207701.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[207701.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[207702.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[207702.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dade80]
>[207702.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dade80] width 1600 pitch 6400 (/4 1600)
>[207702.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207702.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207702.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e7930]
>[207702.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e7930] width 1600 pitch 6400 (/4 1600)
>[207702.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[207702.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[207703.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c67b0]
>[207703.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c67b0] width 1600 pitch 6400 (/4 1600)
>[207703.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c67b0]
>[207704.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c67b0] width 1600 pitch 6400 (/4 1600)
>[207704.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c67b0]
>[207704.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c67b0] width 1600 pitch 6400 (/4 1600)
>[207704.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c67b0]
>[207704.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c67b0] width 1600 pitch 6400 (/4 1600)
>[207777.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e80580]
>[207777.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e80580] width 1600 pitch 6400 (/4 1600)
>[207777.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[207777.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[207778.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4033300]
>[207778.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4033300] width 1600 pitch 6400 (/4 1600)
>[207778.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[207778.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[207786.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8c090]
>[207786.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8c090] width 1600 pitch 6400 (/4 1600)
>[207786.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[207786.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[207787.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[207787.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[207787.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4fea0]
>[207787.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4fea0] width 1600 pitch 6400 (/4 1600)
>[207787.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[207787.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[207788.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0f260]
>[207788.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0f260] width 1600 pitch 6400 (/4 1600)
>[207788.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[207788.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[207788.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[207788.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[207788.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[207788.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[207789.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17fd0]
>[207789.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17fd0] width 1600 pitch 6400 (/4 1600)
>[207789.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27db450]
>[207789.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27db450] width 1600 pitch 6400 (/4 1600)
>[207790.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5052110]
>[207790.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5052110] width 1600 pitch 6400 (/4 1600)
>[207790.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[207790.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[207790.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[207790.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[207791.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[207791.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[207792.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f68e30]
>[207792.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f68e30] width 1600 pitch 6400 (/4 1600)
>[207797.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5048f40]
>[207797.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5048f40] width 1600 pitch 6400 (/4 1600)
>[207797.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb9e10]
>[207797.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb9e10] width 1600 pitch 6400 (/4 1600)
>[207797.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9520]
>[207797.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9520] width 1600 pitch 6400 (/4 1600)
>[207798.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbb2c0]
>[207798.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbb2c0] width 1600 pitch 6400 (/4 1600)
>[207798.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b4d0]
>[207798.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b4d0] width 1600 pitch 6400 (/4 1600)
>[207798.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9520]
>[207798.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9520] width 1600 pitch 6400 (/4 1600)
>[207799.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[207799.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[207799.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824a10]
>[207799.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824a10] width 1600 pitch 6400 (/4 1600)
>[207800.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a620]
>[207800.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a620] width 1600 pitch 6400 (/4 1600)
>[207870.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[207870.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[207870.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a3b0]
>[207870.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a3b0] width 1600 pitch 6400 (/4 1600)
>[207870.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[207870.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1600 pitch 6400 (/4 1600)
>[207870.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207870.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207870.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207870.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207870.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207870.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2d720]
>[207870.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2d720] width 1600 pitch 6400 (/4 1600)
>[207870.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207870.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207874.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[207874.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1600 pitch 6400 (/4 1600)
>[207874.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a3b0]
>[207874.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a3b0] width 1600 pitch 6400 (/4 1600)
>[207874.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207874.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207874.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207874.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207874.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207874.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b00f0]
>[207874.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b00f0] width 1600 pitch 6400 (/4 1600)
>[207874.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207874.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efa530]
>[207886.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efa530] width 1600 pitch 6400 (/4 1600)
>[207886.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edec40]
>[207886.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edec40] width 1600 pitch 6400 (/4 1600)
>[207886.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207886.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207886.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207886.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207886.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207886.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207886.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207886.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f20680]
>[207886.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f20680] width 1600 pitch 6400 (/4 1600)
>[207890.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[207890.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1600 pitch 6400 (/4 1600)
>[207890.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3960a40]
>[207890.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3960a40] width 1600 pitch 6400 (/4 1600)
>[207890.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824a10]
>[207890.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824a10] width 1600 pitch 6400 (/4 1600)
>[207890.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207890.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207890.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207890.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207890.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207890.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207890.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207890.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207890.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207890.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207890.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207890.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207890.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207891.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207891.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207891.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207891.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207891.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207891.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207891.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207891.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207891.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207898.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a620]
>[207898.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a620] width 1600 pitch 6400 (/4 1600)
>[207898.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efa530]
>[207898.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efa530] width 1600 pitch 6400 (/4 1600)
>[207898.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207898.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207898.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207898.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207898.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207898.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207898.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207898.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207898.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207899.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207899.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207899.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207899.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207899.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207899.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207899.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207899.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207899.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207899.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207899.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207899.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207899.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207899.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207899.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207903.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3a60]
>[207903.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3a60] width 1600 pitch 6400 (/4 1600)
>[207903.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcdec0]
>[207903.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcdec0] width 1600 pitch 6400 (/4 1600)
>[207973.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c12c10]
>[207973.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c12c10] width 1600 pitch 6400 (/4 1600)
>[207973.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4dff0]
>[207973.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4dff0] width 1600 pitch 6400 (/4 1600)
>[207973.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c436e0]
>[207973.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c436e0] width 1600 pitch 6400 (/4 1600)
>[207973.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4dff0]
>[207973.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4dff0] width 1600 pitch 6400 (/4 1600)
>[207973.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c436e0]
>[207973.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c436e0] width 1600 pitch 6400 (/4 1600)
>[207973.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efa530]
>[207973.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efa530] width 1600 pitch 6400 (/4 1600)
>[207973.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2617810]
>[207973.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2617810] width 1600 pitch 6400 (/4 1600)
>[207973.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28540f0]
>[207973.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28540f0] width 1600 pitch 6400 (/4 1600)
>[207973.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efa530]
>[207973.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efa530] width 1600 pitch 6400 (/4 1600)
>[207973.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a620]
>[207973.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a620] width 1600 pitch 6400 (/4 1600)
>[207973.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7afd0]
>[207973.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7afd0] width 1600 pitch 6400 (/4 1600)
>[207973.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2fcd0]
>[207973.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2fcd0] width 1600 pitch 6400 (/4 1600)
>[207973.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[207973.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[207977.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edec40]
>[207977.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edec40] width 1600 pitch 6400 (/4 1600)
>[207977.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a3b0]
>[207977.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a3b0] width 1600 pitch 6400 (/4 1600)
>[207977.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a620]
>[207977.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a620] width 1600 pitch 6400 (/4 1600)
>[207977.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2617810]
>[207977.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2617810] width 1600 pitch 6400 (/4 1600)
>[207977.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa3760]
>[207977.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa3760] width 1600 pitch 6400 (/4 1600)
>[207977.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824a10]
>[207977.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824a10] width 1600 pitch 6400 (/4 1600)
>[207977.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efa530]
>[207977.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efa530] width 1600 pitch 6400 (/4 1600)
>[207977.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ac5b0]
>[207977.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ac5b0] width 1600 pitch 6400 (/4 1600)
>[207977.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[207977.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[207977.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ac5b0]
>[207977.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ac5b0] width 1600 pitch 6400 (/4 1600)
>[207977.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[207977.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[207977.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ac5b0]
>[207977.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ac5b0] width 1600 pitch 6400 (/4 1600)
>[207977.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[207977.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[208001.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2617810]
>[208001.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2617810] width 1600 pitch 6400 (/4 1600)
>[208001.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[208001.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[208002.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[208002.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[208003.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208003.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208003.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[208003.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[208003.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[208003.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[208004.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208004.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208044.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208044.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208044.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208044.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208044.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[208044.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[208044.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[208044.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[208044.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208044.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208044.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208044.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208044.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b9520]
>[208044.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b9520] width 1600 pitch 6400 (/4 1600)
>[208044.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208044.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208044.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[208044.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[208044.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208044.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208044.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208044.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208044.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[208044.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[208044.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[208044.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[208044.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ae60]
>[208044.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ae60] width 1600 pitch 6400 (/4 1600)
>[208044.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208044.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208044.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69765d0]
>[208045.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69765d0] width 1600 pitch 6400 (/4 1600)
>[208045.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208045.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208045.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208045.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208045.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208047.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ae60]
>[208047.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ae60] width 1600 pitch 6400 (/4 1600)
>[208048.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208048.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208050.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[208050.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[208050.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[208050.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[208050.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208050.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208050.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208050.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208050.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208050.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208050.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208050.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208050.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208050.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208050.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208050.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208050.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208050.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208050.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208050.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208050.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208050.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208050.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208050.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ae60]
>[208215.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ae60] width 1600 pitch 6400 (/4 1600)
>[208215.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[208215.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[208215.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ae60]
>[208215.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ae60] width 1600 pitch 6400 (/4 1600)
>[208215.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[208215.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[208215.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f3ae60]
>[208215.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f3ae60] width 1600 pitch 6400 (/4 1600)
>[208215.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208215.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208215.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208215.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208215.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208216.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208216.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208216.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208216.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208217.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208217.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208217.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208217.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208218.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208218.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208218.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208218.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208219.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4055040]
>[208219.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4055040] width 1600 pitch 6400 (/4 1600)
>[208237.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9f040]
>[208237.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9f040] width 1600 pitch 6400 (/4 1600)
>[208237.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208237.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208237.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9f040]
>[208237.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9f040] width 1600 pitch 6400 (/4 1600)
>[208237.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208237.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208237.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9f040]
>[208237.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9f040] width 1600 pitch 6400 (/4 1600)
>[208237.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208237.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208237.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9f040]
>[208237.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9f040] width 1600 pitch 6400 (/4 1600)
>[208237.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208237.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208237.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208237.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[208237.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[208237.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208237.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208312.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be40f0]
>[208312.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be40f0] width 1600 pitch 6400 (/4 1600)
>[208312.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[208312.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[208312.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[208312.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[208313.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad1b20]
>[208313.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad1b20] width 1600 pitch 6400 (/4 1600)
>[208315.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[208315.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[208315.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4038e90]
>[208315.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4038e90] width 1600 pitch 6400 (/4 1600)
>[208315.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[208315.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[208316.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[208316.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[208316.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f965e0]
>[208316.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f965e0] width 1600 pitch 6400 (/4 1600)
>[208317.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[208317.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[208317.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[208317.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[208318.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4decd30]
>[208318.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4decd30] width 1600 pitch 6400 (/4 1600)
>[208318.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed06d0]
>[208318.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed06d0] width 1600 pitch 6400 (/4 1600)
>[208318.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[208318.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[208318.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[208318.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[208319.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[208319.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[208320.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[208320.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[208359.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5060]
>[208359.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5060] width 1600 pitch 6400 (/4 1600)
>[208359.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eba0]
>[208359.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eba0] width 1600 pitch 6400 (/4 1600)
>[208360.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8c30]
>[208360.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8c30] width 1600 pitch 6400 (/4 1600)
>[208379.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4be0]
>[208379.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4be0] width 1600 pitch 6400 (/4 1600)
>[208379.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50be0]
>[208379.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50be0] width 1600 pitch 6400 (/4 1600)
>[208379.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[208379.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[208383.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eba0]
>[208383.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eba0] width 1600 pitch 6400 (/4 1600)
>[208383.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[208383.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[208383.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[208383.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[208384.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[208384.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[208385.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07730]
>[208385.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07730] width 1600 pitch 6400 (/4 1600)
>[208385.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[208385.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[208385.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42880]
>[208385.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42880] width 1600 pitch 6400 (/4 1600)
>[208386.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[208386.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[208386.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e89cd0]
>[208386.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e89cd0] width 1600 pitch 6400 (/4 1600)
>[208386.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[208386.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[208386.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b46dc0]
>[208386.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b46dc0] width 1600 pitch 6400 (/4 1600)
>[208387.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50be0]
>[208387.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50be0] width 1600 pitch 6400 (/4 1600)
>[208387.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4034670]
>[208387.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4034670] width 1600 pitch 6400 (/4 1600)
>[208388.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[208388.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[208389.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[208389.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[208390.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62730]
>[208390.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62730] width 1600 pitch 6400 (/4 1600)
>[208391.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403ff70]
>[208391.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403ff70] width 1600 pitch 6400 (/4 1600)
>[208392.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[208392.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[208393.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[208393.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[208394.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27db450]
>[208394.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27db450] width 1600 pitch 6400 (/4 1600)
>[208395.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[208395.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[208396.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[208396.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[208397.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[208397.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[208398.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[208398.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[208399.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42880]
>[208399.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42880] width 1600 pitch 6400 (/4 1600)
>[208400.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fc400]
>[208400.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fc400] width 1600 pitch 6400 (/4 1600)
>[208401.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1f4b0]
>[208401.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1f4b0] width 1600 pitch 6400 (/4 1600)
>[208402.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[208402.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[208403.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f231c0]
>[208403.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f231c0] width 1600 pitch 6400 (/4 1600)
>[208404.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11790]
>[208404.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11790] width 1600 pitch 6400 (/4 1600)
>[208405.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c597b0]
>[208405.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c597b0] width 1600 pitch 6400 (/4 1600)
>[208406.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[208406.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[208407.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[208407.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[208408.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9a910]
>[208408.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9a910] width 1600 pitch 6400 (/4 1600)
>[208409.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ee9da0]
>[208409.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ee9da0] width 1600 pitch 6400 (/4 1600)
>[208410.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eba0]
>[208410.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eba0] width 1600 pitch 6400 (/4 1600)
>[208410.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f08970]
>[208410.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f08970] width 1600 pitch 6400 (/4 1600)
>[208410.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c07730]
>[208410.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c07730] width 1600 pitch 6400 (/4 1600)
>[208411.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a1f0]
>[208411.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a1f0] width 1600 pitch 6400 (/4 1600)
>[208412.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[208412.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[208413.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[208413.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[208413.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c4cc0]
>[208413.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c4cc0] width 1600 pitch 6400 (/4 1600)
>[208413.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[208413.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[208413.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[208413.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[208414.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb7cf0]
>[208414.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb7cf0] width 1600 pitch 6400 (/4 1600)
>[208414.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[208414.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[208415.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[208415.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[208424.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eba0]
>[208424.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eba0] width 1600 pitch 6400 (/4 1600)
>[208424.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64200]
>[208424.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64200] width 1600 pitch 6400 (/4 1600)
>[208424.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[208424.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[208425.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[208425.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[208426.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3300]
>[208426.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3300] width 1600 pitch 6400 (/4 1600)
>[208427.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[208427.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[208427.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[208427.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[208427.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4be0]
>[208427.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4be0] width 1600 pitch 6400 (/4 1600)
>[208428.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[208428.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[208433.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4ed70]
>[208433.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4ed70] width 1600 pitch 6400 (/4 1600)
>[208433.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ea4a0]
>[208433.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ea4a0] width 1600 pitch 6400 (/4 1600)
>[208434.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dab0a0]
>[208434.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dab0a0] width 1600 pitch 6400 (/4 1600)
>[208469.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[208469.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1600 pitch 6400 (/4 1600)
>[208706.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208706.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208706.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208706.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208706.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208706.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208706.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3960cf0]
>[208706.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3960cf0] width 1600 pitch 6400 (/4 1600)
>[208706.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208706.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208706.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[208706.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[208706.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[208706.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[208706.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208706.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208706.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b283b0]
>[208706.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b283b0] width 1600 pitch 6400 (/4 1600)
>[208706.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208706.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208706.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208706.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208706.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[208706.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[208706.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208706.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208706.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[208706.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[208706.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208706.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208706.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[208706.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[208706.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208706.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208707.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208707.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208707.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208707.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208707.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208708.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208708.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208709.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208709.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208711.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[208711.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[208711.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b283b0]
>[208711.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b283b0] width 1600 pitch 6400 (/4 1600)
>[208711.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[208711.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[208711.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[208711.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[208711.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208711.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208711.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[208712.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[208712.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[208712.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[208712.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[208712.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[208712.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208712.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208712.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208712.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208712.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[208712.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[208712.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208712.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208736.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208736.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208736.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208736.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208736.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208736.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208736.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208736.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208736.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208736.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208736.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208736.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208736.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208736.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208736.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208736.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208738.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208738.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208738.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[208738.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[208738.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208738.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208738.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208738.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208738.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208738.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208738.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208738.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208738.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208738.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208738.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208738.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208738.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208738.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208738.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[208738.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[208738.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b283b0]
>[208738.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b283b0] width 1600 pitch 6400 (/4 1600)
>[208738.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[208738.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[208738.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6a8d0]
>[208738.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6a8d0] width 1600 pitch 6400 (/4 1600)
>[208739.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208739.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208739.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b283b0]
>[208739.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b283b0] width 1600 pitch 6400 (/4 1600)
>[208739.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3960cf0]
>[208739.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3960cf0] width 1600 pitch 6400 (/4 1600)
>[208739.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f72860]
>[208739.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f72860] width 1600 pitch 6400 (/4 1600)
>[208739.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[208739.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[208739.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[208739.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[208739.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[208739.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[208739.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208739.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208739.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb5fc0]
>[208739.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb5fc0] width 1600 pitch 6400 (/4 1600)
>[208739.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[208739.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[208739.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208739.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208739.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c26570]
>[208739.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c26570] width 1600 pitch 6400 (/4 1600)
>[208739.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d4c0]
>[208739.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d4c0] width 1600 pitch 6400 (/4 1600)
>[208740.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[208740.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[208741.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208741.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208742.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b283b0]
>[208742.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b283b0] width 1600 pitch 6400 (/4 1600)
>[208746.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[208746.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[208746.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[208746.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebe3e0]
>[208746.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebe3e0] width 1600 pitch 6400 (/4 1600)
>[209216.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a08220]
>[209216.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a08220] width 1600 pitch 6400 (/4 1600)
>[209220.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c520]
>[209220.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c520] width 1600 pitch 6400 (/4 1600)
>[209274.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[209274.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[209274.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a08220]
>[209274.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a08220] width 1600 pitch 6400 (/4 1600)
>[209274.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de100]
>[209274.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de100] width 1600 pitch 6400 (/4 1600)
>[209274.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209274.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209274.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1a0]
>[209274.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1a0] width 1600 pitch 6400 (/4 1600)
>[209274.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4031c30]
>[209274.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4031c30] width 1600 pitch 6400 (/4 1600)
>[209274.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[209274.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[209274.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[209274.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[209274.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050680]
>[209274.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050680] width 1600 pitch 6400 (/4 1600)
>[209274.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209274.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209274.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209274.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209274.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209274.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209274.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc720]
>[209274.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc720] width 1600 pitch 6400 (/4 1600)
>[209274.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[209274.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[209274.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209274.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209274.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9290]
>[209274.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9290] width 1600 pitch 6400 (/4 1600)
>[209274.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63a30]
>[209274.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63a30] width 1600 pitch 6400 (/4 1600)
>[209275.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[209275.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[209275.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050680]
>[209275.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050680] width 1600 pitch 6400 (/4 1600)
>[209275.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209275.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209275.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc720]
>[209275.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc720] width 1600 pitch 6400 (/4 1600)
>[209275.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[209275.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[209275.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc720]
>[209275.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc720] width 1600 pitch 6400 (/4 1600)
>[209275.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209275.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209275.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209275.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209275.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209275.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209275.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209275.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209275.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[209275.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[209275.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5180]
>[209275.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5180] width 1600 pitch 6400 (/4 1600)
>[209275.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[209275.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[209275.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63a30]
>[209275.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63a30] width 1600 pitch 6400 (/4 1600)
>[209275.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[209275.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[209275.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[209275.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1600 pitch 6400 (/4 1600)
>[209275.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de100]
>[209275.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de100] width 1600 pitch 6400 (/4 1600)
>[209275.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[209275.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[209275.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace1a0]
>[209275.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace1a0] width 1600 pitch 6400 (/4 1600)
>[209275.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[209275.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[209276.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de100]
>[209276.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de100] width 1600 pitch 6400 (/4 1600)
>[209276.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[209276.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[209276.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209276.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209276.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4031c30]
>[209276.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4031c30] width 1600 pitch 6400 (/4 1600)
>[209276.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[209276.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[209276.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209276.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209276.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[209276.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[209276.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bc720]
>[209276.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bc720] width 1600 pitch 6400 (/4 1600)
>[209276.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209276.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209276.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[209276.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[209277.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050680]
>[209277.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050680] width 1600 pitch 6400 (/4 1600)
>[209277.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[209277.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[209290.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[209290.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[209290.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209290.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209290.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5180]
>[209290.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5180] width 1600 pitch 6400 (/4 1600)
>[209290.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[209291.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[209291.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209291.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209291.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[209291.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[209291.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[209291.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[209291.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209291.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209291.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[209291.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[209291.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209291.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209291.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f5660]
>[209291.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f5660] width 1600 pitch 6400 (/4 1600)
>[209291.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc6800]
>[209291.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc6800] width 1600 pitch 6400 (/4 1600)
>[209291.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209291.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209291.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9290]
>[209291.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9290] width 1600 pitch 6400 (/4 1600)
>[209291.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50de100]
>[209291.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50de100] width 1600 pitch 6400 (/4 1600)
>[209291.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[209291.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[209291.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f63a30]
>[209291.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f63a30] width 1600 pitch 6400 (/4 1600)
>[209291.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc0f60]
>[209291.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc0f60] width 1600 pitch 6400 (/4 1600)
>[209291.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[209291.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[209291.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5050680]
>[209291.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5050680] width 1600 pitch 6400 (/4 1600)
>[209291.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209291.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209291.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5180]
>[209291.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5180] width 1600 pitch 6400 (/4 1600)
>[209295.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[209295.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[209295.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209295.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209295.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f013c0]
>[209295.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f013c0] width 1600 pitch 6400 (/4 1600)
>[209295.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5101230]
>[209295.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5101230] width 1600 pitch 6400 (/4 1600)
>[209295.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ce00]
>[209295.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ce00] width 1600 pitch 6400 (/4 1600)
>[209295.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[209295.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1600 pitch 6400 (/4 1600)
>[209295.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3410]
>[209295.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3410] width 1600 pitch 6400 (/4 1600)
>[209295.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed5180]
>[209295.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed5180] width 1600 pitch 6400 (/4 1600)
>[209295.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[209295.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[209295.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f725b0]
>[209295.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f725b0] width 1600 pitch 6400 (/4 1600)
>[209295.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9290]
>[209295.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9290] width 1600 pitch 6400 (/4 1600)
>[209295.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c70]
>[209295.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c70] width 1600 pitch 6400 (/4 1600)
>[209295.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a08220]
>[209295.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a08220] width 1600 pitch 6400 (/4 1600)
>[209295.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209295.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209295.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[209295.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[209295.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de5520]
>[209295.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de5520] width 1600 pitch 6400 (/4 1600)
>[209295.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209295.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209295.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9290]
>[209295.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9290] width 1600 pitch 6400 (/4 1600)
>[209295.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[209295.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[209295.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209295.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fdaab0]
>[209295.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fdaab0] width 1600 pitch 6400 (/4 1600)
>[209295.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[209295.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[209301.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209302.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209302.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48f00]
>[209302.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48f00] width 1600 pitch 6400 (/4 1600)
>[209302.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979b60]
>[209302.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979b60] width 1600 pitch 6400 (/4 1600)
>[209302.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c264b0]
>[209302.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c264b0] width 1600 pitch 6400 (/4 1600)
>[209302.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53640]
>[209302.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53640] width 1600 pitch 6400 (/4 1600)
>[209302.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209302.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209302.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26341a0]
>[209302.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26341a0] width 1600 pitch 6400 (/4 1600)
>[209302.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398c910]
>[209302.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398c910] width 1600 pitch 6400 (/4 1600)
>[209302.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209302.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209302.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209302.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209302.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209302.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209302.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209302.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209302.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209302.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209303.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26341a0]
>[209303.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26341a0] width 1600 pitch 6400 (/4 1600)
>[209303.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53640]
>[209303.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53640] width 1600 pitch 6400 (/4 1600)
>[209303.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979b60]
>[209303.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979b60] width 1600 pitch 6400 (/4 1600)
>[209303.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48f00]
>[209303.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48f00] width 1600 pitch 6400 (/4 1600)
>[209303.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209303.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209303.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209303.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209303.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26341a0]
>[209303.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26341a0] width 1600 pitch 6400 (/4 1600)
>[209303.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209303.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209303.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209303.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209303.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48f00]
>[209303.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48f00] width 1600 pitch 6400 (/4 1600)
>[209304.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979b60]
>[209304.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979b60] width 1600 pitch 6400 (/4 1600)
>[209304.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53640]
>[209304.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53640] width 1600 pitch 6400 (/4 1600)
>[209304.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c264b0]
>[209304.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c264b0] width 1600 pitch 6400 (/4 1600)
>[209304.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209304.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209304.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209304.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209304.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209305.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60ec0]
>[209305.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60ec0] width 1600 pitch 6400 (/4 1600)
>[209305.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209305.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209306.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209306.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209306.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be2c40]
>[209306.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be2c40] width 1600 pitch 6400 (/4 1600)
>[209312.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209312.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209312.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4890]
>[209312.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4890] width 1600 pitch 6400 (/4 1600)
>[209312.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209312.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209312.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4890]
>[209312.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4890] width 1600 pitch 6400 (/4 1600)
>[209315.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209315.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209320.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209320.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209320.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209320.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209321.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209321.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209321.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209321.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209321.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209321.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209321.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209321.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209321.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209321.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209321.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209321.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209321.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209321.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209321.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209321.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d0f0]
>[209321.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d0f0] width 1600 pitch 6400 (/4 1600)
>[209321.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209321.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209344.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209344.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209344.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209344.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209344.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209344.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209344.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209344.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209344.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209344.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209344.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209344.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209344.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209344.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209344.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209344.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209344.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209344.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209344.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209344.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209344.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209344.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209344.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209344.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209344.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209344.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209344.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209344.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209344.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209344.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209344.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209344.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209344.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209344.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209344.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209344.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209344.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209344.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209344.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209344.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209344.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209344.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209344.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209344.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209344.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209344.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db83b0]
>[209344.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db83b0] width 1600 pitch 6400 (/4 1600)
>[209344.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209344.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db83b0]
>[209344.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db83b0] width 1600 pitch 6400 (/4 1600)
>[209344.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209344.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db83b0]
>[209344.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db83b0] width 1600 pitch 6400 (/4 1600)
>[209344.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209344.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db83b0]
>[209344.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db83b0] width 1600 pitch 6400 (/4 1600)
>[209344.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209344.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db83b0]
>[209344.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db83b0] width 1600 pitch 6400 (/4 1600)
>[209344.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5064df0]
>[209344.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5064df0] width 1600 pitch 6400 (/4 1600)
>[209345.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209345.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209346.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209346.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209386.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209386.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209387.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209387.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209387.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209387.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209387.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209387.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209387.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209387.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209387.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209387.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209387.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209387.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209387.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209387.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209387.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209387.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209387.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209387.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209387.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f07720]
>[209387.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f07720] width 1600 pitch 6400 (/4 1600)
>[209387.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209387.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209387.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f07720]
>[209387.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f07720] width 1600 pitch 6400 (/4 1600)
>[209387.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209387.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209391.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209391.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209391.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209391.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209391.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209391.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209391.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209391.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209391.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209391.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209391.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209391.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209391.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209391.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209391.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209391.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209391.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209391.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209391.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209391.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209392.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50779e0]
>[209392.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50779e0] width 1600 pitch 6400 (/4 1600)
>[209392.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209392.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209392.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209392.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209392.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209392.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209392.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209392.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209392.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209392.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209392.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209392.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209392.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209392.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209392.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209393.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209393.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209393.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209393.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209393.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209393.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209393.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209393.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209393.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1e630]
>[209393.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1e630] width 1600 pitch 6400 (/4 1600)
>[209393.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209393.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209397.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209397.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209397.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209397.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209397.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209397.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209397.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209397.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209397.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209397.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209397.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209397.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209397.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209397.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209397.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209397.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209397.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209397.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209397.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209397.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404c210]
>[209397.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404c210] width 1600 pitch 6400 (/4 1600)
>[209397.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209397.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209398.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209398.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209398.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209398.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209398.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209398.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209398.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209398.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209398.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209398.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209398.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209398.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209398.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209398.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209398.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209398.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209398.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209398.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209398.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209398.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209398.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209398.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209398.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209398.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209398.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209398.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209398.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209398.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209398.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209398.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209398.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209398.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209398.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209398.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209398.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209398.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209398.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209398.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209398.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209398.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209398.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209398.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209398.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209398.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209398.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209398.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209398.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209398.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209398.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209398.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209398.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7a690]
>[209398.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7a690] width 1600 pitch 6400 (/4 1600)
>[209398.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209398.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209398.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209398.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209398.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209398.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209398.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209398.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209398.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209398.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209398.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209398.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209398.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209398.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209398.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209398.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209398.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209398.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209398.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209398.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209398.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49be0]
>[209398.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49be0] width 1600 pitch 6400 (/4 1600)
>[209398.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209398.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209398.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49be0]
>[209398.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49be0] width 1600 pitch 6400 (/4 1600)
>[209398.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209398.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49be0]
>[209399.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49be0] width 1600 pitch 6400 (/4 1600)
>[209399.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49be0]
>[209399.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49be0] width 1600 pitch 6400 (/4 1600)
>[209399.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b49be0]
>[209399.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b49be0] width 1600 pitch 6400 (/4 1600)
>[209399.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209399.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209399.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209399.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209399.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209399.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209399.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209399.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209399.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209399.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209399.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209399.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209399.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209399.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209399.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209399.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209399.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209399.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209399.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209399.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209399.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209399.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209399.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209399.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209399.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209400.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209400.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209400.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209400.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209400.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eaf0f0]
>[209400.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eaf0f0] width 1600 pitch 6400 (/4 1600)
>[209400.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209400.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209400.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209400.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209401.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209401.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209401.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209401.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209401.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209401.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209401.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209401.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209401.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209401.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209401.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209401.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209401.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209401.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209401.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209401.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209401.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209401.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209401.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209401.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209401.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209401.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209401.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209401.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209401.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209401.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209401.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209401.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209401.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209401.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209401.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209401.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209401.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209401.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209401.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209402.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209402.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209402.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209402.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209403.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209403.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209403.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef1db0]
>[209403.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef1db0] width 1600 pitch 6400 (/4 1600)
>[209404.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209404.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209404.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209404.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209404.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209404.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209404.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209404.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209404.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209404.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209404.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209404.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209404.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209404.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209404.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209404.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209404.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209404.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209404.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209404.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209404.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209404.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209404.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209404.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209414.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3caaa40]
>[209414.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3caaa40] width 1600 pitch 6400 (/4 1600)
>[209414.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209414.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209420.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc8d70]
>[209420.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc8d70] width 1600 pitch 6400 (/4 1600)
>[209420.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8000]
>[209420.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8000] width 1600 pitch 6400 (/4 1600)
>[209420.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209420.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209420.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209420.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209420.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209420.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209420.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209420.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209420.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209420.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209420.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209420.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209420.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209420.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209420.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[209420.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1600 pitch 6400 (/4 1600)
>[209420.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209420.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209420.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[209420.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1600 pitch 6400 (/4 1600)
>[209420.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[209420.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[209444.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209444.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209444.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209444.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209444.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209444.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209444.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[209444.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[209444.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209444.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209444.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209444.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209444.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209444.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209444.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209444.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209444.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209444.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209444.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209444.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209444.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209444.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209444.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209444.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209444.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209444.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209444.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209444.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209444.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209444.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209444.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209444.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209444.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc15b0]
>[209444.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc15b0] width 1600 pitch 6400 (/4 1600)
>[209444.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389a3a0]
>[209444.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389a3a0] width 1600 pitch 6400 (/4 1600)
>[209444.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209444.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209444.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9f310]
>[209444.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9f310] width 1600 pitch 6400 (/4 1600)
>[209444.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209444.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209444.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209444.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209444.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209445.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209445.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209445.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209445.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209445.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209445.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209445.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209445.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209445.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209445.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209445.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209445.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209445.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8a7e0]
>[209445.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8a7e0] width 1600 pitch 6400 (/4 1600)
>[209445.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824620]
>[209445.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824620] width 1600 pitch 6400 (/4 1600)
>[209446.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389c020]
>[209446.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389c020] width 1600 pitch 6400 (/4 1600)
>[209446.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x389c020]
>[209446.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x389c020] width 1600 pitch 6400 (/4 1600)
>[209448.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e91d60]
>[209448.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e91d60] width 1600 pitch 6400 (/4 1600)
>[209448.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e91d60]
>[209448.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e91d60] width 1600 pitch 6400 (/4 1600)
>[209471.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209471.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209471.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209471.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209471.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209471.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209471.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209472.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209472.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f85e0]
>[209472.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f85e0] width 1600 pitch 6400 (/4 1600)
>[209472.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2380]
>[209472.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2380] width 1600 pitch 6400 (/4 1600)
>[209472.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f85e0]
>[209472.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f85e0] width 1600 pitch 6400 (/4 1600)
>[209472.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2380]
>[209472.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2380] width 1600 pitch 6400 (/4 1600)
>[209472.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f85e0]
>[209472.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f85e0] width 1600 pitch 6400 (/4 1600)
>[209472.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2380]
>[209472.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2380] width 1600 pitch 6400 (/4 1600)
>[209472.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f85e0]
>[209472.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f85e0] width 1600 pitch 6400 (/4 1600)
>[209472.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2380]
>[209472.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2380] width 1600 pitch 6400 (/4 1600)
>[209472.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f85e0]
>[209472.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f85e0] width 1600 pitch 6400 (/4 1600)
>[209480.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209480.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209480.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209480.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209480.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209480.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209480.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209480.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209480.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209480.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209480.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209480.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209480.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca380]
>[209480.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca380] width 1600 pitch 6400 (/4 1600)
>[209480.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209480.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209480.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209480.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209480.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209480.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209480.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9c750]
>[209480.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9c750] width 1600 pitch 6400 (/4 1600)
>[209480.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505b160]
>[209480.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505b160] width 1600 pitch 6400 (/4 1600)
>[209480.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209480.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209480.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5102bf0]
>[209480.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5102bf0] width 1600 pitch 6400 (/4 1600)
>[209480.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[209480.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[209480.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209480.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209480.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209480.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209480.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd540]
>[209480.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd540] width 1600 pitch 6400 (/4 1600)
>[209480.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209480.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209480.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd540]
>[209480.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd540] width 1600 pitch 6400 (/4 1600)
>[209480.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209480.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209480.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd540]
>[209480.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd540] width 1600 pitch 6400 (/4 1600)
>[209480.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209480.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209480.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2edd540]
>[209480.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2edd540] width 1600 pitch 6400 (/4 1600)
>[209480.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209480.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209480.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209481.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209481.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96650]
>[209481.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96650] width 1600 pitch 6400 (/4 1600)
>[209481.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505ed10]
>[209481.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505ed10] width 1600 pitch 6400 (/4 1600)
>[209481.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e804e0]
>[209481.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e804e0] width 1600 pitch 6400 (/4 1600)
>[209485.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209485.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209485.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209485.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5066cb0]
>[209485.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5066cb0] width 1600 pitch 6400 (/4 1600)
>[209485.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8220]
>[209485.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8220] width 1600 pitch 6400 (/4 1600)
>[209497.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb2000]
>[209497.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb2000] width 1600 pitch 6400 (/4 1600)
>[209501.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38456a0]
>[209501.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38456a0] width 1600 pitch 6400 (/4 1600)
>[209513.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee5d30]
>[209513.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee5d30] width 1600 pitch 6400 (/4 1600)
>[209513.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f64ef0]
>[209513.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f64ef0] width 1600 pitch 6400 (/4 1600)
>[209513.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x510c4c0]
>[209513.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x510c4c0] width 1600 pitch 6400 (/4 1600)
>[209513.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dea160]
>[209513.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dea160] width 1600 pitch 6400 (/4 1600)
>[209513.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[209513.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[209513.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3f370]
>[209513.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3f370] width 1600 pitch 6400 (/4 1600)
>[209513.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f34830]
>[209514.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f34830] width 1600 pitch 6400 (/4 1600)
>[209514.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83cb0]
>[209514.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83cb0] width 1600 pitch 6400 (/4 1600)
>[209514.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83cb0]
>[209514.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83cb0] width 1600 pitch 6400 (/4 1600)
>[209514.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e83cb0]
>[209514.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e83cb0] width 1600 pitch 6400 (/4 1600)
>[209514.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0090]
>[209514.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0090] width 1600 pitch 6400 (/4 1600)
>[209514.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0090]
>[209514.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0090] width 1600 pitch 6400 (/4 1600)
>[209514.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa0090]
>[209514.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa0090] width 1600 pitch 6400 (/4 1600)
>[209514.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8cad0]
>[209514.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8cad0] width 1600 pitch 6400 (/4 1600)
>[209514.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9fdc0]
>[209514.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9fdc0] width 1600 pitch 6400 (/4 1600)
>[209514.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398efa0]
>[209514.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398efa0] width 1600 pitch 6400 (/4 1600)
>[209514.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9fdc0]
>[209514.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9fdc0] width 1600 pitch 6400 (/4 1600)
>[209514.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398efa0]
>[209514.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398efa0] width 1600 pitch 6400 (/4 1600)
>[209514.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9fdc0]
>[209514.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9fdc0] width 1600 pitch 6400 (/4 1600)
>[209514.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398efa0]
>[209514.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398efa0] width 1600 pitch 6400 (/4 1600)
>[209514.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9fdc0]
>[209514.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9fdc0] width 1600 pitch 6400 (/4 1600)
>[209516.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f32f10]
>[209516.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f32f10] width 1600 pitch 6400 (/4 1600)
>[209516.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33520]
>[209516.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33520] width 1600 pitch 6400 (/4 1600)
>[209565.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e399e0]
>[209565.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e399e0] width 1600 pitch 6400 (/4 1600)
>[209799.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9fc0]
>[209799.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9fc0] width 1600 pitch 6400 (/4 1600)
>[209811.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e1320]
>[209811.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e1320] width 1600 pitch 6400 (/4 1600)
>[209812.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49bea10]
>[209812.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49bea10] width 1600 pitch 6400 (/4 1600)
>[209812.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e332b0]
>[209812.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e332b0] width 1600 pitch 6400 (/4 1600)
>[209812.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e38700]
>[209812.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e38700] width 1600 pitch 6400 (/4 1600)
>[209861.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49bea10]
>[209861.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49bea10] width 1600 pitch 6400 (/4 1600)
>[209861.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300b020]
>[209861.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300b020] width 1600 pitch 6400 (/4 1600)
>[209861.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209861.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209861.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300b020]
>[209861.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300b020] width 1600 pitch 6400 (/4 1600)
>[209861.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d07720]
>[209861.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d07720] width 1600 pitch 6400 (/4 1600)
>[209861.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cacc40]
>[209861.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cacc40] width 1600 pitch 6400 (/4 1600)
>[209861.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d07720]
>[209861.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d07720] width 1600 pitch 6400 (/4 1600)
>[209861.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209861.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209861.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d07720]
>[209861.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d07720] width 1600 pitch 6400 (/4 1600)
>[209861.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209861.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209861.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d07720]
>[209861.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d07720] width 1600 pitch 6400 (/4 1600)
>[209861.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209861.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209862.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209862.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209862.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209862.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209862.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209862.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209862.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209862.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209862.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209862.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209862.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc9200]
>[209862.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc9200] width 1600 pitch 6400 (/4 1600)
>[209862.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209862.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209862.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc9200]
>[209862.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc9200] width 1600 pitch 6400 (/4 1600)
>[209871.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc9200]
>[209871.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc9200] width 1600 pitch 6400 (/4 1600)
>[209871.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209871.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209872.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209872.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209873.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209873.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209873.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2bf80]
>[209873.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2bf80] width 1600 pitch 6400 (/4 1600)
>[209873.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc9200]
>[209873.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc9200] width 1600 pitch 6400 (/4 1600)
>[209873.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c0c0]
>[209873.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c0c0] width 1600 pitch 6400 (/4 1600)
>[209881.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e39f50]
>[209881.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e39f50] width 1600 pitch 6400 (/4 1600)
>[209881.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e39f50]
>[209881.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e39f50] width 1600 pitch 6400 (/4 1600)
>[209881.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209881.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209881.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209882.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209882.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e39f50]
>[209882.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e39f50] width 1600 pitch 6400 (/4 1600)
>[209882.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e39f50]
>[209882.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e39f50] width 1600 pitch 6400 (/4 1600)
>[209891.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[209891.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1600 pitch 6400 (/4 1600)
>[209891.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a0e0]
>[209891.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a0e0] width 1600 pitch 6400 (/4 1600)
>[209891.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209891.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209891.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bdbd30]
>[209891.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bdbd30] width 1600 pitch 6400 (/4 1600)
>[209891.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2b080]
>[209891.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2b080] width 1600 pitch 6400 (/4 1600)
>[209891.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e39f50]
>[209891.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e39f50] width 1600 pitch 6400 (/4 1600)
>[209891.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504db00]
>[209891.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504db00] width 1600 pitch 6400 (/4 1600)
>[209891.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[209891.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[209891.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2863ca0]
>[209891.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2863ca0] width 1600 pitch 6400 (/4 1600)
>[209891.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2a0e0]
>[209891.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2a0e0] width 1600 pitch 6400 (/4 1600)
>[209891.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209891.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209891.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209891.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[209891.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[209896.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209896.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[209896.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[209896.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209896.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209922.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5f4c0]
>[209922.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5f4c0] width 1600 pitch 6400 (/4 1600)
>[209922.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504db00]
>[209922.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504db00] width 1600 pitch 6400 (/4 1600)
>[209923.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e39280]
>[209923.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e39280] width 1600 pitch 6400 (/4 1600)
>[210393.364] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[210393.364] (II) RADEON(0): Printing DDC gathered Modelines:
>[210393.364] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[210393.364] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[210468.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db32b0]
>[210468.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db32b0] width 1600 pitch 6400 (/4 1600)
>[210472.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26680]
>[210472.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26680] width 1600 pitch 6400 (/4 1600)
>[210472.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d67d0]
>[210472.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d67d0] width 1600 pitch 6400 (/4 1600)
>[210472.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a960]
>[210472.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a960] width 1600 pitch 6400 (/4 1600)
>[210473.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a960]
>[210473.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a960] width 1600 pitch 6400 (/4 1600)
>[210481.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d67d0]
>[210481.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d67d0] width 1600 pitch 6400 (/4 1600)
>[210481.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d67d0]
>[210481.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d67d0] width 1600 pitch 6400 (/4 1600)
>[210508.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a960]
>[210508.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a960] width 1600 pitch 6400 (/4 1600)
>[210508.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d67d0]
>[210508.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d67d0] width 1600 pitch 6400 (/4 1600)
>[210515.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210515.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210515.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210515.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210516.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de9240]
>[210516.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de9240] width 1600 pitch 6400 (/4 1600)
>[210516.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de9240]
>[210516.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de9240] width 1600 pitch 6400 (/4 1600)
>[210518.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210518.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210518.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de9240]
>[210518.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de9240] width 1600 pitch 6400 (/4 1600)
>[210518.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de9240]
>[210518.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de9240] width 1600 pitch 6400 (/4 1600)
>[210519.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210519.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210536.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210536.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210536.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1010]
>[210536.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1010] width 1600 pitch 6400 (/4 1600)
>[210536.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38a1010]
>[210536.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38a1010] width 1600 pitch 6400 (/4 1600)
>[210537.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26680]
>[210537.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26680] width 1600 pitch 6400 (/4 1600)
>[210537.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38187b0]
>[210537.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38187b0] width 1600 pitch 6400 (/4 1600)
>[210544.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d2260]
>[210544.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d2260] width 1600 pitch 6400 (/4 1600)
>[210544.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1b030]
>[210544.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1b030] width 1600 pitch 6400 (/4 1600)
>[210544.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265cd80]
>[210544.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265cd80] width 1600 pitch 6400 (/4 1600)
>[210545.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26680]
>[210545.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26680] width 1600 pitch 6400 (/4 1600)
>[210545.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210545.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0b5f0]
>[210545.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0b5f0] width 1600 pitch 6400 (/4 1600)
>[210545.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210545.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210548.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e37990]
>[210548.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e37990] width 1600 pitch 6400 (/4 1600)
>[210548.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210548.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8e130]
>[210549.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8e130] width 1600 pitch 6400 (/4 1600)
>[210549.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50701d0]
>[210549.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50701d0] width 1600 pitch 6400 (/4 1600)
>[210549.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210549.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210549.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e88f20]
>[210549.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e88f20] width 1600 pitch 6400 (/4 1600)
>[210552.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210552.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210552.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210552.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9eaf0]
>[210552.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9eaf0] width 1600 pitch 6400 (/4 1600)
>[210561.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210561.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210561.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210561.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210561.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210561.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210561.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210561.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210561.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210561.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210561.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210561.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210561.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210561.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210561.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210561.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210561.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210561.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210561.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210561.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210562.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210562.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210562.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210562.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f64650]
>[210562.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f64650] width 1600 pitch 6400 (/4 1600)
>[210562.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210562.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3845800]
>[210562.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3845800] width 1600 pitch 6400 (/4 1600)
>[210562.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301eb20]
>[210562.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301eb20] width 1600 pitch 6400 (/4 1600)
>[210564.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ac680]
>[210564.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ac680] width 1600 pitch 6400 (/4 1600)
>[210564.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ac680]
>[210564.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ac680] width 1600 pitch 6400 (/4 1600)
>[210566.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ac680]
>[210566.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ac680] width 1600 pitch 6400 (/4 1600)
>[210566.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[210566.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[210566.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ac680]
>[210566.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ac680] width 1600 pitch 6400 (/4 1600)
>[210566.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[210566.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[210566.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ac680]
>[210566.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ac680] width 1600 pitch 6400 (/4 1600)
>[210566.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df9b40]
>[210566.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df9b40] width 1600 pitch 6400 (/4 1600)
>[210566.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db1bf0]
>[210566.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db1bf0] width 1600 pitch 6400 (/4 1600)
>[210566.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5a40]
>[210566.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5a40] width 1600 pitch 6400 (/4 1600)
>[210566.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db1bf0]
>[210566.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db1bf0] width 1600 pitch 6400 (/4 1600)
>[210566.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5a40]
>[210566.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5a40] width 1600 pitch 6400 (/4 1600)
>[210566.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db1bf0]
>[210566.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db1bf0] width 1600 pitch 6400 (/4 1600)
>[210566.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5a40]
>[210566.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5a40] width 1600 pitch 6400 (/4 1600)
>[210566.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db1bf0]
>[210566.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db1bf0] width 1600 pitch 6400 (/4 1600)
>[210566.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5a40]
>[210566.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5a40] width 1600 pitch 6400 (/4 1600)
>[210605.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426d6d0]
>[210605.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426d6d0] width 1600 pitch 6400 (/4 1600)
>[210605.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[210605.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[210606.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[210606.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[210609.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afd8b0]
>[210609.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afd8b0] width 1600 pitch 6400 (/4 1600)
>[210678.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f71500]
>[210678.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f71500] width 1600 pitch 6400 (/4 1600)
>[210680.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1de20]
>[210680.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1de20] width 1600 pitch 6400 (/4 1600)
>[210680.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea55c0]
>[210680.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea55c0] width 1600 pitch 6400 (/4 1600)
>[210680.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1f30]
>[210680.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1f30] width 1600 pitch 6400 (/4 1600)
>[210680.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36cf0]
>[210680.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36cf0] width 1600 pitch 6400 (/4 1600)
>[210680.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1f30]
>[210680.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1f30] width 1600 pitch 6400 (/4 1600)
>[210680.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36cf0]
>[210680.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36cf0] width 1600 pitch 6400 (/4 1600)
>[210680.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1f30]
>[210680.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1f30] width 1600 pitch 6400 (/4 1600)
>[210680.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36cf0]
>[210680.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36cf0] width 1600 pitch 6400 (/4 1600)
>[210680.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1f30]
>[210680.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1f30] width 1600 pitch 6400 (/4 1600)
>[210680.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36cf0]
>[210680.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36cf0] width 1600 pitch 6400 (/4 1600)
>[210680.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1f30]
>[210680.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1f30] width 1600 pitch 6400 (/4 1600)
>[210680.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4f90]
>[210680.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4f90] width 1600 pitch 6400 (/4 1600)
>[210680.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[210680.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1600 pitch 6400 (/4 1600)
>[210680.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5094d80]
>[210680.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5094d80] width 1600 pitch 6400 (/4 1600)
>[210680.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210680.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210680.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210680.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210680.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210680.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210680.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210680.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210680.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210680.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210680.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210681.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210681.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210681.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210681.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210681.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210681.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210681.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210681.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210681.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210681.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210681.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210681.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2d540]
>[210681.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2d540] width 1600 pitch 6400 (/4 1600)
>[210681.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210681.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210684.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[210684.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[210684.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210684.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210684.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041e40]
>[210684.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041e40] width 1600 pitch 6400 (/4 1600)
>[210684.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8de0]
>[210684.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8de0] width 1600 pitch 6400 (/4 1600)
>[210684.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[210685.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[210685.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[210685.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1600 pitch 6400 (/4 1600)
>[210685.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8de0]
>[210685.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8de0] width 1600 pitch 6400 (/4 1600)
>[210685.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f367e0]
>[210685.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f367e0] width 1600 pitch 6400 (/4 1600)
>[210685.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f71500]
>[210685.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f71500] width 1600 pitch 6400 (/4 1600)
>[210685.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[210685.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[210685.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[210685.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1600 pitch 6400 (/4 1600)
>[210685.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d8de0]
>[210685.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d8de0] width 1600 pitch 6400 (/4 1600)
>[210690.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[210690.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1600 pitch 6400 (/4 1600)
>[210693.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[210693.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1600 pitch 6400 (/4 1600)
>[210693.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[210693.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1600 pitch 6400 (/4 1600)
>[210694.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e95d0]
>[210694.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e95d0] width 1600 pitch 6400 (/4 1600)
>[210694.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4e180]
>[210694.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4e180] width 1600 pitch 6400 (/4 1600)
>[210695.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a9d0]
>[210695.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a9d0] width 1600 pitch 6400 (/4 1600)
>[210698.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210698.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210698.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210698.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210698.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210699.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210699.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210699.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc9590]
>[210699.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc9590] width 1600 pitch 6400 (/4 1600)
>[210700.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210700.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210700.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4a9d0]
>[210700.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4a9d0] width 1600 pitch 6400 (/4 1600)
>[210700.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82fd0]
>[210700.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82fd0] width 1600 pitch 6400 (/4 1600)
>[210700.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210700.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210700.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82fd0]
>[210700.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82fd0] width 1600 pitch 6400 (/4 1600)
>[210700.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210700.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210700.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82fd0]
>[210701.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82fd0] width 1600 pitch 6400 (/4 1600)
>[210701.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210701.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210701.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82fd0]
>[210701.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82fd0] width 1600 pitch 6400 (/4 1600)
>[210701.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506a040]
>[210701.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506a040] width 1600 pitch 6400 (/4 1600)
>[210701.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82fd0]
>[210701.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82fd0] width 1600 pitch 6400 (/4 1600)
>[210701.901] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[210701.901] (II) RADEON(0): Printing DDC gathered Modelines:
>[210701.901] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[210701.901] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[210704.804] (II) AIGLX: Suspending AIGLX clients for VT switch
>[210704.804] (II) RADEON(0): RADEONLeaveVT_KMS
>[210704.804] (II) RADEON(0): Ok, leaving now...
>[210708.938] (II) AIGLX: Resuming AIGLX clients after VT switch
>[210708.938] (II) RADEON(0): RADEONEnterVT_KMS
>[210708.962] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[210708.962] (II) RADEON(0): Printing DDC gathered Modelines:
>[210708.962] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[210708.962] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[210709.022] (II) RADEON(0): RADEONSaveScreen(2)
>[210709.022] (**) Option "Device" "/dev/input/event5"
>[210709.022] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[210709.168] (II) RADEON(0): Allocate new frame buffer 1920x1080 stride 1920
>[210709.168] (II) RADEON(0): VRAM usage limit set to 221119K
>[210709.820] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse2)
>[210709.820] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[210709.820] (II) No input driver specified, ignoring this device.
>[210709.820] (II) This device may have been added with another device file.
>[210709.821] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event7)
>[210709.821] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[210709.821] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[210709.821] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[210709.821] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[210709.821] 	Option "XkbRules" "evdev"
>[210709.821] 	Option "XkbModel" "pc105+inet"
>[210709.821] 	Option "XkbLayout" "us"
>[210709.821] 	Option "_source" "server/udev"
>[210709.821] 	Option "name" "VISENTA V1 "
>[210709.821] 	Option "path" "/dev/input/event7"
>[210709.821] 	Option "device" "/dev/input/event7"
>[210709.821] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input27/event7"
>[210709.821] 	Option "driver" "evdev"
>[210709.821] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[210709.821] (**) VISENTA V1 : always reports core events
>[210709.821] (**) evdev: VISENTA V1 : Device: "/dev/input/event7"
>[210709.822] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[210709.822] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[210709.822] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[210709.822] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[210709.822] (--) evdev: VISENTA V1 : Found relative axes
>[210709.822] (--) evdev: VISENTA V1 : Found x and y relative axes
>[210709.822] (--) evdev: VISENTA V1 : Found absolute axes
>[210709.822] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[210709.822] (--) evdev: VISENTA V1 : Found keys
>[210709.822] (II) evdev: VISENTA V1 : Configuring as mouse
>[210709.822] (II) evdev: VISENTA V1 : Configuring as keyboard
>[210709.822] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[210709.822] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[210709.822] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[210709.822] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input27/event7"
>[210709.822] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 9)
>[210709.822] (**) Option "xkb_rules" "evdev"
>[210709.822] (**) Option "xkb_model" "pc105+inet"
>[210709.822] (**) Option "xkb_layout" "us"
>[210709.822] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[210709.822] (II) XKB: Reusing cached keymap
>[210709.823] (II) evdev: VISENTA V1 : initialized for relative axes.
>[210709.823] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[210709.824] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[210709.824] (**) VISENTA V1 : (accel) acceleration profile 0
>[210709.824] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[210709.824] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[210709.826] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event6)
>[210709.826] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[210709.826] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[210709.826] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[210709.826] 	Option "XkbRules" "evdev"
>[210709.826] 	Option "XkbModel" "pc105+inet"
>[210709.826] 	Option "XkbLayout" "us"
>[210709.826] 	Option "_source" "server/udev"
>[210709.826] 	Option "name" "VISENTA V1 "
>[210709.826] 	Option "path" "/dev/input/event6"
>[210709.826] 	Option "device" "/dev/input/event6"
>[210709.826] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input26/event6"
>[210709.826] 	Option "driver" "evdev"
>[210709.826] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[210709.826] (**) VISENTA V1 : always reports core events
>[210709.826] (**) evdev: VISENTA V1 : Device: "/dev/input/event6"
>[210709.826] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[210709.826] (--) evdev: VISENTA V1 : Found keys
>[210709.826] (II) evdev: VISENTA V1 : Configuring as keyboard
>[210709.826] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input26/event6"
>[210709.827] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 10)
>[210709.827] (**) Option "xkb_rules" "evdev"
>[210709.827] (**) Option "xkb_model" "pc105+inet"
>[210709.827] (**) Option "xkb_layout" "us"
>[210709.827] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[210709.827] (II) XKB: Reusing cached keymap
>[210709.843] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event18)
>[210709.843] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[210709.843] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[210709.843] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[210709.843] 	Option "XkbRules" "evdev"
>[210709.843] 	Option "XkbModel" "pc105+inet"
>[210709.843] 	Option "XkbLayout" "us"
>[210709.843] 	Option "_source" "server/udev"
>[210709.843] 	Option "name" "USB USB Keykoard"
>[210709.843] 	Option "path" "/dev/input/event18"
>[210709.843] 	Option "device" "/dev/input/event18"
>[210709.843] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input29/event18"
>[210709.843] 	Option "driver" "evdev"
>[210709.843] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[210709.843] (**) USB USB Keykoard: always reports core events
>[210709.843] (**) evdev: USB USB Keykoard: Device: "/dev/input/event18"
>[210709.843] (--) evdev: USB USB Keykoard: absolute axis 0x20 [572..0]
>[210709.843] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[210709.843] (--) evdev: USB USB Keykoard: Found 1 mouse buttons
>[210709.843] (--) evdev: USB USB Keykoard: Found scroll wheel(s)
>[210709.843] (--) evdev: USB USB Keykoard: Found relative axes
>[210709.843] (II) evdev: USB USB Keykoard: Forcing relative x/y axes to exist.
>[210709.843] (--) evdev: USB USB Keykoard: Found absolute axes
>[210709.843] (II) evdev: USB USB Keykoard: Forcing absolute x/y axes to exist.
>[210709.843] (--) evdev: USB USB Keykoard: Found keys
>[210709.843] (II) evdev: USB USB Keykoard: Configuring as mouse
>[210709.843] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[210709.843] (II) evdev: USB USB Keykoard: Adding scrollwheel support
>[210709.843] (**) evdev: USB USB Keykoard: YAxisMapping: buttons 4 and 5
>[210709.844] (**) evdev: USB USB Keykoard: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[210709.844] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input29/event18"
>[210709.844] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 11)
>[210709.844] (**) Option "xkb_rules" "evdev"
>[210709.844] (**) Option "xkb_model" "pc105+inet"
>[210709.844] (**) Option "xkb_layout" "us"
>[210709.844] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[210709.844] (II) XKB: Reusing cached keymap
>[210709.844] (II) evdev: USB USB Keykoard: initialized for relative axes.
>[210709.844] (WW) evdev: USB USB Keykoard: ignoring absolute axes.
>[210709.845] (**) USB USB Keykoard: (accel) keeping acceleration scheme 1
>[210709.845] (**) USB USB Keykoard: (accel) acceleration profile 0
>[210709.845] (**) USB USB Keykoard: (accel) acceleration factor: 2.000
>[210709.845] (**) USB USB Keykoard: (accel) acceleration threshold: 4
>[210709.852] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event8)
>[210709.852] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[210709.852] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[210709.852] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[210709.852] 	Option "XkbRules" "evdev"
>[210709.852] 	Option "XkbModel" "pc105+inet"
>[210709.852] 	Option "XkbLayout" "us"
>[210709.852] 	Option "_source" "server/udev"
>[210709.852] 	Option "name" "USB USB Keykoard"
>[210709.852] 	Option "path" "/dev/input/event8"
>[210709.852] 	Option "device" "/dev/input/event8"
>[210709.852] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input28/event8"
>[210709.852] 	Option "driver" "evdev"
>[210709.852] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[210709.852] (**) USB USB Keykoard: always reports core events
>[210709.852] (**) evdev: USB USB Keykoard: Device: "/dev/input/event8"
>[210709.852] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[210709.852] (--) evdev: USB USB Keykoard: Found keys
>[210709.852] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[210709.853] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input28/event8"
>[210709.853] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 17)
>[210709.853] (**) Option "xkb_rules" "evdev"
>[210709.853] (**) Option "xkb_model" "pc105+inet"
>[210709.853] (**) Option "xkb_layout" "us"
>[210709.853] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[210709.853] (II) XKB: Reusing cached keymap
>[210709.856] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse3)
>[210709.857] (II) No input driver specified, ignoring this device.
>[210709.857] (II) This device may have been added with another device file.
>[210709.864] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event19)
>[210709.864] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[210709.864] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[210709.864] 	Option "XkbRules" "evdev"
>[210709.864] 	Option "XkbModel" "evdev"
>[210709.864] 	Option "XkbLayout" "us"
>[210709.864] 	Option "_source" "server/udev"
>[210709.864] 	Option "name" "Logitech USB Optical Mouse"
>[210709.864] 	Option "path" "/dev/input/event19"
>[210709.864] 	Option "device" "/dev/input/event19"
>[210709.864] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input30/event19"
>[210709.864] 	Option "driver" "evdev"
>[210709.864] (**) Logitech USB Optical Mouse: always reports core events
>[210709.864] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event19"
>[210709.865] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[210709.865] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[210709.865] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[210709.865] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[210709.865] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[210709.865] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[210709.865] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[210709.865] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[210709.865] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[210709.865] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input30/event19"
>[210709.865] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 18)
>[210709.865] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[210709.866] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[210709.866] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[210709.866] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[210709.866] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[210710.604] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[210710.604] (II) RADEON(0): Printing DDC gathered Modelines:
>[210710.604] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[210710.604] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[210710.824] (II) RADEON(0): RADEONSaveScreen(2)
>[210710.824] (II) RADEON(0): RADEONSaveScreen(0)
>[210725.698] (II) RADEON(0): RADEONSaveScreen(1)
>[210742.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210742.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210743.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210743.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210743.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210743.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210743.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210743.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210743.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210743.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210743.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210743.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210743.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210743.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210743.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210743.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210743.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210743.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210743.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210743.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210743.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210743.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210743.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210743.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210743.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210743.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210744.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210744.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210744.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210744.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210744.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210744.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210744.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210744.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210744.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210744.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210744.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210744.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210744.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210744.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210744.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210745.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210745.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210745.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210745.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210745.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210745.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210745.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210745.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210745.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210745.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210745.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210745.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210745.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210746.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210746.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210746.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210746.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210746.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210746.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210746.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210746.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210746.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210746.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210746.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210746.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210746.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210746.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210747.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210747.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210747.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bad0]
>[210747.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bad0] width 1920 pitch 7680 (/4 1920)
>[210747.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210747.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210747.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210747.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210747.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210747.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210747.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bad0]
>[210748.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bad0] width 1920 pitch 7680 (/4 1920)
>[210748.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210748.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210748.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210748.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210748.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3d830]
>[210748.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3d830] width 1920 pitch 7680 (/4 1920)
>[210748.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210748.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210748.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210748.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210748.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d6b20]
>[210748.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d6b20] width 1920 pitch 7680 (/4 1920)
>[210748.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210748.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210748.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210748.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210748.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e785a0]
>[210748.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e785a0] width 1920 pitch 7680 (/4 1920)
>[210748.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240b9f0]
>[210748.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240b9f0] width 1920 pitch 7680 (/4 1920)
>[210748.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bad0]
>[210748.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bad0] width 1920 pitch 7680 (/4 1920)
>[211015.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c0c0]
>[211015.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c0c0] width 1920 pitch 7680 (/4 1920)
>[211015.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211015.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211015.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7c0c0]
>[211015.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7c0c0] width 1920 pitch 7680 (/4 1920)
>[211015.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211015.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211015.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211015.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211015.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211015.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211015.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211015.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211015.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211015.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211015.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211015.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211015.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211015.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211015.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211015.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211015.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211015.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211015.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211015.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211016.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211016.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211016.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211016.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211016.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211016.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211016.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211016.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211022.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211022.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211022.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211022.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211023.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211023.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211023.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211023.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211023.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dda6c0]
>[211023.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dda6c0] width 1920 pitch 7680 (/4 1920)
>[211023.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8d5d0]
>[211023.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8d5d0] width 1920 pitch 7680 (/4 1920)
>[211023.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211023.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211023.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211023.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211023.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211023.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211023.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211024.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211024.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211024.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211024.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211024.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211024.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211024.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211024.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211024.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211024.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211024.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211024.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211024.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211025.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[211025.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1920 pitch 7680 (/4 1920)
>[211025.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211025.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211025.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211025.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211025.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211025.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211025.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211025.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211025.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211025.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211025.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211025.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211025.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211025.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211025.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211025.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211025.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211025.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211029.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211029.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211029.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211029.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211030.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211030.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211030.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211030.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211030.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211030.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211030.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211030.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211030.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211030.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211030.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211030.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211030.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211030.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211030.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211030.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211030.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ab020]
>[211030.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ab020] width 1920 pitch 7680 (/4 1920)
>[211031.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211031.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211031.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211031.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211031.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211031.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211031.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211031.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211031.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211031.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211031.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211031.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211031.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211031.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211031.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211031.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211032.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211032.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211032.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211032.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211032.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211032.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211032.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211032.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211032.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211032.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211032.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211032.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211032.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211032.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5f860]
>[211032.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5f860] width 1920 pitch 7680 (/4 1920)
>[211032.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211032.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211033.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211033.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211033.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50da0]
>[211033.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50da0] width 1920 pitch 7680 (/4 1920)
>[211033.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211033.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211033.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211033.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211033.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211033.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211033.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211033.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211033.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211033.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211033.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211033.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211033.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211033.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211033.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211034.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211034.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40516a0]
>[211034.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40516a0] width 1920 pitch 7680 (/4 1920)
>[211034.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211034.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211034.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211034.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211034.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211034.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211034.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211034.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211034.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211034.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211034.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211035.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211035.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211035.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211035.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211035.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211035.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211035.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211035.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211035.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211035.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211035.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211035.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211035.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211035.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211035.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211035.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211035.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[211035.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1920 pitch 7680 (/4 1920)
>[211035.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ad0]
>[211035.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ad0] width 1920 pitch 7680 (/4 1920)
>[211550.349] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[211550.349] (II) RADEON(0): Using hsync ranges from config file
>[211550.349] (II) RADEON(0): Using vrefresh ranges from config file
>[211550.349] (II) RADEON(0): Printing DDC gathered Modelines:
>[211550.349] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[211550.349] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[211550.349] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[211550.349] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[211550.349] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[211550.349] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[211550.349] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[211550.349] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[211550.349] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[211550.349] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[211550.349] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[211640.744] (II) RADEON(0): RADEONSaveScreen(2)
>[211640.744] (II) RADEON(0): RADEONSaveScreen(0)
>[214355.032] (II) RADEON(0): RADEONSaveScreen(1)
>[214369.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214369.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1920 pitch 7680 (/4 1920)
>[214430.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214430.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1920 pitch 7680 (/4 1920)
>[214430.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44b40]
>[214430.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44b40] width 1920 pitch 7680 (/4 1920)
>[214432.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214432.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214432.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214432.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214432.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214433.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214433.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214433.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f147c0]
>[214433.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f147c0] width 1920 pitch 7680 (/4 1920)
>[214433.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214433.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1920 pitch 7680 (/4 1920)
>[214433.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021670]
>[214433.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021670] width 1920 pitch 7680 (/4 1920)
>[214433.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6b60]
>[214433.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6b60] width 1920 pitch 7680 (/4 1920)
>[214433.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021670]
>[214433.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021670] width 1920 pitch 7680 (/4 1920)
>[214433.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6b60]
>[214433.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6b60] width 1920 pitch 7680 (/4 1920)
>[214433.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021670]
>[214433.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021670] width 1920 pitch 7680 (/4 1920)
>[214433.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6b60]
>[214433.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6b60] width 1920 pitch 7680 (/4 1920)
>[214433.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4021670]
>[214433.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4021670] width 1920 pitch 7680 (/4 1920)
>[214433.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca6b60]
>[214433.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca6b60] width 1920 pitch 7680 (/4 1920)
>[214434.685] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[214434.685] (II) RADEON(0): Using hsync ranges from config file
>[214434.685] (II) RADEON(0): Using vrefresh ranges from config file
>[214434.685] (II) RADEON(0): Printing DDC gathered Modelines:
>[214434.685] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[214434.685] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[214434.685] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[214434.685] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[214434.685] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[214434.685] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[214434.685] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[214434.685] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[214434.685] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[214434.685] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[214434.685] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[214434.685] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[214434.686] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[214437.290] (II) AIGLX: Suspending AIGLX clients for VT switch
>[214437.290] (II) RADEON(0): RADEONLeaveVT_KMS
>[214437.290] (II) RADEON(0): Ok, leaving now...
>[214442.145] (II) AIGLX: Resuming AIGLX clients after VT switch
>[214442.145] (II) RADEON(0): RADEONEnterVT_KMS
>[214443.043] (II) RADEON(0): RADEONSaveScreen(2)
>[214443.044] (**) Option "Device" "/dev/input/event5"
>[214443.044] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[214443.044] (EE) evdev: VISENTA V1 : Unable to open evdev device "/dev/input/event7".
>[214443.045] [dix] couldn't enable device 9
>[214443.045] (EE) evdev: VISENTA V1 : Unable to open evdev device "/dev/input/event6".
>[214443.045] [dix] couldn't enable device 10
>[214443.045] (EE) evdev: USB USB Keykoard: Unable to open evdev device "/dev/input/event18".
>[214443.045] [dix] couldn't enable device 11
>[214443.045] (EE) evdev: USB USB Keykoard: Unable to open evdev device "/dev/input/event8".
>[214443.045] [dix] couldn't enable device 17
>[214443.045] (EE) evdev: Logitech USB Optical Mouse: Unable to open evdev device "/dev/input/event19".
>[214443.045] [dix] couldn't enable device 18
>[214443.060] (II) config/udev: removing device USB USB Keykoard
>[214443.060] (II) evdev: USB USB Keykoard: Close
>[214443.060] (II) UnloadModule: "evdev"
>[214443.061] (II) config/udev: removing device USB USB Keykoard
>[214443.061] (II) evdev: USB USB Keykoard: Close
>[214443.061] (II) UnloadModule: "evdev"
>[214443.067] (II) config/udev: removing device Logitech USB Optical Mouse
>[214443.068] (II) evdev: Logitech USB Optical Mouse: Close
>[214443.068] (II) UnloadModule: "evdev"
>[214443.077] (II) config/udev: removing device VISENTA V1 
>[214443.077] (II) evdev: VISENTA V1 : Close
>[214443.077] (II) UnloadModule: "evdev"
>[214443.078] (II) config/udev: removing device VISENTA V1 
>[214443.078] (II) evdev: VISENTA V1 : Close
>[214443.078] (II) UnloadModule: "evdev"
>[214443.293] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[214443.293] (II) RADEON(0): VRAM usage limit set to 223324K
>[214444.166] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[214444.166] (II) RADEON(0): VRAM usage limit set to 223324K
>[214448.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214448.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214462.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214462.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214463.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214463.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214464.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214464.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214464.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214464.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214464.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214464.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214464.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214464.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214464.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214464.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214464.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214464.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214464.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214464.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214464.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214464.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214464.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214464.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214464.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214464.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214465.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214465.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214465.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214465.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214466.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214466.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214466.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214466.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214467.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214467.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214467.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214467.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214467.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214467.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214467.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214467.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214467.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214467.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214467.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214467.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214467.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214467.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214467.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214467.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214467.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214467.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214467.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214467.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214467.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214467.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214467.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214467.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214467.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214467.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214467.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214467.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214467.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214467.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214467.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214467.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214467.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214467.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214467.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214467.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214467.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214468.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214468.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214468.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214468.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214468.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214468.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214468.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214469.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214469.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214469.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214469.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214469.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214469.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214469.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269d4f0]
>[214469.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269d4f0] width 1600 pitch 6400 (/4 1600)
>[214469.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214469.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214469.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269d4f0]
>[214469.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269d4f0] width 1600 pitch 6400 (/4 1600)
>[214469.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a42a90]
>[214469.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a42a90] width 1600 pitch 6400 (/4 1600)
>[214469.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214469.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214469.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214469.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214470.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214470.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214470.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214470.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214470.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214470.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214470.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214470.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214470.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214470.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214470.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214470.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214470.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214470.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214470.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214470.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214470.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214472.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269d4f0]
>[214472.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269d4f0] width 1600 pitch 6400 (/4 1600)
>[214472.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44810]
>[214472.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44810] width 1600 pitch 6400 (/4 1600)
>[214472.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269d4f0]
>[214472.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269d4f0] width 1600 pitch 6400 (/4 1600)
>[214472.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214472.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214472.959] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x269d4f0]
>[214472.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x269d4f0] width 1600 pitch 6400 (/4 1600)
>[214472.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214472.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214473.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9fa0]
>[214473.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9fa0] width 1600 pitch 6400 (/4 1600)
>[214473.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214473.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214474.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214474.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214474.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9fa0]
>[214474.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9fa0] width 1600 pitch 6400 (/4 1600)
>[214474.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214474.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214474.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9fa0]
>[214474.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9fa0] width 1600 pitch 6400 (/4 1600)
>[214474.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214474.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214474.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9fa0]
>[214474.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9fa0] width 1600 pitch 6400 (/4 1600)
>[214474.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214474.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214474.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214474.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214474.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214474.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214475.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240bdf0]
>[214475.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240bdf0] width 1600 pitch 6400 (/4 1600)
>[214475.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214475.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214475.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214475.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214475.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9bd30]
>[214475.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9bd30] width 1600 pitch 6400 (/4 1600)
>[214475.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214475.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214475.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214475.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214475.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214475.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214475.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214476.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214476.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea58b0]
>[214476.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea58b0] width 1600 pitch 6400 (/4 1600)
>[214476.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214476.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214477.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214477.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214477.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214477.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214477.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214477.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214477.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214477.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214477.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214477.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214477.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214477.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214477.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214477.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214477.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214477.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214477.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214477.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214478.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214478.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214478.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214478.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214478.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214478.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214478.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214478.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214478.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214478.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214478.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214478.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214478.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214478.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214478.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4e570]
>[214479.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4e570] width 1600 pitch 6400 (/4 1600)
>[214479.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214479.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214479.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[214479.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1600 pitch 6400 (/4 1600)
>[214479.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214479.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214479.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214479.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214479.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b42b20]
>[214479.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b42b20] width 1600 pitch 6400 (/4 1600)
>[214479.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac77a0]
>[214479.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac77a0] width 1600 pitch 6400 (/4 1600)
>[214479.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214479.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214479.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a42a90]
>[214479.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a42a90] width 1600 pitch 6400 (/4 1600)
>[214479.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3100]
>[214479.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3100] width 1600 pitch 6400 (/4 1600)
>[214479.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a42a90]
>[214479.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a42a90] width 1600 pitch 6400 (/4 1600)
>[214602.914] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[214602.914] (II) RADEON(0): Printing DDC gathered Modelines:
>[214602.914] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[214602.914] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[214604.548] (II) AIGLX: Suspending AIGLX clients for VT switch
>[214604.548] (II) RADEON(0): RADEONLeaveVT_KMS
>[214604.548] (II) RADEON(0): Ok, leaving now...
>[214608.953] (II) AIGLX: Resuming AIGLX clients after VT switch
>[214608.953] (II) RADEON(0): RADEONEnterVT_KMS
>[214608.954] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[214608.954] (II) RADEON(0): Printing DDC gathered Modelines:
>[214608.954] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[214608.954] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[214608.990] (II) RADEON(0): RADEONSaveScreen(2)
>[214608.991] (**) Option "Device" "/dev/input/event5"
>[214608.991] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[214616.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214616.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214622.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214622.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214622.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214622.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214622.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214622.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214622.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214622.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214622.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214622.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214622.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214622.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214622.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214622.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214622.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[214622.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[214622.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264f070]
>[214622.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264f070] width 1600 pitch 6400 (/4 1600)
>[214623.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214623.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be41d0]
>[214623.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be41d0] width 1600 pitch 6400 (/4 1600)
>[214623.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214623.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be41d0]
>[214623.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be41d0] width 1600 pitch 6400 (/4 1600)
>[214623.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214623.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be41d0]
>[214623.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be41d0] width 1600 pitch 6400 (/4 1600)
>[214623.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214623.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be41d0]
>[214623.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be41d0] width 1600 pitch 6400 (/4 1600)
>[214623.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214623.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be41d0]
>[214623.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be41d0] width 1600 pitch 6400 (/4 1600)
>[214623.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214623.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214625.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40256c0]
>[214625.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40256c0] width 1600 pitch 6400 (/4 1600)
>[214625.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214625.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214625.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a42a90]
>[214625.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a42a90] width 1600 pitch 6400 (/4 1600)
>[214625.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214625.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214625.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a42a90]
>[214625.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a42a90] width 1600 pitch 6400 (/4 1600)
>[214625.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214625.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214625.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bcd0]
>[214625.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bcd0] width 1600 pitch 6400 (/4 1600)
>[214625.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214625.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214625.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bcd0]
>[214625.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bcd0] width 1600 pitch 6400 (/4 1600)
>[214625.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[214625.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[214697.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e13310]
>[214697.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e13310] width 1600 pitch 6400 (/4 1600)
>[214697.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e13310]
>[214697.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e13310] width 1600 pitch 6400 (/4 1600)
>[214698.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e13310]
>[214698.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e13310] width 1600 pitch 6400 (/4 1600)
>[214701.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc09f0]
>[214701.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc09f0] width 1600 pitch 6400 (/4 1600)
>[214701.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efb3b0]
>[214701.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efb3b0] width 1600 pitch 6400 (/4 1600)
>[214701.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214701.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214701.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[214701.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1600 pitch 6400 (/4 1600)
>[214701.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214701.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214701.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[214701.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1600 pitch 6400 (/4 1600)
>[214701.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214701.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214701.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[214701.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1600 pitch 6400 (/4 1600)
>[214701.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214701.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214701.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522e5a0]
>[214701.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522e5a0] width 1600 pitch 6400 (/4 1600)
>[214701.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214701.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214787.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[214787.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[214787.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214787.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214788.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f115d0]
>[214788.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f115d0] width 1600 pitch 6400 (/4 1600)
>[214795.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051230]
>[214795.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051230] width 1600 pitch 6400 (/4 1600)
>[214795.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb3ec0]
>[214795.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb3ec0] width 1600 pitch 6400 (/4 1600)
>[214795.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264bcd0]
>[214795.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264bcd0] width 1600 pitch 6400 (/4 1600)
>[214796.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e898b0]
>[214796.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e898b0] width 1600 pitch 6400 (/4 1600)
>[214796.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a49f80]
>[214796.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a49f80] width 1600 pitch 6400 (/4 1600)
>[214796.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[214796.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[214797.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc780]
>[214797.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc780] width 1600 pitch 6400 (/4 1600)
>[214798.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[214798.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[214798.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[214798.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[214799.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[214799.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[214799.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e13310]
>[214799.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e13310] width 1600 pitch 6400 (/4 1600)
>[214801.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[214801.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1600 pitch 6400 (/4 1600)
>[214801.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[214801.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[214801.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381f800]
>[214801.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381f800] width 1600 pitch 6400 (/4 1600)
>[214802.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a35cc0]
>[214802.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a35cc0] width 1600 pitch 6400 (/4 1600)
>[214802.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9b4e0]
>[214802.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9b4e0] width 1600 pitch 6400 (/4 1600)
>[214802.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[214802.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[214803.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aa3fc0]
>[214803.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aa3fc0] width 1600 pitch 6400 (/4 1600)
>[214959.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[214959.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[214959.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[214959.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[214959.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214959.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214959.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcc8d0]
>[214959.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcc8d0] width 1600 pitch 6400 (/4 1600)
>[214960.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f21830]
>[214960.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f21830] width 1600 pitch 6400 (/4 1600)
>[214960.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb7ed0]
>[214960.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb7ed0] width 1600 pitch 6400 (/4 1600)
>[214960.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214960.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214960.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214960.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214960.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214961.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214961.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214961.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214961.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214961.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214961.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214961.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214961.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214961.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214961.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214961.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214961.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214961.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214961.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214961.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214961.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214961.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214961.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214961.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x286df00]
>[214961.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x286df00] width 1600 pitch 6400 (/4 1600)
>[214962.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a940]
>[214962.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a940] width 1600 pitch 6400 (/4 1600)
>[214962.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a000]
>[214962.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a000] width 1600 pitch 6400 (/4 1600)
>[214962.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05290]
>[214962.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05290] width 1600 pitch 6400 (/4 1600)
>[214962.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a940]
>[214962.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a940] width 1600 pitch 6400 (/4 1600)
>[214963.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e05290]
>[214963.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e05290] width 1600 pitch 6400 (/4 1600)
>[214965.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b1a0]
>[214965.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b1a0] width 1600 pitch 6400 (/4 1600)
>[214965.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0c70]
>[214965.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0c70] width 1600 pitch 6400 (/4 1600)
>[214965.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a652b0]
>[214965.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a652b0] width 1600 pitch 6400 (/4 1600)
>[214965.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0c70]
>[214965.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0c70] width 1600 pitch 6400 (/4 1600)
>[214965.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2624630]
>[214965.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2624630] width 1600 pitch 6400 (/4 1600)
>[214965.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a6e0]
>[214965.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a6e0] width 1600 pitch 6400 (/4 1600)
>[214965.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3cde0]
>[214965.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3cde0] width 1600 pitch 6400 (/4 1600)
>[214965.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a6e0]
>[214965.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a6e0] width 1600 pitch 6400 (/4 1600)
>[214965.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3cde0]
>[214965.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3cde0] width 1600 pitch 6400 (/4 1600)
>[214965.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a6e0]
>[214965.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a6e0] width 1600 pitch 6400 (/4 1600)
>[214965.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b700]
>[214965.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b700] width 1600 pitch 6400 (/4 1600)
>[214965.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048e70]
>[214965.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048e70] width 1600 pitch 6400 (/4 1600)
>[214965.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b700]
>[214965.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b700] width 1600 pitch 6400 (/4 1600)
>[214965.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048e70]
>[214965.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048e70] width 1600 pitch 6400 (/4 1600)
>[214965.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b700]
>[214965.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b700] width 1600 pitch 6400 (/4 1600)
>[214965.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048e70]
>[214965.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048e70] width 1600 pitch 6400 (/4 1600)
>[214965.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b700]
>[214965.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b700] width 1600 pitch 6400 (/4 1600)
>[214965.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048e70]
>[214965.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048e70] width 1600 pitch 6400 (/4 1600)
>[214986.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394db10]
>[214986.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394db10] width 1600 pitch 6400 (/4 1600)
>[214986.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0970]
>[214986.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0970] width 1600 pitch 6400 (/4 1600)
>[214998.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69b0130]
>[214998.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69b0130] width 1600 pitch 6400 (/4 1600)
>[214998.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d8d0]
>[214998.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d8d0] width 1600 pitch 6400 (/4 1600)
>[215006.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb1b50]
>[215006.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb1b50] width 1600 pitch 6400 (/4 1600)
>[215012.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3886c60]
>[215012.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3886c60] width 1600 pitch 6400 (/4 1600)
>[215022.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ba3c0]
>[215022.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ba3c0] width 1600 pitch 6400 (/4 1600)
>[215033.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ae070]
>[215033.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ae070] width 1600 pitch 6400 (/4 1600)
>[215107.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c35e30]
>[215107.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c35e30] width 1600 pitch 6400 (/4 1600)
>[215166.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ba040]
>[215166.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ba040] width 1600 pitch 6400 (/4 1600)
>[215166.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c36590]
>[215166.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c36590] width 1600 pitch 6400 (/4 1600)
>[215166.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[215166.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[215166.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21ff0]
>[215166.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21ff0] width 1600 pitch 6400 (/4 1600)
>[215167.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2669880]
>[215167.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2669880] width 1600 pitch 6400 (/4 1600)
>[215167.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[215167.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[215168.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28718c0]
>[215168.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28718c0] width 1600 pitch 6400 (/4 1600)
>[215184.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f70290]
>[215184.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f70290] width 1600 pitch 6400 (/4 1600)
>[215184.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c36590]
>[215184.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c36590] width 1600 pitch 6400 (/4 1600)
>[215184.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f787e0]
>[215185.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f787e0] width 1600 pitch 6400 (/4 1600)
>[215185.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265cca0]
>[215185.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265cca0] width 1600 pitch 6400 (/4 1600)
>[215185.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df13e0]
>[215185.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df13e0] width 1600 pitch 6400 (/4 1600)
>[215186.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381f800]
>[215186.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381f800] width 1600 pitch 6400 (/4 1600)
>[215190.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f8580]
>[215190.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f8580] width 1600 pitch 6400 (/4 1600)
>[215190.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[215190.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[215191.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0d5c0]
>[215191.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0d5c0] width 1600 pitch 6400 (/4 1600)
>[215199.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f8580]
>[215199.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f8580] width 1600 pitch 6400 (/4 1600)
>[215199.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215199.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215199.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b21ff0]
>[215199.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b21ff0] width 1600 pitch 6400 (/4 1600)
>[215199.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215199.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215199.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6b70]
>[215199.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6b70] width 1600 pitch 6400 (/4 1600)
>[215199.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215199.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215200.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efe360]
>[215200.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efe360] width 1600 pitch 6400 (/4 1600)
>[215200.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f8580]
>[215200.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f8580] width 1600 pitch 6400 (/4 1600)
>[215200.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[215200.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[215204.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[215204.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[215207.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[215207.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[215207.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c36590]
>[215207.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c36590] width 1600 pitch 6400 (/4 1600)
>[215207.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[215207.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[215207.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40256c0]
>[215207.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40256c0] width 1600 pitch 6400 (/4 1600)
>[215207.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381f800]
>[215207.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381f800] width 1600 pitch 6400 (/4 1600)
>[215208.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a365f0]
>[215208.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a365f0] width 1600 pitch 6400 (/4 1600)
>[215212.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699dcc0]
>[215213.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699dcc0] width 1600 pitch 6400 (/4 1600)
>[215213.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40256c0]
>[215213.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40256c0] width 1600 pitch 6400 (/4 1600)
>[215213.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x381f800]
>[215213.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x381f800] width 1600 pitch 6400 (/4 1600)
>[215213.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38877f0]
>[215213.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38877f0] width 1600 pitch 6400 (/4 1600)
>[215213.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[215213.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[215213.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[215213.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[215213.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a365f0]
>[215213.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a365f0] width 1600 pitch 6400 (/4 1600)
>[215219.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[215219.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[215219.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac8e20]
>[215219.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac8e20] width 1600 pitch 6400 (/4 1600)
>[215220.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26510b0]
>[215220.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26510b0] width 1600 pitch 6400 (/4 1600)
>[215220.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[215221.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[215221.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26510b0]
>[215221.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26510b0] width 1600 pitch 6400 (/4 1600)
>[215221.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[215221.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[215222.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[215222.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[215222.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[215222.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[215222.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a365f0]
>[215222.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a365f0] width 1600 pitch 6400 (/4 1600)
>[215222.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[215222.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[215232.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[215232.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[215232.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5006140]
>[215232.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5006140] width 1600 pitch 6400 (/4 1600)
>[215232.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b53530]
>[215232.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b53530] width 1600 pitch 6400 (/4 1600)
>[215234.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efe360]
>[215234.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efe360] width 1600 pitch 6400 (/4 1600)
>[215245.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[215245.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[215245.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24b80]
>[215245.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24b80] width 1600 pitch 6400 (/4 1600)
>[215245.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[215245.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[215251.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[215251.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[215251.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5006140]
>[215252.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5006140] width 1600 pitch 6400 (/4 1600)
>[215252.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[215252.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[215323.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[215324.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[215336.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a6e0]
>[215336.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a6e0] width 1600 pitch 6400 (/4 1600)
>[215336.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f787e0]
>[215336.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f787e0] width 1600 pitch 6400 (/4 1600)
>[215336.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0d5c0]
>[215336.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0d5c0] width 1600 pitch 6400 (/4 1600)
>[215336.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3972b00]
>[215336.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3972b00] width 1600 pitch 6400 (/4 1600)
>[215337.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[215337.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[215337.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3b00]
>[215337.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3b00] width 1600 pitch 6400 (/4 1600)
>[215354.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215354.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215354.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0d5c0]
>[215354.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0d5c0] width 1600 pitch 6400 (/4 1600)
>[215426.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f787e0]
>[215426.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f787e0] width 1600 pitch 6400 (/4 1600)
>[215426.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e24b80]
>[215426.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e24b80] width 1600 pitch 6400 (/4 1600)
>[215426.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f787e0]
>[215426.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f787e0] width 1600 pitch 6400 (/4 1600)
>[215451.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a36330]
>[215451.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a36330] width 1600 pitch 6400 (/4 1600)
>[215451.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[215451.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[215452.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adc660]
>[215452.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adc660] width 1600 pitch 6400 (/4 1600)
>[215452.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[215452.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[215452.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[215452.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[215453.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df13e0]
>[215453.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df13e0] width 1600 pitch 6400 (/4 1600)
>[215453.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c24e60]
>[215453.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c24e60] width 1600 pitch 6400 (/4 1600)
>[215453.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[215453.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[215454.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699dcc0]
>[215454.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699dcc0] width 1600 pitch 6400 (/4 1600)
>[215455.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40256c0]
>[215455.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40256c0] width 1600 pitch 6400 (/4 1600)
>[215463.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[215463.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[215463.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f3b00]
>[215463.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f3b00] width 1600 pitch 6400 (/4 1600)
>[215464.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1c630]
>[215464.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1c630] width 1600 pitch 6400 (/4 1600)
>[215464.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce2a0]
>[215464.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce2a0] width 1600 pitch 6400 (/4 1600)
>[215464.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a6e0]
>[215464.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a6e0] width 1600 pitch 6400 (/4 1600)
>[215465.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df13e0]
>[215465.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df13e0] width 1600 pitch 6400 (/4 1600)
>[215465.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0d5c0]
>[215465.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0d5c0] width 1600 pitch 6400 (/4 1600)
>[215465.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9c4f0]
>[215465.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9c4f0] width 1600 pitch 6400 (/4 1600)
>[215466.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ce2a0]
>[215466.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ce2a0] width 1600 pitch 6400 (/4 1600)
>[215467.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb6b70]
>[215467.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb6b70] width 1600 pitch 6400 (/4 1600)
>[215511.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215511.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215511.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[215511.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[215511.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[215511.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[215597.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2631b30]
>[215597.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2631b30] width 1600 pitch 6400 (/4 1600)
>[215644.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ae7a0]
>[215644.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ae7a0] width 1600 pitch 6400 (/4 1600)
>[215697.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264d340]
>[215697.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264d340] width 1600 pitch 6400 (/4 1600)
>[215857.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26510b0]
>[215857.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26510b0] width 1600 pitch 6400 (/4 1600)
>[215857.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[215857.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1600 pitch 6400 (/4 1600)
>[215857.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[215857.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1600 pitch 6400 (/4 1600)
>[215857.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26510b0]
>[215857.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26510b0] width 1600 pitch 6400 (/4 1600)
>[215858.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26510b0]
>[215858.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26510b0] width 1600 pitch 6400 (/4 1600)
>[215858.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b6e0]
>[215858.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b6e0] width 1600 pitch 6400 (/4 1600)
>[215859.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b6e0]
>[215859.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b6e0] width 1600 pitch 6400 (/4 1600)
>[215859.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[215859.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1600 pitch 6400 (/4 1600)
>[215860.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5b6e0]
>[215860.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5b6e0] width 1600 pitch 6400 (/4 1600)
>[216019.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[216019.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[216019.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27db450]
>[216019.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27db450] width 1600 pitch 6400 (/4 1600)
>[216020.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6ce50]
>[216020.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6ce50] width 1600 pitch 6400 (/4 1600)
>[216020.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[216020.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[216020.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3db60]
>[216020.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3db60] width 1600 pitch 6400 (/4 1600)
>[216020.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3db60]
>[216020.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3db60] width 1600 pitch 6400 (/4 1600)
>[216021.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3db60]
>[216021.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3db60] width 1600 pitch 6400 (/4 1600)
>[216021.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f87d0]
>[216021.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f87d0] width 1600 pitch 6400 (/4 1600)
>[216021.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[216021.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[216022.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811a30]
>[216022.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811a30] width 1600 pitch 6400 (/4 1600)
>[216022.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3018fb0]
>[216022.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3018fb0] width 1600 pitch 6400 (/4 1600)
>[216023.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[216023.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[216024.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216024.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216044.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4be0]
>[216044.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4be0] width 1600 pitch 6400 (/4 1600)
>[216044.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5fe0]
>[216044.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5fe0] width 1600 pitch 6400 (/4 1600)
>[216045.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[216045.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[216045.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27db450]
>[216045.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27db450] width 1600 pitch 6400 (/4 1600)
>[216045.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[216045.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[216046.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea3e0]
>[216046.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea3e0] width 1600 pitch 6400 (/4 1600)
>[216046.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5100]
>[216046.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5100] width 1600 pitch 6400 (/4 1600)
>[216046.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a760]
>[216046.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a760] width 1600 pitch 6400 (/4 1600)
>[216049.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcbb30]
>[216049.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcbb30] width 1600 pitch 6400 (/4 1600)
>[216177.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[216177.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[216177.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[216177.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[216178.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[216178.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[216178.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5fe0]
>[216178.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5fe0] width 1600 pitch 6400 (/4 1600)
>[216179.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3882f10]
>[216179.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3882f10] width 1600 pitch 6400 (/4 1600)
>[216179.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[216179.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[216179.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5fe0]
>[216179.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5fe0] width 1600 pitch 6400 (/4 1600)
>[216180.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3882f10]
>[216180.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3882f10] width 1600 pitch 6400 (/4 1600)
>[216182.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc5fe0]
>[216182.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc5fe0] width 1600 pitch 6400 (/4 1600)
>[216182.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24010]
>[216182.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24010] width 1600 pitch 6400 (/4 1600)
>[216183.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[216183.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[216183.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[216183.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[216184.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a650]
>[216184.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a650] width 1600 pitch 6400 (/4 1600)
>[216184.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069bb0]
>[216184.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069bb0] width 1600 pitch 6400 (/4 1600)
>[216188.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d5b390]
>[216188.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d5b390] width 1600 pitch 6400 (/4 1600)
>[216221.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ed330]
>[216222.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ed330] width 1600 pitch 6400 (/4 1600)
>[216222.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[216222.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[216222.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[216222.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[216223.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216223.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216223.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[216223.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[216237.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fe2340]
>[216237.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fe2340] width 1600 pitch 6400 (/4 1600)
>[216241.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd6db0]
>[216241.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd6db0] width 1600 pitch 6400 (/4 1600)
>[216241.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216241.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216241.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3932c00]
>[216241.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3932c00] width 1600 pitch 6400 (/4 1600)
>[216241.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216241.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216261.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[216261.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[216277.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aac2b0]
>[216277.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aac2b0] width 1600 pitch 6400 (/4 1600)
>[216277.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5c2a0]
>[216277.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5c2a0] width 1600 pitch 6400 (/4 1600)
>[216277.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[216277.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[216277.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5c2a0]
>[216277.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5c2a0] width 1600 pitch 6400 (/4 1600)
>[216277.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[216277.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[216277.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5c2a0]
>[216277.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5c2a0] width 1600 pitch 6400 (/4 1600)
>[216277.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[216277.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[216277.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5c2a0]
>[216277.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5c2a0] width 1600 pitch 6400 (/4 1600)
>[216278.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e45b0]
>[216278.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e45b0] width 1600 pitch 6400 (/4 1600)
>[216278.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fa9480]
>[216278.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fa9480] width 1600 pitch 6400 (/4 1600)
>[216278.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81da0]
>[216278.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81da0] width 1600 pitch 6400 (/4 1600)
>[216278.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3932cc0]
>[216278.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3932cc0] width 1600 pitch 6400 (/4 1600)
>[216278.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e81da0]
>[216278.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e81da0] width 1600 pitch 6400 (/4 1600)
>[216310.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fa9010]
>[216310.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fa9010] width 1600 pitch 6400 (/4 1600)
>[216313.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[216313.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[216313.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2834be0]
>[216313.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2834be0] width 1600 pitch 6400 (/4 1600)
>[216313.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5fa9480]
>[216313.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5fa9480] width 1600 pitch 6400 (/4 1600)
>[216314.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5ea50]
>[216314.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5ea50] width 1600 pitch 6400 (/4 1600)
>[216314.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3e0b0]
>[216314.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3e0b0] width 1600 pitch 6400 (/4 1600)
>[216316.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aad490]
>[216316.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aad490] width 1600 pitch 6400 (/4 1600)
>[216316.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3934ae0]
>[216316.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3934ae0] width 1600 pitch 6400 (/4 1600)
>[216316.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fd49b0]
>[216316.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fd49b0] width 1600 pitch 6400 (/4 1600)
>[216316.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3934ae0]
>[216316.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3934ae0] width 1600 pitch 6400 (/4 1600)
>[216316.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[216316.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1600 pitch 6400 (/4 1600)
>[216317.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9e820]
>[216317.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9e820] width 1600 pitch 6400 (/4 1600)
>[216317.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e45b0]
>[216317.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e45b0] width 1600 pitch 6400 (/4 1600)
>[216317.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[216317.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1600 pitch 6400 (/4 1600)
>[216318.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216318.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216367.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[216367.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1600 pitch 6400 (/4 1600)
>[216367.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[216367.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[216368.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf0990]
>[216368.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf0990] width 1600 pitch 6400 (/4 1600)
>[216368.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[216368.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[216368.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3890fb0]
>[216368.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3890fb0] width 1600 pitch 6400 (/4 1600)
>[216368.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[216369.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[216369.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[216369.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[216369.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ed330]
>[216369.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ed330] width 1600 pitch 6400 (/4 1600)
>[216370.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3890fb0]
>[216370.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3890fb0] width 1600 pitch 6400 (/4 1600)
>[216372.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[216372.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[216372.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9c4f0]
>[216372.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9c4f0] width 1600 pitch 6400 (/4 1600)
>[216373.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a5100]
>[216373.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a5100] width 1600 pitch 6400 (/4 1600)
>[216375.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb8590]
>[216375.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb8590] width 1600 pitch 6400 (/4 1600)
>[216380.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8140]
>[216380.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8140] width 1600 pitch 6400 (/4 1600)
>[216380.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[216380.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[216380.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fcc2c0]
>[216381.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fcc2c0] width 1600 pitch 6400 (/4 1600)
>[216381.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d900f0]
>[216381.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d900f0] width 1600 pitch 6400 (/4 1600)
>[216381.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d900f0]
>[216381.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d900f0] width 1600 pitch 6400 (/4 1600)
>[216384.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec43c0]
>[216384.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec43c0] width 1600 pitch 6400 (/4 1600)
>[216384.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d900f0]
>[216384.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d900f0] width 1600 pitch 6400 (/4 1600)
>[216385.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cab6d0]
>[216385.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cab6d0] width 1600 pitch 6400 (/4 1600)
>[216385.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3680]
>[216385.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3680] width 1600 pitch 6400 (/4 1600)
>[216522.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cacd0]
>[216522.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cacd0] width 1600 pitch 6400 (/4 1600)
>[216580.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[216580.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[216580.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faee90]
>[216580.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faee90] width 1600 pitch 6400 (/4 1600)
>[216581.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[216581.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1600 pitch 6400 (/4 1600)
>[216581.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aad490]
>[216581.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aad490] width 1600 pitch 6400 (/4 1600)
>[216582.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cfe3b0]
>[216582.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cfe3b0] width 1600 pitch 6400 (/4 1600)
>[216587.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df71d0]
>[216587.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df71d0] width 1600 pitch 6400 (/4 1600)
>[216647.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa2d60]
>[216647.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa2d60] width 1600 pitch 6400 (/4 1600)
>[216647.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a9ca0]
>[216648.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a9ca0] width 1600 pitch 6400 (/4 1600)
>[216648.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3882f10]
>[216648.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3882f10] width 1600 pitch 6400 (/4 1600)
>[216648.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e45b0]
>[216648.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e45b0] width 1600 pitch 6400 (/4 1600)
>[216670.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[216670.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[216670.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71bb0]
>[216670.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71bb0] width 1600 pitch 6400 (/4 1600)
>[216671.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[216671.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[216671.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[216671.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[216671.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ca0d0]
>[216671.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ca0d0] width 1600 pitch 6400 (/4 1600)
>[216671.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[216671.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[216671.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[216672.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[216672.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[216672.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[216672.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[216672.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[216672.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[216672.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[216672.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[216672.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[216672.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[216672.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[216672.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[216672.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[216677.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59d30]
>[216677.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59d30] width 1600 pitch 6400 (/4 1600)
>[216713.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8100]
>[216713.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8100] width 1600 pitch 6400 (/4 1600)
>[216719.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[216719.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[216719.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269310]
>[216720.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269310] width 1600 pitch 6400 (/4 1600)
>[216720.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[216720.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[216720.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef8100]
>[216720.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef8100] width 1600 pitch 6400 (/4 1600)
>[216790.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a26b90]
>[216790.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a26b90] width 1600 pitch 6400 (/4 1600)
>[216872.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b20]
>[216872.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b20] width 1600 pitch 6400 (/4 1600)
>[216872.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[216872.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[216906.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5a780]
>[216906.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5a780] width 1600 pitch 6400 (/4 1600)
>[216922.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc3ff0]
>[216922.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc3ff0] width 1600 pitch 6400 (/4 1600)
>[216989.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be740]
>[216990.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be740] width 1600 pitch 6400 (/4 1600)
>[217003.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3881930]
>[217003.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3881930] width 1600 pitch 6400 (/4 1600)
>[217004.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3f60]
>[217004.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3f60] width 1600 pitch 6400 (/4 1600)
>[217004.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df3a0]
>[217004.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df3a0] width 1600 pitch 6400 (/4 1600)
>[217004.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd3f60]
>[217004.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd3f60] width 1600 pitch 6400 (/4 1600)
>[217004.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50df3a0]
>[217005.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50df3a0] width 1600 pitch 6400 (/4 1600)
>[217054.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eff4a0]
>[217054.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eff4a0] width 1600 pitch 6400 (/4 1600)
>[217221.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e65050]
>[217221.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e65050] width 1600 pitch 6400 (/4 1600)
>[217221.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29140]
>[217221.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29140] width 1600 pitch 6400 (/4 1600)
>[217222.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[217222.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[217223.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4be0]
>[217223.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4be0] width 1600 pitch 6400 (/4 1600)
>[217223.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4020810]
>[217223.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4020810] width 1600 pitch 6400 (/4 1600)
>[217224.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[217224.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[217224.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f13b40]
>[217224.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f13b40] width 1600 pitch 6400 (/4 1600)
>[217224.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[217224.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1600 pitch 6400 (/4 1600)
>[217339.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db5910]
>[217339.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db5910] width 1600 pitch 6400 (/4 1600)
>[217339.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db5910]
>[217339.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db5910] width 1600 pitch 6400 (/4 1600)
>[217340.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[217340.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1600 pitch 6400 (/4 1600)
>[217350.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def160]
>[217350.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def160] width 1600 pitch 6400 (/4 1600)
>[217350.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[217351.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[217351.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9c4f0]
>[217351.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9c4f0] width 1600 pitch 6400 (/4 1600)
>[217351.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[217351.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[217351.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[217351.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[217354.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5053c30]
>[217354.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5053c30] width 1600 pitch 6400 (/4 1600)
>[217354.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3db60]
>[217354.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3db60] width 1600 pitch 6400 (/4 1600)
>[217354.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a9ca0]
>[217354.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a9ca0] width 1600 pitch 6400 (/4 1600)
>[217355.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b560]
>[217355.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b560] width 1600 pitch 6400 (/4 1600)
>[217355.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[217355.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[217356.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[217356.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[217357.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb000]
>[217357.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb000] width 1600 pitch 6400 (/4 1600)
>[217357.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f150]
>[217357.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f150] width 1600 pitch 6400 (/4 1600)
>[217357.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[217357.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[217358.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269310]
>[217358.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269310] width 1600 pitch 6400 (/4 1600)
>[217358.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef61f0]
>[217358.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef61f0] width 1600 pitch 6400 (/4 1600)
>[217358.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269310]
>[217358.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269310] width 1600 pitch 6400 (/4 1600)
>[217358.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef61f0]
>[217358.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef61f0] width 1600 pitch 6400 (/4 1600)
>[217358.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269310]
>[217358.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269310] width 1600 pitch 6400 (/4 1600)
>[217358.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef61f0]
>[217358.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef61f0] width 1600 pitch 6400 (/4 1600)
>[217358.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269310]
>[217358.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269310] width 1600 pitch 6400 (/4 1600)
>[217359.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[217359.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[217359.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef61f0]
>[217359.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef61f0] width 1600 pitch 6400 (/4 1600)
>[217359.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea3bf0]
>[217359.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea3bf0] width 1600 pitch 6400 (/4 1600)
>[217359.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4ae40]
>[217359.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4ae40] width 1600 pitch 6400 (/4 1600)
>[217359.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fd570]
>[217359.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fd570] width 1600 pitch 6400 (/4 1600)
>[217359.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a9ca0]
>[217359.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a9ca0] width 1600 pitch 6400 (/4 1600)
>[217359.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ca1a0]
>[217359.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ca1a0] width 1600 pitch 6400 (/4 1600)
>[217359.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3db60]
>[217359.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3db60] width 1600 pitch 6400 (/4 1600)
>[217360.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f11220]
>[217360.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f11220] width 1600 pitch 6400 (/4 1600)
>[217377.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1d680]
>[217377.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1d680] width 1600 pitch 6400 (/4 1600)
>[217434.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc53d0]
>[217434.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc53d0] width 1600 pitch 6400 (/4 1600)
>[217518.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24390]
>[217518.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24390] width 1600 pitch 6400 (/4 1600)
>[217679.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ca1a0]
>[217679.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ca1a0] width 1600 pitch 6400 (/4 1600)
>[217679.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264c1b0]
>[217679.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264c1b0] width 1600 pitch 6400 (/4 1600)
>[217680.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4a760]
>[217680.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4a760] width 1600 pitch 6400 (/4 1600)
>[217680.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[217680.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[217681.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[217681.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[218004.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40278a0]
>[218004.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40278a0] width 1600 pitch 6400 (/4 1600)
>[218055.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f0c50]
>[218055.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f0c50] width 1600 pitch 6400 (/4 1600)
>[218055.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b30]
>[218055.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b30] width 1600 pitch 6400 (/4 1600)
>[218055.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef2a0]
>[218055.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef2a0] width 1600 pitch 6400 (/4 1600)
>[218160.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698e1b0]
>[218160.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698e1b0] width 1600 pitch 6400 (/4 1600)
>[218160.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37650]
>[218160.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37650] width 1600 pitch 6400 (/4 1600)
>[218161.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698e1b0]
>[218161.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698e1b0] width 1600 pitch 6400 (/4 1600)
>[218161.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[218161.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[218161.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef61f0]
>[218161.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef61f0] width 1600 pitch 6400 (/4 1600)
>[218162.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ddb20]
>[218162.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ddb20] width 1600 pitch 6400 (/4 1600)
>[218162.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[218162.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[218162.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9c4f0]
>[218162.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9c4f0] width 1600 pitch 6400 (/4 1600)
>[218163.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71bb0]
>[218163.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71bb0] width 1600 pitch 6400 (/4 1600)
>[218164.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71bb0]
>[218164.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71bb0] width 1600 pitch 6400 (/4 1600)
>[218164.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5e240]
>[218164.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5e240] width 1600 pitch 6400 (/4 1600)
>[218165.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a650]
>[218165.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a650] width 1600 pitch 6400 (/4 1600)
>[218244.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698c790]
>[218244.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698c790] width 1600 pitch 6400 (/4 1600)
>[218281.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a0a0]
>[218281.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a0a0] width 1600 pitch 6400 (/4 1600)
>[218306.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9b4e0]
>[218306.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9b4e0] width 1600 pitch 6400 (/4 1600)
>[218306.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f71bb0]
>[218306.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f71bb0] width 1600 pitch 6400 (/4 1600)
>[218307.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec03d0]
>[218307.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec03d0] width 1600 pitch 6400 (/4 1600)
>[218308.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dbf50]
>[218308.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dbf50] width 1600 pitch 6400 (/4 1600)
>[218308.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7410]
>[218308.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7410] width 1600 pitch 6400 (/4 1600)
>[218454.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6abf670]
>[218454.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6abf670] width 1600 pitch 6400 (/4 1600)
>[218454.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[218454.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[218455.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[218455.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[218455.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698db70]
>[218455.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698db70] width 1600 pitch 6400 (/4 1600)
>[218455.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4b8c0]
>[218455.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4b8c0] width 1600 pitch 6400 (/4 1600)
>[218456.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9b4e0]
>[218456.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9b4e0] width 1600 pitch 6400 (/4 1600)
>[218456.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e4460]
>[218456.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e4460] width 1600 pitch 6400 (/4 1600)
>[218457.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3e4b0]
>[218457.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3e4b0] width 1600 pitch 6400 (/4 1600)
>[218541.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041e40]
>[218541.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041e40] width 1600 pitch 6400 (/4 1600)
>[218541.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[218541.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[218541.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a650]
>[218541.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a650] width 1600 pitch 6400 (/4 1600)
>[218542.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970690]
>[218542.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970690] width 1600 pitch 6400 (/4 1600)
>[218542.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a77b0]
>[218542.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a77b0] width 1600 pitch 6400 (/4 1600)
>[218543.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970690]
>[218543.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970690] width 1600 pitch 6400 (/4 1600)
>[218543.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[218543.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[218543.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a9ca0]
>[218543.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a9ca0] width 1600 pitch 6400 (/4 1600)
>[218548.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a5a0]
>[218548.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a5a0] width 1600 pitch 6400 (/4 1600)
>[218548.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed6e80]
>[218548.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed6e80] width 1600 pitch 6400 (/4 1600)
>[218548.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[218548.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[218549.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504f790]
>[218549.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504f790] width 1600 pitch 6400 (/4 1600)
>[218549.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00910]
>[218549.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00910] width 1600 pitch 6400 (/4 1600)
>[218549.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504f790]
>[218549.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504f790] width 1600 pitch 6400 (/4 1600)
>[218550.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f69190]
>[218550.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f69190] width 1600 pitch 6400 (/4 1600)
>[218550.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3090]
>[218550.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3090] width 1600 pitch 6400 (/4 1600)
>[218550.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[218550.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[218550.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a71d0]
>[218551.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a71d0] width 1600 pitch 6400 (/4 1600)
>[218551.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041e40]
>[218551.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041e40] width 1600 pitch 6400 (/4 1600)
>[218551.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39a71d0]
>[218551.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39a71d0] width 1600 pitch 6400 (/4 1600)
>[218657.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041e40]
>[218657.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041e40] width 1600 pitch 6400 (/4 1600)
>[218657.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041e40]
>[218658.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041e40] width 1600 pitch 6400 (/4 1600)
>[218658.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00910]
>[218658.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00910] width 1600 pitch 6400 (/4 1600)
>[218658.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[218658.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[218658.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051230]
>[218658.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051230] width 1600 pitch 6400 (/4 1600)
>[218659.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3877a60]
>[218659.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3877a60] width 1600 pitch 6400 (/4 1600)
>[218659.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf31e0]
>[218660.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf31e0] width 1600 pitch 6400 (/4 1600)
>[218734.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc7200]
>[218734.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc7200] width 1600 pitch 6400 (/4 1600)
>[218735.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[218735.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[218735.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2d0d0]
>[218735.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2d0d0] width 1600 pitch 6400 (/4 1600)
>[218735.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1ed0]
>[218736.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1ed0] width 1600 pitch 6400 (/4 1600)
>[218736.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc7200]
>[218736.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc7200] width 1600 pitch 6400 (/4 1600)
>[218736.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf31e0]
>[218736.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf31e0] width 1600 pitch 6400 (/4 1600)
>[218736.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc8c20]
>[218736.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc8c20] width 1600 pitch 6400 (/4 1600)
>[218737.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed73c0]
>[218737.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed73c0] width 1600 pitch 6400 (/4 1600)
>[218738.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f66b20]
>[218738.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f66b20] width 1600 pitch 6400 (/4 1600)
>[218738.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9a4e0]
>[218738.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9a4e0] width 1600 pitch 6400 (/4 1600)
>[218745.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f66b20]
>[218745.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f66b20] width 1600 pitch 6400 (/4 1600)
>[218745.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3988ce0]
>[218745.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3988ce0] width 1600 pitch 6400 (/4 1600)
>[218745.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512ee80]
>[218745.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512ee80] width 1600 pitch 6400 (/4 1600)
>[218746.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9f050]
>[218746.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9f050] width 1600 pitch 6400 (/4 1600)
>[218746.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3970690]
>[218746.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3970690] width 1600 pitch 6400 (/4 1600)
>[218746.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc7200]
>[218747.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc7200] width 1600 pitch 6400 (/4 1600)
>[218747.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698db70]
>[218747.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698db70] width 1600 pitch 6400 (/4 1600)
>[218747.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e4480]
>[218747.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e4480] width 1600 pitch 6400 (/4 1600)
>[218748.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d925d0]
>[218748.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d925d0] width 1600 pitch 6400 (/4 1600)
>[218748.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[218748.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[218749.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[218749.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[218947.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6eb0]
>[218948.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6eb0] width 1600 pitch 6400 (/4 1600)
>[218948.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5d6b0]
>[218948.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5d6b0] width 1600 pitch 6400 (/4 1600)
>[218948.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[218948.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[218948.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[218948.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[218949.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a650]
>[218949.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a650] width 1600 pitch 6400 (/4 1600)
>[218949.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ddb20]
>[218949.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ddb20] width 1600 pitch 6400 (/4 1600)
>[218949.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19bf0]
>[218949.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19bf0] width 1600 pitch 6400 (/4 1600)
>[219101.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f5c40]
>[219102.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f5c40] width 1600 pitch 6400 (/4 1600)
>[219104.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf31e0]
>[219104.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf31e0] width 1600 pitch 6400 (/4 1600)
>[219104.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[219104.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[219104.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3027be0]
>[219104.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3027be0] width 1600 pitch 6400 (/4 1600)
>[219104.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3027be0]
>[219104.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3027be0] width 1600 pitch 6400 (/4 1600)
>[219104.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3864d60]
>[219104.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3864d60] width 1600 pitch 6400 (/4 1600)
>[219104.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6ec0]
>[219105.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6ec0] width 1600 pitch 6400 (/4 1600)
>[219105.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39590]
>[219105.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39590] width 1600 pitch 6400 (/4 1600)
>[219124.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d02310]
>[219124.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d02310] width 1600 pitch 6400 (/4 1600)
>[219281.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865190]
>[219281.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865190] width 1600 pitch 6400 (/4 1600)
>[219281.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865800]
>[219281.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865800] width 1600 pitch 6400 (/4 1600)
>[219281.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fe20]
>[219281.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fe20] width 1600 pitch 6400 (/4 1600)
>[219281.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865800]
>[219281.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865800] width 1600 pitch 6400 (/4 1600)
>[219281.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fe20]
>[219281.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fe20] width 1600 pitch 6400 (/4 1600)
>[219281.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865800]
>[219281.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865800] width 1600 pitch 6400 (/4 1600)
>[219281.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fe20]
>[219281.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fe20] width 1600 pitch 6400 (/4 1600)
>[219281.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865800]
>[219281.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865800] width 1600 pitch 6400 (/4 1600)
>[219286.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386b610]
>[219286.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386b610] width 1600 pitch 6400 (/4 1600)
>[219286.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cec060]
>[219286.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cec060] width 1600 pitch 6400 (/4 1600)
>[219286.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38eee20]
>[219286.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38eee20] width 1600 pitch 6400 (/4 1600)
>[219286.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[219286.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[219286.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa34c0]
>[219286.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa34c0] width 1600 pitch 6400 (/4 1600)
>[219290.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6997030]
>[219290.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6997030] width 1600 pitch 6400 (/4 1600)
>[219293.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa34c0]
>[219293.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa34c0] width 1600 pitch 6400 (/4 1600)
>[219293.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cec060]
>[219293.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cec060] width 1600 pitch 6400 (/4 1600)
>[219293.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa34c0]
>[219293.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa34c0] width 1600 pitch 6400 (/4 1600)
>[219293.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e5a0]
>[219293.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e5a0] width 1600 pitch 6400 (/4 1600)
>[219293.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68675d0]
>[219293.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68675d0] width 1600 pitch 6400 (/4 1600)
>[219294.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c79d0]
>[219294.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c79d0] width 1600 pitch 6400 (/4 1600)
>[219301.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c2e60]
>[219301.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c2e60] width 1600 pitch 6400 (/4 1600)
>[219310.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7910]
>[219310.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7910] width 1600 pitch 6400 (/4 1600)
>[219314.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bee5e0]
>[219314.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bee5e0] width 1600 pitch 6400 (/4 1600)
>[219315.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be88a0]
>[219315.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be88a0] width 1600 pitch 6400 (/4 1600)
>[219334.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4784040]
>[219334.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4784040] width 1600 pitch 6400 (/4 1600)
>[219340.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c3f70]
>[219340.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c3f70] width 1600 pitch 6400 (/4 1600)
>[219340.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cee10]
>[219340.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cee10] width 1600 pitch 6400 (/4 1600)
>[219340.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cefe0]
>[219340.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cefe0] width 1600 pitch 6400 (/4 1600)
>[219340.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cec30]
>[219340.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cec30] width 1600 pitch 6400 (/4 1600)
>[219340.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cec30]
>[219340.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cec30] width 1600 pitch 6400 (/4 1600)
>[219340.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cef60]
>[219340.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cef60] width 1600 pitch 6400 (/4 1600)
>[219342.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48090f0]
>[219343.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48090f0] width 1600 pitch 6400 (/4 1600)
>[219343.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4809090]
>[219343.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4809090] width 1600 pitch 6400 (/4 1600)
>[219343.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ceb70]
>[219343.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ceb70] width 1600 pitch 6400 (/4 1600)
>[219343.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b4860]
>[219343.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b4860] width 1600 pitch 6400 (/4 1600)
>[219345.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cbc200]
>[219345.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cbc200] width 1600 pitch 6400 (/4 1600)
>[219345.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b33f0]
>[219345.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b33f0] width 1600 pitch 6400 (/4 1600)
>[219345.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cef60]
>[219345.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cef60] width 1600 pitch 6400 (/4 1600)
>[219345.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b33f0]
>[219345.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b33f0] width 1600 pitch 6400 (/4 1600)
>[219345.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47cef60]
>[219345.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47cef60] width 1600 pitch 6400 (/4 1600)
>[219345.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9a230]
>[219345.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9a230] width 1600 pitch 6400 (/4 1600)
>[219345.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9c660]
>[219345.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9c660] width 1600 pitch 6400 (/4 1600)
>[219345.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219346.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219354.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c86c0]
>[219354.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c86c0] width 1600 pitch 6400 (/4 1600)
>[219354.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219354.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219354.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896ff0]
>[219354.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896ff0] width 1600 pitch 6400 (/4 1600)
>[219354.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219354.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219354.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f480]
>[219355.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f480] width 1600 pitch 6400 (/4 1600)
>[219355.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c86c0]
>[219355.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c86c0] width 1600 pitch 6400 (/4 1600)
>[219355.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1f480]
>[219355.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1f480] width 1600 pitch 6400 (/4 1600)
>[219355.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68655f0]
>[219355.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68655f0] width 1600 pitch 6400 (/4 1600)
>[219356.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3941930]
>[219356.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3941930] width 1600 pitch 6400 (/4 1600)
>[219356.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026990]
>[219356.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026990] width 1600 pitch 6400 (/4 1600)
>[219357.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219357.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219357.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e293d0]
>[219357.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e293d0] width 1600 pitch 6400 (/4 1600)
>[219357.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[219357.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[219357.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[219357.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[219357.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bdd00]
>[219357.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bdd00] width 1600 pitch 6400 (/4 1600)
>[219358.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9a650]
>[219358.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9a650] width 1600 pitch 6400 (/4 1600)
>[219358.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219358.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219358.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dbd0]
>[219358.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dbd0] width 1600 pitch 6400 (/4 1600)
>[219358.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0570]
>[219358.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0570] width 1600 pitch 6400 (/4 1600)
>[219358.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbd380]
>[219358.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbd380] width 1600 pitch 6400 (/4 1600)
>[219359.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8b3e0]
>[219359.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8b3e0] width 1600 pitch 6400 (/4 1600)
>[219359.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac9580]
>[219359.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac9580] width 1600 pitch 6400 (/4 1600)
>[219359.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4026990]
>[219359.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4026990] width 1600 pitch 6400 (/4 1600)
>[219359.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e293d0]
>[219359.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e293d0] width 1600 pitch 6400 (/4 1600)
>[219360.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bdd00]
>[219360.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bdd00] width 1600 pitch 6400 (/4 1600)
>[219360.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219360.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219361.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219361.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219361.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca5a30]
>[219361.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca5a30] width 1600 pitch 6400 (/4 1600)
>[219362.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac4210]
>[219362.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac4210] width 1600 pitch 6400 (/4 1600)
>[219363.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1aae0]
>[219363.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1aae0] width 1600 pitch 6400 (/4 1600)
>[219363.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dbd0]
>[219363.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dbd0] width 1600 pitch 6400 (/4 1600)
>[219363.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219363.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219367.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a490]
>[219367.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a490] width 1600 pitch 6400 (/4 1600)
>[219367.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219367.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219367.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ef040]
>[219367.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ef040] width 1600 pitch 6400 (/4 1600)
>[219367.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219367.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219367.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a490]
>[219367.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a490] width 1600 pitch 6400 (/4 1600)
>[219367.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219367.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219367.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282a490]
>[219367.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282a490] width 1600 pitch 6400 (/4 1600)
>[219367.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219367.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219367.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6896ff0]
>[219368.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6896ff0] width 1600 pitch 6400 (/4 1600)
>[219368.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf31e0]
>[219368.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf31e0] width 1600 pitch 6400 (/4 1600)
>[219368.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[219368.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[219368.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4051230]
>[219368.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4051230] width 1600 pitch 6400 (/4 1600)
>[219393.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eeba0]
>[219393.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eeba0] width 1600 pitch 6400 (/4 1600)
>[219400.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efbbf0]
>[219400.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efbbf0] width 1600 pitch 6400 (/4 1600)
>[219400.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0a700]
>[219400.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0a700] width 1600 pitch 6400 (/4 1600)
>[219400.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219400.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219400.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[219400.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[219400.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c165c0]
>[219400.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c165c0] width 1600 pitch 6400 (/4 1600)
>[219400.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea8360]
>[219400.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea8360] width 1600 pitch 6400 (/4 1600)
>[219400.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970970]
>[219401.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970970] width 1600 pitch 6400 (/4 1600)
>[219403.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bee6d0]
>[219403.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bee6d0] width 1600 pitch 6400 (/4 1600)
>[219403.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a032a0]
>[219403.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a032a0] width 1600 pitch 6400 (/4 1600)
>[219403.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3a430]
>[219403.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3a430] width 1600 pitch 6400 (/4 1600)
>[219423.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c0020]
>[219423.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c0020] width 1600 pitch 6400 (/4 1600)
>[219476.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a8e0]
>[219476.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a8e0] width 1600 pitch 6400 (/4 1600)
>[219477.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a032a0]
>[219477.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a032a0] width 1600 pitch 6400 (/4 1600)
>[219477.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca7880]
>[219477.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca7880] width 1600 pitch 6400 (/4 1600)
>[219477.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dbd0]
>[219477.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dbd0] width 1600 pitch 6400 (/4 1600)
>[219477.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287ef20]
>[219478.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287ef20] width 1600 pitch 6400 (/4 1600)
>[219478.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dbd0]
>[219478.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dbd0] width 1600 pitch 6400 (/4 1600)
>[219529.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a17d90]
>[219529.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a17d90] width 1600 pitch 6400 (/4 1600)
>[219532.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf31e0]
>[219532.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf31e0] width 1600 pitch 6400 (/4 1600)
>[219532.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e293d0]
>[219532.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e293d0] width 1600 pitch 6400 (/4 1600)
>[219532.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f00e0]
>[219532.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f00e0] width 1600 pitch 6400 (/4 1600)
>[219532.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[219532.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[219532.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6ee0]
>[219532.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6ee0] width 1600 pitch 6400 (/4 1600)
>[219532.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c03c0]
>[219532.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c03c0] width 1600 pitch 6400 (/4 1600)
>[219532.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30120]
>[219533.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30120] width 1600 pitch 6400 (/4 1600)
>[219533.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c19250]
>[219533.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c19250] width 1600 pitch 6400 (/4 1600)
>[219552.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3865b30]
>[219552.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3865b30] width 1600 pitch 6400 (/4 1600)
>[219584.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47801c0]
>[219584.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47801c0] width 1600 pitch 6400 (/4 1600)
>[219584.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044b20]
>[219584.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044b20] width 1600 pitch 6400 (/4 1600)
>[219584.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3becb90]
>[219584.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3becb90] width 1600 pitch 6400 (/4 1600)
>[219585.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3becb90]
>[219585.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3becb90] width 1600 pitch 6400 (/4 1600)
>[219585.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3becb90]
>[219585.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3becb90] width 1600 pitch 6400 (/4 1600)
>[219585.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b697b0]
>[219586.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b697b0] width 1600 pitch 6400 (/4 1600)
>[219587.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478c8c0]
>[219587.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478c8c0] width 1600 pitch 6400 (/4 1600)
>[219587.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a053a0]
>[219587.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a053a0] width 1600 pitch 6400 (/4 1600)
>[219587.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[219587.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[219587.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[219588.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[219588.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[219588.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[219588.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[219588.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[219588.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df60d0]
>[219588.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df60d0] width 1600 pitch 6400 (/4 1600)
>[219588.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f278a0]
>[219588.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f278a0] width 1600 pitch 6400 (/4 1600)
>[219588.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507dbd0]
>[219588.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507dbd0] width 1600 pitch 6400 (/4 1600)
>[219588.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a7c0]
>[219588.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a7c0] width 1600 pitch 6400 (/4 1600)
>[219588.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fac750]
>[219588.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fac750] width 1600 pitch 6400 (/4 1600)
>[219588.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b6ee0]
>[219588.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b6ee0] width 1600 pitch 6400 (/4 1600)
>[219817.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219817.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219817.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219817.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219817.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388cf30]
>[219817.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388cf30] width 1600 pitch 6400 (/4 1600)
>[219817.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219817.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219817.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388cf30]
>[219817.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388cf30] width 1600 pitch 6400 (/4 1600)
>[219818.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219818.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219818.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388cf30]
>[219818.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388cf30] width 1600 pitch 6400 (/4 1600)
>[219822.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c80b50]
>[219822.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c80b50] width 1600 pitch 6400 (/4 1600)
>[219822.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219822.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219822.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a46d0]
>[219822.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a46d0] width 1600 pitch 6400 (/4 1600)
>[219822.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219822.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219822.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a46d0]
>[219822.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a46d0] width 1600 pitch 6400 (/4 1600)
>[219823.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219823.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219823.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219823.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219823.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219823.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219823.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219823.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219823.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219823.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219823.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219823.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219823.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[219823.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1600 pitch 6400 (/4 1600)
>[219823.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad7130]
>[219823.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad7130] width 1600 pitch 6400 (/4 1600)
>[219934.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398c190]
>[219934.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398c190] width 1600 pitch 6400 (/4 1600)
>[219941.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d62730]
>[219941.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d62730] width 1600 pitch 6400 (/4 1600)
>[219941.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f459c0]
>[219941.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f459c0] width 1600 pitch 6400 (/4 1600)
>[219941.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b56eb0]
>[219941.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b56eb0] width 1600 pitch 6400 (/4 1600)
>[219941.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26ed390]
>[219942.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26ed390] width 1600 pitch 6400 (/4 1600)
>[219942.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[219942.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1600 pitch 6400 (/4 1600)
>[219942.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x500fc80]
>[219942.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x500fc80] width 1600 pitch 6400 (/4 1600)
>[219942.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b10460]
>[219942.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b10460] width 1600 pitch 6400 (/4 1600)
>[219942.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebe360]
>[219942.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebe360] width 1600 pitch 6400 (/4 1600)
>[219942.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48460]
>[219942.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48460] width 1600 pitch 6400 (/4 1600)
>[219942.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[219942.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[219942.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b50c0]
>[219942.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b50c0] width 1600 pitch 6400 (/4 1600)
>[219942.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b27bf0]
>[219942.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b27bf0] width 1600 pitch 6400 (/4 1600)
>[219942.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a46d0]
>[219942.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a46d0] width 1600 pitch 6400 (/4 1600)
>[219942.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872b40]
>[219942.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872b40] width 1600 pitch 6400 (/4 1600)
>[219942.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac6780]
>[219942.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac6780] width 1600 pitch 6400 (/4 1600)
>[219942.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eee70]
>[219942.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eee70] width 1600 pitch 6400 (/4 1600)
>[219942.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa8430]
>[219942.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa8430] width 1600 pitch 6400 (/4 1600)
>[219942.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[219942.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[220498.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3989e70]
>[220498.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3989e70] width 1600 pitch 6400 (/4 1600)
>[220498.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a61a00]
>[220498.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a61a00] width 1600 pitch 6400 (/4 1600)
>[220498.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4036e80]
>[220498.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4036e80] width 1600 pitch 6400 (/4 1600)
>[220498.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeeed0]
>[220498.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeeed0] width 1600 pitch 6400 (/4 1600)
>[220498.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc74f0]
>[220498.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc74f0] width 1600 pitch 6400 (/4 1600)
>[220498.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855cf0]
>[220498.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855cf0] width 1600 pitch 6400 (/4 1600)
>[220499.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f01150]
>[220499.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f01150] width 1600 pitch 6400 (/4 1600)
>[220499.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944690]
>[220499.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944690] width 1600 pitch 6400 (/4 1600)
>[220500.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c18bf0]
>[220500.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c18bf0] width 1600 pitch 6400 (/4 1600)
>[220500.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e27810]
>[220500.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e27810] width 1600 pitch 6400 (/4 1600)
>[220500.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2826350]
>[220500.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2826350] width 1600 pitch 6400 (/4 1600)
>[220501.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3889460]
>[220501.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3889460] width 1600 pitch 6400 (/4 1600)
>[220501.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b44780]
>[220501.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b44780] width 1600 pitch 6400 (/4 1600)
>[220501.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad2b0]
>[220501.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad2b0] width 1600 pitch 6400 (/4 1600)
>[220501.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a97200]
>[220501.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a97200] width 1600 pitch 6400 (/4 1600)
>[220518.125] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event6)
>[220518.125] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[220518.125] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[220518.125] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[220518.125] 	Option "XkbRules" "evdev"
>[220518.125] 	Option "XkbModel" "pc105+inet"
>[220518.125] 	Option "XkbLayout" "us"
>[220518.125] 	Option "_source" "server/udev"
>[220518.125] 	Option "name" "VISENTA V1 "
>[220518.125] 	Option "path" "/dev/input/event6"
>[220518.125] 	Option "device" "/dev/input/event6"
>[220518.125] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input31/event6"
>[220518.125] 	Option "driver" "evdev"
>[220518.125] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[220518.125] (**) VISENTA V1 : always reports core events
>[220518.125] (**) evdev: VISENTA V1 : Device: "/dev/input/event6"
>[220518.125] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[220518.125] (--) evdev: VISENTA V1 : Found keys
>[220518.125] (II) evdev: VISENTA V1 : Configuring as keyboard
>[220518.125] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input31/event6"
>[220518.125] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 9)
>[220518.125] (**) Option "xkb_rules" "evdev"
>[220518.125] (**) Option "xkb_model" "pc105+inet"
>[220518.125] (**) Option "xkb_layout" "us"
>[220518.125] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[220518.125] (II) XKB: Reusing cached keymap
>[220518.127] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event7)
>[220518.127] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[220518.127] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[220518.127] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[220518.127] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[220518.127] 	Option "XkbRules" "evdev"
>[220518.127] 	Option "XkbModel" "pc105+inet"
>[220518.127] 	Option "XkbLayout" "us"
>[220518.127] 	Option "_source" "server/udev"
>[220518.127] 	Option "name" "VISENTA V1 "
>[220518.127] 	Option "path" "/dev/input/event7"
>[220518.127] 	Option "device" "/dev/input/event7"
>[220518.127] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input32/event7"
>[220518.127] 	Option "driver" "evdev"
>[220518.127] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[220518.127] (**) VISENTA V1 : always reports core events
>[220518.127] (**) evdev: VISENTA V1 : Device: "/dev/input/event7"
>[220518.127] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[220518.127] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[220518.127] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[220518.127] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[220518.127] (--) evdev: VISENTA V1 : Found relative axes
>[220518.127] (--) evdev: VISENTA V1 : Found x and y relative axes
>[220518.127] (--) evdev: VISENTA V1 : Found absolute axes
>[220518.127] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[220518.127] (--) evdev: VISENTA V1 : Found keys
>[220518.127] (II) evdev: VISENTA V1 : Configuring as mouse
>[220518.127] (II) evdev: VISENTA V1 : Configuring as keyboard
>[220518.127] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[220518.127] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[220518.127] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[220518.127] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input32/event7"
>[220518.128] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 10)
>[220518.128] (**) Option "xkb_rules" "evdev"
>[220518.128] (**) Option "xkb_model" "pc105+inet"
>[220518.128] (**) Option "xkb_layout" "us"
>[220518.128] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[220518.128] (II) XKB: Reusing cached keymap
>[220518.128] (II) evdev: VISENTA V1 : initialized for relative axes.
>[220518.128] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[220518.129] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[220518.129] (**) VISENTA V1 : (accel) acceleration profile 0
>[220518.130] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[220518.130] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[220518.131] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse2)
>[220518.131] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[220518.131] (II) No input driver specified, ignoring this device.
>[220518.131] (II) This device may have been added with another device file.
>[220518.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad2b0]
>[220518.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad2b0] width 1600 pitch 6400 (/4 1600)
>[220518.283] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event8)
>[220518.284] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[220518.284] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[220518.284] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[220518.284] 	Option "XkbRules" "evdev"
>[220518.284] 	Option "XkbModel" "pc105+inet"
>[220518.284] 	Option "XkbLayout" "us"
>[220518.284] 	Option "_source" "server/udev"
>[220518.284] 	Option "name" "USB USB Keykoard"
>[220518.284] 	Option "path" "/dev/input/event8"
>[220518.284] 	Option "device" "/dev/input/event8"
>[220518.284] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input33/event8"
>[220518.284] 	Option "driver" "evdev"
>[220518.284] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[220518.284] (**) USB USB Keykoard: always reports core events
>[220518.284] (**) evdev: USB USB Keykoard: Device: "/dev/input/event8"
>[220518.284] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[220518.284] (--) evdev: USB USB Keykoard: Found keys
>[220518.284] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[220518.284] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input33/event8"
>[220518.284] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 11)
>[220518.284] (**) Option "xkb_rules" "evdev"
>[220518.284] (**) Option "xkb_model" "pc105+inet"
>[220518.284] (**) Option "xkb_layout" "us"
>[220518.284] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[220518.284] (II) XKB: Reusing cached keymap
>[220518.285] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event18)
>[220518.285] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[220518.285] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[220518.285] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[220518.285] 	Option "XkbRules" "evdev"
>[220518.285] 	Option "XkbModel" "pc105+inet"
>[220518.285] 	Option "XkbLayout" "us"
>[220518.285] 	Option "_source" "server/udev"
>[220518.285] 	Option "name" "USB USB Keykoard"
>[220518.285] 	Option "path" "/dev/input/event18"
>[220518.285] 	Option "device" "/dev/input/event18"
>[220518.285] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input34/event18"
>[220518.285] 	Option "driver" "evdev"
>[220518.285] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[220518.285] (**) USB USB Keykoard: always reports core events
>[220518.285] (**) evdev: USB USB Keykoard: Device: "/dev/input/event18"
>[220518.285] (--) evdev: USB USB Keykoard: absolute axis 0x20 [572..0]
>[220518.285] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[220518.285] (--) evdev: USB USB Keykoard: Found 1 mouse buttons
>[220518.285] (--) evdev: USB USB Keykoard: Found scroll wheel(s)
>[220518.285] (--) evdev: USB USB Keykoard: Found relative axes
>[220518.285] (II) evdev: USB USB Keykoard: Forcing relative x/y axes to exist.
>[220518.285] (--) evdev: USB USB Keykoard: Found absolute axes
>[220518.285] (II) evdev: USB USB Keykoard: Forcing absolute x/y axes to exist.
>[220518.285] (--) evdev: USB USB Keykoard: Found keys
>[220518.285] (II) evdev: USB USB Keykoard: Configuring as mouse
>[220518.285] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[220518.285] (II) evdev: USB USB Keykoard: Adding scrollwheel support
>[220518.285] (**) evdev: USB USB Keykoard: YAxisMapping: buttons 4 and 5
>[220518.285] (**) evdev: USB USB Keykoard: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[220518.285] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input34/event18"
>[220518.285] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 17)
>[220518.285] (**) Option "xkb_rules" "evdev"
>[220518.285] (**) Option "xkb_model" "pc105+inet"
>[220518.285] (**) Option "xkb_layout" "us"
>[220518.285] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[220518.285] (II) XKB: Reusing cached keymap
>[220518.285] (II) evdev: USB USB Keykoard: initialized for relative axes.
>[220518.285] (WW) evdev: USB USB Keykoard: ignoring absolute axes.
>[220518.285] (**) USB USB Keykoard: (accel) keeping acceleration scheme 1
>[220518.285] (**) USB USB Keykoard: (accel) acceleration profile 0
>[220518.285] (**) USB USB Keykoard: (accel) acceleration factor: 2.000
>[220518.285] (**) USB USB Keykoard: (accel) acceleration threshold: 4
>[220518.439] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[220518.439] (II) RADEON(0): Printing DDC gathered Modelines:
>[220518.439] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[220518.439] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[220518.499] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event19)
>[220518.499] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[220518.499] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[220518.499] 	Option "XkbRules" "evdev"
>[220518.499] 	Option "XkbModel" "evdev"
>[220518.499] 	Option "XkbLayout" "us"
>[220518.499] 	Option "_source" "server/udev"
>[220518.499] 	Option "name" "Logitech USB Optical Mouse"
>[220518.499] 	Option "path" "/dev/input/event19"
>[220518.499] 	Option "device" "/dev/input/event19"
>[220518.499] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input35/event19"
>[220518.499] 	Option "driver" "evdev"
>[220518.499] (**) Logitech USB Optical Mouse: always reports core events
>[220518.499] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event19"
>[220518.507] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[220518.507] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[220518.507] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[220518.507] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[220518.507] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[220518.507] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[220518.507] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[220518.507] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[220518.507] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[220518.507] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input35/event19"
>[220518.507] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 18)
>[220518.507] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[220518.508] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[220518.508] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[220518.508] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[220518.508] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[220518.509] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse3)
>[220518.509] (II) No input driver specified, ignoring this device.
>[220518.509] (II) This device may have been added with another device file.
>[220519.132] (II) RADEON(0): Allocate new frame buffer 1920x1080 stride 1920
>[220519.132] (II) RADEON(0): VRAM usage limit set to 221119K
>[220521.521] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[220521.521] (II) RADEON(0): Printing DDC gathered Modelines:
>[220521.521] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[220521.521] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[220521.948] (II) RADEON(0): RADEONSaveScreen(2)
>[220521.948] (II) RADEON(0): RADEONSaveScreen(0)
>[220523.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69af580]
>[264187.518] (II) RADEON(0): RADEONSaveScreen(1)
>[264187.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69af580] width 1920 pitch 7680 (/4 1920)
>[264187.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[264187.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[264188.258] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[264188.258] (II) RADEON(0): Using hsync ranges from config file
>[264188.258] (II) RADEON(0): Using vrefresh ranges from config file
>[264188.258] (II) RADEON(0): Printing DDC gathered Modelines:
>[264188.258] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[264188.258] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[264188.258] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[264188.258] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[264188.258] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[264188.258] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[264188.258] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[264188.258] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[264188.258] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[264188.258] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[264188.258] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[264220.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eefbf0]
>[264220.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eefbf0] width 1920 pitch 7680 (/4 1920)
>[264577.753] (II) RADEON(0): RADEONSaveScreen(2)
>[264577.753] (II) RADEON(0): RADEONSaveScreen(0)
>[350232.532] (II) RADEON(0): RADEONSaveScreen(1)
>[350247.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db2c10]
>[350247.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db2c10] width 1920 pitch 7680 (/4 1920)
>[350249.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[350250.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[350250.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350250.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350250.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad9850]
>[350250.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad9850] width 1920 pitch 7680 (/4 1920)
>[350251.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[350251.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[350251.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4b80]
>[350251.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4b80] width 1920 pitch 7680 (/4 1920)
>[350251.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5ce0]
>[350251.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5ce0] width 1920 pitch 7680 (/4 1920)
>[350252.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0a5b0]
>[350252.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0a5b0] width 1920 pitch 7680 (/4 1920)
>[350252.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b4ce0]
>[350252.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b4ce0] width 1920 pitch 7680 (/4 1920)
>[350252.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f755a0]
>[350252.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f755a0] width 1920 pitch 7680 (/4 1920)
>[350252.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2930]
>[350253.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2930] width 1920 pitch 7680 (/4 1920)
>[350253.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350253.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350253.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[350253.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[350253.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57740]
>[350253.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57740] width 1920 pitch 7680 (/4 1920)
>[350253.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad9850]
>[350253.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad9850] width 1920 pitch 7680 (/4 1920)
>[350253.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb1de0]
>[350253.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb1de0] width 1920 pitch 7680 (/4 1920)
>[350253.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[350253.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1920 pitch 7680 (/4 1920)
>[350253.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26250f0]
>[350253.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26250f0] width 1920 pitch 7680 (/4 1920)
>[350253.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[350253.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[350253.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23bf0]
>[350253.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23bf0] width 1920 pitch 7680 (/4 1920)
>[350254.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c50b0]
>[350254.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c50b0] width 1920 pitch 7680 (/4 1920)
>[350254.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c302b0]
>[350254.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c302b0] width 1920 pitch 7680 (/4 1920)
>[350254.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b4ce0]
>[350254.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b4ce0] width 1920 pitch 7680 (/4 1920)
>[350254.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f755a0]
>[350254.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f755a0] width 1920 pitch 7680 (/4 1920)
>[350254.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2930]
>[350254.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2930] width 1920 pitch 7680 (/4 1920)
>[350254.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53860]
>[350254.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53860] width 1920 pitch 7680 (/4 1920)
>[350254.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[350254.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[350254.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807f0]
>[350254.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807f0] width 1920 pitch 7680 (/4 1920)
>[350254.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad9850]
>[350254.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad9850] width 1920 pitch 7680 (/4 1920)
>[350254.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d617b0]
>[350254.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d617b0] width 1920 pitch 7680 (/4 1920)
>[350254.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29010]
>[350254.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29010] width 1920 pitch 7680 (/4 1920)
>[350254.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb1de0]
>[350254.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb1de0] width 1920 pitch 7680 (/4 1920)
>[350254.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[350254.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[350255.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350255.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350255.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb90e0]
>[350255.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb90e0] width 1920 pitch 7680 (/4 1920)
>[350255.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b4c0]
>[350255.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b4c0] width 1920 pitch 7680 (/4 1920)
>[350255.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88820]
>[350255.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88820] width 1920 pitch 7680 (/4 1920)
>[350255.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ef20]
>[350255.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ef20] width 1920 pitch 7680 (/4 1920)
>[350255.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[350255.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[350255.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc6880]
>[350255.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc6880] width 1920 pitch 7680 (/4 1920)
>[350255.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[350255.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1920 pitch 7680 (/4 1920)
>[350255.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce46f0]
>[350255.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce46f0] width 1920 pitch 7680 (/4 1920)
>[350255.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[350255.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1920 pitch 7680 (/4 1920)
>[350255.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4370]
>[350255.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4370] width 1920 pitch 7680 (/4 1920)
>[350255.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26250f0]
>[350255.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26250f0] width 1920 pitch 7680 (/4 1920)
>[350255.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4b80]
>[350255.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4b80] width 1920 pitch 7680 (/4 1920)
>[350255.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92350]
>[350255.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92350] width 1920 pitch 7680 (/4 1920)
>[350255.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9eb90]
>[350255.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9eb90] width 1920 pitch 7680 (/4 1920)
>[350255.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3c7a0]
>[350255.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3c7a0] width 1920 pitch 7680 (/4 1920)
>[350255.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284e720]
>[350255.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284e720] width 1920 pitch 7680 (/4 1920)
>[350255.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e8f0]
>[350255.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e8f0] width 1920 pitch 7680 (/4 1920)
>[350255.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3ee0]
>[350256.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3ee0] width 1920 pitch 7680 (/4 1920)
>[350256.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a36200]
>[350256.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a36200] width 1920 pitch 7680 (/4 1920)
>[350257.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb480]
>[350257.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb480] width 1920 pitch 7680 (/4 1920)
>[350257.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f710]
>[350257.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f710] width 1920 pitch 7680 (/4 1920)
>[350257.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cddff0]
>[350257.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cddff0] width 1920 pitch 7680 (/4 1920)
>[350257.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f23bf0]
>[350257.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f23bf0] width 1920 pitch 7680 (/4 1920)
>[350257.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebd110]
>[350257.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebd110] width 1920 pitch 7680 (/4 1920)
>[350257.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab38b0]
>[350257.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab38b0] width 1920 pitch 7680 (/4 1920)
>[350257.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40564b0]
>[350257.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40564b0] width 1920 pitch 7680 (/4 1920)
>[350257.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[350257.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1920 pitch 7680 (/4 1920)
>[350257.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c302b0]
>[350257.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c302b0] width 1920 pitch 7680 (/4 1920)
>[350257.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[350257.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1920 pitch 7680 (/4 1920)
>[350260.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a5030]
>[350260.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a5030] width 1920 pitch 7680 (/4 1920)
>[350260.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c543e0]
>[350260.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c543e0] width 1920 pitch 7680 (/4 1920)
>[350260.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db2c10]
>[350260.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db2c10] width 1920 pitch 7680 (/4 1920)
>[350260.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0f00]
>[350260.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0f00] width 1920 pitch 7680 (/4 1920)
>[350266.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b99b0]
>[350266.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b99b0] width 1920 pitch 7680 (/4 1920)
>[350266.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[350266.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1920 pitch 7680 (/4 1920)
>[350266.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[350266.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1920 pitch 7680 (/4 1920)
>[350267.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ef20]
>[350267.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ef20] width 1920 pitch 7680 (/4 1920)
>[350267.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[350267.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1920 pitch 7680 (/4 1920)
>[350267.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[350267.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[350268.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc6880]
>[350268.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc6880] width 1920 pitch 7680 (/4 1920)
>[350268.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[350268.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1920 pitch 7680 (/4 1920)
>[350268.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[350268.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[350268.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4b80]
>[350269.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4b80] width 1920 pitch 7680 (/4 1920)
>[350269.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5ce0]
>[350269.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5ce0] width 1920 pitch 7680 (/4 1920)
>[350269.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9eb90]
>[350269.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9eb90] width 1920 pitch 7680 (/4 1920)
>[350269.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284e720]
>[350269.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284e720] width 1920 pitch 7680 (/4 1920)
>[350269.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc5f0]
>[350269.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc5f0] width 1920 pitch 7680 (/4 1920)
>[350269.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f2e8f0]
>[350269.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f2e8f0] width 1920 pitch 7680 (/4 1920)
>[350269.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b850]
>[350270.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b850] width 1920 pitch 7680 (/4 1920)
>[350270.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a73f0]
>[350270.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a73f0] width 1920 pitch 7680 (/4 1920)
>[350270.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b4ce0]
>[350270.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b4ce0] width 1920 pitch 7680 (/4 1920)
>[350270.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ef20]
>[350271.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ef20] width 1920 pitch 7680 (/4 1920)
>[350271.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[350271.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1920 pitch 7680 (/4 1920)
>[350271.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[350271.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1920 pitch 7680 (/4 1920)
>[350272.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f710]
>[350272.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f710] width 1920 pitch 7680 (/4 1920)
>[350273.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a73f0]
>[350273.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a73f0] width 1920 pitch 7680 (/4 1920)
>[350273.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0a5b0]
>[350273.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0a5b0] width 1920 pitch 7680 (/4 1920)
>[350273.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0f00]
>[350273.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0f00] width 1920 pitch 7680 (/4 1920)
>[350273.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f755a0]
>[350273.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f755a0] width 1920 pitch 7680 (/4 1920)
>[350273.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb90e0]
>[350273.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb90e0] width 1920 pitch 7680 (/4 1920)
>[350273.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350274.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350274.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3950]
>[350274.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3950] width 1920 pitch 7680 (/4 1920)
>[350274.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[350274.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[350276.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26250f0]
>[350276.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26250f0] width 1920 pitch 7680 (/4 1920)
>[350276.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92350]
>[350277.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92350] width 1920 pitch 7680 (/4 1920)
>[350277.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc5f0]
>[350278.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc5f0] width 1920 pitch 7680 (/4 1920)
>[350278.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa3ee0]
>[350278.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa3ee0] width 1920 pitch 7680 (/4 1920)
>[350279.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240a070]
>[350279.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240a070] width 1920 pitch 7680 (/4 1920)
>[350279.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4de0]
>[350279.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4de0] width 1920 pitch 7680 (/4 1920)
>[350279.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0e2f0]
>[350279.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0e2f0] width 1920 pitch 7680 (/4 1920)
>[350280.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[350280.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[350281.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebd110]
>[350281.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebd110] width 1920 pitch 7680 (/4 1920)
>[350282.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[350282.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[350283.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350283.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350283.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3950]
>[350283.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3950] width 1920 pitch 7680 (/4 1920)
>[350284.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[350284.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1920 pitch 7680 (/4 1920)
>[350284.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3950]
>[350285.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3950] width 1920 pitch 7680 (/4 1920)
>[350285.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[350286.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1920 pitch 7680 (/4 1920)
>[350287.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44df0]
>[350287.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44df0] width 1920 pitch 7680 (/4 1920)
>[350289.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2930]
>[350289.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2930] width 1920 pitch 7680 (/4 1920)
>[350291.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44df0]
>[350291.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44df0] width 1920 pitch 7680 (/4 1920)
>[350292.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[350292.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[350292.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[350293.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1920 pitch 7680 (/4 1920)
>[350293.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[350293.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1920 pitch 7680 (/4 1920)
>[350294.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6adb480]
>[350294.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6adb480] width 1920 pitch 7680 (/4 1920)
>[350295.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44d10]
>[350295.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44d10] width 1920 pitch 7680 (/4 1920)
>[350295.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db2c10]
>[350295.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db2c10] width 1920 pitch 7680 (/4 1920)
>[350296.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x282b4c0]
>[350296.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x282b4c0] width 1920 pitch 7680 (/4 1920)
>[350296.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807f0]
>[350296.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807f0] width 1920 pitch 7680 (/4 1920)
>[350297.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350297.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350297.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d53860]
>[350297.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d53860] width 1920 pitch 7680 (/4 1920)
>[350298.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350298.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350298.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350298.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350298.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350298.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350298.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350298.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350299.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[350299.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[350299.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29010]
>[350299.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29010] width 1920 pitch 7680 (/4 1920)
>[350299.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[350300.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[350302.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29010]
>[350302.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29010] width 1920 pitch 7680 (/4 1920)
>[350303.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[350303.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[350304.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[350304.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1920 pitch 7680 (/4 1920)
>[350304.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[350304.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[350304.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[350304.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1920 pitch 7680 (/4 1920)
>[350304.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[350304.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[350305.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f46c20]
>[350305.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f46c20] width 1920 pitch 7680 (/4 1920)
>[350306.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce46f0]
>[350306.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce46f0] width 1920 pitch 7680 (/4 1920)
>[350306.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4de0]
>[350306.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4de0] width 1920 pitch 7680 (/4 1920)
>[350306.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce46f0]
>[350307.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce46f0] width 1920 pitch 7680 (/4 1920)
>[350307.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab38b0]
>[350307.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab38b0] width 1920 pitch 7680 (/4 1920)
>[350307.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebd110]
>[350307.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebd110] width 1920 pitch 7680 (/4 1920)
>[350307.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab38b0]
>[350307.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab38b0] width 1920 pitch 7680 (/4 1920)
>[350308.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[350308.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[350358.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[350359.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[350359.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09360]
>[350359.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09360] width 1920 pitch 7680 (/4 1920)
>[350359.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a36200]
>[350359.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a36200] width 1920 pitch 7680 (/4 1920)
>[350387.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f755a0]
>[350387.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f755a0] width 1920 pitch 7680 (/4 1920)
>[350388.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f29010]
>[350388.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f29010] width 1920 pitch 7680 (/4 1920)
>[350390.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[350390.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1920 pitch 7680 (/4 1920)
>[350390.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6a00]
>[350390.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6a00] width 1920 pitch 7680 (/4 1920)
>[350390.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec2930]
>[350390.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec2930] width 1920 pitch 7680 (/4 1920)
>[350391.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd3950]
>[350391.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd3950] width 1920 pitch 7680 (/4 1920)
>[350391.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[350392.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[350392.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x240eb30]
>[350392.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x240eb30] width 1920 pitch 7680 (/4 1920)
>[350392.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f807f0]
>[350392.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f807f0] width 1920 pitch 7680 (/4 1920)
>[350393.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[350393.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[350393.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f134a0]
>[350393.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f134a0] width 1920 pitch 7680 (/4 1920)
>[350393.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1ab10]
>[350393.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1ab10] width 1920 pitch 7680 (/4 1920)
>[350393.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f134a0]
>[350393.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f134a0] width 1920 pitch 7680 (/4 1920)
>[350393.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a73f0]
>[350393.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a73f0] width 1920 pitch 7680 (/4 1920)
>[350393.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f134a0]
>[350393.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f134a0] width 1920 pitch 7680 (/4 1920)
>[350393.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a73f0]
>[350393.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a73f0] width 1920 pitch 7680 (/4 1920)
>[350434.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350434.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350434.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fe2d0]
>[350434.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fe2d0] width 1920 pitch 7680 (/4 1920)
>[350434.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fe2d0]
>[350434.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fe2d0] width 1920 pitch 7680 (/4 1920)
>[350434.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[350434.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1920 pitch 7680 (/4 1920)
>[350434.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350434.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350434.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b254e0]
>[350434.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b254e0] width 1920 pitch 7680 (/4 1920)
>[350434.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046790]
>[350434.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046790] width 1920 pitch 7680 (/4 1920)
>[350434.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4b090]
>[350434.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4b090] width 1920 pitch 7680 (/4 1920)
>[350434.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6998260]
>[350434.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6998260] width 1920 pitch 7680 (/4 1920)
>[350434.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046790]
>[350435.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046790] width 1920 pitch 7680 (/4 1920)
>[350435.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b254e0]
>[350435.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b254e0] width 1920 pitch 7680 (/4 1920)
>[350435.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350435.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350435.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[350435.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1920 pitch 7680 (/4 1920)
>[350435.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350435.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350435.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aff970]
>[350435.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aff970] width 1920 pitch 7680 (/4 1920)
>[350435.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350435.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350435.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a8b0]
>[350435.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a8b0] width 1920 pitch 7680 (/4 1920)
>[350435.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350435.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350435.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350435.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350436.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350436.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350436.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4046790]
>[350436.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4046790] width 1920 pitch 7680 (/4 1920)
>[350436.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[350436.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1920 pitch 7680 (/4 1920)
>[350436.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a8b0]
>[350436.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a8b0] width 1920 pitch 7680 (/4 1920)
>[350436.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350436.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350436.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c350f0]
>[350436.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c350f0] width 1920 pitch 7680 (/4 1920)
>[350437.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350437.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350437.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350437.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350437.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aff970]
>[350437.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aff970] width 1920 pitch 7680 (/4 1920)
>[350437.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3e60]
>[350437.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3e60] width 1920 pitch 7680 (/4 1920)
>[350437.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[350437.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1920 pitch 7680 (/4 1920)
>[350438.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350438.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350438.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c51140]
>[350438.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c51140] width 1920 pitch 7680 (/4 1920)
>[350438.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75e80]
>[350438.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75e80] width 1920 pitch 7680 (/4 1920)
>[350438.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b254e0]
>[350438.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b254e0] width 1920 pitch 7680 (/4 1920)
>[350438.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350438.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350453.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350454.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350454.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a8b0]
>[350454.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a8b0] width 1920 pitch 7680 (/4 1920)
>[350454.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b254e0]
>[350454.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b254e0] width 1920 pitch 7680 (/4 1920)
>[350454.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[350454.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1920 pitch 7680 (/4 1920)
>[350454.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3e60]
>[350454.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3e60] width 1920 pitch 7680 (/4 1920)
>[350454.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aff970]
>[350454.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aff970] width 1920 pitch 7680 (/4 1920)
>[350455.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c77770]
>[350455.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c77770] width 1920 pitch 7680 (/4 1920)
>[350455.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350455.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350455.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c51140]
>[350455.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c51140] width 1920 pitch 7680 (/4 1920)
>[350456.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75e80]
>[350456.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75e80] width 1920 pitch 7680 (/4 1920)
>[350456.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fe2d0]
>[350456.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fe2d0] width 1920 pitch 7680 (/4 1920)
>[350456.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350456.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350456.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350456.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350456.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b254e0]
>[350457.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b254e0] width 1920 pitch 7680 (/4 1920)
>[350457.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c77770]
>[350457.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c77770] width 1920 pitch 7680 (/4 1920)
>[350457.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a8b0]
>[350457.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a8b0] width 1920 pitch 7680 (/4 1920)
>[350457.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bed80]
>[350457.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bed80] width 1920 pitch 7680 (/4 1920)
>[350457.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e34860]
>[350457.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e34860] width 1920 pitch 7680 (/4 1920)
>[350458.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75e80]
>[350458.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75e80] width 1920 pitch 7680 (/4 1920)
>[350466.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75e80]
>[350466.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75e80] width 1920 pitch 7680 (/4 1920)
>[350466.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7c740]
>[350466.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7c740] width 1920 pitch 7680 (/4 1920)
>[350466.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2e50]
>[350466.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2e50] width 1920 pitch 7680 (/4 1920)
>[350466.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c77770]
>[350466.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c77770] width 1920 pitch 7680 (/4 1920)
>[350466.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec0be0]
>[350466.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec0be0] width 1920 pitch 7680 (/4 1920)
>[350466.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a8b0]
>[350466.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a8b0] width 1920 pitch 7680 (/4 1920)
>[350466.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3aff970]
>[350467.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3aff970] width 1920 pitch 7680 (/4 1920)
>[350467.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f40010]
>[350467.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f40010] width 1920 pitch 7680 (/4 1920)
>[350467.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350467.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350467.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ab30]
>[350467.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ab30] width 1920 pitch 7680 (/4 1920)
>[350467.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75640]
>[350468.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75640] width 1920 pitch 7680 (/4 1920)
>[350468.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6ab30]
>[350468.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6ab30] width 1920 pitch 7680 (/4 1920)
>[350468.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f75640]
>[350468.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f75640] width 1920 pitch 7680 (/4 1920)
>[350468.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a810]
>[350468.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a810] width 1920 pitch 7680 (/4 1920)
>[350587.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350587.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350587.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040110]
>[350587.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040110] width 1920 pitch 7680 (/4 1920)
>[350587.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[350587.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[350587.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350587.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350587.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350587.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350587.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c4f0]
>[350587.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c4f0] width 1920 pitch 7680 (/4 1920)
>[350587.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350587.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350587.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350587.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350587.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350587.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350587.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350588.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350588.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350588.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350588.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350588.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350588.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350588.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350588.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350588.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350588.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350588.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350592.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350592.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350592.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350592.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350592.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350592.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350592.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350592.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350592.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350592.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350592.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350592.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350592.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350592.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350594.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c4f0]
>[350594.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c4f0] width 1920 pitch 7680 (/4 1920)
>[350594.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350594.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350601.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350601.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350601.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350601.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350601.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350601.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350601.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350601.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350601.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350601.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350601.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350601.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350605.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350605.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350605.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350605.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350605.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350605.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350605.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350605.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350605.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350605.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350605.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350605.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350605.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350605.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350655.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350655.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350655.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350655.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350655.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350655.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350655.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040110]
>[350655.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040110] width 1920 pitch 7680 (/4 1920)
>[350655.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350655.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350655.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350655.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350656.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350656.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350656.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350656.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350656.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350656.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350656.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350656.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350656.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350656.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350656.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350656.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350657.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350657.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350657.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350657.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350657.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350657.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350657.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350657.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350657.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350657.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350657.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350657.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350657.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350657.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350657.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c4f0]
>[350658.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c4f0] width 1920 pitch 7680 (/4 1920)
>[350658.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350658.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350677.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350677.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350677.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350677.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350677.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c4f0]
>[350677.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c4f0] width 1920 pitch 7680 (/4 1920)
>[350684.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c4f0]
>[350684.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c4f0] width 1920 pitch 7680 (/4 1920)
>[350684.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350684.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350684.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350684.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350684.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350684.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350684.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350684.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350692.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350692.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350692.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aaf8b0]
>[350692.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aaf8b0] width 1920 pitch 7680 (/4 1920)
>[350692.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350692.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350692.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[350692.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[350692.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a3d0]
>[350692.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a3d0] width 1920 pitch 7680 (/4 1920)
>[350692.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350692.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350692.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[350692.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[350692.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de0f80]
>[350692.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de0f80] width 1920 pitch 7680 (/4 1920)
>[350786.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f759f0]
>[350786.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f759f0] width 1920 pitch 7680 (/4 1920)
>[350786.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350786.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350786.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f759f0]
>[350786.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f759f0] width 1920 pitch 7680 (/4 1920)
>[350786.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350786.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350786.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f759f0]
>[350786.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f759f0] width 1920 pitch 7680 (/4 1920)
>[350786.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350786.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350786.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f759f0]
>[350786.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f759f0] width 1920 pitch 7680 (/4 1920)
>[350879.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350879.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350879.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350879.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350879.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350879.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350879.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350879.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350879.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350879.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350879.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350879.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350882.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[350882.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[350882.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3600]
>[350883.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3600] width 1920 pitch 7680 (/4 1920)
>[350883.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9ef0]
>[350883.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9ef0] width 1920 pitch 7680 (/4 1920)
>[350883.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3600]
>[350883.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3600] width 1920 pitch 7680 (/4 1920)
>[350883.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[350883.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[350883.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[350883.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[350883.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[350883.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[350922.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ddf400]
>[350922.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ddf400] width 1920 pitch 7680 (/4 1920)
>[350923.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350923.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350923.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[350923.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[350923.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350923.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350923.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[350923.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[350923.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350923.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350924.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[350924.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[350925.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[350926.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[350926.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350926.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[350926.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[350926.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[350926.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2f360]
>[350926.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2f360] width 1920 pitch 7680 (/4 1920)
>[351000.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[351000.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[351000.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a0e0]
>[351000.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a0e0] width 1920 pitch 7680 (/4 1920)
>[351000.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[351000.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[351000.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[351000.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[351005.492] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[351005.493] (II) RADEON(0): Using hsync ranges from config file
>[351005.493] (II) RADEON(0): Using vrefresh ranges from config file
>[351005.493] (II) RADEON(0): Printing DDC gathered Modelines:
>[351005.493] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[351005.493] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[351005.493] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[351005.493] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[351005.493] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[351005.493] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[351005.493] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[351005.493] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[351005.493] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[351005.493] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[351005.493] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[351395.742] (II) RADEON(0): RADEONSaveScreen(2)
>[351395.742] (II) RADEON(0): RADEONSaveScreen(0)
>[360259.630] (II) RADEON(0): RADEONSaveScreen(1)
>[360649.747] (II) RADEON(0): RADEONSaveScreen(2)
>[360649.747] (II) RADEON(0): RADEONSaveScreen(0)
>[391425.768] (II) RADEON(0): RADEONSaveScreen(1)
>[391430.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a0e0]
>[391430.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a0e0] width 1920 pitch 7680 (/4 1920)
>[391434.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[391434.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1920 pitch 7680 (/4 1920)
>[391435.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388a300]
>[391435.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388a300] width 1920 pitch 7680 (/4 1920)
>[391440.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[391440.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[391440.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0260]
>[391440.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0260] width 1920 pitch 7680 (/4 1920)
>[391440.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[391440.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[391440.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0260]
>[391440.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0260] width 1920 pitch 7680 (/4 1920)
>[391440.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[391440.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[391440.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0260]
>[391440.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0260] width 1920 pitch 7680 (/4 1920)
>[391440.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[391440.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[391449.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d506e0]
>[391449.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d506e0] width 1920 pitch 7680 (/4 1920)
>[391450.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25f9da0]
>[391450.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25f9da0] width 1920 pitch 7680 (/4 1920)
>[391454.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[391454.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[391457.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54d20]
>[391457.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54d20] width 1920 pitch 7680 (/4 1920)
>[391462.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f759f0]
>[391462.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f759f0] width 1920 pitch 7680 (/4 1920)
>[391466.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[391466.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[391469.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[391469.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1920 pitch 7680 (/4 1920)
>[391469.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4ddd0]
>[391469.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4ddd0] width 1920 pitch 7680 (/4 1920)
>[391469.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a0e0]
>[391470.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a0e0] width 1920 pitch 7680 (/4 1920)
>[391470.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x400a0e0]
>[391470.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x400a0e0] width 1920 pitch 7680 (/4 1920)
>[391485.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[391485.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1920 pitch 7680 (/4 1920)
>[391485.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54d20]
>[391485.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54d20] width 1920 pitch 7680 (/4 1920)
>[391485.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[391485.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[391496.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a14bf0]
>[391496.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a14bf0] width 1920 pitch 7680 (/4 1920)
>[391497.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[391497.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[391497.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[391497.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[391497.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7940]
>[391497.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7940] width 1920 pitch 7680 (/4 1920)
>[391497.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f4cf0]
>[391498.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f4cf0] width 1920 pitch 7680 (/4 1920)
>[391498.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388a300]
>[391498.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388a300] width 1920 pitch 7680 (/4 1920)
>[391498.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f4cf0]
>[391498.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f4cf0] width 1920 pitch 7680 (/4 1920)
>[391840.240] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[391840.240] (II) RADEON(0): Using hsync ranges from config file
>[391840.240] (II) RADEON(0): Using vrefresh ranges from config file
>[391840.240] (II) RADEON(0): Printing DDC gathered Modelines:
>[391840.240] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[391840.240] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[391840.240] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[391840.240] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[391840.240] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[391840.240] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[391840.240] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[391840.241] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[391840.241] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[391840.241] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[391840.241] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[391840.241] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[391930.751] (II) RADEON(0): RADEONSaveScreen(2)
>[391930.751] (II) RADEON(0): RADEONSaveScreen(0)
>[430634.398] (II) RADEON(0): RADEONSaveScreen(1)
>[431024.742] (II) RADEON(0): RADEONSaveScreen(2)
>[431024.742] (II) RADEON(0): RADEONSaveScreen(0)
>[431082.100] (II) RADEON(0): RADEONSaveScreen(1)
>[431426.210] (II) config/udev: removing device VISENTA V1 
>[431426.211] (II) evdev: VISENTA V1 : Close
>[431426.211] (II) UnloadModule: "evdev"
>[431426.236] (II) config/udev: removing device VISENTA V1 
>[431426.238] (II) evdev: VISENTA V1 : Close
>[431426.238] (II) UnloadModule: "evdev"
>[431795.751] (II) RADEON(0): RADEONSaveScreen(2)
>[431795.751] (II) RADEON(0): RADEONSaveScreen(0)
>[434828.906] (II) RADEON(0): RADEONSaveScreen(1)
>[435219.751] (II) RADEON(0): RADEONSaveScreen(2)
>[435219.751] (II) RADEON(0): RADEONSaveScreen(0)
>[449556.536] (II) RADEON(0): RADEONSaveScreen(1)
>[449946.743] (II) RADEON(0): RADEONSaveScreen(2)
>[449946.743] (II) RADEON(0): RADEONSaveScreen(0)
>[559681.648] (II) RADEON(0): RADEONSaveScreen(1)
>[559694.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4e750]
>[559694.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4e750] width 1920 pitch 7680 (/4 1920)
>[559694.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[559694.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[559694.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[559694.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[559694.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[559694.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[559694.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[559695.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[559695.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[559695.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[559695.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[559695.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[559698.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[559698.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[559698.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[559698.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[559698.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32480]
>[559698.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32480] width 1920 pitch 7680 (/4 1920)
>[559699.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[559699.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[559699.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7bcc0]
>[559699.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7bcc0] width 1920 pitch 7680 (/4 1920)
>[559699.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f17160]
>[559699.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f17160] width 1920 pitch 7680 (/4 1920)
>[559699.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[559699.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[559700.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[559700.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1920 pitch 7680 (/4 1920)
>[559700.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0980]
>[559700.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0980] width 1920 pitch 7680 (/4 1920)
>[559700.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f323e0]
>[559701.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f323e0] width 1920 pitch 7680 (/4 1920)
>[559701.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5025ba0]
>[559702.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5025ba0] width 1920 pitch 7680 (/4 1920)
>[559702.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54d20]
>[559702.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54d20] width 1920 pitch 7680 (/4 1920)
>[559702.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40311c0]
>[559703.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40311c0] width 1920 pitch 7680 (/4 1920)
>[559719.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a30af0]
>[559719.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a30af0] width 1920 pitch 7680 (/4 1920)
>[559720.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[559720.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[559720.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d820]
>[559720.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d820] width 1920 pitch 7680 (/4 1920)
>[559721.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32480]
>[559721.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32480] width 1920 pitch 7680 (/4 1920)
>[559721.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[559721.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[559722.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32480]
>[559722.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32480] width 1920 pitch 7680 (/4 1920)
>[559722.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[559722.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[559723.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d820]
>[559723.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d820] width 1920 pitch 7680 (/4 1920)
>[559723.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d820]
>[559723.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d820] width 1920 pitch 7680 (/4 1920)
>[559723.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba8770]
>[559723.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba8770] width 1920 pitch 7680 (/4 1920)
>[559723.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc9f00]
>[559724.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc9f00] width 1920 pitch 7680 (/4 1920)
>[559725.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[559726.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[559726.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3940030]
>[559726.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3940030] width 1920 pitch 7680 (/4 1920)
>[559726.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebcdb0]
>[559726.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebcdb0] width 1920 pitch 7680 (/4 1920)
>[559727.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559727.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559727.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559727.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559727.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559727.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559727.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559727.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559728.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559728.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559728.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559728.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559728.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559728.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559729.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559729.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559729.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559729.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559729.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559729.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559730.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9400]
>[559730.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9400] width 1920 pitch 7680 (/4 1920)
>[559730.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b039b0]
>[559730.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b039b0] width 1920 pitch 7680 (/4 1920)
>[559730.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2860250]
>[559731.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2860250] width 1920 pitch 7680 (/4 1920)
>[559731.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c98220]
>[559731.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c98220] width 1920 pitch 7680 (/4 1920)
>[559731.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd940]
>[559731.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd940] width 1920 pitch 7680 (/4 1920)
>[559753.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8b080]
>[559754.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8b080] width 1920 pitch 7680 (/4 1920)
>[559754.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ca2d0]
>[559754.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ca2d0] width 1920 pitch 7680 (/4 1920)
>[559754.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9aa20]
>[559754.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9aa20] width 1920 pitch 7680 (/4 1920)
>[559758.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4d60]
>[559758.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4d60] width 1920 pitch 7680 (/4 1920)
>[559758.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686b9b0]
>[559758.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686b9b0] width 1920 pitch 7680 (/4 1920)
>[559758.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4d60]
>[559758.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4d60] width 1920 pitch 7680 (/4 1920)
>[559758.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686b9b0]
>[559758.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686b9b0] width 1920 pitch 7680 (/4 1920)
>[559760.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f998e0]
>[559760.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f998e0] width 1920 pitch 7680 (/4 1920)
>[559760.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1c30]
>[559760.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1c30] width 1920 pitch 7680 (/4 1920)
>[559760.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd1c30]
>[559760.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd1c30] width 1920 pitch 7680 (/4 1920)
>[559760.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6260]
>[559760.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6260] width 1920 pitch 7680 (/4 1920)
>[559760.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e326e0]
>[559760.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e326e0] width 1920 pitch 7680 (/4 1920)
>[559773.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ef1a0]
>[559773.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ef1a0] width 1920 pitch 7680 (/4 1920)
>[559799.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee1ce0]
>[559799.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee1ce0] width 1920 pitch 7680 (/4 1920)
>[559810.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c3520]
>[559810.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c3520] width 1920 pitch 7680 (/4 1920)
>[559813.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50254d0]
>[559813.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50254d0] width 1920 pitch 7680 (/4 1920)
>[559813.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9aa20]
>[559813.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9aa20] width 1920 pitch 7680 (/4 1920)
>[559813.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6fe0]
>[559813.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6fe0] width 1920 pitch 7680 (/4 1920)
>[559813.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de2170]
>[559813.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de2170] width 1920 pitch 7680 (/4 1920)
>[559814.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e27a0]
>[559814.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e27a0] width 1920 pitch 7680 (/4 1920)
>[559818.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6fe0]
>[559818.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6fe0] width 1920 pitch 7680 (/4 1920)
>[559819.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699fe80]
>[559819.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699fe80] width 1920 pitch 7680 (/4 1920)
>[559821.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d84b0]
>[559821.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d84b0] width 1920 pitch 7680 (/4 1920)
>[559821.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd9c0]
>[559821.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd9c0] width 1920 pitch 7680 (/4 1920)
>[559821.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d84b0]
>[559821.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d84b0] width 1920 pitch 7680 (/4 1920)
>[559821.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc4ac0]
>[559821.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc4ac0] width 1920 pitch 7680 (/4 1920)
>[559823.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69f4b60]
>[559823.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69f4b60] width 1920 pitch 7680 (/4 1920)
>[559824.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad84f0]
>[559824.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad84f0] width 1920 pitch 7680 (/4 1920)
>[559824.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284fbd0]
>[559824.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284fbd0] width 1920 pitch 7680 (/4 1920)
>[559825.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284fbd0]
>[559825.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284fbd0] width 1920 pitch 7680 (/4 1920)
>[560355.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c85f80]
>[560355.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c85f80] width 1920 pitch 7680 (/4 1920)
>[560361.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e2840]
>[560361.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e2840] width 1920 pitch 7680 (/4 1920)
>[560361.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c728f0]
>[560361.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c728f0] width 1920 pitch 7680 (/4 1920)
>[560361.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512d9e0]
>[560361.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512d9e0] width 1920 pitch 7680 (/4 1920)
>[560361.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef9f90]
>[560361.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef9f90] width 1920 pitch 7680 (/4 1920)
>[560361.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad9290]
>[560361.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad9290] width 1920 pitch 7680 (/4 1920)
>[560361.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a6fe0]
>[560361.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a6fe0] width 1920 pitch 7680 (/4 1920)
>[560467.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b6200]
>[560468.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b6200] width 1920 pitch 7680 (/4 1920)
>[560468.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a6160]
>[560468.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a6160] width 1920 pitch 7680 (/4 1920)
>[560468.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b6200]
>[560468.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b6200] width 1920 pitch 7680 (/4 1920)
>[560468.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27a6160]
>[560468.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27a6160] width 1920 pitch 7680 (/4 1920)
>[560468.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b6200]
>[560468.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b6200] width 1920 pitch 7680 (/4 1920)
>[560472.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53640]
>[560472.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53640] width 1920 pitch 7680 (/4 1920)
>[560472.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee080]
>[560472.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee080] width 1920 pitch 7680 (/4 1920)
>[560472.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e747d0]
>[560472.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e747d0] width 1920 pitch 7680 (/4 1920)
>[560472.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee080]
>[560472.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee080] width 1920 pitch 7680 (/4 1920)
>[560473.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5fb70]
>[560473.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5fb70] width 1920 pitch 7680 (/4 1920)
>[560542.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2e6d0]
>[560542.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2e6d0] width 1920 pitch 7680 (/4 1920)
>[560569.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afc4a0]
>[560569.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afc4a0] width 1920 pitch 7680 (/4 1920)
>[560585.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3aa70]
>[560586.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3aa70] width 1920 pitch 7680 (/4 1920)
>[560586.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7def0]
>[560586.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7def0] width 1920 pitch 7680 (/4 1920)
>[560586.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e010]
>[560586.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e010] width 1920 pitch 7680 (/4 1920)
>[560586.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a410]
>[560586.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a410] width 1920 pitch 7680 (/4 1920)
>[560587.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4afdc50]
>[560587.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4afdc50] width 1920 pitch 7680 (/4 1920)
>[560587.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e010]
>[560587.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e010] width 1920 pitch 7680 (/4 1920)
>[560587.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6560]
>[560587.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6560] width 1920 pitch 7680 (/4 1920)
>[560587.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b27720]
>[560587.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b27720] width 1920 pitch 7680 (/4 1920)
>[560587.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea330]
>[560587.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea330] width 1920 pitch 7680 (/4 1920)
>[560587.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6560]
>[560587.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6560] width 1920 pitch 7680 (/4 1920)
>[560587.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de9e50]
>[560587.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de9e50] width 1920 pitch 7680 (/4 1920)
>[560587.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6560]
>[560587.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6560] width 1920 pitch 7680 (/4 1920)
>[560587.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea330]
>[560587.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea330] width 1920 pitch 7680 (/4 1920)
>[560587.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e010]
>[560587.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e010] width 1920 pitch 7680 (/4 1920)
>[560587.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a4c0]
>[560587.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a4c0] width 1920 pitch 7680 (/4 1920)
>[560588.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e010]
>[560588.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e010] width 1920 pitch 7680 (/4 1920)
>[560588.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e010]
>[560588.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e010] width 1920 pitch 7680 (/4 1920)
>[560588.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f13840]
>[560588.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f13840] width 1920 pitch 7680 (/4 1920)
>[560615.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6490]
>[560615.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6490] width 1920 pitch 7680 (/4 1920)
>[560616.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6490]
>[560616.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6490] width 1920 pitch 7680 (/4 1920)
>[560616.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea330]
>[560616.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea330] width 1920 pitch 7680 (/4 1920)
>[560616.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab6490]
>[560616.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab6490] width 1920 pitch 7680 (/4 1920)
>[560616.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea330]
>[560616.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea330] width 1920 pitch 7680 (/4 1920)
>[560616.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe730]
>[560617.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe730] width 1920 pitch 7680 (/4 1920)
>[560617.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8ada0]
>[560617.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8ada0] width 1920 pitch 7680 (/4 1920)
>[560617.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b53ad0]
>[560617.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b53ad0] width 1920 pitch 7680 (/4 1920)
>[560617.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38399d0]
>[560617.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38399d0] width 1920 pitch 7680 (/4 1920)
>[560624.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0a790]
>[560624.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0a790] width 1920 pitch 7680 (/4 1920)
>[560627.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3a6d0]
>[560627.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3a6d0] width 1920 pitch 7680 (/4 1920)
>[560627.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97e60]
>[560627.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97e60] width 1920 pitch 7680 (/4 1920)
>[560627.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53890]
>[560628.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53890] width 1920 pitch 7680 (/4 1920)
>[560628.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3a6d0]
>[560628.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3a6d0] width 1920 pitch 7680 (/4 1920)
>[560628.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53890]
>[560628.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53890] width 1920 pitch 7680 (/4 1920)
>[560628.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f53890]
>[560628.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f53890] width 1920 pitch 7680 (/4 1920)
>[560628.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b8a50]
>[560628.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b8a50] width 1920 pitch 7680 (/4 1920)
>[560629.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f7dfb0]
>[560629.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f7dfb0] width 1920 pitch 7680 (/4 1920)
>[560629.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab1700]
>[560629.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab1700] width 1920 pitch 7680 (/4 1920)
>[560707.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0cd0]
>[560707.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0cd0] width 1920 pitch 7680 (/4 1920)
>[560707.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e15380]
>[560707.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e15380] width 1920 pitch 7680 (/4 1920)
>[560707.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971710]
>[560707.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971710] width 1920 pitch 7680 (/4 1920)
>[560708.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[560709.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[560709.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971710]
>[560709.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971710] width 1920 pitch 7680 (/4 1920)
>[560710.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a9c0]
>[560710.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a9c0] width 1920 pitch 7680 (/4 1920)
>[560710.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971710]
>[560710.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971710] width 1920 pitch 7680 (/4 1920)
>[560711.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd0cd0]
>[560711.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd0cd0] width 1920 pitch 7680 (/4 1920)
>[560711.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e15380]
>[560711.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e15380] width 1920 pitch 7680 (/4 1920)
>[560712.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a9c0]
>[560712.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a9c0] width 1920 pitch 7680 (/4 1920)
>[560713.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c550f0]
>[560713.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c550f0] width 1920 pitch 7680 (/4 1920)
>[560725.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a9c0]
>[560725.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a9c0] width 1920 pitch 7680 (/4 1920)
>[560725.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4e0b0]
>[560725.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4e0b0] width 1920 pitch 7680 (/4 1920)
>[560725.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e15380]
>[560726.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e15380] width 1920 pitch 7680 (/4 1920)
>[560726.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971710]
>[560726.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971710] width 1920 pitch 7680 (/4 1920)
>[560726.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[560726.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[560727.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef3300]
>[560727.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef3300] width 1920 pitch 7680 (/4 1920)
>[560727.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[560727.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[560727.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560727.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560727.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[560727.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[560727.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560727.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560727.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[560727.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[560728.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560728.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560728.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb1d40]
>[560728.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb1d40] width 1920 pitch 7680 (/4 1920)
>[560729.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560729.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560729.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[560729.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1920 pitch 7680 (/4 1920)
>[560729.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[560729.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[560729.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[560730.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1920 pitch 7680 (/4 1920)
>[560730.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[560730.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[560730.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[560730.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1920 pitch 7680 (/4 1920)
>[560730.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d837b0]
>[560730.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d837b0] width 1920 pitch 7680 (/4 1920)
>[560730.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fde1b0]
>[560730.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fde1b0] width 1920 pitch 7680 (/4 1920)
>[560731.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0980]
>[560731.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0980] width 1920 pitch 7680 (/4 1920)
>[560731.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0980]
>[560731.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0980] width 1920 pitch 7680 (/4 1920)
>[560732.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[560732.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[560732.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5025ba0]
>[560732.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5025ba0] width 1920 pitch 7680 (/4 1920)
>[560732.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[560732.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[560732.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[560732.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1920 pitch 7680 (/4 1920)
>[560732.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[560732.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[560732.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[560732.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1920 pitch 7680 (/4 1920)
>[560732.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[560732.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[560733.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df5990]
>[560733.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df5990] width 1920 pitch 7680 (/4 1920)
>[560733.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[560733.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[560733.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a46d0]
>[560733.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a46d0] width 1920 pitch 7680 (/4 1920)
>[560733.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[560733.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[560733.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a46d0]
>[560733.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a46d0] width 1920 pitch 7680 (/4 1920)
>[560733.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f0e0]
>[560733.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f0e0] width 1920 pitch 7680 (/4 1920)
>[560733.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[560733.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[560734.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40311c0]
>[560734.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40311c0] width 1920 pitch 7680 (/4 1920)
>[560734.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b0980]
>[560734.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b0980] width 1920 pitch 7680 (/4 1920)
>[560734.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[560734.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[560735.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3afc0]
>[560735.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3afc0] width 1920 pitch 7680 (/4 1920)
>[560735.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a9c0]
>[560735.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a9c0] width 1920 pitch 7680 (/4 1920)
>[560735.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[560735.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[560735.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[560736.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[560736.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560736.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560736.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[560736.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1920 pitch 7680 (/4 1920)
>[560736.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e988f0]
>[560736.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e988f0] width 1920 pitch 7680 (/4 1920)
>[560737.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[560737.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[560738.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[560738.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[560738.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c72c10]
>[560738.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c72c10] width 1920 pitch 7680 (/4 1920)
>[560739.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[560739.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[560739.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a93f0]
>[560739.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a93f0] width 1920 pitch 7680 (/4 1920)
>[560739.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38438e0]
>[560739.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38438e0] width 1920 pitch 7680 (/4 1920)
>[560739.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c72c10]
>[560739.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c72c10] width 1920 pitch 7680 (/4 1920)
>[560739.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[560739.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[560740.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4080]
>[560740.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4080] width 1920 pitch 7680 (/4 1920)
>[560740.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a30af0]
>[560740.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a30af0] width 1920 pitch 7680 (/4 1920)
>[560740.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4080]
>[560741.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4080] width 1920 pitch 7680 (/4 1920)
>[560741.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a30af0]
>[560741.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a30af0] width 1920 pitch 7680 (/4 1920)
>[560742.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4080]
>[560742.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4080] width 1920 pitch 7680 (/4 1920)
>[560743.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4e750]
>[560743.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4e750] width 1920 pitch 7680 (/4 1920)
>[560743.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[560743.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[560743.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c147d0]
>[560743.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c147d0] width 1920 pitch 7680 (/4 1920)
>[560743.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e15380]
>[560743.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e15380] width 1920 pitch 7680 (/4 1920)
>[560743.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c147d0]
>[560743.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c147d0] width 1920 pitch 7680 (/4 1920)
>[560748.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f323e0]
>[560748.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f323e0] width 1920 pitch 7680 (/4 1920)
>[560748.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0d0b0]
>[560748.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0d0b0] width 1920 pitch 7680 (/4 1920)
>[560748.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad4050]
>[560748.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad4050] width 1920 pitch 7680 (/4 1920)
>[560748.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e95e10]
>[560749.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e95e10] width 1920 pitch 7680 (/4 1920)
>[560749.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[560749.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[560755.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[560755.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[560759.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb540]
>[560759.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb540] width 1920 pitch 7680 (/4 1920)
>[560761.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ae110]
>[560761.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ae110] width 1920 pitch 7680 (/4 1920)
>[560761.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5da0]
>[560761.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5da0] width 1920 pitch 7680 (/4 1920)
>[560761.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ae110]
>[560761.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ae110] width 1920 pitch 7680 (/4 1920)
>[560761.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5da0]
>[560761.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5da0] width 1920 pitch 7680 (/4 1920)
>[560762.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971710]
>[560762.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971710] width 1920 pitch 7680 (/4 1920)
>[560763.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f22a90]
>[560763.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f22a90] width 1920 pitch 7680 (/4 1920)
>[560763.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7a90]
>[560763.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7a90] width 1920 pitch 7680 (/4 1920)
>[560763.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262ea0]
>[560763.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262ea0] width 1920 pitch 7680 (/4 1920)
>[560763.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7a90]
>[560763.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7a90] width 1920 pitch 7680 (/4 1920)
>[560763.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4262ea0]
>[560763.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4262ea0] width 1920 pitch 7680 (/4 1920)
>[560774.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a2e2a0]
>[560774.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a2e2a0] width 1920 pitch 7680 (/4 1920)
>[560775.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[560775.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1920 pitch 7680 (/4 1920)
>[560809.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[560809.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[560811.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[560811.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[560811.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398ca60]
>[560811.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398ca60] width 1920 pitch 7680 (/4 1920)
>[560820.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b0e0]
>[560820.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b0e0] width 1920 pitch 7680 (/4 1920)
>[560821.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc6be0]
>[560821.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc6be0] width 1920 pitch 7680 (/4 1920)
>[560821.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3b0e0]
>[560821.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3b0e0] width 1920 pitch 7680 (/4 1920)
>[560830.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5a030]
>[560830.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5a030] width 1920 pitch 7680 (/4 1920)
>[560830.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d94040]
>[560830.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d94040] width 1920 pitch 7680 (/4 1920)
>[560831.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5a030]
>[560831.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5a030] width 1920 pitch 7680 (/4 1920)
>[560838.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6e250]
>[560838.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6e250] width 1920 pitch 7680 (/4 1920)
>[560838.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3886890]
>[560838.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3886890] width 1920 pitch 7680 (/4 1920)
>[560839.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49f20]
>[560839.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49f20] width 1920 pitch 7680 (/4 1920)
>[560847.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef9120]
>[560847.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef9120] width 1920 pitch 7680 (/4 1920)
>[560852.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58538a0]
>[560852.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58538a0] width 1920 pitch 7680 (/4 1920)
>[560852.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced0f0]
>[560852.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced0f0] width 1920 pitch 7680 (/4 1920)
>[560855.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e97100]
>[560855.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e97100] width 1920 pitch 7680 (/4 1920)
>[560866.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ade6b0]
>[560867.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ade6b0] width 1920 pitch 7680 (/4 1920)
>[560878.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea2920]
>[560878.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea2920] width 1920 pitch 7680 (/4 1920)
>[560915.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3971770]
>[560915.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3971770] width 1920 pitch 7680 (/4 1920)
>[560923.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a32900]
>[560923.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a32900] width 1920 pitch 7680 (/4 1920)
>[560980.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecf870]
>[560980.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecf870] width 1920 pitch 7680 (/4 1920)
>[560982.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b456b0]
>[560982.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b456b0] width 1920 pitch 7680 (/4 1920)
>[561041.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057e50]
>[561041.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057e50] width 1920 pitch 7680 (/4 1920)
>[561097.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb05a0]
>[561097.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb05a0] width 1920 pitch 7680 (/4 1920)
>[561100.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e707c0]
>[561100.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e707c0] width 1920 pitch 7680 (/4 1920)
>[561119.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e82ed0]
>[561119.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e82ed0] width 1920 pitch 7680 (/4 1920)
>[561156.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5057cb0]
>[561156.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5057cb0] width 1920 pitch 7680 (/4 1920)
>[561171.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f49f70]
>[561171.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f49f70] width 1920 pitch 7680 (/4 1920)
>[561173.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3010090]
>[561173.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3010090] width 1920 pitch 7680 (/4 1920)
>[561179.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b59720]
>[561179.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b59720] width 1920 pitch 7680 (/4 1920)
>[561227.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b45020]
>[561227.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b45020] width 1920 pitch 7680 (/4 1920)
>[561267.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36270]
>[561267.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36270] width 1920 pitch 7680 (/4 1920)
>[561269.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc45d0]
>[561269.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc45d0] width 1920 pitch 7680 (/4 1920)
>[561269.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f36270]
>[561269.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f36270] width 1920 pitch 7680 (/4 1920)
>[561270.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fd40]
>[561270.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fd40] width 1920 pitch 7680 (/4 1920)
>[561303.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e74b0]
>[561303.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e74b0] width 1920 pitch 7680 (/4 1920)
>[561307.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0520]
>[561307.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0520] width 1920 pitch 7680 (/4 1920)
>[561318.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2513e20]
>[561318.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2513e20] width 1920 pitch 7680 (/4 1920)
>[561334.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea4d40]
>[561334.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea4d40] width 1920 pitch 7680 (/4 1920)
>[561342.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb0800]
>[561342.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb0800] width 1920 pitch 7680 (/4 1920)
>[561350.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3e580]
>[561350.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3e580] width 1920 pitch 7680 (/4 1920)
>[561359.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9ae20]
>[561359.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9ae20] width 1920 pitch 7680 (/4 1920)
>[561361.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x391c1e0]
>[561361.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x391c1e0] width 1920 pitch 7680 (/4 1920)
>[561385.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb03a0]
>[561385.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb03a0] width 1920 pitch 7680 (/4 1920)
>[561385.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0d0b0]
>[561385.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0d0b0] width 1920 pitch 7680 (/4 1920)
>[561385.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50770]
>[561385.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50770] width 1920 pitch 7680 (/4 1920)
>[561385.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[561385.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[561387.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea4f0]
>[561387.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea4f0] width 1920 pitch 7680 (/4 1920)
>[561387.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[561387.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[561387.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea4f0]
>[561387.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea4f0] width 1920 pitch 7680 (/4 1920)
>[561387.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[561387.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[561387.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bea4f0]
>[561387.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bea4f0] width 1920 pitch 7680 (/4 1920)
>[561388.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db3130]
>[561388.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db3130] width 1920 pitch 7680 (/4 1920)
>[561388.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0abd0]
>[561388.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0abd0] width 1920 pitch 7680 (/4 1920)
>[561388.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[561388.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[561388.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0abd0]
>[561389.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0abd0] width 1920 pitch 7680 (/4 1920)
>[561389.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[561389.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[561391.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deacd0]
>[561391.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deacd0] width 1920 pitch 7680 (/4 1920)
>[561391.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afd1e0]
>[561392.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afd1e0] width 1920 pitch 7680 (/4 1920)
>[561392.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[561392.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[561397.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853470]
>[561397.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853470] width 1920 pitch 7680 (/4 1920)
>[561398.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853470]
>[561398.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853470] width 1920 pitch 7680 (/4 1920)
>[561410.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e31ee0]
>[561410.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e31ee0] width 1920 pitch 7680 (/4 1920)
>[561412.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef22c0]
>[561412.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef22c0] width 1920 pitch 7680 (/4 1920)
>[561412.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01470]
>[561412.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01470] width 1920 pitch 7680 (/4 1920)
>[561412.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01470]
>[561412.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01470] width 1920 pitch 7680 (/4 1920)
>[561531.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86380]
>[561531.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86380] width 1920 pitch 7680 (/4 1920)
>[561532.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a324b0]
>[561532.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a324b0] width 1920 pitch 7680 (/4 1920)
>[561542.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1c60]
>[561542.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1c60] width 1920 pitch 7680 (/4 1920)
>[561546.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1c60]
>[561546.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1c60] width 1920 pitch 7680 (/4 1920)
>[561546.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1ff0]
>[561546.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1ff0] width 1920 pitch 7680 (/4 1920)
>[561546.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1ff0]
>[561546.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1ff0] width 1920 pitch 7680 (/4 1920)
>[561546.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c1ff0]
>[561546.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c1ff0] width 1920 pitch 7680 (/4 1920)
>[561552.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[561552.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[561552.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2bb50]
>[561553.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2bb50] width 1920 pitch 7680 (/4 1920)
>[561553.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3981180]
>[561553.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3981180] width 1920 pitch 7680 (/4 1920)
>[561553.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a29b0]
>[561553.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a29b0] width 1920 pitch 7680 (/4 1920)
>[561553.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a29b0]
>[561553.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a29b0] width 1920 pitch 7680 (/4 1920)
>[561559.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3919120]
>[561559.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3919120] width 1920 pitch 7680 (/4 1920)
>[561559.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561559.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561559.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561559.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561559.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561559.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561559.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561559.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561559.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561559.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561559.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561559.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561559.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561559.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561559.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561559.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561559.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561560.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561560.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561560.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561560.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561560.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561560.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4adc940]
>[561560.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4adc940] width 1920 pitch 7680 (/4 1920)
>[561560.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561560.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561560.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a3300]
>[561560.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a3300] width 1920 pitch 7680 (/4 1920)
>[561561.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c60270]
>[561561.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c60270] width 1920 pitch 7680 (/4 1920)
>[561561.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeacc0]
>[561561.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeacc0] width 1920 pitch 7680 (/4 1920)
>[561562.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8a600]
>[561562.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8a600] width 1920 pitch 7680 (/4 1920)
>[561562.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32e60]
>[561562.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32e60] width 1920 pitch 7680 (/4 1920)
>[561562.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6010]
>[561562.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6010] width 1920 pitch 7680 (/4 1920)
>[561562.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32e60]
>[561563.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32e60] width 1920 pitch 7680 (/4 1920)
>[561563.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6010]
>[561563.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6010] width 1920 pitch 7680 (/4 1920)
>[561563.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8160]
>[561563.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8160] width 1920 pitch 7680 (/4 1920)
>[561563.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6010]
>[561563.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6010] width 1920 pitch 7680 (/4 1920)
>[561563.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef8160]
>[561563.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef8160] width 1920 pitch 7680 (/4 1920)
>[561563.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6010]
>[561563.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6010] width 1920 pitch 7680 (/4 1920)
>[561563.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32e60]
>[561563.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32e60] width 1920 pitch 7680 (/4 1920)
>[561563.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e96f40]
>[561563.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e96f40] width 1920 pitch 7680 (/4 1920)
>[561563.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a6010]
>[561563.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a6010] width 1920 pitch 7680 (/4 1920)
>[561564.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b350]
>[561564.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b350] width 1920 pitch 7680 (/4 1920)
>[561564.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeacc0]
>[561564.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeacc0] width 1920 pitch 7680 (/4 1920)
>[561571.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561571.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561571.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9a0]
>[561571.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9a0] width 1920 pitch 7680 (/4 1920)
>[561572.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32e60]
>[561572.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32e60] width 1920 pitch 7680 (/4 1920)
>[561572.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9a0]
>[561572.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9a0] width 1920 pitch 7680 (/4 1920)
>[561572.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32e60]
>[561572.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32e60] width 1920 pitch 7680 (/4 1920)
>[561572.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc9a0]
>[561572.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc9a0] width 1920 pitch 7680 (/4 1920)
>[561572.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561572.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561572.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561572.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561572.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8290]
>[561572.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8290] width 1920 pitch 7680 (/4 1920)
>[561572.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561572.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561572.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561572.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561573.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561574.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561574.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561574.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561575.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561580.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561581.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561581.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561581.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8290]
>[561581.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8290] width 1920 pitch 7680 (/4 1920)
>[561581.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561582.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561582.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561582.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561583.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561583.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561583.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561583.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561583.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8290]
>[561583.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8290] width 1920 pitch 7680 (/4 1920)
>[561583.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561583.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561583.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d7fb0]
>[561583.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d7fb0] width 1920 pitch 7680 (/4 1920)
>[561583.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d8290]
>[561583.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d8290] width 1920 pitch 7680 (/4 1920)
>[561583.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27ea0]
>[561583.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27ea0] width 1920 pitch 7680 (/4 1920)
>[561583.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561583.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561583.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27ea0]
>[561583.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27ea0] width 1920 pitch 7680 (/4 1920)
>[561583.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561583.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561583.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f27ea0]
>[561583.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f27ea0] width 1920 pitch 7680 (/4 1920)
>[561583.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561584.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561584.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10460]
>[561584.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10460] width 1920 pitch 7680 (/4 1920)
>[561584.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561584.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561584.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a64350]
>[561585.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a64350] width 1920 pitch 7680 (/4 1920)
>[561585.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c600e0]
>[561585.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c600e0] width 1920 pitch 7680 (/4 1920)
>[561585.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401dd60]
>[561585.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401dd60] width 1920 pitch 7680 (/4 1920)
>[561664.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db1170]
>[561664.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db1170] width 1920 pitch 7680 (/4 1920)
>[561664.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a37550]
>[561665.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a37550] width 1920 pitch 7680 (/4 1920)
>[561665.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a55150]
>[561665.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a55150] width 1920 pitch 7680 (/4 1920)
>[561665.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a37550]
>[561665.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a37550] width 1920 pitch 7680 (/4 1920)
>[561665.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a55150]
>[561665.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a55150] width 1920 pitch 7680 (/4 1920)
>[561665.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a55150]
>[561665.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a55150] width 1920 pitch 7680 (/4 1920)
>[561665.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db14c0]
>[561665.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db14c0] width 1920 pitch 7680 (/4 1920)
>[561665.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811010]
>[561665.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811010] width 1920 pitch 7680 (/4 1920)
>[561665.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db13f0]
>[561665.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db13f0] width 1920 pitch 7680 (/4 1920)
>[561665.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a55150]
>[561665.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a55150] width 1920 pitch 7680 (/4 1920)
>[561691.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48460]
>[561691.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48460] width 1920 pitch 7680 (/4 1920)
>[561691.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b850]
>[561691.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b850] width 1920 pitch 7680 (/4 1920)
>[561691.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a08220]
>[561691.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a08220] width 1920 pitch 7680 (/4 1920)
>[561694.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x404b020]
>[561694.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x404b020] width 1920 pitch 7680 (/4 1920)
>[561694.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[561694.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[561695.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef02a0]
>[561695.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef02a0] width 1920 pitch 7680 (/4 1920)
>[561695.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eea1f0]
>[561695.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eea1f0] width 1920 pitch 7680 (/4 1920)
>[561695.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40f3110]
>[561695.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40f3110] width 1920 pitch 7680 (/4 1920)
>[561695.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed00b0]
>[561695.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed00b0] width 1920 pitch 7680 (/4 1920)
>[561695.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561695.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561695.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402e180]
>[561696.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402e180] width 1920 pitch 7680 (/4 1920)
>[561696.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1a260]
>[561696.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1a260] width 1920 pitch 7680 (/4 1920)
>[561696.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ced6c0]
>[561696.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ced6c0] width 1920 pitch 7680 (/4 1920)
>[561696.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7e600]
>[561696.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7e600] width 1920 pitch 7680 (/4 1920)
>[561708.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[561708.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[561708.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44d10]
>[561708.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44d10] width 1920 pitch 7680 (/4 1920)
>[561708.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f134a0]
>[561708.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f134a0] width 1920 pitch 7680 (/4 1920)
>[561708.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[561708.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1920 pitch 7680 (/4 1920)
>[561708.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5e530]
>[561708.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5e530] width 1920 pitch 7680 (/4 1920)
>[561709.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c9f90]
>[561709.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c9f90] width 1920 pitch 7680 (/4 1920)
>[561709.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e93030]
>[561709.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e93030] width 1920 pitch 7680 (/4 1920)
>[561709.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7e600]
>[561709.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7e600] width 1920 pitch 7680 (/4 1920)
>[561710.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x283ea40]
>[561710.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x283ea40] width 1920 pitch 7680 (/4 1920)
>[561710.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef02a0]
>[561710.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef02a0] width 1920 pitch 7680 (/4 1920)
>[561711.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbe540]
>[561711.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbe540] width 1920 pitch 7680 (/4 1920)
>[561711.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561711.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561711.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ef20]
>[561712.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ef20] width 1920 pitch 7680 (/4 1920)
>[561712.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c302b0]
>[561712.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c302b0] width 1920 pitch 7680 (/4 1920)
>[561712.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[561712.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1920 pitch 7680 (/4 1920)
>[561712.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1d0]
>[561713.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1d0] width 1920 pitch 7680 (/4 1920)
>[561902.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d750]
>[561902.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d750] width 1920 pitch 7680 (/4 1920)
>[561902.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561902.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561902.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b35900]
>[561902.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b35900] width 1920 pitch 7680 (/4 1920)
>[561902.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19590]
>[561902.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19590] width 1920 pitch 7680 (/4 1920)
>[561906.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebda10]
>[561906.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebda10] width 1920 pitch 7680 (/4 1920)
>[561906.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f660]
>[561906.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f660] width 1920 pitch 7680 (/4 1920)
>[561906.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ef20]
>[561906.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ef20] width 1920 pitch 7680 (/4 1920)
>[561906.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b35900]
>[561906.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b35900] width 1920 pitch 7680 (/4 1920)
>[561907.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2c510]
>[561907.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2c510] width 1920 pitch 7680 (/4 1920)
>[561907.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12280]
>[561907.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12280] width 1920 pitch 7680 (/4 1920)
>[561907.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561908.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561908.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561908.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561908.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[561908.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[561908.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f48460]
>[561908.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f48460] width 1920 pitch 7680 (/4 1920)
>[561908.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561908.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561908.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ebda10]
>[561909.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ebda10] width 1920 pitch 7680 (/4 1920)
>[561912.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d750]
>[561912.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d750] width 1920 pitch 7680 (/4 1920)
>[561912.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[561912.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[561912.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f60]
>[561912.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f60] width 1920 pitch 7680 (/4 1920)
>[561912.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c26e20]
>[561913.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c26e20] width 1920 pitch 7680 (/4 1920)
>[561913.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fad0]
>[561913.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fad0] width 1920 pitch 7680 (/4 1920)
>[561914.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561914.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561914.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed3f60]
>[561914.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed3f60] width 1920 pitch 7680 (/4 1920)
>[561914.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fbe540]
>[561914.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fbe540] width 1920 pitch 7680 (/4 1920)
>[561915.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f660]
>[561915.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f660] width 1920 pitch 7680 (/4 1920)
>[561915.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f439b0]
>[561915.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f439b0] width 1920 pitch 7680 (/4 1920)
>[561915.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d750]
>[561915.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d750] width 1920 pitch 7680 (/4 1920)
>[561915.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbe900]
>[561915.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbe900] width 1920 pitch 7680 (/4 1920)
>[561915.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d750]
>[561915.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d750] width 1920 pitch 7680 (/4 1920)
>[561915.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbe900]
>[561915.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbe900] width 1920 pitch 7680 (/4 1920)
>[561915.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d750]
>[561915.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d750] width 1920 pitch 7680 (/4 1920)
>[561915.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbe900]
>[561915.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbe900] width 1920 pitch 7680 (/4 1920)
>[561915.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561915.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561915.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561915.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561915.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561915.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561915.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561915.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561915.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561915.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561915.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561915.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561915.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561915.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561915.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561916.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561916.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561916.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561916.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561916.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561916.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561916.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561916.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561916.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561916.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[561916.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[561916.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4aa0]
>[561916.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4aa0] width 1920 pitch 7680 (/4 1920)
>[561916.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561916.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561917.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561917.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561917.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561917.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561917.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4acd340]
>[561917.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4acd340] width 1920 pitch 7680 (/4 1920)
>[561918.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561918.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561918.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fbce40]
>[561918.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fbce40] width 1920 pitch 7680 (/4 1920)
>[561918.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561918.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561918.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561918.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561919.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[561919.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[561919.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[561919.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1920 pitch 7680 (/4 1920)
>[561919.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[561919.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1920 pitch 7680 (/4 1920)
>[561919.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561919.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561919.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fa50]
>[561919.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fa50] width 1920 pitch 7680 (/4 1920)
>[561919.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561920.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561920.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fa50]
>[561920.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fa50] width 1920 pitch 7680 (/4 1920)
>[561920.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561920.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561920.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4fa50]
>[561920.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4fa50] width 1920 pitch 7680 (/4 1920)
>[561920.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561920.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561922.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[561922.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1920 pitch 7680 (/4 1920)
>[561922.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561922.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561922.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50683e0]
>[561922.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50683e0] width 1920 pitch 7680 (/4 1920)
>[561922.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561922.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561922.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[561922.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[561922.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39848c0]
>[561922.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39848c0] width 1920 pitch 7680 (/4 1920)
>[561926.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[561926.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[561926.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce98b0]
>[561926.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce98b0] width 1920 pitch 7680 (/4 1920)
>[561926.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[561926.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[561926.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b591b0]
>[561926.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b591b0] width 1920 pitch 7680 (/4 1920)
>[561926.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a5fb0]
>[561926.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a5fb0] width 1920 pitch 7680 (/4 1920)
>[561932.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b270]
>[561933.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b270] width 1920 pitch 7680 (/4 1920)
>[561935.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54d20]
>[561935.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54d20] width 1920 pitch 7680 (/4 1920)
>[561936.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def470]
>[561936.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def470] width 1920 pitch 7680 (/4 1920)
>[561936.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084300]
>[561936.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084300] width 1920 pitch 7680 (/4 1920)
>[561936.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def470]
>[561936.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def470] width 1920 pitch 7680 (/4 1920)
>[561936.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084300]
>[561936.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084300] width 1920 pitch 7680 (/4 1920)
>[561936.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def470]
>[561937.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def470] width 1920 pitch 7680 (/4 1920)
>[561937.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def470]
>[561937.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def470] width 1920 pitch 7680 (/4 1920)
>[561937.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f7e600]
>[561937.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f7e600] width 1920 pitch 7680 (/4 1920)
>[561953.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[561953.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1920 pitch 7680 (/4 1920)
>[561954.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[561954.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[561954.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[561954.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1920 pitch 7680 (/4 1920)
>[561954.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40311c0]
>[561955.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40311c0] width 1920 pitch 7680 (/4 1920)
>[561955.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[561955.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1920 pitch 7680 (/4 1920)
>[561980.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0abd0]
>[561980.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0abd0] width 1920 pitch 7680 (/4 1920)
>[561981.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388a160]
>[561981.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388a160] width 1920 pitch 7680 (/4 1920)
>[562000.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e66f0]
>[562000.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e66f0] width 1920 pitch 7680 (/4 1920)
>[562018.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e66f0]
>[562018.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e66f0] width 1920 pitch 7680 (/4 1920)
>[562109.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8fb0]
>[562109.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8fb0] width 1920 pitch 7680 (/4 1920)
>[562109.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[562109.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[562109.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea9f0]
>[562109.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea9f0] width 1920 pitch 7680 (/4 1920)
>[562109.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929e00]
>[562109.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929e00] width 1920 pitch 7680 (/4 1920)
>[562109.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afd1e0]
>[562109.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afd1e0] width 1920 pitch 7680 (/4 1920)
>[562109.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebcdb0]
>[562109.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebcdb0] width 1920 pitch 7680 (/4 1920)
>[562110.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3dbf0]
>[562110.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3dbf0] width 1920 pitch 7680 (/4 1920)
>[562110.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3dbf0]
>[562110.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3dbf0] width 1920 pitch 7680 (/4 1920)
>[562110.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1c0d0]
>[562110.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1c0d0] width 1920 pitch 7680 (/4 1920)
>[562110.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef7f70]
>[562110.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef7f70] width 1920 pitch 7680 (/4 1920)
>[562110.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3dbf0]
>[562110.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3dbf0] width 1920 pitch 7680 (/4 1920)
>[562119.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[562119.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1920 pitch 7680 (/4 1920)
>[562129.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eef720]
>[562130.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eef720] width 1920 pitch 7680 (/4 1920)
>[562233.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44d10]
>[562233.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44d10] width 1920 pitch 7680 (/4 1920)
>[562233.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[562233.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[562234.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb1a20]
>[562234.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb1a20] width 1920 pitch 7680 (/4 1920)
>[562234.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683800]
>[562234.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683800] width 1920 pitch 7680 (/4 1920)
>[562234.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65f10]
>[562234.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65f10] width 1920 pitch 7680 (/4 1920)
>[562266.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cdf0]
>[562266.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cdf0] width 1920 pitch 7680 (/4 1920)
>[562266.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6860]
>[562266.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6860] width 1920 pitch 7680 (/4 1920)
>[562266.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c7cdf0]
>[562266.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c7cdf0] width 1920 pitch 7680 (/4 1920)
>[562266.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50bc470]
>[562266.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50bc470] width 1920 pitch 7680 (/4 1920)
>[562266.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c780e0]
>[562266.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c780e0] width 1920 pitch 7680 (/4 1920)
>[562267.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5920]
>[562267.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5920] width 1920 pitch 7680 (/4 1920)
>[562272.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37530]
>[562272.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37530] width 1920 pitch 7680 (/4 1920)
>[562272.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70870]
>[562273.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70870] width 1920 pitch 7680 (/4 1920)
>[562273.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df4ad0]
>[562273.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df4ad0] width 1920 pitch 7680 (/4 1920)
>[562273.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8c660]
>[562273.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8c660] width 1920 pitch 7680 (/4 1920)
>[562273.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df4ad0]
>[562274.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df4ad0] width 1920 pitch 7680 (/4 1920)
>[562282.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bbf0]
>[562282.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bbf0] width 1920 pitch 7680 (/4 1920)
>[562282.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebcdb0]
>[562282.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebcdb0] width 1920 pitch 7680 (/4 1920)
>[562283.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bbf0]
>[562283.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bbf0] width 1920 pitch 7680 (/4 1920)
>[562283.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebcdb0]
>[562283.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebcdb0] width 1920 pitch 7680 (/4 1920)
>[562283.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507bbf0]
>[562283.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507bbf0] width 1920 pitch 7680 (/4 1920)
>[562284.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebcdb0]
>[562284.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebcdb0] width 1920 pitch 7680 (/4 1920)
>[562284.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bef290]
>[562284.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bef290] width 1920 pitch 7680 (/4 1920)
>[562619.026] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[562619.026] (II) RADEON(0): Using hsync ranges from config file
>[562619.026] (II) RADEON(0): Using vrefresh ranges from config file
>[562619.026] (II) RADEON(0): Printing DDC gathered Modelines:
>[562619.026] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[562619.026] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[562619.026] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[562619.026] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[562619.026] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[562619.026] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[562619.026] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[562619.026] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[562619.026] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[562619.026] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[562619.026] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[562708.788] (II) RADEON(0): RADEONSaveScreen(2)
>[562708.794] (II) RADEON(0): RADEONSaveScreen(0)
>[601167.004] (II) RADEON(0): RADEONSaveScreen(1)
>[601179.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9de70]
>[601179.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9de70] width 1920 pitch 7680 (/4 1920)
>[601179.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1aa90]
>[601179.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1aa90] width 1920 pitch 7680 (/4 1920)
>[601513.487] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[601513.487] (II) RADEON(0): Using hsync ranges from config file
>[601513.487] (II) RADEON(0): Using vrefresh ranges from config file
>[601513.487] (II) RADEON(0): Printing DDC gathered Modelines:
>[601513.487] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[601513.487] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[601513.487] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[601513.487] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[601513.487] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[601513.487] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[601513.487] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[601513.487] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[601513.487] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[601513.487] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[601513.487] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[601513.487] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[601513.487] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[601513.487] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[601513.487] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[601513.488] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[601603.743] (II) RADEON(0): RADEONSaveScreen(2)
>[601603.743] (II) RADEON(0): RADEONSaveScreen(0)
>[601872.113] (II) RADEON(0): RADEONSaveScreen(1)
>[601905.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x385f0f0]
>[601905.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x385f0f0] width 1920 pitch 7680 (/4 1920)
>[602176.239] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event6)
>[602176.241] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[602176.241] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602176.241] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[602176.241] 	Option "XkbRules" "evdev"
>[602176.241] 	Option "XkbModel" "pc105+inet"
>[602176.241] 	Option "XkbLayout" "us"
>[602176.241] 	Option "_source" "server/udev"
>[602176.241] 	Option "name" "VISENTA V1 "
>[602176.241] 	Option "path" "/dev/input/event6"
>[602176.241] 	Option "device" "/dev/input/event6"
>[602176.241] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input36/event6"
>[602176.241] 	Option "driver" "evdev"
>[602176.241] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[602176.241] (**) VISENTA V1 : always reports core events
>[602176.241] (**) evdev: VISENTA V1 : Device: "/dev/input/event6"
>[602176.249] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[602176.249] (--) evdev: VISENTA V1 : Found keys
>[602176.249] (II) evdev: VISENTA V1 : Configuring as keyboard
>[602176.249] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.0/input/input36/event6"
>[602176.249] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 9)
>[602176.249] (**) Option "xkb_rules" "evdev"
>[602176.249] (**) Option "xkb_model" "pc105+inet"
>[602176.249] (**) Option "xkb_layout" "us"
>[602176.249] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[602176.250] (II) XKB: Reusing cached keymap
>[602176.271] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse2)
>[602176.271] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602176.271] (II) No input driver specified, ignoring this device.
>[602176.271] (II) This device may have been added with another device file.
>[602176.271] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event7)
>[602176.271] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[602176.271] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[602176.271] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602176.271] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[602176.271] 	Option "XkbRules" "evdev"
>[602176.271] 	Option "XkbModel" "pc105+inet"
>[602176.271] 	Option "XkbLayout" "us"
>[602176.271] 	Option "_source" "server/udev"
>[602176.271] 	Option "name" "VISENTA V1 "
>[602176.271] 	Option "path" "/dev/input/event7"
>[602176.271] 	Option "device" "/dev/input/event7"
>[602176.271] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input37/event7"
>[602176.271] 	Option "driver" "evdev"
>[602176.271] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[602176.271] (**) VISENTA V1 : always reports core events
>[602176.271] (**) evdev: VISENTA V1 : Device: "/dev/input/event7"
>[602176.271] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[602176.271] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[602176.271] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[602176.271] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[602176.271] (--) evdev: VISENTA V1 : Found relative axes
>[602176.271] (--) evdev: VISENTA V1 : Found x and y relative axes
>[602176.271] (--) evdev: VISENTA V1 : Found absolute axes
>[602176.271] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[602176.271] (--) evdev: VISENTA V1 : Found keys
>[602176.271] (II) evdev: VISENTA V1 : Configuring as mouse
>[602176.271] (II) evdev: VISENTA V1 : Configuring as keyboard
>[602176.271] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[602176.271] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[602176.271] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[602176.271] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.4/1-1.4.4:1.1/input/input37/event7"
>[602176.271] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 10)
>[602176.271] (**) Option "xkb_rules" "evdev"
>[602176.271] (**) Option "xkb_model" "pc105+inet"
>[602176.271] (**) Option "xkb_layout" "us"
>[602176.271] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[602176.271] (II) XKB: Reusing cached keymap
>[602176.272] (II) evdev: VISENTA V1 : initialized for relative axes.
>[602176.272] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[602176.272] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[602176.272] (**) VISENTA V1 : (accel) acceleration profile 0
>[602176.272] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[602176.272] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[602176.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e996d0]
>[602176.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e996d0] width 1920 pitch 7680 (/4 1920)
>[602177.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[602177.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1920 pitch 7680 (/4 1920)
>[602248.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[602248.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[602250.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3d4f0]
>[602250.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3d4f0] width 1920 pitch 7680 (/4 1920)
>[602250.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57740]
>[602250.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57740] width 1920 pitch 7680 (/4 1920)
>[602250.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50137f0]
>[602251.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50137f0] width 1920 pitch 7680 (/4 1920)
>[602251.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c08890]
>[602251.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c08890] width 1920 pitch 7680 (/4 1920)
>[602251.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57740]
>[602251.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57740] width 1920 pitch 7680 (/4 1920)
>[602251.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[602251.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1920 pitch 7680 (/4 1920)
>[602251.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d120]
>[602251.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d120] width 1920 pitch 7680 (/4 1920)
>[602252.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38821c0]
>[602252.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38821c0] width 1920 pitch 7680 (/4 1920)
>[602252.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68864f0]
>[602252.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68864f0] width 1920 pitch 7680 (/4 1920)
>[602272.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a04ec0]
>[602272.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a04ec0] width 1920 pitch 7680 (/4 1920)
>[602349.771] (II) config/udev: removing device VISENTA V1 
>[602349.772] (II) evdev: VISENTA V1 : Close
>[602349.772] (II) UnloadModule: "evdev"
>[602349.787] (II) config/udev: removing device VISENTA V1 
>[602349.789] (II) evdev: VISENTA V1 : Close
>[602349.789] (II) UnloadModule: "evdev"
>[602352.268] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event6)
>[602352.268] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[602352.268] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602352.268] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[602352.269] 	Option "XkbRules" "evdev"
>[602352.269] 	Option "XkbModel" "pc105+inet"
>[602352.269] 	Option "XkbLayout" "us"
>[602352.269] 	Option "_source" "server/udev"
>[602352.269] 	Option "name" "VISENTA V1 "
>[602352.269] 	Option "path" "/dev/input/event6"
>[602352.269] 	Option "device" "/dev/input/event6"
>[602352.269] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1c.7/0000:26:00.0/usb3/3-2/3-2:1.0/input/input38/event6"
>[602352.269] 	Option "driver" "evdev"
>[602352.269] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[602352.269] (**) VISENTA V1 : always reports core events
>[602352.269] (**) evdev: VISENTA V1 : Device: "/dev/input/event6"
>[602352.269] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[602352.269] (--) evdev: VISENTA V1 : Found keys
>[602352.269] (II) evdev: VISENTA V1 : Configuring as keyboard
>[602352.269] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1c.7/0000:26:00.0/usb3/3-2/3-2:1.0/input/input38/event6"
>[602352.269] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 9)
>[602352.269] (**) Option "xkb_rules" "evdev"
>[602352.269] (**) Option "xkb_model" "pc105+inet"
>[602352.269] (**) Option "xkb_layout" "us"
>[602352.269] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[602352.269] (II) XKB: Reusing cached keymap
>[602352.271] (II) config/udev: Adding input device VISENTA V1  (/dev/input/mouse2)
>[602352.271] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602352.271] (II) No input driver specified, ignoring this device.
>[602352.271] (II) This device may have been added with another device file.
>[602352.271] (II) config/udev: Adding input device VISENTA V1  (/dev/input/event7)
>[602352.271] (**) VISENTA V1 : Applying InputClass "evdev pointer catchall"
>[602352.271] (**) VISENTA V1 : Applying InputClass "evdev keyboard catchall"
>[602352.271] (**) VISENTA V1 : Applying InputClass "system-setup-keyboard"
>[602352.271] (II) Using input driver 'evdev' for 'VISENTA V1 '
>[602352.271] 	Option "XkbRules" "evdev"
>[602352.271] 	Option "XkbModel" "pc105+inet"
>[602352.271] 	Option "XkbLayout" "us"
>[602352.271] 	Option "_source" "server/udev"
>[602352.271] 	Option "name" "VISENTA V1 "
>[602352.271] 	Option "path" "/dev/input/event7"
>[602352.271] 	Option "device" "/dev/input/event7"
>[602352.271] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1c.7/0000:26:00.0/usb3/3-2/3-2:1.1/input/input39/event7"
>[602352.271] 	Option "driver" "evdev"
>[602352.271] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[602352.271] (**) VISENTA V1 : always reports core events
>[602352.272] (**) evdev: VISENTA V1 : Device: "/dev/input/event7"
>[602352.272] (--) evdev: VISENTA V1 : absolute axis 0x20 [896..0]
>[602352.272] (--) evdev: VISENTA V1 : Vendor 0x4d9 Product 0x2519
>[602352.272] (--) evdev: VISENTA V1 : Found 3 mouse buttons
>[602352.272] (--) evdev: VISENTA V1 : Found scroll wheel(s)
>[602352.272] (--) evdev: VISENTA V1 : Found relative axes
>[602352.272] (--) evdev: VISENTA V1 : Found x and y relative axes
>[602352.272] (--) evdev: VISENTA V1 : Found absolute axes
>[602352.272] (II) evdev: VISENTA V1 : Forcing absolute x/y axes to exist.
>[602352.272] (--) evdev: VISENTA V1 : Found keys
>[602352.272] (II) evdev: VISENTA V1 : Configuring as mouse
>[602352.272] (II) evdev: VISENTA V1 : Configuring as keyboard
>[602352.272] (II) evdev: VISENTA V1 : Adding scrollwheel support
>[602352.272] (**) evdev: VISENTA V1 : YAxisMapping: buttons 4 and 5
>[602352.272] (**) evdev: VISENTA V1 : EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[602352.272] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1c.7/0000:26:00.0/usb3/3-2/3-2:1.1/input/input39/event7"
>[602352.272] (II) XINPUT: Adding extended input device "VISENTA V1 " (type: KEYBOARD, id 10)
>[602352.272] (**) Option "xkb_rules" "evdev"
>[602352.272] (**) Option "xkb_model" "pc105+inet"
>[602352.272] (**) Option "xkb_layout" "us"
>[602352.272] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[602352.272] (II) XKB: Reusing cached keymap
>[602352.273] (II) evdev: VISENTA V1 : initialized for relative axes.
>[602352.273] (WW) evdev: VISENTA V1 : ignoring absolute axes.
>[602352.273] (**) VISENTA V1 : (accel) keeping acceleration scheme 1
>[602352.273] (**) VISENTA V1 : (accel) acceleration profile 0
>[602352.273] (**) VISENTA V1 : (accel) acceleration factor: 2.000
>[602352.273] (**) VISENTA V1 : (accel) acceleration threshold: 4
>[602353.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c210]
>[602353.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c210] width 1920 pitch 7680 (/4 1920)
>[602373.682] (II) config/udev: removing device VISENTA V1 
>[602373.684] (II) evdev: VISENTA V1 : Close
>[602373.684] (II) UnloadModule: "evdev"
>[602373.723] (II) config/udev: removing device VISENTA V1 
>[602373.724] (II) evdev: VISENTA V1 : Close
>[602373.724] (II) UnloadModule: "evdev"
>[602399.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929e00]
>[602399.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929e00] width 1920 pitch 7680 (/4 1920)
>[602399.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47100]
>[602399.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47100] width 1920 pitch 7680 (/4 1920)
>[602399.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597a830]
>[602399.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597a830] width 1920 pitch 7680 (/4 1920)
>[602399.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47100]
>[602399.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47100] width 1920 pitch 7680 (/4 1920)
>[602399.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597a830]
>[602399.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597a830] width 1920 pitch 7680 (/4 1920)
>[602399.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b47100]
>[602399.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b47100] width 1920 pitch 7680 (/4 1920)
>[602399.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597a830]
>[602399.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597a830] width 1920 pitch 7680 (/4 1920)
>[602401.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da3e20]
>[602401.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da3e20] width 1920 pitch 7680 (/4 1920)
>[602402.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b591b0]
>[602402.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b591b0] width 1920 pitch 7680 (/4 1920)
>[602402.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30240]
>[602402.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30240] width 1920 pitch 7680 (/4 1920)
>[602402.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b591b0]
>[602402.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b591b0] width 1920 pitch 7680 (/4 1920)
>[602402.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30240]
>[602402.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30240] width 1920 pitch 7680 (/4 1920)
>[602707.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913400]
>[602707.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913400] width 1920 pitch 7680 (/4 1920)
>[602850.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7dc70]
>[602850.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7dc70] width 1920 pitch 7680 (/4 1920)
>[602850.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1b9f0]
>[602850.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1b9f0] width 1920 pitch 7680 (/4 1920)
>[602851.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7dc70]
>[602851.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7dc70] width 1920 pitch 7680 (/4 1920)
>[602851.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1b9f0]
>[602851.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1b9f0] width 1920 pitch 7680 (/4 1920)
>[602853.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d96e0]
>[602853.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d96e0] width 1920 pitch 7680 (/4 1920)
>[602853.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507db60]
>[602853.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507db60] width 1920 pitch 7680 (/4 1920)
>[602853.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c05320]
>[602853.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c05320] width 1920 pitch 7680 (/4 1920)
>[602854.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3934420]
>[602854.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3934420] width 1920 pitch 7680 (/4 1920)
>[602857.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3934420]
>[602857.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3934420] width 1920 pitch 7680 (/4 1920)
>[602857.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9ff50]
>[602857.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9ff50] width 1920 pitch 7680 (/4 1920)
>[602857.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[602857.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[602857.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4deab00]
>[602857.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4deab00] width 1920 pitch 7680 (/4 1920)
>[602857.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[602857.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[602859.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625670]
>[602859.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625670] width 1920 pitch 7680 (/4 1920)
>[602859.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ef20]
>[602859.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ef20] width 1920 pitch 7680 (/4 1920)
>[602859.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[602859.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[602859.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3935070]
>[602860.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3935070] width 1920 pitch 7680 (/4 1920)
>[603366.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[603366.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[603366.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9e70]
>[603366.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9e70] width 1920 pitch 7680 (/4 1920)
>[603366.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[603366.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[603367.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9e70]
>[603367.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9e70] width 1920 pitch 7680 (/4 1920)
>[603367.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[603367.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[603372.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9e70]
>[603372.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9e70] width 1920 pitch 7680 (/4 1920)
>[603372.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e84d90]
>[603372.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e84d90] width 1920 pitch 7680 (/4 1920)
>[603372.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9e70]
>[603372.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9e70] width 1920 pitch 7680 (/4 1920)
>[603372.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b270]
>[603372.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b270] width 1920 pitch 7680 (/4 1920)
>[603373.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb1320]
>[603373.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb1320] width 1920 pitch 7680 (/4 1920)
>[603373.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1b270]
>[603373.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1b270] width 1920 pitch 7680 (/4 1920)
>[603865.448] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[603865.448] (II) RADEON(0): Using hsync ranges from config file
>[603865.448] (II) RADEON(0): Using vrefresh ranges from config file
>[603865.448] (II) RADEON(0): Printing DDC gathered Modelines:
>[603865.448] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[603865.448] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[603865.448] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[603865.448] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[603865.448] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[603865.448] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[603865.448] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[603865.448] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[603865.448] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[603865.448] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[603865.448] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[603955.761] (II) RADEON(0): RADEONSaveScreen(2)
>[603955.761] (II) RADEON(0): RADEONSaveScreen(0)
>[605368.526] (II) RADEON(0): RADEONSaveScreen(1)
>[605380.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50770]
>[605381.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50770] width 1920 pitch 7680 (/4 1920)
>[605382.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c30240]
>[605382.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c30240] width 1920 pitch 7680 (/4 1920)
>[605382.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0bda0]
>[605382.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0bda0] width 1920 pitch 7680 (/4 1920)
>[605382.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f210]
>[605383.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f210] width 1920 pitch 7680 (/4 1920)
>[605383.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4062980]
>[605383.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4062980] width 1920 pitch 7680 (/4 1920)
>[605383.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[605383.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[605383.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebdbb0]
>[605383.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebdbb0] width 1920 pitch 7680 (/4 1920)
>[605383.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeacc0]
>[605384.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeacc0] width 1920 pitch 7680 (/4 1920)
>[605384.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc74c0]
>[605384.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc74c0] width 1920 pitch 7680 (/4 1920)
>[605384.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[605384.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[605384.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[605384.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1920 pitch 7680 (/4 1920)
>[605384.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[605384.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[605384.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[605385.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1920 pitch 7680 (/4 1920)
>[605385.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[605385.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[605385.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[605385.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1920 pitch 7680 (/4 1920)
>[605385.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecafc0]
>[605385.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecafc0] width 1920 pitch 7680 (/4 1920)
>[605385.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5025ba0]
>[605385.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5025ba0] width 1920 pitch 7680 (/4 1920)
>[605385.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[605385.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[605385.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[605386.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[605386.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[605386.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[605386.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[605386.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[605386.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[605386.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[605386.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[605386.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[605388.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5084300]
>[605388.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5084300] width 1920 pitch 7680 (/4 1920)
>[605388.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3540]
>[605388.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3540] width 1920 pitch 7680 (/4 1920)
>[605388.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[605388.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[605388.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b53150]
>[605388.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b53150] width 1920 pitch 7680 (/4 1920)
>[605389.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50158e0]
>[605389.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50158e0] width 1920 pitch 7680 (/4 1920)
>[605389.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cdff0]
>[605389.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cdff0] width 1920 pitch 7680 (/4 1920)
>[605389.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cdff0]
>[605390.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cdff0] width 1920 pitch 7680 (/4 1920)
>[605390.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50158e0]
>[605390.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50158e0] width 1920 pitch 7680 (/4 1920)
>[605390.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6973d40]
>[605390.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6973d40] width 1920 pitch 7680 (/4 1920)
>[605390.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50158e0]
>[605390.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50158e0] width 1920 pitch 7680 (/4 1920)
>[605411.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0ca0]
>[605411.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0ca0] width 1920 pitch 7680 (/4 1920)
>[605414.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58a10]
>[605414.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58a10] width 1920 pitch 7680 (/4 1920)
>[605414.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a560]
>[605414.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a560] width 1920 pitch 7680 (/4 1920)
>[605414.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58ae0]
>[605415.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58ae0] width 1920 pitch 7680 (/4 1920)
>[605416.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58f00]
>[605416.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58f00] width 1920 pitch 7680 (/4 1920)
>[605431.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698fe50]
>[605431.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698fe50] width 1920 pitch 7680 (/4 1920)
>[605643.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9ee00]
>[605643.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9ee00] width 1920 pitch 7680 (/4 1920)
>[605647.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b998c0]
>[605647.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b998c0] width 1920 pitch 7680 (/4 1920)
>[605647.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a150]
>[605648.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a150] width 1920 pitch 7680 (/4 1920)
>[605648.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dec810]
>[605648.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dec810] width 1920 pitch 7680 (/4 1920)
>[605648.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dec810]
>[605648.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dec810] width 1920 pitch 7680 (/4 1920)
>[605648.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4a150]
>[605648.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4a150] width 1920 pitch 7680 (/4 1920)
>[605658.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ece3f0]
>[605659.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ece3f0] width 1920 pitch 7680 (/4 1920)
>[605665.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d55440]
>[605665.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d55440] width 1920 pitch 7680 (/4 1920)
>[605665.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4def470]
>[605666.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4def470] width 1920 pitch 7680 (/4 1920)
>[605666.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9d4d0]
>[605666.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9d4d0] width 1920 pitch 7680 (/4 1920)
>[605666.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28436d0]
>[605666.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28436d0] width 1920 pitch 7680 (/4 1920)
>[605666.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[605666.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[605666.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4f660]
>[605666.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4f660] width 1920 pitch 7680 (/4 1920)
>[605666.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50104b0]
>[605666.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50104b0] width 1920 pitch 7680 (/4 1920)
>[605667.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3950]
>[605667.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3950] width 1920 pitch 7680 (/4 1920)
>[605667.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e66f0]
>[605667.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e66f0] width 1920 pitch 7680 (/4 1920)
>[605667.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[605667.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1920 pitch 7680 (/4 1920)
>[605668.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[605668.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[605668.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e02730]
>[605668.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e02730] width 1920 pitch 7680 (/4 1920)
>[605668.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f40]
>[605669.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f40] width 1920 pitch 7680 (/4 1920)
>[605696.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8ef20]
>[605696.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8ef20] width 1920 pitch 7680 (/4 1920)
>[605696.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[605696.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1920 pitch 7680 (/4 1920)
>[605696.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0d0b0]
>[605696.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0d0b0] width 1920 pitch 7680 (/4 1920)
>[605696.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f080]
>[605696.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f080] width 1920 pitch 7680 (/4 1920)
>[605696.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c0120]
>[605696.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c0120] width 1920 pitch 7680 (/4 1920)
>[605700.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3ea0]
>[605700.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3ea0] width 1920 pitch 7680 (/4 1920)
>[605700.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f52260]
>[605700.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f52260] width 1920 pitch 7680 (/4 1920)
>[605700.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50104b0]
>[605700.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50104b0] width 1920 pitch 7680 (/4 1920)
>[605700.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c0120]
>[605700.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c0120] width 1920 pitch 7680 (/4 1920)
>[605700.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50104b0]
>[605700.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50104b0] width 1920 pitch 7680 (/4 1920)
>[605700.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c0120]
>[605700.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c0120] width 1920 pitch 7680 (/4 1920)
>[605701.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992a70]
>[605701.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992a70] width 1920 pitch 7680 (/4 1920)
>[605701.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f080]
>[605701.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f080] width 1920 pitch 7680 (/4 1920)
>[605701.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6992a70]
>[605702.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6992a70] width 1920 pitch 7680 (/4 1920)
>[605702.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f080]
>[605702.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f080] width 1920 pitch 7680 (/4 1920)
>[605702.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[605702.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[605702.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c54a70]
>[605702.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c54a70] width 1920 pitch 7680 (/4 1920)
>[605710.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605710.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605710.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[605710.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[605710.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605710.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605711.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28662e0]
>[605711.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28662e0] width 1920 pitch 7680 (/4 1920)
>[605711.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605711.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605711.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda2d0]
>[605711.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda2d0] width 1920 pitch 7680 (/4 1920)
>[605711.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605711.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605713.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda2d0]
>[605713.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda2d0] width 1920 pitch 7680 (/4 1920)
>[605713.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605713.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605713.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda2d0]
>[605713.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda2d0] width 1920 pitch 7680 (/4 1920)
>[605713.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[605713.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[605713.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f323e0]
>[605713.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f323e0] width 1920 pitch 7680 (/4 1920)
>[606076.757] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[606076.841] (II) RADEON(0): Using hsync ranges from config file
>[606076.841] (II) RADEON(0): Using vrefresh ranges from config file
>[606076.841] (II) RADEON(0): Printing DDC gathered Modelines:
>[606076.841] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[606076.841] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[606076.841] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[606076.841] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[606076.841] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[606076.841] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[606076.841] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[606076.841] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[606076.841] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[606076.841] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[606076.841] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[606166.743] (II) RADEON(0): RADEONSaveScreen(2)
>[606166.773] (II) RADEON(0): RADEONSaveScreen(0)
>[607180.887] (II) RADEON(0): RADEONSaveScreen(1)
>[607199.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b4800]
>[607199.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b4800] width 1920 pitch 7680 (/4 1920)
>[607208.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[607209.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1920 pitch 7680 (/4 1920)
>[607209.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[607209.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[607209.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1d0]
>[607209.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1d0] width 1920 pitch 7680 (/4 1920)
>[607210.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607210.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607210.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393b390]
>[607210.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393b390] width 1920 pitch 7680 (/4 1920)
>[607211.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607211.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607211.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50770]
>[607211.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50770] width 1920 pitch 7680 (/4 1920)
>[607211.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4030f40]
>[607211.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4030f40] width 1920 pitch 7680 (/4 1920)
>[607212.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8710]
>[607212.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8710] width 1920 pitch 7680 (/4 1920)
>[607212.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f52260]
>[607212.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f52260] width 1920 pitch 7680 (/4 1920)
>[607213.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc79a0]
>[607213.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc79a0] width 1920 pitch 7680 (/4 1920)
>[607213.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x41489d0]
>[607213.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x41489d0] width 1920 pitch 7680 (/4 1920)
>[607214.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[607214.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1920 pitch 7680 (/4 1920)
>[607214.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32480]
>[607214.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32480] width 1920 pitch 7680 (/4 1920)
>[607214.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0d0b0]
>[607214.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0d0b0] width 1920 pitch 7680 (/4 1920)
>[607214.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b32480]
>[607214.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b32480] width 1920 pitch 7680 (/4 1920)
>[607215.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[607215.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[607215.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625670]
>[607215.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625670] width 1920 pitch 7680 (/4 1920)
>[607215.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[607215.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[607215.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625670]
>[607215.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625670] width 1920 pitch 7680 (/4 1920)
>[607218.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e380d0]
>[607218.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e380d0] width 1920 pitch 7680 (/4 1920)
>[607218.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b4800]
>[607218.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b4800] width 1920 pitch 7680 (/4 1920)
>[607220.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607220.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607220.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[607220.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[607220.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607220.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607222.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[607222.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[607222.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607222.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607222.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a963e0]
>[607222.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a963e0] width 1920 pitch 7680 (/4 1920)
>[607222.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607222.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607234.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3924b70]
>[607234.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3924b70] width 1920 pitch 7680 (/4 1920)
>[607246.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb13e0]
>[607246.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb13e0] width 1920 pitch 7680 (/4 1920)
>[607376.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be4310]
>[607376.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be4310] width 1920 pitch 7680 (/4 1920)
>[607682.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe05d0]
>[607682.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe05d0] width 1920 pitch 7680 (/4 1920)
>[607682.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b99b0]
>[607682.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b99b0] width 1920 pitch 7680 (/4 1920)
>[607683.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[607683.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1920 pitch 7680 (/4 1920)
>[607683.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[607683.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1920 pitch 7680 (/4 1920)
>[607683.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd2d0]
>[607683.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd2d0] width 1920 pitch 7680 (/4 1920)
>[607684.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef88c0]
>[607684.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef88c0] width 1920 pitch 7680 (/4 1920)
>[607684.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[607684.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1920 pitch 7680 (/4 1920)
>[607684.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb6560]
>[607685.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb6560] width 1920 pitch 7680 (/4 1920)
>[607685.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[607685.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1920 pitch 7680 (/4 1920)
>[607686.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4080]
>[607686.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4080] width 1920 pitch 7680 (/4 1920)
>[607828.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4050800]
>[607828.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4050800] width 1920 pitch 7680 (/4 1920)
>[607829.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9140]
>[607829.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9140] width 1920 pitch 7680 (/4 1920)
>[607829.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2560]
>[607829.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2560] width 1920 pitch 7680 (/4 1920)
>[607830.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607830.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607830.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88390]
>[607830.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88390] width 1920 pitch 7680 (/4 1920)
>[607830.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607830.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607830.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504f1c0]
>[607831.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504f1c0] width 1920 pitch 7680 (/4 1920)
>[607831.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607831.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607831.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504f1c0]
>[607831.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504f1c0] width 1920 pitch 7680 (/4 1920)
>[607831.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607831.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607831.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504f1c0]
>[607831.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504f1c0] width 1920 pitch 7680 (/4 1920)
>[607831.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607831.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607832.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e50]
>[607832.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e50] width 1920 pitch 7680 (/4 1920)
>[607832.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607832.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607832.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e50]
>[607832.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e50] width 1920 pitch 7680 (/4 1920)
>[607832.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607832.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607832.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39e50]
>[607832.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39e50] width 1920 pitch 7680 (/4 1920)
>[607833.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df7e60]
>[607833.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df7e60] width 1920 pitch 7680 (/4 1920)
>[607833.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f52fc0]
>[607833.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f52fc0] width 1920 pitch 7680 (/4 1920)
>[607834.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00140]
>[607834.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00140] width 1920 pitch 7680 (/4 1920)
>[607834.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0d0b0]
>[607834.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0d0b0] width 1920 pitch 7680 (/4 1920)
>[607834.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b50790]
>[607834.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b50790] width 1920 pitch 7680 (/4 1920)
>[607835.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[607835.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1920 pitch 7680 (/4 1920)
>[607836.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918a90]
>[607836.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918a90] width 1920 pitch 7680 (/4 1920)
>[607836.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc4640]
>[607836.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc4640] width 1920 pitch 7680 (/4 1920)
>[607836.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f75940]
>[607836.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f75940] width 1920 pitch 7680 (/4 1920)
>[607843.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2515460]
>[607844.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2515460] width 1920 pitch 7680 (/4 1920)
>[607844.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625670]
>[607844.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625670] width 1920 pitch 7680 (/4 1920)
>[607912.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301fab0]
>[607912.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301fab0] width 1920 pitch 7680 (/4 1920)
>[607912.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44d10]
>[607912.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44d10] width 1920 pitch 7680 (/4 1920)
>[607913.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[607913.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1920 pitch 7680 (/4 1920)
>[607913.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[607913.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1920 pitch 7680 (/4 1920)
>[607914.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f4cbd0]
>[607914.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f4cbd0] width 1920 pitch 7680 (/4 1920)
>[607914.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50104b0]
>[607914.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50104b0] width 1920 pitch 7680 (/4 1920)
>[607914.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2855210]
>[607914.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2855210] width 1920 pitch 7680 (/4 1920)
>[608210.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[608210.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1920 pitch 7680 (/4 1920)
>[608210.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9140]
>[608210.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9140] width 1920 pitch 7680 (/4 1920)
>[608210.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c36610]
>[608211.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c36610] width 1920 pitch 7680 (/4 1920)
>[608211.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8710]
>[608211.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8710] width 1920 pitch 7680 (/4 1920)
>[608211.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aeea0]
>[608211.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aeea0] width 1920 pitch 7680 (/4 1920)
>[608211.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3968420]
>[608211.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3968420] width 1920 pitch 7680 (/4 1920)
>[608212.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7c4f0]
>[608212.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7c4f0] width 1920 pitch 7680 (/4 1920)
>[608212.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2617a30]
>[608212.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2617a30] width 1920 pitch 7680 (/4 1920)
>[608213.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2617a30]
>[608213.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2617a30] width 1920 pitch 7680 (/4 1920)
>[608278.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[608278.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[608316.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc79a0]
>[608316.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc79a0] width 1920 pitch 7680 (/4 1920)
>[608328.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3981210]
>[608328.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3981210] width 1920 pitch 7680 (/4 1920)
>[608376.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[608376.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1920 pitch 7680 (/4 1920)
>[608395.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0f220]
>[608395.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0f220] width 1920 pitch 7680 (/4 1920)
>[608395.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39329c0]
>[608395.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39329c0] width 1920 pitch 7680 (/4 1920)
>[608395.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb5450]
>[608395.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb5450] width 1920 pitch 7680 (/4 1920)
>[608395.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39329c0]
>[608395.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39329c0] width 1920 pitch 7680 (/4 1920)
>[608395.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb5450]
>[608395.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb5450] width 1920 pitch 7680 (/4 1920)
>[608395.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c55610]
>[608395.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c55610] width 1920 pitch 7680 (/4 1920)
>[608395.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5006220]
>[608395.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5006220] width 1920 pitch 7680 (/4 1920)
>[608404.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd5c0]
>[608404.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd5c0] width 1920 pitch 7680 (/4 1920)
>[608404.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[608404.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[608404.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd5c0]
>[608404.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd5c0] width 1920 pitch 7680 (/4 1920)
>[608404.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[608404.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[608404.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd5c0]
>[608404.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd5c0] width 1920 pitch 7680 (/4 1920)
>[608404.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15940]
>[608404.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15940] width 1920 pitch 7680 (/4 1920)
>[608404.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd5c0]
>[608404.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd5c0] width 1920 pitch 7680 (/4 1920)
>[608404.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ae80]
>[608404.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ae80] width 1920 pitch 7680 (/4 1920)
>[608408.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[608408.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1920 pitch 7680 (/4 1920)
>[608413.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25c9640]
>[608413.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25c9640] width 1920 pitch 7680 (/4 1920)
>[608413.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625670]
>[608413.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625670] width 1920 pitch 7680 (/4 1920)
>[608413.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c293d0]
>[608413.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c293d0] width 1920 pitch 7680 (/4 1920)
>[608413.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8010]
>[608413.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8010] width 1920 pitch 7680 (/4 1920)
>[608413.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301fab0]
>[608413.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301fab0] width 1920 pitch 7680 (/4 1920)
>[608413.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ff8010]
>[608413.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ff8010] width 1920 pitch 7680 (/4 1920)
>[608413.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301fab0]
>[608413.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301fab0] width 1920 pitch 7680 (/4 1920)
>[608431.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[608431.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[608431.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e538d0]
>[608431.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e538d0] width 1920 pitch 7680 (/4 1920)
>[608431.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[608431.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[608431.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e538d0]
>[608431.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e538d0] width 1920 pitch 7680 (/4 1920)
>[608431.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[608431.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[608431.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e538d0]
>[608431.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e538d0] width 1920 pitch 7680 (/4 1920)
>[608431.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[608431.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[608437.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393b390]
>[608437.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393b390] width 1920 pitch 7680 (/4 1920)
>[608538.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3981210]
>[608538.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3981210] width 1920 pitch 7680 (/4 1920)
>[608545.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e8ce0]
>[608545.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e8ce0] width 1920 pitch 7680 (/4 1920)
>[608620.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b2f080]
>[608620.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b2f080] width 1920 pitch 7680 (/4 1920)
>[608638.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f75940]
>[608638.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f75940] width 1920 pitch 7680 (/4 1920)
>[608640.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3890940]
>[608640.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3890940] width 1920 pitch 7680 (/4 1920)
>[608640.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401e700]
>[608640.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401e700] width 1920 pitch 7680 (/4 1920)
>[608640.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8c920]
>[608640.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8c920] width 1920 pitch 7680 (/4 1920)
>[608640.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401e700]
>[608640.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401e700] width 1920 pitch 7680 (/4 1920)
>[608640.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3890940]
>[608640.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3890940] width 1920 pitch 7680 (/4 1920)
>[608640.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x401e700]
>[608640.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x401e700] width 1920 pitch 7680 (/4 1920)
>[608640.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3890940]
>[608640.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3890940] width 1920 pitch 7680 (/4 1920)
>[608661.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c293d0]
>[608661.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c293d0] width 1920 pitch 7680 (/4 1920)
>[608661.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00140]
>[608661.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00140] width 1920 pitch 7680 (/4 1920)
>[608661.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c293d0]
>[608661.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c293d0] width 1920 pitch 7680 (/4 1920)
>[608661.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00140]
>[608661.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00140] width 1920 pitch 7680 (/4 1920)
>[608661.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c293d0]
>[608661.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c293d0] width 1920 pitch 7680 (/4 1920)
>[608661.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e00140]
>[608661.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e00140] width 1920 pitch 7680 (/4 1920)
>[608661.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c293d0]
>[608661.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c293d0] width 1920 pitch 7680 (/4 1920)
>[608718.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[608718.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[608727.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc79a0]
>[608727.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc79a0] width 1920 pitch 7680 (/4 1920)
>[608803.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40523b0]
>[608803.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40523b0] width 1920 pitch 7680 (/4 1920)
>[608838.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[608838.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1920 pitch 7680 (/4 1920)
>[608843.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b53150]
>[608843.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b53150] width 1920 pitch 7680 (/4 1920)
>[608849.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3941490]
>[608849.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3941490] width 1920 pitch 7680 (/4 1920)
>[608889.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55a50]
>[608889.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55a50] width 1920 pitch 7680 (/4 1920)
>[609016.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3981c30]
>[609016.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3981c30] width 1920 pitch 7680 (/4 1920)
>[609020.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301bd60]
>[609020.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301bd60] width 1920 pitch 7680 (/4 1920)
>[609024.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699ebe0]
>[609024.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699ebe0] width 1920 pitch 7680 (/4 1920)
>[609045.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a0b40]
>[609045.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a0b40] width 1920 pitch 7680 (/4 1920)
>[609133.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b4d800]
>[609133.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b4d800] width 1920 pitch 7680 (/4 1920)
>[609136.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e230]
>[609136.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e230] width 1920 pitch 7680 (/4 1920)
>[609327.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecc1d0]
>[609327.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecc1d0] width 1920 pitch 7680 (/4 1920)
>[609327.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285fa70]
>[609327.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285fa70] width 1920 pitch 7680 (/4 1920)
>[609328.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6a00]
>[609328.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6a00] width 1920 pitch 7680 (/4 1920)
>[609328.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf6a70]
>[609328.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf6a70] width 1920 pitch 7680 (/4 1920)
>[609328.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49be6e0]
>[609328.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49be6e0] width 1920 pitch 7680 (/4 1920)
>[609329.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd2d0]
>[609329.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd2d0] width 1920 pitch 7680 (/4 1920)
>[609329.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a7ae0]
>[609329.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a7ae0] width 1920 pitch 7680 (/4 1920)
>[609329.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe05d0]
>[609329.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe05d0] width 1920 pitch 7680 (/4 1920)
>[609329.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a7ae0]
>[609329.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a7ae0] width 1920 pitch 7680 (/4 1920)
>[609629.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6290]
>[609629.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6290] width 1920 pitch 7680 (/4 1920)
>[609629.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef2550]
>[609630.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef2550] width 1920 pitch 7680 (/4 1920)
>[609630.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bacd80]
>[609630.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bacd80] width 1920 pitch 7680 (/4 1920)
>[609630.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51302f0]
>[609630.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51302f0] width 1920 pitch 7680 (/4 1920)
>[609630.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc4260]
>[609630.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc4260] width 1920 pitch 7680 (/4 1920)
>[609630.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609630.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609630.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609630.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609630.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609630.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609630.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609631.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609631.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609631.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609631.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609631.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609631.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609631.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609631.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609631.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609634.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609634.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609634.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d710]
>[609634.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d710] width 1920 pitch 7680 (/4 1920)
>[609634.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609634.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609635.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d710]
>[609635.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d710] width 1920 pitch 7680 (/4 1920)
>[609635.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609635.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609635.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d710]
>[609636.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d710] width 1920 pitch 7680 (/4 1920)
>[609636.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b860]
>[609636.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b860] width 1920 pitch 7680 (/4 1920)
>[609636.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0d710]
>[609636.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0d710] width 1920 pitch 7680 (/4 1920)
>[609637.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609637.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609648.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed6290]
>[609648.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed6290] width 1920 pitch 7680 (/4 1920)
>[609649.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6db0]
>[609649.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6db0] width 1920 pitch 7680 (/4 1920)
>[609649.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6db0]
>[609649.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6db0] width 1920 pitch 7680 (/4 1920)
>[609650.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609650.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609650.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6db0]
>[609650.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6db0] width 1920 pitch 7680 (/4 1920)
>[609651.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3ea0]
>[609651.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3ea0] width 1920 pitch 7680 (/4 1920)
>[609652.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4becff0]
>[609652.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4becff0] width 1920 pitch 7680 (/4 1920)
>[609652.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e3ea0]
>[609652.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e3ea0] width 1920 pitch 7680 (/4 1920)
>[609652.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609652.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609652.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4becff0]
>[609653.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4becff0] width 1920 pitch 7680 (/4 1920)
>[609653.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609653.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609745.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec8c0]
>[609745.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec8c0] width 1920 pitch 7680 (/4 1920)
>[609745.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c05d30]
>[609745.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c05d30] width 1920 pitch 7680 (/4 1920)
>[609746.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4268830]
>[609746.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4268830] width 1920 pitch 7680 (/4 1920)
>[609746.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609746.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609746.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609746.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609747.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609747.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609788.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd870]
>[609788.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd870] width 1920 pitch 7680 (/4 1920)
>[609788.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb94f0]
>[609788.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb94f0] width 1920 pitch 7680 (/4 1920)
>[609790.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609790.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609790.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609790.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609791.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609791.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609791.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609791.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609791.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609791.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609791.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609791.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609791.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609791.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609792.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609792.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609792.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609792.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609792.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609792.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609792.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041440]
>[609792.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041440] width 1920 pitch 7680 (/4 1920)
>[609792.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609792.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609792.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609792.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609792.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609793.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609793.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609793.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609793.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609793.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609793.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609793.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609794.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609794.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609794.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609794.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[609794.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef5b30]
>[609794.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef5b30] width 1920 pitch 7680 (/4 1920)
>[609794.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dedf10]
>[609794.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dedf10] width 1920 pitch 7680 (/4 1920)
>[610442.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5025300]
>[610442.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5025300] width 1920 pitch 7680 (/4 1920)
>[610444.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[610444.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1920 pitch 7680 (/4 1920)
>[610444.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a61540]
>[610444.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a61540] width 1920 pitch 7680 (/4 1920)
>[610444.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a61540]
>[610444.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a61540] width 1920 pitch 7680 (/4 1920)
>[610445.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395e110]
>[610445.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395e110] width 1920 pitch 7680 (/4 1920)
>[610445.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf6f0]
>[610445.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf6f0] width 1920 pitch 7680 (/4 1920)
>[610445.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a15980]
>[610445.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a15980] width 1920 pitch 7680 (/4 1920)
>[610445.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841850]
>[610445.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841850] width 1920 pitch 7680 (/4 1920)
>[610445.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f80b0]
>[610445.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f80b0] width 1920 pitch 7680 (/4 1920)
>[610465.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cdeb80]
>[610465.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cdeb80] width 1920 pitch 7680 (/4 1920)
>[610571.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dba760]
>[610571.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dba760] width 1920 pitch 7680 (/4 1920)
>[610571.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96ce0]
>[610571.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96ce0] width 1920 pitch 7680 (/4 1920)
>[610571.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49ba640]
>[610571.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49ba640] width 1920 pitch 7680 (/4 1920)
>[610571.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[610571.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1920 pitch 7680 (/4 1920)
>[610571.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284f940]
>[610571.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284f940] width 1920 pitch 7680 (/4 1920)
>[610571.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[610571.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1920 pitch 7680 (/4 1920)
>[610646.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c240]
>[610646.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c240] width 1920 pitch 7680 (/4 1920)
>[610647.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baf470]
>[610647.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baf470] width 1920 pitch 7680 (/4 1920)
>[610647.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c9550]
>[610648.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c9550] width 1920 pitch 7680 (/4 1920)
>[610648.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c95b0]
>[610648.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c95b0] width 1920 pitch 7680 (/4 1920)
>[610648.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c95b0]
>[610648.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c95b0] width 1920 pitch 7680 (/4 1920)
>[610648.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d770]
>[610648.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d770] width 1920 pitch 7680 (/4 1920)
>[610657.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f5490]
>[610657.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f5490] width 1920 pitch 7680 (/4 1920)
>[610657.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4b260]
>[610657.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4b260] width 1920 pitch 7680 (/4 1920)
>[610657.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a16390]
>[610658.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a16390] width 1920 pitch 7680 (/4 1920)
>[610658.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3842910]
>[610658.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3842910] width 1920 pitch 7680 (/4 1920)
>[610890.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402c3e0]
>[610890.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402c3e0] width 1920 pitch 7680 (/4 1920)
>[610892.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd150]
>[610892.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd150] width 1920 pitch 7680 (/4 1920)
>[610892.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5dff0]
>[610892.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5dff0] width 1920 pitch 7680 (/4 1920)
>[610892.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe5130]
>[610892.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe5130] width 1920 pitch 7680 (/4 1920)
>[610892.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f43630]
>[610893.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f43630] width 1920 pitch 7680 (/4 1920)
>[610912.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[610912.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1920 pitch 7680 (/4 1920)
>[610972.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58534d0]
>[610972.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58534d0] width 1920 pitch 7680 (/4 1920)
>[610972.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[610972.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1920 pitch 7680 (/4 1920)
>[610972.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca3ac0]
>[610972.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca3ac0] width 1920 pitch 7680 (/4 1920)
>[610972.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[610972.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1920 pitch 7680 (/4 1920)
>[610972.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca3ac0]
>[610972.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca3ac0] width 1920 pitch 7680 (/4 1920)
>[611109.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3884ee0]
>[611109.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3884ee0] width 1920 pitch 7680 (/4 1920)
>[611109.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[611110.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[611110.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e020]
>[611110.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e020] width 1920 pitch 7680 (/4 1920)
>[611111.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686d3a0]
>[611111.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686d3a0] width 1920 pitch 7680 (/4 1920)
>[611111.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388e040]
>[611111.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388e040] width 1920 pitch 7680 (/4 1920)
>[611111.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[611111.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[611111.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611111.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611111.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[611111.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[611111.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611112.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611112.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[611112.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[611112.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611112.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611112.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[611112.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[611113.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611113.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611113.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686d3a0]
>[611113.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686d3a0] width 1920 pitch 7680 (/4 1920)
>[611113.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611113.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611113.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686d3a0]
>[611113.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686d3a0] width 1920 pitch 7680 (/4 1920)
>[611113.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebfd0]
>[611113.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebfd0] width 1920 pitch 7680 (/4 1920)
>[611113.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686d3a0]
>[611113.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686d3a0] width 1920 pitch 7680 (/4 1920)
>[611438.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d2ab0]
>[611438.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d2ab0] width 1920 pitch 7680 (/4 1920)
>[611438.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d2ab0]
>[611438.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d2ab0] width 1920 pitch 7680 (/4 1920)
>[611439.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[611439.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1920 pitch 7680 (/4 1920)
>[611440.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e4c240]
>[611440.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e4c240] width 1920 pitch 7680 (/4 1920)
>[611451.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[611451.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1920 pitch 7680 (/4 1920)
>[611644.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27013f0]
>[611645.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27013f0] width 1920 pitch 7680 (/4 1920)
>[611645.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699d780]
>[611645.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699d780] width 1920 pitch 7680 (/4 1920)
>[611645.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27013f0]
>[611645.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27013f0] width 1920 pitch 7680 (/4 1920)
>[611646.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bba7c0]
>[611646.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bba7c0] width 1920 pitch 7680 (/4 1920)
>[611647.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac8150]
>[611647.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac8150] width 1920 pitch 7680 (/4 1920)
>[611861.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39420]
>[611861.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39420] width 1920 pitch 7680 (/4 1920)
>[612117.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[612117.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[612117.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7f10]
>[612117.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7f10] width 1920 pitch 7680 (/4 1920)
>[612117.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[612117.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[612117.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7f10]
>[612117.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7f10] width 1920 pitch 7680 (/4 1920)
>[612117.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[612117.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[612118.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405d360]
>[612118.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405d360] width 1920 pitch 7680 (/4 1920)
>[612137.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f771a0]
>[612137.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f771a0] width 1920 pitch 7680 (/4 1920)
>[612464.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f4db0]
>[612464.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f4db0] width 1920 pitch 7680 (/4 1920)
>[612464.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe5160]
>[612464.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe5160] width 1920 pitch 7680 (/4 1920)
>[612464.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fcabe0]
>[612464.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fcabe0] width 1920 pitch 7680 (/4 1920)
>[612464.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5025300]
>[612464.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5025300] width 1920 pitch 7680 (/4 1920)
>[612485.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ec020]
>[612485.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ec020] width 1920 pitch 7680 (/4 1920)
>[612488.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[612488.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1920 pitch 7680 (/4 1920)
>[612488.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec1a50]
>[612488.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec1a50] width 1920 pitch 7680 (/4 1920)
>[612488.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[612488.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1920 pitch 7680 (/4 1920)
>[612488.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e89a0]
>[612488.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e89a0] width 1920 pitch 7680 (/4 1920)
>[612488.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e89a0]
>[612488.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e89a0] width 1920 pitch 7680 (/4 1920)
>[612488.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e89a0]
>[612489.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e89a0] width 1920 pitch 7680 (/4 1920)
>[612500.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39f57d0]
>[612500.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39f57d0] width 1920 pitch 7680 (/4 1920)
>[612500.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50af920]
>[612500.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50af920] width 1920 pitch 7680 (/4 1920)
>[612500.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b5e0]
>[612500.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b5e0] width 1920 pitch 7680 (/4 1920)
>[612799.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38df290]
>[612799.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38df290] width 1920 pitch 7680 (/4 1920)
>[612801.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c18ae0]
>[612801.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c18ae0] width 1920 pitch 7680 (/4 1920)
>[612802.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c18ae0]
>[612802.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c18ae0] width 1920 pitch 7680 (/4 1920)
>[612803.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f38370]
>[612803.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f38370] width 1920 pitch 7680 (/4 1920)
>[612804.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b64120]
>[612804.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b64120] width 1920 pitch 7680 (/4 1920)
>[612806.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[612806.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1920 pitch 7680 (/4 1920)
>[612806.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[612806.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1920 pitch 7680 (/4 1920)
>[612806.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7990]
>[612806.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7990] width 1920 pitch 7680 (/4 1920)
>[612806.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977a50]
>[612806.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977a50] width 1920 pitch 7680 (/4 1920)
>[612808.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67c70]
>[612808.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67c70] width 1920 pitch 7680 (/4 1920)
>[612808.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bb8a0]
>[612808.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bb8a0] width 1920 pitch 7680 (/4 1920)
>[612809.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67c70]
>[612809.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67c70] width 1920 pitch 7680 (/4 1920)
>[612809.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bb8a0]
>[612809.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bb8a0] width 1920 pitch 7680 (/4 1920)
>[612811.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bb8a0]
>[612811.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bb8a0] width 1920 pitch 7680 (/4 1920)
>[612811.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977d40]
>[612811.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977d40] width 1920 pitch 7680 (/4 1920)
>[612821.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3810]
>[612822.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3810] width 1920 pitch 7680 (/4 1920)
>[612917.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40560b0]
>[612917.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40560b0] width 1920 pitch 7680 (/4 1920)
>[612917.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5975a50]
>[612917.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5975a50] width 1920 pitch 7680 (/4 1920)
>[612918.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40560b0]
>[612918.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40560b0] width 1920 pitch 7680 (/4 1920)
>[612918.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5975a50]
>[612918.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5975a50] width 1920 pitch 7680 (/4 1920)
>[612918.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5975a50]
>[612918.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5975a50] width 1920 pitch 7680 (/4 1920)
>[612919.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5977d40]
>[612919.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5977d40] width 1920 pitch 7680 (/4 1920)
>[613024.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59775b0]
>[613024.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59775b0] width 1920 pitch 7680 (/4 1920)
>[613024.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b61190]
>[613024.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b61190] width 1920 pitch 7680 (/4 1920)
>[613024.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[613025.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1920 pitch 7680 (/4 1920)
>[613212.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[613212.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1920 pitch 7680 (/4 1920)
>[613213.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68818a0]
>[613213.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68818a0] width 1920 pitch 7680 (/4 1920)
>[613213.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[613213.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1920 pitch 7680 (/4 1920)
>[613213.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68818a0]
>[613213.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68818a0] width 1920 pitch 7680 (/4 1920)
>[613215.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[613215.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1920 pitch 7680 (/4 1920)
>[613216.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68818a0]
>[613216.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68818a0] width 1920 pitch 7680 (/4 1920)
>[613217.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612d0]
>[613217.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612d0] width 1920 pitch 7680 (/4 1920)
>[613217.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612d0]
>[613218.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612d0] width 1920 pitch 7680 (/4 1920)
>[613518.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613518.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613518.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612d0]
>[613518.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612d0] width 1920 pitch 7680 (/4 1920)
>[613518.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613518.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613518.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612d0]
>[613518.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612d0] width 1920 pitch 7680 (/4 1920)
>[613518.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613519.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613519.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612d0]
>[613519.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612d0] width 1920 pitch 7680 (/4 1920)
>[613519.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613519.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613520.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613520.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613520.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613521.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613521.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613521.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613529.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613529.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613529.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613529.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613529.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613529.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613529.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613530.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613530.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613530.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613530.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613530.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613531.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613531.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613531.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894230]
>[613531.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894230] width 1920 pitch 7680 (/4 1920)
>[613532.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40296f0]
>[613532.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40296f0] width 1920 pitch 7680 (/4 1920)
>[613532.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613532.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613532.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40296f0]
>[613532.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40296f0] width 1920 pitch 7680 (/4 1920)
>[613532.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613532.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613532.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40296f0]
>[613533.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40296f0] width 1920 pitch 7680 (/4 1920)
>[613534.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613534.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613535.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c90]
>[613535.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c90] width 1920 pitch 7680 (/4 1920)
>[613535.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613535.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613535.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613535.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613626.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613627.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613627.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a465b0]
>[613627.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a465b0] width 1920 pitch 7680 (/4 1920)
>[613627.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a465b0]
>[613627.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a465b0] width 1920 pitch 7680 (/4 1920)
>[613628.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d2ab0]
>[613628.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d2ab0] width 1920 pitch 7680 (/4 1920)
>[613628.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b331d0]
>[613628.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b331d0] width 1920 pitch 7680 (/4 1920)
>[613628.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c8d50]
>[613629.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c8d50] width 1920 pitch 7680 (/4 1920)
>[613629.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c8b40]
>[613629.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c8b40] width 1920 pitch 7680 (/4 1920)
>[613629.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b331d0]
>[613630.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b331d0] width 1920 pitch 7680 (/4 1920)
>[613630.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b612a0]
>[613630.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b612a0] width 1920 pitch 7680 (/4 1920)
>[613630.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e23ba0]
>[613630.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e23ba0] width 1920 pitch 7680 (/4 1920)
>[613651.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a7790]
>[613652.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a7790] width 1920 pitch 7680 (/4 1920)
>[613655.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5895d20]
>[613655.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5895d20] width 1920 pitch 7680 (/4 1920)
>[613655.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dec20]
>[613655.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dec20] width 1920 pitch 7680 (/4 1920)
>[613655.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeee70]
>[613655.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeee70] width 1920 pitch 7680 (/4 1920)
>[613655.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e7b0]
>[613655.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e7b0] width 1920 pitch 7680 (/4 1920)
>[613668.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c7380]
>[613668.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c7380] width 1920 pitch 7680 (/4 1920)
>[613670.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf01c0]
>[613670.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf01c0] width 1920 pitch 7680 (/4 1920)
>[613670.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b66e30]
>[613671.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b66e30] width 1920 pitch 7680 (/4 1920)
>[613671.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de8ee0]
>[613671.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de8ee0] width 1920 pitch 7680 (/4 1920)
>[613671.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b85ed0]
>[613671.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b85ed0] width 1920 pitch 7680 (/4 1920)
>[613671.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982bb0]
>[613671.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982bb0] width 1920 pitch 7680 (/4 1920)
>[613672.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613672.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613672.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613672.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613673.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613673.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613673.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613673.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613673.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613673.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613673.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613673.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613673.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613674.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613674.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613674.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613674.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613674.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613674.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b86df0]
>[613675.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b86df0] width 1920 pitch 7680 (/4 1920)
>[613675.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59163c0]
>[613675.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59163c0] width 1920 pitch 7680 (/4 1920)
>[613675.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5915a50]
>[613675.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5915a50] width 1920 pitch 7680 (/4 1920)
>[613677.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a2b00]
>[613677.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a2b00] width 1920 pitch 7680 (/4 1920)
>[613681.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[613681.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1920 pitch 7680 (/4 1920)
>[613681.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613681.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613681.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5915a50]
>[613681.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5915a50] width 1920 pitch 7680 (/4 1920)
>[613695.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f07890]
>[613695.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f07890] width 1920 pitch 7680 (/4 1920)
>[613761.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f07930]
>[613761.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f07930] width 1920 pitch 7680 (/4 1920)
>[613762.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38df0c0]
>[613762.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38df0c0] width 1920 pitch 7680 (/4 1920)
>[613763.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3cee0]
>[613763.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3cee0] width 1920 pitch 7680 (/4 1920)
>[613763.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c4f0]
>[613763.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c4f0] width 1920 pitch 7680 (/4 1920)
>[613763.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c4f0]
>[613763.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c4f0] width 1920 pitch 7680 (/4 1920)
>[613763.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300ad60]
>[613763.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300ad60] width 1920 pitch 7680 (/4 1920)
>[613769.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a8970]
>[613769.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a8970] width 1920 pitch 7680 (/4 1920)
>[613777.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[613777.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[613778.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4781ae0]
>[613778.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4781ae0] width 1920 pitch 7680 (/4 1920)
>[613778.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478ed50]
>[613778.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478ed50] width 1920 pitch 7680 (/4 1920)
>[613783.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478e180]
>[613783.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478e180] width 1920 pitch 7680 (/4 1920)
>[613783.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[613783.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[613784.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[613784.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[613784.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4781ae0]
>[613784.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4781ae0] width 1920 pitch 7680 (/4 1920)
>[613784.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300ad60]
>[613784.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300ad60] width 1920 pitch 7680 (/4 1920)
>[613784.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478e180]
>[613784.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478e180] width 1920 pitch 7680 (/4 1920)
>[613784.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[613784.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[613785.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49bb780]
>[613786.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49bb780] width 1920 pitch 7680 (/4 1920)
>[613786.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49bb780]
>[613786.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49bb780] width 1920 pitch 7680 (/4 1920)
>[613788.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383feb0]
>[613788.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383feb0] width 1920 pitch 7680 (/4 1920)
>[613788.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5130]
>[613788.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5130] width 1920 pitch 7680 (/4 1920)
>[613789.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47814c0]
>[613789.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47814c0] width 1920 pitch 7680 (/4 1920)
>[613789.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x383feb0]
>[613790.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x383feb0] width 1920 pitch 7680 (/4 1920)
>[613790.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef440]
>[613790.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef440] width 1920 pitch 7680 (/4 1920)
>[613790.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef2f0]
>[613790.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef2f0] width 1920 pitch 7680 (/4 1920)
>[613790.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef440]
>[613790.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef440] width 1920 pitch 7680 (/4 1920)
>[613792.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a9b50]
>[613793.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a9b50] width 1920 pitch 7680 (/4 1920)
>[613798.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a2b00]
>[613798.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a2b00] width 1920 pitch 7680 (/4 1920)
>[613798.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a2b00]
>[613798.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a2b00] width 1920 pitch 7680 (/4 1920)
>[613806.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478e180]
>[613806.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478e180] width 1920 pitch 7680 (/4 1920)
>[613806.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df2cf0]
>[613806.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df2cf0] width 1920 pitch 7680 (/4 1920)
>[613831.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a4aa00]
>[613831.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a4aa00] width 1920 pitch 7680 (/4 1920)
>[613831.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613831.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613831.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd65d0]
>[613831.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd65d0] width 1920 pitch 7680 (/4 1920)
>[613832.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[613832.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[613832.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a5c20]
>[613832.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a5c20] width 1920 pitch 7680 (/4 1920)
>[613832.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c53670]
>[613832.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c53670] width 1920 pitch 7680 (/4 1920)
>[613847.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[613847.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[613847.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b61680]
>[613847.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b61680] width 1920 pitch 7680 (/4 1920)
>[613848.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c45f80]
>[613848.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c45f80] width 1920 pitch 7680 (/4 1920)
>[613848.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613848.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613848.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5017710]
>[613849.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5017710] width 1920 pitch 7680 (/4 1920)
>[613849.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613849.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613853.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49acd90]
>[613853.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49acd90] width 1920 pitch 7680 (/4 1920)
>[613853.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613853.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613853.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x504ad60]
>[613853.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x504ad60] width 1920 pitch 7680 (/4 1920)
>[613854.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[613854.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[613854.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[613854.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[613855.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[613855.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[613859.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[613859.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[613859.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9de70]
>[613859.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9de70] width 1920 pitch 7680 (/4 1920)
>[613860.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[613860.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[613860.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7a90]
>[613860.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7a90] width 1920 pitch 7680 (/4 1920)
>[613860.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7a90]
>[613860.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7a90] width 1920 pitch 7680 (/4 1920)
>[613886.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0a5b0]
>[613886.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0a5b0] width 1920 pitch 7680 (/4 1920)
>[613886.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[613886.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1920 pitch 7680 (/4 1920)
>[613887.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3cb40]
>[613887.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3cb40] width 1920 pitch 7680 (/4 1920)
>[613887.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9540]
>[613888.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9540] width 1920 pitch 7680 (/4 1920)
>[613888.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ff0]
>[613888.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ff0] width 1920 pitch 7680 (/4 1920)
>[613888.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fc40]
>[613888.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fc40] width 1920 pitch 7680 (/4 1920)
>[613888.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5f020]
>[613888.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5f020] width 1920 pitch 7680 (/4 1920)
>[613888.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03850]
>[613888.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03850] width 1920 pitch 7680 (/4 1920)
>[613889.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3928220]
>[613889.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3928220] width 1920 pitch 7680 (/4 1920)
>[613889.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3928220]
>[613889.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3928220] width 1920 pitch 7680 (/4 1920)
>[613890.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fc40]
>[613890.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fc40] width 1920 pitch 7680 (/4 1920)
>[613891.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9de70]
>[613891.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9de70] width 1920 pitch 7680 (/4 1920)
>[613891.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[613891.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[613891.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613891.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613892.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[613892.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1920 pitch 7680 (/4 1920)
>[613892.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3aa40]
>[613892.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3aa40] width 1920 pitch 7680 (/4 1920)
>[613892.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5f020]
>[613893.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5f020] width 1920 pitch 7680 (/4 1920)
>[613908.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[613908.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[613908.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[613908.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[613908.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40c6d10]
>[613908.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40c6d10] width 1920 pitch 7680 (/4 1920)
>[613935.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b61680]
>[613935.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b61680] width 1920 pitch 7680 (/4 1920)
>[613935.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[613935.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[614165.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4798970]
>[614165.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4798970] width 1920 pitch 7680 (/4 1920)
>[614308.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9de70]
>[614308.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9de70] width 1920 pitch 7680 (/4 1920)
>[614308.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3928220]
>[614308.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3928220] width 1920 pitch 7680 (/4 1920)
>[614500.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a24e30]
>[614500.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a24e30] width 1920 pitch 7680 (/4 1920)
>[614515.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940e70]
>[614515.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940e70] width 1920 pitch 7680 (/4 1920)
>[614566.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47994e0]
>[614567.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47994e0] width 1920 pitch 7680 (/4 1920)
>[614678.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59414e0]
>[614679.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59414e0] width 1920 pitch 7680 (/4 1920)
>[615540.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59436c0]
>[615540.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59436c0] width 1920 pitch 7680 (/4 1920)
>[615560.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a0460]
>[615560.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a0460] width 1920 pitch 7680 (/4 1920)
>[615937.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47902e0]
>[615937.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47902e0] width 1920 pitch 7680 (/4 1920)
>[616080.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5941290]
>[616080.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5941290] width 1920 pitch 7680 (/4 1920)
>[616093.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e14e0]
>[616093.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e14e0] width 1920 pitch 7680 (/4 1920)
>[616137.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a24a0]
>[616137.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a24a0] width 1920 pitch 7680 (/4 1920)
>[616142.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6370]
>[616143.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6370] width 1920 pitch 7680 (/4 1920)
>[616143.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c9de70]
>[616143.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c9de70] width 1920 pitch 7680 (/4 1920)
>[616143.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6370]
>[616143.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6370] width 1920 pitch 7680 (/4 1920)
>[616205.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5941040]
>[616205.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5941040] width 1920 pitch 7680 (/4 1920)
>[616425.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5f020]
>[616425.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5f020] width 1920 pitch 7680 (/4 1920)
>[616425.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69aeea0]
>[616425.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69aeea0] width 1920 pitch 7680 (/4 1920)
>[616460.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865fa0]
>[616460.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865fa0] width 1920 pitch 7680 (/4 1920)
>[616461.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fc40]
>[616461.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fc40] width 1920 pitch 7680 (/4 1920)
>[616461.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf3590]
>[616461.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf3590] width 1920 pitch 7680 (/4 1920)
>[616461.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fc40]
>[616461.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fc40] width 1920 pitch 7680 (/4 1920)
>[616509.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479dcf0]
>[616509.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479dcf0] width 1920 pitch 7680 (/4 1920)
>[616509.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6bb0]
>[616509.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6bb0] width 1920 pitch 7680 (/4 1920)
>[616509.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780560]
>[616510.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780560] width 1920 pitch 7680 (/4 1920)
>[616510.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28480]
>[616510.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28480] width 1920 pitch 7680 (/4 1920)
>[616550.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bed660]
>[616550.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bed660] width 1920 pitch 7680 (/4 1920)
>[616694.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1dbd0]
>[616694.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1dbd0] width 1920 pitch 7680 (/4 1920)
>[616695.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5f020]
>[616695.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5f020] width 1920 pitch 7680 (/4 1920)
>[616695.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[616695.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[616696.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fe3f0]
>[616696.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fe3f0] width 1920 pitch 7680 (/4 1920)
>[616696.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fe3f0]
>[616696.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fe3f0] width 1920 pitch 7680 (/4 1920)
>[617119.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a30af0]
>[617119.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a30af0] width 1920 pitch 7680 (/4 1920)
>[617119.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc84d0]
>[617119.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc84d0] width 1920 pitch 7680 (/4 1920)
>[617688.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59da990]
>[617688.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59da990] width 1920 pitch 7680 (/4 1920)
>[617688.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28480]
>[617688.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28480] width 1920 pitch 7680 (/4 1920)
>[617688.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b61680]
>[617688.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b61680] width 1920 pitch 7680 (/4 1920)
>[617689.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[617689.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[617689.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[617689.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[617689.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50d9170]
>[617689.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50d9170] width 1920 pitch 7680 (/4 1920)
>[617690.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[617690.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[617690.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a21c20]
>[617690.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a21c20] width 1920 pitch 7680 (/4 1920)
>[617690.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[617690.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[617710.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e3a0]
>[617710.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e3a0] width 1920 pitch 7680 (/4 1920)
>[617710.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1c760]
>[617710.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1c760] width 1920 pitch 7680 (/4 1920)
>[617990.899] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[617990.899] (II) RADEON(0): Using hsync ranges from config file
>[617990.899] (II) RADEON(0): Using vrefresh ranges from config file
>[617990.899] (II) RADEON(0): Printing DDC gathered Modelines:
>[617990.899] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[617990.899] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[617990.899] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[617990.899] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[617990.899] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[617990.899] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[617990.899] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[617990.899] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[617990.899] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[617990.899] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[617990.899] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[618080.755] (II) RADEON(0): RADEONSaveScreen(2)
>[618080.755] (II) RADEON(0): RADEONSaveScreen(0)
>[618219.855] (II) RADEON(0): RADEONSaveScreen(1)
>[618231.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[618231.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[618316.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6f60]
>[618316.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6f60] width 1920 pitch 7680 (/4 1920)
>[618316.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[618316.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[618317.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf3590]
>[618317.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf3590] width 1920 pitch 7680 (/4 1920)
>[618317.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb2370]
>[618317.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb2370] width 1920 pitch 7680 (/4 1920)
>[618318.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a418b0]
>[618318.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a418b0] width 1920 pitch 7680 (/4 1920)
>[618736.617] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[618736.617] (II) RADEON(0): Using hsync ranges from config file
>[618736.617] (II) RADEON(0): Using vrefresh ranges from config file
>[618736.617] (II) RADEON(0): Printing DDC gathered Modelines:
>[618736.617] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[618736.617] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[618736.617] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[618736.618] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[618736.618] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[618736.618] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[618736.618] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[618736.618] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[618736.618] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[618736.618] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[618736.618] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[618826.799] (II) RADEON(0): RADEONSaveScreen(2)
>[618826.799] (II) RADEON(0): RADEONSaveScreen(0)
>[619682.899] (II) RADEON(0): RADEONSaveScreen(1)
>[620073.747] (II) RADEON(0): RADEONSaveScreen(2)
>[620073.748] (II) RADEON(0): RADEONSaveScreen(0)
>[621655.075] (II) RADEON(0): RADEONSaveScreen(1)
>[621713.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d55440]
>[621714.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d55440] width 1920 pitch 7680 (/4 1920)
>[621714.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0a120]
>[621714.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0a120] width 1920 pitch 7680 (/4 1920)
>[621871.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f9e60]
>[621871.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f9e60] width 1920 pitch 7680 (/4 1920)
>[621871.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0bda0]
>[621871.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0bda0] width 1920 pitch 7680 (/4 1920)
>[621871.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6f60]
>[621871.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6f60] width 1920 pitch 7680 (/4 1920)
>[621872.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28480]
>[621872.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28480] width 1920 pitch 7680 (/4 1920)
>[621872.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780560]
>[621872.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780560] width 1920 pitch 7680 (/4 1920)
>[621872.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d4600]
>[621872.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d4600] width 1920 pitch 7680 (/4 1920)
>[621872.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3928220]
>[621872.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3928220] width 1920 pitch 7680 (/4 1920)
>[621872.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a310]
>[621872.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a310] width 1920 pitch 7680 (/4 1920)
>[621872.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a41730]
>[621872.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a41730] width 1920 pitch 7680 (/4 1920)
>[621872.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f9aa0]
>[621872.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f9aa0] width 1920 pitch 7680 (/4 1920)
>[621872.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef9cf0]
>[621872.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef9cf0] width 1920 pitch 7680 (/4 1920)
>[621872.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fc40]
>[621873.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fc40] width 1920 pitch 7680 (/4 1920)
>[621873.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a360d0]
>[621873.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a360d0] width 1920 pitch 7680 (/4 1920)
>[621893.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59da990]
>[621893.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59da990] width 1920 pitch 7680 (/4 1920)
>[621893.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1cea0]
>[621893.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1cea0] width 1920 pitch 7680 (/4 1920)
>[621893.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0bda0]
>[621894.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0bda0] width 1920 pitch 7680 (/4 1920)
>[622665.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3de0]
>[622665.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3de0] width 1920 pitch 7680 (/4 1920)
>[622904.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[622904.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1920 pitch 7680 (/4 1920)
>[622904.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4d960]
>[622904.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4d960] width 1920 pitch 7680 (/4 1920)
>[622904.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[622904.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1920 pitch 7680 (/4 1920)
>[622907.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4d960]
>[622907.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4d960] width 1920 pitch 7680 (/4 1920)
>[622907.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26338f0]
>[622907.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26338f0] width 1920 pitch 7680 (/4 1920)
>[622907.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2a4c0]
>[622908.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2a4c0] width 1920 pitch 7680 (/4 1920)
>[623593.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e000]
>[623593.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e000] width 1920 pitch 7680 (/4 1920)
>[623593.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a34f0]
>[623593.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a34f0] width 1920 pitch 7680 (/4 1920)
>[623593.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e000]
>[623593.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e000] width 1920 pitch 7680 (/4 1920)
>[623593.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a34f0]
>[623593.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a34f0] width 1920 pitch 7680 (/4 1920)
>[623593.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e000]
>[623593.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e000] width 1920 pitch 7680 (/4 1920)
>[623594.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e000]
>[623594.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e000] width 1920 pitch 7680 (/4 1920)
>[623599.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a34f0]
>[623599.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a34f0] width 1920 pitch 7680 (/4 1920)
>[623599.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a1a60]
>[623599.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a1a60] width 1920 pitch 7680 (/4 1920)
>[623599.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a34f0]
>[623599.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a34f0] width 1920 pitch 7680 (/4 1920)
>[623599.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3e000]
>[623599.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3e000] width 1920 pitch 7680 (/4 1920)
>[623599.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a34f0]
>[623599.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a34f0] width 1920 pitch 7680 (/4 1920)
>[624029.407] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[624029.407] (II) RADEON(0): Using hsync ranges from config file
>[624029.407] (II) RADEON(0): Using vrefresh ranges from config file
>[624029.407] (II) RADEON(0): Printing DDC gathered Modelines:
>[624029.407] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[624029.408] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[624029.408] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[624029.408] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[624029.408] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[624029.408] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[624029.408] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[624029.408] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[624029.408] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[624029.408] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[624029.408] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[624104.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59410e0]
>[624104.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59410e0] width 1920 pitch 7680 (/4 1920)
>[624115.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597ff80]
>[624115.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597ff80] width 1920 pitch 7680 (/4 1920)
>[624140.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301fab0]
>[624140.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301fab0] width 1920 pitch 7680 (/4 1920)
>[624140.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0f00]
>[624140.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0f00] width 1920 pitch 7680 (/4 1920)
>[624717.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40292a0]
>[624717.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40292a0] width 1920 pitch 7680 (/4 1920)
>[624717.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913400]
>[624717.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913400] width 1920 pitch 7680 (/4 1920)
>[624718.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f918c0]
>[624718.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f918c0] width 1920 pitch 7680 (/4 1920)
>[624718.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6370]
>[624718.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6370] width 1920 pitch 7680 (/4 1920)
>[624718.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[624718.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1920 pitch 7680 (/4 1920)
>[624719.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[624719.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1920 pitch 7680 (/4 1920)
>[624719.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a300]
>[624719.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a300] width 1920 pitch 7680 (/4 1920)
>[624719.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bacee0]
>[624719.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bacee0] width 1920 pitch 7680 (/4 1920)
>[624719.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6370]
>[624719.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6370] width 1920 pitch 7680 (/4 1920)
>[624719.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bacee0]
>[624719.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bacee0] width 1920 pitch 7680 (/4 1920)
>[624720.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687fe00]
>[624720.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687fe00] width 1920 pitch 7680 (/4 1920)
>[624720.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f918c0]
>[624720.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f918c0] width 1920 pitch 7680 (/4 1920)
>[624720.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e347e0]
>[624721.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e347e0] width 1920 pitch 7680 (/4 1920)
>[624721.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef4080]
>[624721.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef4080] width 1920 pitch 7680 (/4 1920)
>[624721.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x509cb30]
>[624721.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x509cb30] width 1920 pitch 7680 (/4 1920)
>[624721.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4df70]
>[624722.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4df70] width 1920 pitch 7680 (/4 1920)
>[625337.550] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[625337.550] (II) RADEON(0): Using hsync ranges from config file
>[625337.550] (II) RADEON(0): Using vrefresh ranges from config file
>[625337.550] (II) RADEON(0): Printing DDC gathered Modelines:
>[625337.550] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[625337.550] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[625337.550] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[625337.550] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[625337.550] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[625337.550] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[625337.550] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[625337.550] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[625337.550] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[625337.550] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[625337.550] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[625427.753] (II) RADEON(0): RADEONSaveScreen(2)
>[625427.754] (II) RADEON(0): RADEONSaveScreen(0)
>[626691.403] (II) RADEON(0): RADEONSaveScreen(1)
>[626704.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c56e30]
>[626704.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c56e30] width 1920 pitch 7680 (/4 1920)
>[626705.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683540]
>[626705.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683540] width 1920 pitch 7680 (/4 1920)
>[626705.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9ef0]
>[626705.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9ef0] width 1920 pitch 7680 (/4 1920)
>[626706.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393aba0]
>[626706.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393aba0] width 1920 pitch 7680 (/4 1920)
>[626715.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3981210]
>[626715.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3981210] width 1920 pitch 7680 (/4 1920)
>[626715.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5957100]
>[626715.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5957100] width 1920 pitch 7680 (/4 1920)
>[626715.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9140]
>[626715.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9140] width 1920 pitch 7680 (/4 1920)
>[627506.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4d500]
>[627506.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4d500] width 1920 pitch 7680 (/4 1920)
>[627506.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ade670]
>[627506.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ade670] width 1920 pitch 7680 (/4 1920)
>[627507.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f0200]
>[627507.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f0200] width 1920 pitch 7680 (/4 1920)
>[627507.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce66c0]
>[627507.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce66c0] width 1920 pitch 7680 (/4 1920)
>[627507.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590ddb0]
>[627507.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590ddb0] width 1920 pitch 7680 (/4 1920)
>[627508.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c3a40]
>[627508.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c3a40] width 1920 pitch 7680 (/4 1920)
>[627509.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f15e10]
>[627509.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f15e10] width 1920 pitch 7680 (/4 1920)
>[627509.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f144d0]
>[627509.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f144d0] width 1920 pitch 7680 (/4 1920)
>[627509.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2fb80]
>[627509.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2fb80] width 1920 pitch 7680 (/4 1920)
>[627543.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c210]
>[627543.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c210] width 1920 pitch 7680 (/4 1920)
>[627543.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5a4d0]
>[627543.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5a4d0] width 1920 pitch 7680 (/4 1920)
>[627543.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c210]
>[627543.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c210] width 1920 pitch 7680 (/4 1920)
>[627543.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5a4d0]
>[627543.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5a4d0] width 1920 pitch 7680 (/4 1920)
>[627543.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9c210]
>[627543.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9c210] width 1920 pitch 7680 (/4 1920)
>[627543.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b5a4d0]
>[627544.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b5a4d0] width 1920 pitch 7680 (/4 1920)
>[627544.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c25a0]
>[627544.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c25a0] width 1920 pitch 7680 (/4 1920)
>[627545.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a27310]
>[627545.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a27310] width 1920 pitch 7680 (/4 1920)
>[627545.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59ac0]
>[627545.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59ac0] width 1920 pitch 7680 (/4 1920)
>[627545.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853330]
>[627545.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853330] width 1920 pitch 7680 (/4 1920)
>[627545.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59ac0]
>[627545.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59ac0] width 1920 pitch 7680 (/4 1920)
>[627545.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853330]
>[627545.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853330] width 1920 pitch 7680 (/4 1920)
>[627545.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59ac0]
>[627545.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59ac0] width 1920 pitch 7680 (/4 1920)
>[627545.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f2cb50]
>[627545.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f2cb50] width 1920 pitch 7680 (/4 1920)
>[627546.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e743a0]
>[627546.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e743a0] width 1920 pitch 7680 (/4 1920)
>[627547.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d120]
>[627547.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d120] width 1920 pitch 7680 (/4 1920)
>[627547.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e06390]
>[627547.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e06390] width 1920 pitch 7680 (/4 1920)
>[627548.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0d0b0]
>[627548.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0d0b0] width 1920 pitch 7680 (/4 1920)
>[627548.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e44d10]
>[627548.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e44d10] width 1920 pitch 7680 (/4 1920)
>[627552.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb9f0]
>[627552.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb9f0] width 1920 pitch 7680 (/4 1920)
>[627552.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec6fe0]
>[627552.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec6fe0] width 1920 pitch 7680 (/4 1920)
>[627553.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9cfe0]
>[627553.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9cfe0] width 1920 pitch 7680 (/4 1920)
>[627553.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f30b60]
>[627553.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f30b60] width 1920 pitch 7680 (/4 1920)
>[627553.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f74470]
>[627553.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f74470] width 1920 pitch 7680 (/4 1920)
>[627573.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60980]
>[627573.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60980] width 1920 pitch 7680 (/4 1920)
>[627580.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb9f0]
>[627580.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb9f0] width 1920 pitch 7680 (/4 1920)
>[627580.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc4d90]
>[627580.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc4d90] width 1920 pitch 7680 (/4 1920)
>[627580.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b96f70]
>[627580.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b96f70] width 1920 pitch 7680 (/4 1920)
>[627580.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5898ac0]
>[627580.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5898ac0] width 1920 pitch 7680 (/4 1920)
>[627584.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5983b30]
>[627584.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5983b30] width 1920 pitch 7680 (/4 1920)
>[627590.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5898ac0]
>[627590.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5898ac0] width 1920 pitch 7680 (/4 1920)
>[627590.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f0200]
>[627590.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f0200] width 1920 pitch 7680 (/4 1920)
>[627590.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49f0200]
>[627591.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49f0200] width 1920 pitch 7680 (/4 1920)
>[627591.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bacee0]
>[627591.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bacee0] width 1920 pitch 7680 (/4 1920)
>[627736.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041270]
>[627736.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041270] width 1920 pitch 7680 (/4 1920)
>[627737.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dfd90]
>[627737.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dfd90] width 1920 pitch 7680 (/4 1920)
>[627737.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dfd90]
>[627737.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dfd90] width 1920 pitch 7680 (/4 1920)
>[627737.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c7a60]
>[627737.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c7a60] width 1920 pitch 7680 (/4 1920)
>[627738.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a67920]
>[627738.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a67920] width 1920 pitch 7680 (/4 1920)
>[627739.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627739.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627739.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627739.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627739.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681dc70]
>[627739.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681dc70] width 1920 pitch 7680 (/4 1920)
>[627741.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681dc70]
>[627741.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681dc70] width 1920 pitch 7680 (/4 1920)
>[627741.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c23e40]
>[627741.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c23e40] width 1920 pitch 7680 (/4 1920)
>[627741.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c7dd0]
>[627741.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c7dd0] width 1920 pitch 7680 (/4 1920)
>[627742.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868f20]
>[627742.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868f20] width 1920 pitch 7680 (/4 1920)
>[627744.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964780]
>[627744.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964780] width 1920 pitch 7680 (/4 1920)
>[627744.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be6240]
>[627744.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be6240] width 1920 pitch 7680 (/4 1920)
>[627744.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fdd0]
>[627744.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fdd0] width 1920 pitch 7680 (/4 1920)
>[627744.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a840e0]
>[627744.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a840e0] width 1920 pitch 7680 (/4 1920)
>[627744.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x426a760]
>[627744.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x426a760] width 1920 pitch 7680 (/4 1920)
>[627744.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58852f0]
>[627744.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58852f0] width 1920 pitch 7680 (/4 1920)
>[627744.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d4fdd0]
>[627745.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d4fdd0] width 1920 pitch 7680 (/4 1920)
>[627745.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3842580]
>[627745.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3842580] width 1920 pitch 7680 (/4 1920)
>[627745.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0bda0]
>[627745.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0bda0] width 1920 pitch 7680 (/4 1920)
>[627751.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5044c20]
>[627751.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5044c20] width 1920 pitch 7680 (/4 1920)
>[627752.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5973410]
>[627752.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5973410] width 1920 pitch 7680 (/4 1920)
>[627756.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce90b0]
>[627756.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce90b0] width 1920 pitch 7680 (/4 1920)
>[627757.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c3d7d0]
>[627757.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c3d7d0] width 1920 pitch 7680 (/4 1920)
>[627758.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59568b0]
>[627758.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59568b0] width 1920 pitch 7680 (/4 1920)
>[627779.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67437d0]
>[627779.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67437d0] width 1920 pitch 7680 (/4 1920)
>[627787.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494bd80]
>[627787.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494bd80] width 1920 pitch 7680 (/4 1920)
>[627799.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494a820]
>[627799.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494a820] width 1920 pitch 7680 (/4 1920)
>[627799.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994c90]
>[627799.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994c90] width 1920 pitch 7680 (/4 1920)
>[627799.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681dc70]
>[627799.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681dc70] width 1920 pitch 7680 (/4 1920)
>[627799.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994c90]
>[627799.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994c90] width 1920 pitch 7680 (/4 1920)
>[627801.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6a00]
>[627801.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6a00] width 1920 pitch 7680 (/4 1920)
>[627801.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494a9d0]
>[627801.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494a9d0] width 1920 pitch 7680 (/4 1920)
>[627801.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de8b30]
>[627801.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de8b30] width 1920 pitch 7680 (/4 1920)
>[627802.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494a9d0]
>[627802.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494a9d0] width 1920 pitch 7680 (/4 1920)
>[627802.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5061670]
>[627802.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5061670] width 1920 pitch 7680 (/4 1920)
>[627804.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67428d0]
>[627804.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67428d0] width 1920 pitch 7680 (/4 1920)
>[627807.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4986af0]
>[627807.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4986af0] width 1920 pitch 7680 (/4 1920)
>[627807.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d8620]
>[627807.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d8620] width 1920 pitch 7680 (/4 1920)
>[627807.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e2e0]
>[627807.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e2e0] width 1920 pitch 7680 (/4 1920)
>[627809.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b09eb0]
>[627809.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b09eb0] width 1920 pitch 7680 (/4 1920)
>[627809.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de8b30]
>[627809.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de8b30] width 1920 pitch 7680 (/4 1920)
>[627809.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b52a10]
>[627809.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b52a10] width 1920 pitch 7680 (/4 1920)
>[627809.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de8b30]
>[627809.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de8b30] width 1920 pitch 7680 (/4 1920)
>[627809.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265bf60]
>[627810.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265bf60] width 1920 pitch 7680 (/4 1920)
>[627810.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[627810.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1920 pitch 7680 (/4 1920)
>[627810.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265bf60]
>[627810.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265bf60] width 1920 pitch 7680 (/4 1920)
>[627811.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa90]
>[627811.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa90] width 1920 pitch 7680 (/4 1920)
>[627811.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6a70]
>[627811.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6a70] width 1920 pitch 7680 (/4 1920)
>[627811.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830940]
>[627811.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830940] width 1920 pitch 7680 (/4 1920)
>[627811.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6a70]
>[627812.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6a70] width 1920 pitch 7680 (/4 1920)
>[627812.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6830ac0]
>[627812.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6830ac0] width 1920 pitch 7680 (/4 1920)
>[627812.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c1980]
>[627812.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c1980] width 1920 pitch 7680 (/4 1920)
>[627812.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6a70]
>[627812.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6a70] width 1920 pitch 7680 (/4 1920)
>[627812.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c1980]
>[627812.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c1980] width 1920 pitch 7680 (/4 1920)
>[627812.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6a70]
>[627812.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6a70] width 1920 pitch 7680 (/4 1920)
>[627814.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892df0]
>[627814.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892df0] width 1920 pitch 7680 (/4 1920)
>[627815.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a901f0]
>[627816.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a901f0] width 1920 pitch 7680 (/4 1920)
>[627816.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf6a70]
>[627816.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf6a70] width 1920 pitch 7680 (/4 1920)
>[627816.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a901f0]
>[627816.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a901f0] width 1920 pitch 7680 (/4 1920)
>[627821.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x682fe60]
>[627821.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x682fe60] width 1920 pitch 7680 (/4 1920)
>[627821.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fabc20]
>[627821.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fabc20] width 1920 pitch 7680 (/4 1920)
>[627821.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a901f0]
>[627822.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a901f0] width 1920 pitch 7680 (/4 1920)
>[627822.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d8620]
>[627822.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d8620] width 1920 pitch 7680 (/4 1920)
>[627822.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a901f0]
>[627822.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a901f0] width 1920 pitch 7680 (/4 1920)
>[627989.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e30dc0]
>[627989.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e30dc0] width 1920 pitch 7680 (/4 1920)
>[627989.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2490]
>[627989.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2490] width 1920 pitch 7680 (/4 1920)
>[627989.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa30]
>[627989.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa30] width 1920 pitch 7680 (/4 1920)
>[627990.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7ae0]
>[627990.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7ae0] width 1920 pitch 7680 (/4 1920)
>[627990.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627990.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627990.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627990.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627991.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627991.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627991.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627991.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627991.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627991.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627991.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb940]
>[627991.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb940] width 1920 pitch 7680 (/4 1920)
>[627991.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627991.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627991.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bbb940]
>[627991.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bbb940] width 1920 pitch 7680 (/4 1920)
>[627992.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627992.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627992.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627992.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627992.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627992.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627992.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627992.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627992.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627992.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627992.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627992.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627992.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b06dd0]
>[627992.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b06dd0] width 1920 pitch 7680 (/4 1920)
>[627992.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627992.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627993.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[627993.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[627993.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0eb60]
>[627993.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0eb60] width 1920 pitch 7680 (/4 1920)
>[628135.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e2090]
>[628135.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e2090] width 1920 pitch 7680 (/4 1920)
>[628251.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479c0a0]
>[628251.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479c0a0] width 1920 pitch 7680 (/4 1920)
>[628400.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfb030]
>[628400.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfb030] width 1920 pitch 7680 (/4 1920)
>[628540.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d980]
>[628540.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d980] width 1920 pitch 7680 (/4 1920)
>[628582.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38dc020]
>[628582.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38dc020] width 1920 pitch 7680 (/4 1920)
>[628641.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bcefc0]
>[628641.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bcefc0] width 1920 pitch 7680 (/4 1920)
>[628833.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942fb0]
>[628833.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942fb0] width 1920 pitch 7680 (/4 1920)
>[628834.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628834.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628834.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3984710]
>[628834.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3984710] width 1920 pitch 7680 (/4 1920)
>[628835.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628836.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628841.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e1100]
>[628841.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e1100] width 1920 pitch 7680 (/4 1920)
>[628842.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628842.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628842.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bce10]
>[628842.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bce10] width 1920 pitch 7680 (/4 1920)
>[628842.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628842.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628843.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bce10]
>[628843.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bce10] width 1920 pitch 7680 (/4 1920)
>[628844.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628844.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628844.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bce10]
>[628844.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bce10] width 1920 pitch 7680 (/4 1920)
>[628844.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628845.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628845.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5b700]
>[628845.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5b700] width 1920 pitch 7680 (/4 1920)
>[628854.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6994e50]
>[628855.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6994e50] width 1920 pitch 7680 (/4 1920)
>[628855.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c51230]
>[628855.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c51230] width 1920 pitch 7680 (/4 1920)
>[628855.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4b870]
>[628855.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4b870] width 1920 pitch 7680 (/4 1920)
>[628856.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a3ad0]
>[628856.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a3ad0] width 1920 pitch 7680 (/4 1920)
>[628857.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628857.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628857.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bce10]
>[628857.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bce10] width 1920 pitch 7680 (/4 1920)
>[628858.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5106230]
>[628858.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5106230] width 1920 pitch 7680 (/4 1920)
>[628859.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bce10]
>[628859.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bce10] width 1920 pitch 7680 (/4 1920)
>[628859.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978400]
>[628859.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978400] width 1920 pitch 7680 (/4 1920)
>[628859.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcaed0]
>[628859.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcaed0] width 1920 pitch 7680 (/4 1920)
>[628863.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14c40]
>[628863.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14c40] width 1920 pitch 7680 (/4 1920)
>[628863.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a6e0]
>[628863.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a6e0] width 1920 pitch 7680 (/4 1920)
>[628864.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b14c40]
>[628864.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b14c40] width 1920 pitch 7680 (/4 1920)
>[628864.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2a6e0]
>[628864.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2a6e0] width 1920 pitch 7680 (/4 1920)
>[628865.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd6750]
>[628865.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd6750] width 1920 pitch 7680 (/4 1920)
>[628866.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4025400]
>[628866.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4025400] width 1920 pitch 7680 (/4 1920)
>[628868.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3978400]
>[628868.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3978400] width 1920 pitch 7680 (/4 1920)
>[628869.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dcaed0]
>[628869.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dcaed0] width 1920 pitch 7680 (/4 1920)
>[628870.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f62710]
>[628870.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f62710] width 1920 pitch 7680 (/4 1920)
>[628870.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ecbb0]
>[628870.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ecbb0] width 1920 pitch 7680 (/4 1920)
>[628894.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4270f40]
>[628894.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4270f40] width 1920 pitch 7680 (/4 1920)
>[628895.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee17a0]
>[628895.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee17a0] width 1920 pitch 7680 (/4 1920)
>[628914.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4c30]
>[628914.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4c30] width 1920 pitch 7680 (/4 1920)
>[628961.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674a650]
>[628961.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674a650] width 1920 pitch 7680 (/4 1920)
>[628979.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee1750]
>[628980.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee1750] width 1920 pitch 7680 (/4 1920)
>[628980.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfb310]
>[628980.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfb310] width 1920 pitch 7680 (/4 1920)
>[628980.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6738730]
>[628980.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6738730] width 1920 pitch 7680 (/4 1920)
>[628980.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0eb60]
>[628980.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0eb60] width 1920 pitch 7680 (/4 1920)
>[629007.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4c30]
>[629007.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4c30] width 1920 pitch 7680 (/4 1920)
>[629007.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfdd10]
>[629007.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfdd10] width 1920 pitch 7680 (/4 1920)
>[629009.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a5dd0]
>[629009.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a5dd0] width 1920 pitch 7680 (/4 1920)
>[629232.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfe270]
>[629232.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfe270] width 1920 pitch 7680 (/4 1920)
>[629234.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4788aa0]
>[629234.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4788aa0] width 1920 pitch 7680 (/4 1920)
>[629234.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db4c30]
>[629234.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db4c30] width 1920 pitch 7680 (/4 1920)
>[629235.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b90]
>[629235.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b90] width 1920 pitch 7680 (/4 1920)
>[629235.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b90]
>[629235.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b90] width 1920 pitch 7680 (/4 1920)
>[629238.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e640]
>[629238.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e640] width 1920 pitch 7680 (/4 1920)
>[629238.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501cbf0]
>[629238.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501cbf0] width 1920 pitch 7680 (/4 1920)
>[629238.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e540]
>[629238.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e540] width 1920 pitch 7680 (/4 1920)
>[629238.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b01390]
>[629238.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b01390] width 1920 pitch 7680 (/4 1920)
>[629239.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e540]
>[629239.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e540] width 1920 pitch 7680 (/4 1920)
>[629240.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c6e460]
>[629240.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c6e460] width 1920 pitch 7680 (/4 1920)
>[629240.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bda340]
>[629240.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bda340] width 1920 pitch 7680 (/4 1920)
>[629382.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b60]
>[629382.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b60] width 1920 pitch 7680 (/4 1920)
>[629383.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e260]
>[629383.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e260] width 1920 pitch 7680 (/4 1920)
>[629383.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa30]
>[629383.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa30] width 1920 pitch 7680 (/4 1920)
>[629383.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c7e70]
>[629383.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c7e70] width 1920 pitch 7680 (/4 1920)
>[629383.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa30]
>[629383.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa30] width 1920 pitch 7680 (/4 1920)
>[629384.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[629384.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[629384.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa30]
>[629384.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa30] width 1920 pitch 7680 (/4 1920)
>[629384.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2490]
>[629385.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2490] width 1920 pitch 7680 (/4 1920)
>[629385.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c8970]
>[629385.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c8970] width 1920 pitch 7680 (/4 1920)
>[629385.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2490]
>[629385.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2490] width 1920 pitch 7680 (/4 1920)
>[629385.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c8970]
>[629385.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c8970] width 1920 pitch 7680 (/4 1920)
>[629385.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab2490]
>[629385.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab2490] width 1920 pitch 7680 (/4 1920)
>[629385.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c8970]
>[629385.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c8970] width 1920 pitch 7680 (/4 1920)
>[629385.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7ae0]
>[629385.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7ae0] width 1920 pitch 7680 (/4 1920)
>[629385.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7ae0]
>[629385.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7ae0] width 1920 pitch 7680 (/4 1920)
>[629385.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f755a0]
>[629386.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f755a0] width 1920 pitch 7680 (/4 1920)
>[629386.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7ae0]
>[629386.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7ae0] width 1920 pitch 7680 (/4 1920)
>[629386.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c10]
>[629386.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c10] width 1920 pitch 7680 (/4 1920)
>[629387.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872f70]
>[629387.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872f70] width 1920 pitch 7680 (/4 1920)
>[629387.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69baae0]
>[629387.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69baae0] width 1920 pitch 7680 (/4 1920)
>[629387.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eca080]
>[629387.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eca080] width 1920 pitch 7680 (/4 1920)
>[629388.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c8970]
>[629388.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c8970] width 1920 pitch 7680 (/4 1920)
>[629388.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7540]
>[629389.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7540] width 1920 pitch 7680 (/4 1920)
>[629389.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4ac0]
>[629389.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4ac0] width 1920 pitch 7680 (/4 1920)
>[629389.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[629389.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[629389.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0aa30]
>[629390.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0aa30] width 1920 pitch 7680 (/4 1920)
>[629391.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd2d0]
>[629391.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd2d0] width 1920 pitch 7680 (/4 1920)
>[629391.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686c070]
>[629391.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686c070] width 1920 pitch 7680 (/4 1920)
>[629392.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6884140]
>[629392.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6884140] width 1920 pitch 7680 (/4 1920)
>[629392.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[629392.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[629392.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ed0]
>[629392.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ed0] width 1920 pitch 7680 (/4 1920)
>[629392.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[629392.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[629392.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ed0]
>[629392.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ed0] width 1920 pitch 7680 (/4 1920)
>[629392.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[629392.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[629393.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ed0]
>[629393.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ed0] width 1920 pitch 7680 (/4 1920)
>[629393.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2810e40]
>[629393.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2810e40] width 1920 pitch 7680 (/4 1920)
>[629393.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ed0]
>[629394.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ed0] width 1920 pitch 7680 (/4 1920)
>[629394.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5740]
>[629394.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5740] width 1920 pitch 7680 (/4 1920)
>[629394.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[629394.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[629394.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5040ed0]
>[629394.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5040ed0] width 1920 pitch 7680 (/4 1920)
>[629394.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cd5c0]
>[629394.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cd5c0] width 1920 pitch 7680 (/4 1920)
>[629394.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3819c10]
>[629394.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3819c10] width 1920 pitch 7680 (/4 1920)
>[629395.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281ccc0]
>[629395.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281ccc0] width 1920 pitch 7680 (/4 1920)
>[629395.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c8970]
>[629395.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c8970] width 1920 pitch 7680 (/4 1920)
>[629395.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe3190]
>[629395.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe3190] width 1920 pitch 7680 (/4 1920)
>[629396.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f60fb0]
>[629396.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f60fb0] width 1920 pitch 7680 (/4 1920)
>[629397.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a26950]
>[629397.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a26950] width 1920 pitch 7680 (/4 1920)
>[629397.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014b60]
>[629397.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014b60] width 1920 pitch 7680 (/4 1920)
>[629398.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef88c0]
>[629398.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef88c0] width 1920 pitch 7680 (/4 1920)
>[629398.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e260]
>[629398.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e260] width 1920 pitch 7680 (/4 1920)
>[629474.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687f420]
>[629474.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687f420] width 1920 pitch 7680 (/4 1920)
>[629570.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[629570.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1920 pitch 7680 (/4 1920)
>[629582.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad620]
>[629582.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad620] width 1920 pitch 7680 (/4 1920)
>[629598.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d07990]
>[629598.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d07990] width 1920 pitch 7680 (/4 1920)
>[629777.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f89690]
>[629777.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f89690] width 1920 pitch 7680 (/4 1920)
>[629777.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef88c0]
>[629777.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef88c0] width 1920 pitch 7680 (/4 1920)
>[629891.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dbda0]
>[629891.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dbda0] width 1920 pitch 7680 (/4 1920)
>[630079.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab9840]
>[630079.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab9840] width 1920 pitch 7680 (/4 1920)
>[630115.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1650]
>[630115.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1650] width 1920 pitch 7680 (/4 1920)
>[630229.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d84a0]
>[630229.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d84a0] width 1920 pitch 7680 (/4 1920)
>[630458.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674acb0]
>[630458.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674acb0] width 1920 pitch 7680 (/4 1920)
>[630568.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd1800]
>[630568.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd1800] width 1920 pitch 7680 (/4 1920)
>[630695.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868f30]
>[630695.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868f30] width 1920 pitch 7680 (/4 1920)
>[630735.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11910]
>[630735.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11910] width 1920 pitch 7680 (/4 1920)
>[631068.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3d790]
>[631068.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3d790] width 1920 pitch 7680 (/4 1920)
>[631547.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a05ef0]
>[631547.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a05ef0] width 1920 pitch 7680 (/4 1920)
>[631660.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59da540]
>[631660.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59da540] width 1920 pitch 7680 (/4 1920)
>[631713.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c5530]
>[631713.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c5530] width 1920 pitch 7680 (/4 1920)
>[631713.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f3d260]
>[631713.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f3d260] width 1920 pitch 7680 (/4 1920)
>[631739.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a9fa0]
>[631739.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a9fa0] width 1920 pitch 7680 (/4 1920)
>[631739.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c01c0]
>[631740.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c01c0] width 1920 pitch 7680 (/4 1920)
>[631749.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59da520]
>[631749.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59da520] width 1920 pitch 7680 (/4 1920)
>[631857.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e46130]
>[631858.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e46130] width 1920 pitch 7680 (/4 1920)
>[631901.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcb2b0]
>[631901.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcb2b0] width 1920 pitch 7680 (/4 1920)
>[632030.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38befe0]
>[632030.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38befe0] width 1920 pitch 7680 (/4 1920)
>[632336.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940360]
>[632336.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940360] width 1920 pitch 7680 (/4 1920)
>[632343.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad5610]
>[632343.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad5610] width 1920 pitch 7680 (/4 1920)
>[632355.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e46240]
>[632355.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e46240] width 1920 pitch 7680 (/4 1920)
>[632416.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59403c0]
>[632416.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59403c0] width 1920 pitch 7680 (/4 1920)
>[632525.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d6830]
>[632526.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d6830] width 1920 pitch 7680 (/4 1920)
>[632541.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cfbe0]
>[632541.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cfbe0] width 1920 pitch 7680 (/4 1920)
>[632556.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674aca0]
>[632556.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674aca0] width 1920 pitch 7680 (/4 1920)
>[632590.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940360]
>[632590.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940360] width 1920 pitch 7680 (/4 1920)
>[632618.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[632618.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1920 pitch 7680 (/4 1920)
>[632898.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e20f70]
>[632899.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e20f70] width 1920 pitch 7680 (/4 1920)
>[632908.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37c90]
>[632908.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37c90] width 1920 pitch 7680 (/4 1920)
>[632908.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db7f40]
>[632908.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db7f40] width 1920 pitch 7680 (/4 1920)
>[632957.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a580]
>[632957.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a580] width 1920 pitch 7680 (/4 1920)
>[632957.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad800]
>[632957.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad800] width 1920 pitch 7680 (/4 1920)
>[632957.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a580]
>[632957.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a580] width 1920 pitch 7680 (/4 1920)
>[632957.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad800]
>[632957.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad800] width 1920 pitch 7680 (/4 1920)
>[632957.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a580]
>[632957.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a580] width 1920 pitch 7680 (/4 1920)
>[632957.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ad800]
>[632957.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ad800] width 1920 pitch 7680 (/4 1920)
>[632961.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cfaa0]
>[632961.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cfaa0] width 1920 pitch 7680 (/4 1920)
>[632963.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f222e0]
>[632963.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f222e0] width 1920 pitch 7680 (/4 1920)
>[632963.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940360]
>[632963.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940360] width 1920 pitch 7680 (/4 1920)
>[632963.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f222e0]
>[632963.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f222e0] width 1920 pitch 7680 (/4 1920)
>[632963.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940360]
>[632963.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940360] width 1920 pitch 7680 (/4 1920)
>[632963.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f222e0]
>[632963.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f222e0] width 1920 pitch 7680 (/4 1920)
>[632963.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940360]
>[632963.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940360] width 1920 pitch 7680 (/4 1920)
>[632964.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5940410]
>[632964.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5940410] width 1920 pitch 7680 (/4 1920)
>[632966.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386c1c0]
>[632966.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386c1c0] width 1920 pitch 7680 (/4 1920)
>[632966.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cfa40]
>[632966.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cfa40] width 1920 pitch 7680 (/4 1920)
>[632966.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x386c1c0]
>[632966.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x386c1c0] width 1920 pitch 7680 (/4 1920)
>[632972.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f22320]
>[632972.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f22320] width 1920 pitch 7680 (/4 1920)
>[632972.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad54c0]
>[632972.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad54c0] width 1920 pitch 7680 (/4 1920)
>[632972.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad54c0]
>[632973.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad54c0] width 1920 pitch 7680 (/4 1920)
>[632973.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6883660]
>[632973.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6883660] width 1920 pitch 7680 (/4 1920)
>[632973.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16e80]
>[632973.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16e80] width 1920 pitch 7680 (/4 1920)
>[632974.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8080]
>[632974.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8080] width 1920 pitch 7680 (/4 1920)
>[632975.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da4680]
>[632975.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da4680] width 1920 pitch 7680 (/4 1920)
>[632975.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db8080]
>[632975.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db8080] width 1920 pitch 7680 (/4 1920)
>[632975.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da4680]
>[632975.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da4680] width 1920 pitch 7680 (/4 1920)
>[632975.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da4680]
>[632976.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da4680] width 1920 pitch 7680 (/4 1920)
>[632976.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f55bb0]
>[632976.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f55bb0] width 1920 pitch 7680 (/4 1920)
>[632978.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd6f0]
>[632979.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd6f0] width 1920 pitch 7680 (/4 1920)
>[632979.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c99720]
>[632979.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c99720] width 1920 pitch 7680 (/4 1920)
>[632979.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f295b0]
>[632979.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f295b0] width 1920 pitch 7680 (/4 1920)
>[632980.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f66010]
>[632980.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f66010] width 1920 pitch 7680 (/4 1920)
>[632980.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5955430]
>[632980.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5955430] width 1920 pitch 7680 (/4 1920)
>[632980.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632980.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632980.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632980.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632980.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632980.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632980.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632980.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632980.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632980.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632981.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632981.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632981.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632982.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632982.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632982.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632982.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632982.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632982.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632982.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632982.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632982.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632983.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632983.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632983.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632983.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632983.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632984.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632984.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853780]
>[632984.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853780] width 1920 pitch 7680 (/4 1920)
>[632984.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632984.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632984.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853780]
>[632985.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853780] width 1920 pitch 7680 (/4 1920)
>[632985.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632985.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632985.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853780]
>[632985.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853780] width 1920 pitch 7680 (/4 1920)
>[632985.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632985.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632985.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632985.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632986.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96b40]
>[632986.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96b40] width 1920 pitch 7680 (/4 1920)
>[632986.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5853890]
>[632986.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5853890] width 1920 pitch 7680 (/4 1920)
>[632990.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aded0]
>[632990.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aded0] width 1920 pitch 7680 (/4 1920)
>[632990.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f34a40]
>[632990.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f34a40] width 1920 pitch 7680 (/4 1920)
>[632990.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf5510]
>[632990.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf5510] width 1920 pitch 7680 (/4 1920)
>[632990.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a0bfa0]
>[632990.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a0bfa0] width 1920 pitch 7680 (/4 1920)
>[632990.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf5510]
>[632990.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf5510] width 1920 pitch 7680 (/4 1920)
>[632990.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ea650]
>[632990.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ea650] width 1920 pitch 7680 (/4 1920)
>[633001.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486d6f0]
>[633001.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486d6f0] width 1920 pitch 7680 (/4 1920)
>[633001.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67462f0]
>[633001.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67462f0] width 1920 pitch 7680 (/4 1920)
>[633009.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c7f20]
>[633009.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c7f20] width 1920 pitch 7680 (/4 1920)
>[633010.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c7e80]
>[633010.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c7e80] width 1920 pitch 7680 (/4 1920)
>[633010.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c7f20]
>[633010.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c7f20] width 1920 pitch 7680 (/4 1920)
>[633014.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cff0d0]
>[633014.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cff0d0] width 1920 pitch 7680 (/4 1920)
>[633014.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c4c7b0]
>[633014.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c4c7b0] width 1920 pitch 7680 (/4 1920)
>[633014.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf54d0]
>[633014.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf54d0] width 1920 pitch 7680 (/4 1920)
>[633014.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ae070]
>[633014.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ae070] width 1920 pitch 7680 (/4 1920)
>[633014.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf42a0]
>[633014.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf42a0] width 1920 pitch 7680 (/4 1920)
>[633016.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x485f8b0]
>[633016.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x485f8b0] width 1920 pitch 7680 (/4 1920)
>[633016.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5955430]
>[633016.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5955430] width 1920 pitch 7680 (/4 1920)
>[633016.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c9350]
>[633016.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c9350] width 1920 pitch 7680 (/4 1920)
>[633016.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4ed80]
>[633016.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4ed80] width 1920 pitch 7680 (/4 1920)
>[633016.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5885f30]
>[633016.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5885f30] width 1920 pitch 7680 (/4 1920)
>[633017.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x485f9c0]
>[633017.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x485f9c0] width 1920 pitch 7680 (/4 1920)
>[633017.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497d3e0]
>[633017.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497d3e0] width 1920 pitch 7680 (/4 1920)
>[633017.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5955430]
>[633017.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5955430] width 1920 pitch 7680 (/4 1920)
>[633018.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cfa40]
>[633018.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cfa40] width 1920 pitch 7680 (/4 1920)
>[633018.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da4680]
>[633018.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da4680] width 1920 pitch 7680 (/4 1920)
>[633018.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cfa40]
>[633018.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cfa40] width 1920 pitch 7680 (/4 1920)
>[633039.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f7a0]
>[633039.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f7a0] width 1920 pitch 7680 (/4 1920)
>[633074.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[633074.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1920 pitch 7680 (/4 1920)
>[633074.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da1c70]
>[633074.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da1c70] width 1920 pitch 7680 (/4 1920)
>[633075.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a16950]
>[633075.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a16950] width 1920 pitch 7680 (/4 1920)
>[633075.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[633075.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1920 pitch 7680 (/4 1920)
>[633075.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[633075.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1920 pitch 7680 (/4 1920)
>[633077.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820e50]
>[633077.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820e50] width 1920 pitch 7680 (/4 1920)
>[633077.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4995420]
>[633078.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4995420] width 1920 pitch 7680 (/4 1920)
>[633080.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861190]
>[633080.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861190] width 1920 pitch 7680 (/4 1920)
>[633384.926] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[633384.926] (II) RADEON(0): Using hsync ranges from config file
>[633384.926] (II) RADEON(0): Using vrefresh ranges from config file
>[633384.926] (II) RADEON(0): Printing DDC gathered Modelines:
>[633384.926] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[633384.927] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[633384.927] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[633384.927] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[633384.927] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[633384.927] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[633384.927] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[633384.927] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[633384.927] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[633384.927] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[633384.927] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[633474.744] (II) RADEON(0): RADEONSaveScreen(2)
>[633474.744] (II) RADEON(0): RADEONSaveScreen(0)
>[704671.797] (II) RADEON(0): RADEONSaveScreen(1)
>[704689.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820e50]
>[704689.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820e50] width 1920 pitch 7680 (/4 1920)
>[704689.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820e50]
>[704689.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820e50] width 1920 pitch 7680 (/4 1920)
>[704689.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704689.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704691.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820e50]
>[704691.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820e50] width 1920 pitch 7680 (/4 1920)
>[704691.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704691.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704692.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704692.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704692.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4874e30]
>[704692.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4874e30] width 1920 pitch 7680 (/4 1920)
>[704693.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704693.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704693.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4874e30]
>[704693.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4874e30] width 1920 pitch 7680 (/4 1920)
>[704693.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704693.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704693.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4874e30]
>[704693.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4874e30] width 1920 pitch 7680 (/4 1920)
>[704694.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[704694.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[704695.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0b7b0]
>[704695.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0b7b0] width 1920 pitch 7680 (/4 1920)
>[704695.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733be0]
>[704695.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733be0] width 1920 pitch 7680 (/4 1920)
>[705027.961] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[705027.961] (II) RADEON(0): Using hsync ranges from config file
>[705027.961] (II) RADEON(0): Using vrefresh ranges from config file
>[705027.961] (II) RADEON(0): Printing DDC gathered Modelines:
>[705027.961] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[705027.961] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[705027.961] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[705027.961] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[705027.961] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[705027.961] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[705027.961] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[705027.961] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[705027.961] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[705027.961] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[705027.961] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[705117.755] (II) RADEON(0): RADEONSaveScreen(2)
>[705117.755] (II) RADEON(0): RADEONSaveScreen(0)
>[707213.840] (II) RADEON(0): RADEONSaveScreen(1)
>[707603.743] (II) RADEON(0): RADEONSaveScreen(2)
>[707603.743] (II) RADEON(0): RADEONSaveScreen(0)
>[715830.705] (II) RADEON(0): RADEONSaveScreen(1)
>[716244.747] (II) RADEON(0): RADEONSaveScreen(2)
>[716244.747] (II) RADEON(0): RADEONSaveScreen(0)
>[718681.506] (II) RADEON(0): RADEONSaveScreen(1)
>[718700.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d1f0]
>[718700.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d1f0] width 1920 pitch 7680 (/4 1920)
>[718706.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d1f0]
>[718706.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d1f0] width 1920 pitch 7680 (/4 1920)
>[718716.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02e0]
>[718716.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02e0] width 1920 pitch 7680 (/4 1920)
>[718716.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718716.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718716.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718716.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718716.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718716.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718716.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718716.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718717.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718717.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718717.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718717.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718717.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718717.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718717.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718717.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718717.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718717.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718717.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718717.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718717.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718717.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718718.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718718.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718718.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718718.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718718.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718718.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718718.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718718.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718718.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5861e20]
>[718718.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5861e20] width 1920 pitch 7680 (/4 1920)
>[718718.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860710]
>[718719.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860710] width 1920 pitch 7680 (/4 1920)
>[718719.781] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[718719.781] (II) RADEON(0): Using hsync ranges from config file
>[718719.781] (II) RADEON(0): Using vrefresh ranges from config file
>[718719.781] (II) RADEON(0): Printing DDC gathered Modelines:
>[718719.781] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[718719.781] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[718719.781] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[718719.782] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[718719.782] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[718719.782] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[718719.782] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[718719.782] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[718719.782] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[718719.782] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[718719.782] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[718735.395] (II) config/udev: removing device USB USB Keykoard
>[718735.396] (II) evdev: USB USB Keykoard: Close
>[718735.461] (II) UnloadModule: "evdev"
>[718735.461] (II) config/udev: removing device USB USB Keykoard
>[718735.462] (II) evdev: USB USB Keykoard: Close
>[718735.552] (II) UnloadModule: "evdev"
>[718735.552] (II) config/udev: removing device Logitech USB Optical Mouse
>[718735.552] (II) evdev: Logitech USB Optical Mouse: Close
>[718735.552] (II) UnloadModule: "evdev"
>[718738.041] (II) AIGLX: Suspending AIGLX clients for VT switch
>[718738.041] (II) RADEON(0): RADEONLeaveVT_KMS
>[718738.041] (II) RADEON(0): Ok, leaving now...
>[718743.872] (II) AIGLX: Resuming AIGLX clients after VT switch
>[718743.872] (II) RADEON(0): RADEONEnterVT_KMS
>[718744.326] (II) RADEON(0): RADEONSaveScreen(2)
>[718745.205] (**) Option "Device" "/dev/input/event5"
>[718745.215] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[718747.747] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[718747.749] (II) RADEON(0): VRAM usage limit set to 223324K
>[718750.840] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[718750.840] (II) RADEON(0): VRAM usage limit set to 223324K
>[718762.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718762.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718764.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718764.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718767.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718767.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718767.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718767.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718768.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718768.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718768.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39147f0]
>[718769.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39147f0] width 1600 pitch 6400 (/4 1600)
>[718769.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718769.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718769.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718769.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718769.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718769.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718769.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718769.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718769.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718769.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718769.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718769.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718769.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718769.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718769.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718769.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718769.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718769.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718769.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718769.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718770.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718770.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718770.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718770.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718770.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718770.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718770.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718770.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718770.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718770.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718770.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718770.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718770.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718770.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718771.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718771.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718771.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718771.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718771.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718773.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718773.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718773.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718773.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718773.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718773.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718773.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718773.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718773.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718773.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718773.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718773.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718773.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718773.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718774.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718774.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718774.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718774.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718774.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718774.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718774.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718774.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718774.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718774.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718774.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718774.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718774.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718774.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718774.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718774.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718774.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718774.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718774.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718774.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718774.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718775.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718775.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718775.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718775.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718775.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718775.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718775.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718775.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718775.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718775.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718775.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718775.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718775.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718775.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718775.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718775.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718775.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718775.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718775.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718775.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718775.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718775.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718775.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718775.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718775.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718775.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718775.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718775.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718775.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718775.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718775.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718775.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718775.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718775.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718775.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718775.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718775.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718775.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718775.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718775.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718775.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718775.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718776.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718776.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718776.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718776.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718776.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718776.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718776.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718776.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718776.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718776.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718776.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718776.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718776.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718776.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718776.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718780.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718780.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718780.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718780.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718780.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718780.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718780.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718780.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718780.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718780.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718780.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718780.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718780.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718780.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718780.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718780.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718780.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718780.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718780.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718780.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718780.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718780.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718781.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718782.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718782.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718782.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718782.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718782.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718782.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718782.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718782.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718782.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718782.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718782.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718782.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718782.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718782.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718782.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718782.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718782.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718782.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718782.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718782.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718782.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718782.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718782.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718782.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718782.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718782.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718782.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718783.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718783.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718783.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718783.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718783.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718783.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718783.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718783.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718783.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718783.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718784.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718784.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718791.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718791.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718791.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718791.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718791.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872bd0]
>[718791.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872bd0] width 1600 pitch 6400 (/4 1600)
>[718791.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718791.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718791.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718791.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718791.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718791.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718791.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718791.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718791.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a23bc0]
>[718791.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a23bc0] width 1600 pitch 6400 (/4 1600)
>[718791.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad58c0]
>[718791.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad58c0] width 1600 pitch 6400 (/4 1600)
>[718792.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a23bc0]
>[718792.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a23bc0] width 1600 pitch 6400 (/4 1600)
>[718793.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718793.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718793.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718793.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718795.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718795.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718802.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718802.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718807.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718807.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718807.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718807.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718807.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718807.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718807.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718807.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718807.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718807.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718807.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718807.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718811.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718811.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718811.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718811.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718811.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718811.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718811.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718811.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718811.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718811.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718811.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718811.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718811.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718811.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718811.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718811.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718811.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718811.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718811.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718812.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718812.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718812.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718812.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718812.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718812.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718812.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718812.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718812.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718812.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718812.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718812.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718812.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718812.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718812.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718812.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718812.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718812.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718812.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718812.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718812.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718812.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718812.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718812.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718812.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718812.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718812.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718812.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718812.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718812.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718812.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718812.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718812.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718812.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718812.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718812.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718812.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718812.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718812.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718812.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718812.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718812.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718812.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718812.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718812.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718812.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718812.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718812.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718812.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718812.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718812.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718812.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718812.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718812.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718812.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718812.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718812.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718812.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718813.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718813.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718813.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718813.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718813.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718813.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718813.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718813.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718813.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718813.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718813.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718813.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718813.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718813.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718813.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718813.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718813.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718813.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718813.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718813.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718813.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718813.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718813.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718813.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718813.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718813.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718813.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718813.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718813.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718813.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718813.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718813.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718813.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718813.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718813.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718813.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718813.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718813.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718813.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718813.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718813.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718813.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718814.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718814.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718814.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718814.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718814.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718814.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718814.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718814.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718814.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718814.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718814.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718814.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718814.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718814.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718814.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718814.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718814.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718814.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718814.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718814.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718814.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718814.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718814.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718814.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718814.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718814.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718814.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718814.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718814.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718814.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718814.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718814.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718814.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718814.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718814.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718814.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718814.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718814.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718814.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718814.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea4b50]
>[718814.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea4b50] width 1600 pitch 6400 (/4 1600)
>[718814.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2879d40]
>[718814.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2879d40] width 1600 pitch 6400 (/4 1600)
>[718814.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[718814.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[718814.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96480]
>[718814.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96480] width 1600 pitch 6400 (/4 1600)
>[718814.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a98d0]
>[718814.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a98d0] width 1600 pitch 6400 (/4 1600)
>[718814.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736a00]
>[718814.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736a00] width 1600 pitch 6400 (/4 1600)
>[718814.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f04ba0]
>[718815.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f04ba0] width 1600 pitch 6400 (/4 1600)
>[718815.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868c20]
>[718815.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868c20] width 1600 pitch 6400 (/4 1600)
>[718815.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50249b0]
>[718815.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50249b0] width 1600 pitch 6400 (/4 1600)
>[718824.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30158c0]
>[718825.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30158c0] width 1600 pitch 6400 (/4 1600)
>[718825.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x485eb60]
>[718825.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x485eb60] width 1600 pitch 6400 (/4 1600)
>[718826.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f30fe0]
>[718826.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f30fe0] width 1600 pitch 6400 (/4 1600)
>[718826.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6973250]
>[718826.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6973250] width 1600 pitch 6400 (/4 1600)
>[718827.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f66010]
>[718827.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f66010] width 1600 pitch 6400 (/4 1600)
>[718827.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4e490]
>[718827.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4e490] width 1600 pitch 6400 (/4 1600)
>[718827.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b90]
>[718827.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b90] width 1600 pitch 6400 (/4 1600)
>[718827.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[718827.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[718827.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22cc0]
>[718827.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22cc0] width 1600 pitch 6400 (/4 1600)
>[718827.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad5480]
>[718827.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad5480] width 1600 pitch 6400 (/4 1600)
>[718827.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3982c90]
>[718827.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3982c90] width 1600 pitch 6400 (/4 1600)
>[718827.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37bf0]
>[718827.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37bf0] width 1600 pitch 6400 (/4 1600)
>[718827.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b90]
>[718827.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b90] width 1600 pitch 6400 (/4 1600)
>[718827.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37bf0]
>[718827.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37bf0] width 1600 pitch 6400 (/4 1600)
>[718827.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad5480]
>[718827.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad5480] width 1600 pitch 6400 (/4 1600)
>[718827.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[718827.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[718827.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38bee70]
>[718827.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38bee70] width 1600 pitch 6400 (/4 1600)
>[718827.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37bf0]
>[718827.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37bf0] width 1600 pitch 6400 (/4 1600)
>[718827.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681f270]
>[718827.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681f270] width 1600 pitch 6400 (/4 1600)
>[718827.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bb7b90]
>[718827.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bb7b90] width 1600 pitch 6400 (/4 1600)
>[718827.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9ef0]
>[718827.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9ef0] width 1600 pitch 6400 (/4 1600)
>[718827.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d490]
>[718827.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d490] width 1600 pitch 6400 (/4 1600)
>[718827.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22cc0]
>[718828.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22cc0] width 1600 pitch 6400 (/4 1600)
>[718828.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d490]
>[718828.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d490] width 1600 pitch 6400 (/4 1600)
>[718828.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d490]
>[718828.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d490] width 1600 pitch 6400 (/4 1600)
>[718828.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22cc0]
>[718828.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22cc0] width 1600 pitch 6400 (/4 1600)
>[718828.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9ef0]
>[718828.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9ef0] width 1600 pitch 6400 (/4 1600)
>[718828.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1d490]
>[718828.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1d490] width 1600 pitch 6400 (/4 1600)
>[718856.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6d80]
>[718856.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6d80] width 1600 pitch 6400 (/4 1600)
>[718880.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf4d70]
>[718880.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf4d70] width 1600 pitch 6400 (/4 1600)
>[718880.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf4d70]
>[718880.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf4d70] width 1600 pitch 6400 (/4 1600)
>[718881.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992d10]
>[718881.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992d10] width 1600 pitch 6400 (/4 1600)
>[718881.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0270]
>[718881.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0270] width 1600 pitch 6400 (/4 1600)
>[718881.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02f0]
>[718881.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02f0] width 1600 pitch 6400 (/4 1600)
>[718882.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ac9ef0]
>[718882.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ac9ef0] width 1600 pitch 6400 (/4 1600)
>[718909.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02f0]
>[718910.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02f0] width 1600 pitch 6400 (/4 1600)
>[718910.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992d10]
>[718910.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992d10] width 1600 pitch 6400 (/4 1600)
>[718911.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02f0]
>[718911.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02f0] width 1600 pitch 6400 (/4 1600)
>[718911.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992d10]
>[718911.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992d10] width 1600 pitch 6400 (/4 1600)
>[718911.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02f0]
>[718911.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02f0] width 1600 pitch 6400 (/4 1600)
>[718911.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6aa0]
>[718911.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6aa0] width 1600 pitch 6400 (/4 1600)
>[718912.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992d10]
>[718912.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992d10] width 1600 pitch 6400 (/4 1600)
>[718912.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e02f0]
>[718912.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e02f0] width 1600 pitch 6400 (/4 1600)
>[718912.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992d10]
>[718912.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992d10] width 1600 pitch 6400 (/4 1600)
>[718958.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5003af0]
>[718958.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5003af0] width 1600 pitch 6400 (/4 1600)
>[719837.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbdbf0]
>[719837.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbdbf0] width 1600 pitch 6400 (/4 1600)
>[719839.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac2e70]
>[719839.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac2e70] width 1600 pitch 6400 (/4 1600)
>[719839.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[719839.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[720295.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50cea90]
>[720295.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50cea90] width 1600 pitch 6400 (/4 1600)
>[720295.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bda160]
>[720295.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bda160] width 1600 pitch 6400 (/4 1600)
>[720296.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ae80]
>[720296.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ae80] width 1600 pitch 6400 (/4 1600)
>[720296.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x425e050]
>[720296.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x425e050] width 1600 pitch 6400 (/4 1600)
>[720296.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcc920]
>[720296.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcc920] width 1600 pitch 6400 (/4 1600)
>[720296.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4040]
>[720296.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4040] width 1600 pitch 6400 (/4 1600)
>[720296.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f23760]
>[720296.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f23760] width 1600 pitch 6400 (/4 1600)
>[720352.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[720352.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[720352.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cff270]
>[720352.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cff270] width 1600 pitch 6400 (/4 1600)
>[720353.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[720353.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[720357.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a0cfb0]
>[720358.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a0cfb0] width 1600 pitch 6400 (/4 1600)
>[720358.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92c50]
>[720358.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92c50] width 1600 pitch 6400 (/4 1600)
>[720358.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[720358.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1600 pitch 6400 (/4 1600)
>[720358.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c3010]
>[720359.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c3010] width 1600 pitch 6400 (/4 1600)
>[720359.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12280]
>[720359.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12280] width 1600 pitch 6400 (/4 1600)
>[720359.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebeaa0]
>[720359.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebeaa0] width 1600 pitch 6400 (/4 1600)
>[720359.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c9740]
>[720359.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c9740] width 1600 pitch 6400 (/4 1600)
>[720360.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75c60]
>[720360.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75c60] width 1600 pitch 6400 (/4 1600)
>[720360.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405b2c0]
>[720360.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405b2c0] width 1600 pitch 6400 (/4 1600)
>[720361.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe0570]
>[720361.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe0570] width 1600 pitch 6400 (/4 1600)
>[720361.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f39590]
>[720361.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f39590] width 1600 pitch 6400 (/4 1600)
>[720361.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2839400]
>[720361.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2839400] width 1600 pitch 6400 (/4 1600)
>[720363.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce4de0]
>[720363.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce4de0] width 1600 pitch 6400 (/4 1600)
>[720363.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3940]
>[720363.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3940] width 1600 pitch 6400 (/4 1600)
>[720456.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x264cf30]
>[720456.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x264cf30] width 1600 pitch 6400 (/4 1600)
>[720457.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27f56d0]
>[720457.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27f56d0] width 1600 pitch 6400 (/4 1600)
>[720457.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5022970]
>[720457.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5022970] width 1600 pitch 6400 (/4 1600)
>[720457.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50677d0]
>[720457.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50677d0] width 1600 pitch 6400 (/4 1600)
>[720458.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fba2a0]
>[720458.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fba2a0] width 1600 pitch 6400 (/4 1600)
>[720458.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa910]
>[720458.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa910] width 1600 pitch 6400 (/4 1600)
>[720458.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5a2d0]
>[720458.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5a2d0] width 1600 pitch 6400 (/4 1600)
>[720466.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baca10]
>[720466.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baca10] width 1600 pitch 6400 (/4 1600)
>[720467.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4273720]
>[720467.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4273720] width 1600 pitch 6400 (/4 1600)
>[720476.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5ce0]
>[720476.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5ce0] width 1600 pitch 6400 (/4 1600)
>[720476.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83c40]
>[720476.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83c40] width 1600 pitch 6400 (/4 1600)
>[720477.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[720477.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[720477.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ac950]
>[720477.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ac950] width 1600 pitch 6400 (/4 1600)
>[720477.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eccd50]
>[720477.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eccd50] width 1600 pitch 6400 (/4 1600)
>[720477.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1ae80]
>[720477.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1ae80] width 1600 pitch 6400 (/4 1600)
>[720624.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[720624.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[720625.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[720625.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[720625.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68badd0]
>[720625.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68badd0] width 1600 pitch 6400 (/4 1600)
>[720626.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[720626.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[720626.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba7610]
>[720626.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba7610] width 1600 pitch 6400 (/4 1600)
>[720626.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc0bc0]
>[720626.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc0bc0] width 1600 pitch 6400 (/4 1600)
>[720890.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[720890.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[720890.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[720890.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[720890.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[720890.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[720890.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[720890.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[720890.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[720890.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[720890.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[720891.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[720891.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdbd00]
>[720891.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdbd00] width 1600 pitch 6400 (/4 1600)
>[720891.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[720891.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[720895.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[720895.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[720895.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[720895.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[720895.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[720895.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[720895.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[720895.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[720895.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[720895.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[720895.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[720895.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[720895.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[720895.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[720895.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e01a00]
>[720895.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e01a00] width 1600 pitch 6400 (/4 1600)
>[720928.645] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[720928.645] (II) RADEON(0): Printing DDC gathered Modelines:
>[720928.645] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[720928.645] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[721019.798] (II) RADEON(0): RADEONSaveScreen(2)
>[721019.804] (II) RADEON(0): RADEONSaveScreen(0)
>[721277.555] (II) RADEON(0): RADEONSaveScreen(1)
>[721284.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e101b0]
>[721284.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e101b0] width 1600 pitch 6400 (/4 1600)
>[721289.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a38b0]
>[721289.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a38b0] width 1600 pitch 6400 (/4 1600)
>[721289.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab4630]
>[721289.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab4630] width 1600 pitch 6400 (/4 1600)
>[721289.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[721290.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[721291.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2827c20]
>[721291.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2827c20] width 1600 pitch 6400 (/4 1600)
>[721291.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5093d10]
>[721291.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5093d10] width 1600 pitch 6400 (/4 1600)
>[721322.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab8230]
>[721322.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab8230] width 1600 pitch 6400 (/4 1600)
>[721322.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x405b2c0]
>[721323.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x405b2c0] width 1600 pitch 6400 (/4 1600)
>[721323.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75c60]
>[721323.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75c60] width 1600 pitch 6400 (/4 1600)
>[721323.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc0bc0]
>[721324.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc0bc0] width 1600 pitch 6400 (/4 1600)
>[721324.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e538d0]
>[721324.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e538d0] width 1600 pitch 6400 (/4 1600)
>[721324.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5a2d0]
>[721324.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5a2d0] width 1600 pitch 6400 (/4 1600)
>[721324.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa910]
>[721325.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa910] width 1600 pitch 6400 (/4 1600)
>[721397.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698a1d0]
>[721397.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698a1d0] width 1600 pitch 6400 (/4 1600)
>[721397.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[721398.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[721398.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593d320]
>[721398.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593d320] width 1600 pitch 6400 (/4 1600)
>[721398.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c10c80]
>[721398.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c10c80] width 1600 pitch 6400 (/4 1600)
>[721399.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586c1a0]
>[721399.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586c1a0] width 1600 pitch 6400 (/4 1600)
>[721399.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[721399.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1600 pitch 6400 (/4 1600)
>[721399.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a2560]
>[721399.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a2560] width 1600 pitch 6400 (/4 1600)
>[721399.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c9740]
>[721400.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c9740] width 1600 pitch 6400 (/4 1600)
>[721400.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de2de0]
>[721400.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de2de0] width 1600 pitch 6400 (/4 1600)
>[721400.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721400.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721400.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721400.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721400.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721400.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721400.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721400.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721400.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721400.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721400.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721400.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721401.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721401.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721401.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721401.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fb4a0]
>[721401.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fb4a0] width 1600 pitch 6400 (/4 1600)
>[721401.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dbf020]
>[721401.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dbf020] width 1600 pitch 6400 (/4 1600)
>[721401.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[721401.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[721401.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0ee0]
>[721401.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0ee0] width 1600 pitch 6400 (/4 1600)
>[721401.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[721401.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[721401.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0ee0]
>[721401.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0ee0] width 1600 pitch 6400 (/4 1600)
>[721401.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[721401.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[721401.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e0ee0]
>[721402.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e0ee0] width 1600 pitch 6400 (/4 1600)
>[721411.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2858fa0]
>[721411.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2858fa0] width 1600 pitch 6400 (/4 1600)
>[721411.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b09eb0]
>[721411.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b09eb0] width 1600 pitch 6400 (/4 1600)
>[721412.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1aa90]
>[721412.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1aa90] width 1600 pitch 6400 (/4 1600)
>[721412.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0a700]
>[721412.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0a700] width 1600 pitch 6400 (/4 1600)
>[721412.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5ce0]
>[721412.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5ce0] width 1600 pitch 6400 (/4 1600)
>[721413.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2d0d0]
>[721413.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2d0d0] width 1600 pitch 6400 (/4 1600)
>[721413.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a38b0]
>[721413.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a38b0] width 1600 pitch 6400 (/4 1600)
>[721467.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c1c10]
>[721467.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c1c10] width 1600 pitch 6400 (/4 1600)
>[721467.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929e00]
>[721467.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929e00] width 1600 pitch 6400 (/4 1600)
>[721468.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fa3a0]
>[721468.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fa3a0] width 1600 pitch 6400 (/4 1600)
>[721468.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721468.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721468.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[721468.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[721468.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683540]
>[721469.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683540] width 1600 pitch 6400 (/4 1600)
>[721469.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[721469.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[721470.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721470.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721470.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721470.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721470.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721470.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721470.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721470.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721470.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721470.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721470.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721471.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721471.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721471.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721472.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721472.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721472.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721472.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721472.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721472.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721472.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721472.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721473.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721473.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721473.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721473.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721477.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721477.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721480.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721481.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721481.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721481.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721481.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721481.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721481.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3011ff0]
>[721481.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3011ff0] width 1600 pitch 6400 (/4 1600)
>[721481.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09450]
>[721481.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09450] width 1600 pitch 6400 (/4 1600)
>[721483.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be0900]
>[721483.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be0900] width 1600 pitch 6400 (/4 1600)
>[721483.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721483.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721483.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9d310]
>[721483.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9d310] width 1600 pitch 6400 (/4 1600)
>[721483.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721483.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721483.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9d310]
>[721483.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9d310] width 1600 pitch 6400 (/4 1600)
>[721483.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721483.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721488.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721488.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721488.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e84840]
>[721488.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e84840] width 1600 pitch 6400 (/4 1600)
>[721490.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[721490.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[721490.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39302d0]
>[721490.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39302d0] width 1600 pitch 6400 (/4 1600)
>[721491.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[721491.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[721491.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39302d0]
>[721491.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39302d0] width 1600 pitch 6400 (/4 1600)
>[721492.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[721492.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[721492.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39302d0]
>[721492.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39302d0] width 1600 pitch 6400 (/4 1600)
>[721494.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[721494.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[721494.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39302d0]
>[721494.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39302d0] width 1600 pitch 6400 (/4 1600)
>[721501.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a5fb0]
>[721501.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a5fb0] width 1600 pitch 6400 (/4 1600)
>[721502.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd7530]
>[721502.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd7530] width 1600 pitch 6400 (/4 1600)
>[721502.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c2e50]
>[721502.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c2e50] width 1600 pitch 6400 (/4 1600)
>[721502.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099550]
>[721502.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099550] width 1600 pitch 6400 (/4 1600)
>[721503.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d59030]
>[721503.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d59030] width 1600 pitch 6400 (/4 1600)
>[721503.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c290c0]
>[721503.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c290c0] width 1600 pitch 6400 (/4 1600)
>[721503.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2625700]
>[721503.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2625700] width 1600 pitch 6400 (/4 1600)
>[721503.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dea670]
>[721503.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dea670] width 1600 pitch 6400 (/4 1600)
>[721503.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301a860]
>[721503.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301a860] width 1600 pitch 6400 (/4 1600)
>[721503.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fb9190]
>[721503.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fb9190] width 1600 pitch 6400 (/4 1600)
>[721503.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd0290]
>[721503.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd0290] width 1600 pitch 6400 (/4 1600)
>[721503.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4048f50]
>[721503.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4048f50] width 1600 pitch 6400 (/4 1600)
>[721504.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec71a0]
>[721504.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec71a0] width 1600 pitch 6400 (/4 1600)
>[721504.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b39b90]
>[721504.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b39b90] width 1600 pitch 6400 (/4 1600)
>[721504.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5020]
>[721504.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5020] width 1600 pitch 6400 (/4 1600)
>[721504.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2849660]
>[721504.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2849660] width 1600 pitch 6400 (/4 1600)
>[721504.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3f270]
>[721504.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3f270] width 1600 pitch 6400 (/4 1600)
>[721504.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4960c50]
>[721504.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4960c50] width 1600 pitch 6400 (/4 1600)
>[721505.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdc260]
>[721505.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdc260] width 1600 pitch 6400 (/4 1600)
>[721505.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50dd770]
>[721505.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50dd770] width 1600 pitch 6400 (/4 1600)
>[721505.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6910]
>[721505.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6910] width 1600 pitch 6400 (/4 1600)
>[721505.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5116720]
>[721505.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5116720] width 1600 pitch 6400 (/4 1600)
>[721505.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3921dc0]
>[721505.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3921dc0] width 1600 pitch 6400 (/4 1600)
>[721505.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce7780]
>[721505.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce7780] width 1600 pitch 6400 (/4 1600)
>[721505.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b12ef0]
>[721505.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b12ef0] width 1600 pitch 6400 (/4 1600)
>[721505.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8d510]
>[721505.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8d510] width 1600 pitch 6400 (/4 1600)
>[721505.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3e60]
>[721505.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3e60] width 1600 pitch 6400 (/4 1600)
>[721505.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96e90]
>[721505.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96e90] width 1600 pitch 6400 (/4 1600)
>[721505.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388cdd0]
>[721505.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388cdd0] width 1600 pitch 6400 (/4 1600)
>[721505.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b53f70]
>[721505.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b53f70] width 1600 pitch 6400 (/4 1600)
>[721506.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678d2b0]
>[721506.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678d2b0] width 1600 pitch 6400 (/4 1600)
>[721506.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b6740]
>[721506.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b6740] width 1600 pitch 6400 (/4 1600)
>[721506.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50a10]
>[721506.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50a10] width 1600 pitch 6400 (/4 1600)
>[721506.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cfa0]
>[721506.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cfa0] width 1600 pitch 6400 (/4 1600)
>[721506.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x30187c0]
>[721506.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x30187c0] width 1600 pitch 6400 (/4 1600)
>[721506.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d09450]
>[721506.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d09450] width 1600 pitch 6400 (/4 1600)
>[721506.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3011ff0]
>[721506.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3011ff0] width 1600 pitch 6400 (/4 1600)
>[721506.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1e870]
>[721506.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1e870] width 1600 pitch 6400 (/4 1600)
>[721506.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0e490]
>[721506.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0e490] width 1600 pitch 6400 (/4 1600)
>[721506.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a84070]
>[721506.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a84070] width 1600 pitch 6400 (/4 1600)
>[721506.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b355a0]
>[721506.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b355a0] width 1600 pitch 6400 (/4 1600)
>[721506.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dbd900]
>[721506.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dbd900] width 1600 pitch 6400 (/4 1600)
>[721507.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9dd70]
>[721507.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9dd70] width 1600 pitch 6400 (/4 1600)
>[721508.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4660]
>[721509.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4660] width 1600 pitch 6400 (/4 1600)
>[721509.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bde270]
>[721509.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bde270] width 1600 pitch 6400 (/4 1600)
>[721509.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8de40]
>[721509.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8de40] width 1600 pitch 6400 (/4 1600)
>[721509.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3770]
>[721509.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3770] width 1600 pitch 6400 (/4 1600)
>[721509.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3dd80]
>[721509.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3dd80] width 1600 pitch 6400 (/4 1600)
>[721509.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c3ca0]
>[721509.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c3ca0] width 1600 pitch 6400 (/4 1600)
>[721509.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0fef0]
>[721509.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0fef0] width 1600 pitch 6400 (/4 1600)
>[721509.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40b1950]
>[721509.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40b1950] width 1600 pitch 6400 (/4 1600)
>[721510.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3967a30]
>[721510.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3967a30] width 1600 pitch 6400 (/4 1600)
>[721510.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f76b70]
>[721510.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f76b70] width 1600 pitch 6400 (/4 1600)
>[721510.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d68d0]
>[721510.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d68d0] width 1600 pitch 6400 (/4 1600)
>[721510.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50a1d10]
>[721510.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50a1d10] width 1600 pitch 6400 (/4 1600)
>[721510.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fcc50]
>[721510.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fcc50] width 1600 pitch 6400 (/4 1600)
>[721510.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495ccd0]
>[721510.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495ccd0] width 1600 pitch 6400 (/4 1600)
>[721510.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284f310]
>[721510.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284f310] width 1600 pitch 6400 (/4 1600)
>[721510.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5957a30]
>[721510.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5957a30] width 1600 pitch 6400 (/4 1600)
>[721510.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f40010]
>[721510.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f40010] width 1600 pitch 6400 (/4 1600)
>[721510.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811950]
>[721510.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811950] width 1600 pitch 6400 (/4 1600)
>[721510.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc2af0]
>[721510.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc2af0] width 1600 pitch 6400 (/4 1600)
>[721511.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b51980]
>[721511.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b51980] width 1600 pitch 6400 (/4 1600)
>[721511.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c580]
>[721511.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c580] width 1600 pitch 6400 (/4 1600)
>[721511.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f4e80]
>[721511.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f4e80] width 1600 pitch 6400 (/4 1600)
>[721511.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96890]
>[721512.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96890] width 1600 pitch 6400 (/4 1600)
>[721512.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec3770]
>[721512.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec3770] width 1600 pitch 6400 (/4 1600)
>[721512.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e38730]
>[721512.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e38730] width 1600 pitch 6400 (/4 1600)
>[721512.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26f5ce0]
>[721512.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26f5ce0] width 1600 pitch 6400 (/4 1600)
>[721512.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50104b0]
>[721512.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50104b0] width 1600 pitch 6400 (/4 1600)
>[721621.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[721621.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1600 pitch 6400 (/4 1600)
>[721661.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc74c0]
>[721661.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc74c0] width 1600 pitch 6400 (/4 1600)
>[721661.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e282a0]
>[721661.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e282a0] width 1600 pitch 6400 (/4 1600)
>[721661.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683540]
>[721662.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683540] width 1600 pitch 6400 (/4 1600)
>[721663.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[721663.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[721663.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ad980]
>[721663.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ad980] width 1600 pitch 6400 (/4 1600)
>[721664.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1c1e0]
>[721664.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1c1e0] width 1600 pitch 6400 (/4 1600)
>[721664.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683540]
>[721664.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683540] width 1600 pitch 6400 (/4 1600)
>[721664.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2683540]
>[721664.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2683540] width 1600 pitch 6400 (/4 1600)
>[721665.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[721665.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[721665.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[721665.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1600 pitch 6400 (/4 1600)
>[722286.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[722286.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[722286.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722286.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722286.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[722286.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[722286.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722286.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722286.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[722286.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[722286.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722286.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722286.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722286.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722286.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722286.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722290.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722290.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722290.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722290.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722290.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722290.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722290.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722290.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722290.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722290.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722290.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722290.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722290.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722290.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722290.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722290.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722300.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722300.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722300.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[722300.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[722300.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[722300.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[722304.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722304.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722304.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b28150]
>[722304.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b28150] width 1600 pitch 6400 (/4 1600)
>[722304.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722304.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722304.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b28150]
>[722304.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b28150] width 1600 pitch 6400 (/4 1600)
>[722304.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722304.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722304.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b28150]
>[722304.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b28150] width 1600 pitch 6400 (/4 1600)
>[722304.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722304.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722304.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b28150]
>[722304.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b28150] width 1600 pitch 6400 (/4 1600)
>[722304.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687aac0]
>[722304.753] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687aac0] width 1600 pitch 6400 (/4 1600)
>[722905.488] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[722905.488] (II) RADEON(0): Printing DDC gathered Modelines:
>[722905.488] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[722905.488] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[722996.100] (II) RADEON(0): RADEONSaveScreen(2)
>[722996.123] (II) RADEON(0): RADEONSaveScreen(0)
>[723264.183] (II) RADEON(0): RADEONSaveScreen(1)
>[723384.267] (II) AIGLX: Suspending AIGLX clients for VT switch
>[723384.267] (II) RADEON(0): RADEONLeaveVT_KMS
>[723384.267] (II) RADEON(0): Ok, leaving now...
>[723510.207] (II) AIGLX: Resuming AIGLX clients after VT switch
>[723510.227] (II) RADEON(0): RADEONEnterVT_KMS
>[723510.268] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[723510.268] (II) RADEON(0): Printing DDC gathered Modelines:
>[723510.268] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[723510.268] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[723510.301] (II) RADEON(0): RADEONSaveScreen(2)
>[723510.302] (**) Option "Device" "/dev/input/event5"
>[723510.302] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[723511.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4f1b0]
>[723511.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4f1b0] width 1600 pitch 6400 (/4 1600)
>[723511.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d5a650]
>[723512.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d5a650] width 1600 pitch 6400 (/4 1600)
>[723512.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cef860]
>[723512.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cef860] width 1600 pitch 6400 (/4 1600)
>[723615.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26ff0]
>[723616.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26ff0] width 1600 pitch 6400 (/4 1600)
>[723616.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ccb0]
>[723616.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ccb0] width 1600 pitch 6400 (/4 1600)
>[723616.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[723616.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1600 pitch 6400 (/4 1600)
>[723616.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ccb0]
>[723616.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ccb0] width 1600 pitch 6400 (/4 1600)
>[723616.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[723616.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1600 pitch 6400 (/4 1600)
>[723616.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ccb0]
>[723616.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ccb0] width 1600 pitch 6400 (/4 1600)
>[723616.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[723616.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1600 pitch 6400 (/4 1600)
>[723616.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ccb0]
>[723616.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ccb0] width 1600 pitch 6400 (/4 1600)
>[723617.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[723617.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1600 pitch 6400 (/4 1600)
>[723617.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507ccb0]
>[723617.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507ccb0] width 1600 pitch 6400 (/4 1600)
>[723617.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[723617.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1600 pitch 6400 (/4 1600)
>[723617.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723617.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723617.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723617.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723617.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723617.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723617.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723617.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723617.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723617.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723617.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723617.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723617.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723617.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723617.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723617.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723617.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723618.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723618.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723618.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723618.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723618.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723618.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723618.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723618.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[723618.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[723618.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958430]
>[723618.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958430] width 1600 pitch 6400 (/4 1600)
>[723618.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26ff0]
>[723618.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26ff0] width 1600 pitch 6400 (/4 1600)
>[723618.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958430]
>[723618.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958430] width 1600 pitch 6400 (/4 1600)
>[723618.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26ff0]
>[723618.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26ff0] width 1600 pitch 6400 (/4 1600)
>[723624.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[723624.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[723624.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b44a0]
>[723624.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b44a0] width 1600 pitch 6400 (/4 1600)
>[723624.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958430]
>[723624.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958430] width 1600 pitch 6400 (/4 1600)
>[723670.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac85c0]
>[723670.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac85c0] width 1600 pitch 6400 (/4 1600)
>[723674.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723674.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723674.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723674.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723674.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[723675.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[723675.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723675.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723675.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[723675.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[723675.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e1f0]
>[723675.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e1f0] width 1600 pitch 6400 (/4 1600)
>[723675.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[723675.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[723675.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723675.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723675.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[723675.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[723675.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723675.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723675.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[723675.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[723677.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e1f0]
>[723677.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e1f0] width 1600 pitch 6400 (/4 1600)
>[723677.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723677.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723677.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929510]
>[723677.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929510] width 1600 pitch 6400 (/4 1600)
>[723677.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e1f0]
>[723677.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e1f0] width 1600 pitch 6400 (/4 1600)
>[723678.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929510]
>[723678.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929510] width 1600 pitch 6400 (/4 1600)
>[723678.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e330]
>[723678.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e330] width 1600 pitch 6400 (/4 1600)
>[723679.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e36cc0]
>[723679.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e36cc0] width 1600 pitch 6400 (/4 1600)
>[723679.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586eca0]
>[723679.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586eca0] width 1600 pitch 6400 (/4 1600)
>[723706.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50993b0]
>[723706.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50993b0] width 1600 pitch 6400 (/4 1600)
>[723706.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301c1a0]
>[723707.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301c1a0] width 1600 pitch 6400 (/4 1600)
>[723707.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4022ca0]
>[723707.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4022ca0] width 1600 pitch 6400 (/4 1600)
>[723707.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4db2f40]
>[723707.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4db2f40] width 1600 pitch 6400 (/4 1600)
>[723707.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c052f0]
>[723707.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c052f0] width 1600 pitch 6400 (/4 1600)
>[723707.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723707.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723708.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0cdd0]
>[723708.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0cdd0] width 1600 pitch 6400 (/4 1600)
>[723717.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7810]
>[723717.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7810] width 1600 pitch 6400 (/4 1600)
>[723717.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4d8b0]
>[723717.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4d8b0] width 1600 pitch 6400 (/4 1600)
>[723717.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723717.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723718.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723718.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723718.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723718.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723719.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723719.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723719.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723719.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723719.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723719.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723719.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723719.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723720.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723720.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723720.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723720.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723720.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723720.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723720.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723720.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723720.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723720.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723720.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723721.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723721.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723721.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723721.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723721.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723721.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723721.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723721.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723721.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723722.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723722.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723722.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723722.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723722.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723722.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723722.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723722.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723722.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723722.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723723.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723723.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723723.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723723.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723723.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96e90]
>[723723.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96e90] width 1600 pitch 6400 (/4 1600)
>[723723.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf3460]
>[723724.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf3460] width 1600 pitch 6400 (/4 1600)
>[723724.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a96e90]
>[723724.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a96e90] width 1600 pitch 6400 (/4 1600)
>[723724.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e60b0]
>[723724.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e60b0] width 1600 pitch 6400 (/4 1600)
>[723724.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723724.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723724.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723724.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723724.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d6530]
>[723724.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d6530] width 1600 pitch 6400 (/4 1600)
>[723724.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723724.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723724.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68d6530]
>[723724.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68d6530] width 1600 pitch 6400 (/4 1600)
>[723724.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723724.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723724.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723724.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723724.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723724.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723724.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723725.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723725.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723725.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723725.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723725.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723725.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723725.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723726.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723726.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723726.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723726.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723726.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723726.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723726.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723726.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723726.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723726.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723727.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723727.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723727.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723727.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723727.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0d480]
>[723727.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0d480] width 1600 pitch 6400 (/4 1600)
>[723728.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0d480]
>[723728.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0d480] width 1600 pitch 6400 (/4 1600)
>[723728.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723728.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723728.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0d480]
>[723728.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0d480] width 1600 pitch 6400 (/4 1600)
>[723728.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723728.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723728.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723728.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723728.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723728.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723728.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723728.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723728.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723728.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723728.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723728.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723728.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723728.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723728.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723728.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723729.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723729.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723729.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723729.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723729.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0d480]
>[723729.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0d480] width 1600 pitch 6400 (/4 1600)
>[723729.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723729.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723729.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723730.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723730.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723730.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723730.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723730.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723730.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723730.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723731.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723731.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723731.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723731.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723731.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723731.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723731.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723731.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723731.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723731.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723731.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723731.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723731.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723732.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723732.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723732.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723732.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723732.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723732.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723732.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723732.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723732.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723732.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723732.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723732.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723732.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723732.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723732.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723732.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723732.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723732.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723732.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723733.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723733.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723733.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723733.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723733.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723733.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723733.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723733.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723733.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723733.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723733.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723733.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723733.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723733.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723734.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723734.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723734.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723734.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723734.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723734.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723734.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723734.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723734.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723734.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723735.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce7780]
>[723735.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce7780] width 1600 pitch 6400 (/4 1600)
>[723735.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf90e0]
>[723735.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf90e0] width 1600 pitch 6400 (/4 1600)
>[723736.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec7410]
>[723736.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec7410] width 1600 pitch 6400 (/4 1600)
>[723736.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be6e0]
>[723736.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be6e0] width 1600 pitch 6400 (/4 1600)
>[723736.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be6e0]
>[723736.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be6e0] width 1600 pitch 6400 (/4 1600)
>[723737.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6de0]
>[723737.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6de0] width 1600 pitch 6400 (/4 1600)
>[723738.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7dfc0]
>[723738.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7dfc0] width 1600 pitch 6400 (/4 1600)
>[723738.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be6e0]
>[723738.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be6e0] width 1600 pitch 6400 (/4 1600)
>[723738.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df810]
>[723738.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df810] width 1600 pitch 6400 (/4 1600)
>[723738.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[723738.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[723804.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f0a0]
>[723804.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f0a0] width 1600 pitch 6400 (/4 1600)
>[723897.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ecfb0]
>[723897.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ecfb0] width 1600 pitch 6400 (/4 1600)
>[723897.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df810]
>[723897.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df810] width 1600 pitch 6400 (/4 1600)
>[723898.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf1b60]
>[723898.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf1b60] width 1600 pitch 6400 (/4 1600)
>[723898.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3ed0]
>[723898.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3ed0] width 1600 pitch 6400 (/4 1600)
>[723899.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eebf70]
>[723899.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eebf70] width 1600 pitch 6400 (/4 1600)
>[723899.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d521b0]
>[723899.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d521b0] width 1600 pitch 6400 (/4 1600)
>[723899.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699f320]
>[723899.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699f320] width 1600 pitch 6400 (/4 1600)
>[723900.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df810]
>[723900.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df810] width 1600 pitch 6400 (/4 1600)
>[723900.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ed60]
>[723900.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ed60] width 1600 pitch 6400 (/4 1600)
>[723900.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ed60]
>[723900.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ed60] width 1600 pitch 6400 (/4 1600)
>[723901.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d6940]
>[723901.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d6940] width 1600 pitch 6400 (/4 1600)
>[723902.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d6940]
>[723902.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d6940] width 1600 pitch 6400 (/4 1600)
>[723902.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d28c0]
>[723902.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d28c0] width 1600 pitch 6400 (/4 1600)
>[723902.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723903.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723903.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723903.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723903.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723903.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723907.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723907.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723907.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723908.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723908.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723908.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723908.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723908.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723909.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d140]
>[723909.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d140] width 1600 pitch 6400 (/4 1600)
>[723909.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723909.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723909.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723909.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723910.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723910.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723910.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723910.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723910.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723910.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723910.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d140]
>[723910.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d140] width 1600 pitch 6400 (/4 1600)
>[723911.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723911.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723911.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[723911.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[723911.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723911.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723911.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50240]
>[723911.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50240] width 1600 pitch 6400 (/4 1600)
>[723911.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723911.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723911.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723912.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723912.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723912.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723912.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723912.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723912.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723912.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723912.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723912.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723912.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723912.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723912.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[723912.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[723912.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723912.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723912.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d140]
>[723913.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d140] width 1600 pitch 6400 (/4 1600)
>[723913.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723913.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723913.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723913.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723913.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723913.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723913.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfa250]
>[723913.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfa250] width 1600 pitch 6400 (/4 1600)
>[723914.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723914.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723914.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723914.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723916.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eeb7a0]
>[723916.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eeb7a0] width 1600 pitch 6400 (/4 1600)
>[723916.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7870]
>[723916.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7870] width 1600 pitch 6400 (/4 1600)
>[723917.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd7870]
>[723917.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd7870] width 1600 pitch 6400 (/4 1600)
>[723917.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723917.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723917.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec71a0]
>[723917.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec71a0] width 1600 pitch 6400 (/4 1600)
>[723917.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec71a0]
>[723918.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec71a0] width 1600 pitch 6400 (/4 1600)
>[723919.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c52b30]
>[723919.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c52b30] width 1600 pitch 6400 (/4 1600)
>[723919.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47b0a90]
>[723919.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47b0a90] width 1600 pitch 6400 (/4 1600)
>[723920.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c980]
>[723920.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c980] width 1600 pitch 6400 (/4 1600)
>[723920.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47b0a90]
>[723921.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47b0a90] width 1600 pitch 6400 (/4 1600)
>[723921.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3ed0]
>[723921.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3ed0] width 1600 pitch 6400 (/4 1600)
>[723921.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723921.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723923.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300c980]
>[723923.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300c980] width 1600 pitch 6400 (/4 1600)
>[723923.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c087b0]
>[723924.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c087b0] width 1600 pitch 6400 (/4 1600)
>[723924.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c087b0]
>[723924.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c087b0] width 1600 pitch 6400 (/4 1600)
>[723929.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723929.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723929.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4959260]
>[723929.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4959260] width 1600 pitch 6400 (/4 1600)
>[723929.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ee7820]
>[723929.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ee7820] width 1600 pitch 6400 (/4 1600)
>[723968.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820f20]
>[723969.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820f20] width 1600 pitch 6400 (/4 1600)
>[723969.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3e3d0]
>[723969.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3e3d0] width 1600 pitch 6400 (/4 1600)
>[723969.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6820f20]
>[723969.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6820f20] width 1600 pitch 6400 (/4 1600)
>[723969.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723969.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723969.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a3e3d0]
>[723970.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a3e3d0] width 1600 pitch 6400 (/4 1600)
>[723970.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723970.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723970.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723970.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1b80]
>[723972.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1b80] width 1600 pitch 6400 (/4 1600)
>[723972.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723972.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4963b00]
>[723972.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4963b00] width 1600 pitch 6400 (/4 1600)
>[723972.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723972.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4963b00]
>[723972.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4963b00] width 1600 pitch 6400 (/4 1600)
>[723972.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723972.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f541c0]
>[723972.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f541c0] width 1600 pitch 6400 (/4 1600)
>[723972.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723972.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f541c0]
>[723972.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f541c0] width 1600 pitch 6400 (/4 1600)
>[723972.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723972.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723972.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f541c0]
>[723972.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f541c0] width 1600 pitch 6400 (/4 1600)
>[723973.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041040]
>[723974.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041040] width 1600 pitch 6400 (/4 1600)
>[723974.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674e280]
>[723974.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674e280] width 1600 pitch 6400 (/4 1600)
>[723974.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674e280]
>[723974.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674e280] width 1600 pitch 6400 (/4 1600)
>[723974.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674e280]
>[723974.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674e280] width 1600 pitch 6400 (/4 1600)
>[723974.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09ee0]
>[723975.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09ee0] width 1600 pitch 6400 (/4 1600)
>[723975.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f541c0]
>[723975.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f541c0] width 1600 pitch 6400 (/4 1600)
>[723975.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674e280]
>[723975.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674e280] width 1600 pitch 6400 (/4 1600)
>[723975.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09ee0]
>[723975.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09ee0] width 1600 pitch 6400 (/4 1600)
>[723976.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee620]
>[723976.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee620] width 1600 pitch 6400 (/4 1600)
>[723976.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09ee0]
>[723976.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09ee0] width 1600 pitch 6400 (/4 1600)
>[723976.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f541c0]
>[723976.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f541c0] width 1600 pitch 6400 (/4 1600)
>[723976.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09ee0]
>[723976.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09ee0] width 1600 pitch 6400 (/4 1600)
>[723977.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f09ee0]
>[723977.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f09ee0] width 1600 pitch 6400 (/4 1600)
>[723977.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb570]
>[723977.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb570] width 1600 pitch 6400 (/4 1600)
>[723977.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723977.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723978.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723978.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723978.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723978.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723978.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723978.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723978.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c9d0]
>[723978.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c9d0] width 1600 pitch 6400 (/4 1600)
>[723978.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c6b20]
>[723978.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c6b20] width 1600 pitch 6400 (/4 1600)
>[723985.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723985.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723985.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c9d0]
>[723985.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c9d0] width 1600 pitch 6400 (/4 1600)
>[723985.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723985.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723985.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c9d0]
>[723985.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c9d0] width 1600 pitch 6400 (/4 1600)
>[723985.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723985.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723985.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c9d0]
>[723985.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c9d0] width 1600 pitch 6400 (/4 1600)
>[723985.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723985.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723985.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723985.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723985.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723985.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723988.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723988.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723988.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723988.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723989.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723989.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723989.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723989.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723989.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723989.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723989.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723989.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723989.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723989.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723989.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723989.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723989.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723989.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723989.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723989.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723989.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723989.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723990.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723990.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723990.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723990.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723990.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723990.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723990.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723990.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723990.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723990.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723991.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723991.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[723991.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb570]
>[723991.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb570] width 1600 pitch 6400 (/4 1600)
>[723991.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6cf0]
>[723991.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6cf0] width 1600 pitch 6400 (/4 1600)
>[723992.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e6cf0]
>[723992.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e6cf0] width 1600 pitch 6400 (/4 1600)
>[723992.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4960c50]
>[723992.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4960c50] width 1600 pitch 6400 (/4 1600)
>[723992.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478dda0]
>[723992.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478dda0] width 1600 pitch 6400 (/4 1600)
>[723992.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723992.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723993.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3896980]
>[723993.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3896980] width 1600 pitch 6400 (/4 1600)
>[723993.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4963b00]
>[723993.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4963b00] width 1600 pitch 6400 (/4 1600)
>[723993.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4bd0]
>[723993.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4bd0] width 1600 pitch 6400 (/4 1600)
>[723993.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723993.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723994.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723994.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723994.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f96b70]
>[723994.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f96b70] width 1600 pitch 6400 (/4 1600)
>[723994.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507cc20]
>[723994.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507cc20] width 1600 pitch 6400 (/4 1600)
>[724073.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5885a70]
>[724073.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5885a70] width 1600 pitch 6400 (/4 1600)
>[724073.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee620]
>[724074.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee620] width 1600 pitch 6400 (/4 1600)
>[724074.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674e280]
>[724074.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674e280] width 1600 pitch 6400 (/4 1600)
>[724074.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ed60]
>[724074.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ed60] width 1600 pitch 6400 (/4 1600)
>[724074.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0ed60]
>[724074.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0ed60] width 1600 pitch 6400 (/4 1600)
>[724075.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c5180]
>[724075.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c5180] width 1600 pitch 6400 (/4 1600)
>[724081.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4997520]
>[724081.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4997520] width 1600 pitch 6400 (/4 1600)
>[724081.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85fc0]
>[724081.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85fc0] width 1600 pitch 6400 (/4 1600)
>[724082.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c5180]
>[724082.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c5180] width 1600 pitch 6400 (/4 1600)
>[724082.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4997520]
>[724082.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4997520] width 1600 pitch 6400 (/4 1600)
>[724082.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[724082.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[724083.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38c5180]
>[724083.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38c5180] width 1600 pitch 6400 (/4 1600)
>[724083.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[724083.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[724083.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[724083.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[724083.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724084.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724084.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[724084.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[724087.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aeaf0]
>[724087.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aeaf0] width 1600 pitch 6400 (/4 1600)
>[724087.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[724087.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[724087.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724087.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724087.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a1e1f0]
>[724087.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a1e1f0] width 1600 pitch 6400 (/4 1600)
>[724087.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724087.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724087.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5919670]
>[724087.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5919670] width 1600 pitch 6400 (/4 1600)
>[724087.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724087.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724087.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[724087.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[724090.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[724090.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[724090.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724090.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724090.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811fd0]
>[724090.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811fd0] width 1600 pitch 6400 (/4 1600)
>[724090.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4c910]
>[724090.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4c910] width 1600 pitch 6400 (/4 1600)
>[724090.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec1a50]
>[724090.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec1a50] width 1600 pitch 6400 (/4 1600)
>[724090.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4c910]
>[724090.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4c910] width 1600 pitch 6400 (/4 1600)
>[724091.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dba580]
>[724091.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dba580] width 1600 pitch 6400 (/4 1600)
>[724091.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3945af0]
>[724091.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3945af0] width 1600 pitch 6400 (/4 1600)
>[724091.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e0b5e0]
>[724091.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e0b5e0] width 1600 pitch 6400 (/4 1600)
>[724091.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6520]
>[724091.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6520] width 1600 pitch 6400 (/4 1600)
>[724092.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1fbd0]
>[724092.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1fbd0] width 1600 pitch 6400 (/4 1600)
>[724092.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b35be0]
>[724092.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b35be0] width 1600 pitch 6400 (/4 1600)
>[724092.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[724092.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[724092.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724092.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724092.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11b30]
>[724092.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11b30] width 1600 pitch 6400 (/4 1600)
>[724092.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aa5bd0]
>[724092.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aa5bd0] width 1600 pitch 6400 (/4 1600)
>[724093.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec1a50]
>[724093.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec1a50] width 1600 pitch 6400 (/4 1600)
>[724093.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[724093.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[724093.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b50c0]
>[724093.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b50c0] width 1600 pitch 6400 (/4 1600)
>[724093.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[724093.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[724093.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b50c0]
>[724093.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b50c0] width 1600 pitch 6400 (/4 1600)
>[724093.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ca41c0]
>[724093.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ca41c0] width 1600 pitch 6400 (/4 1600)
>[724093.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b50c0]
>[724093.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b50c0] width 1600 pitch 6400 (/4 1600)
>[724093.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[724093.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1600 pitch 6400 (/4 1600)
>[724094.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3945af0]
>[724094.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3945af0] width 1600 pitch 6400 (/4 1600)
>[724094.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e89a0]
>[724094.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e89a0] width 1600 pitch 6400 (/4 1600)
>[724095.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[724095.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[724095.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27013f0]
>[724095.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27013f0] width 1600 pitch 6400 (/4 1600)
>[724218.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918970]
>[724218.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918970] width 1600 pitch 6400 (/4 1600)
>[724483.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[724483.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[724483.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[724483.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[724483.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b924a0]
>[724483.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b924a0] width 1600 pitch 6400 (/4 1600)
>[724483.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811fd0]
>[724483.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811fd0] width 1600 pitch 6400 (/4 1600)
>[724483.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[724483.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[724488.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebf550]
>[724488.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebf550] width 1600 pitch 6400 (/4 1600)
>[724488.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6989c20]
>[724488.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6989c20] width 1600 pitch 6400 (/4 1600)
>[724488.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b50c0]
>[724488.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b50c0] width 1600 pitch 6400 (/4 1600)
>[724488.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5c9e0]
>[724488.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5c9e0] width 1600 pitch 6400 (/4 1600)
>[724488.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3faa620]
>[724488.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3faa620] width 1600 pitch 6400 (/4 1600)
>[724488.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e940]
>[724488.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e940] width 1600 pitch 6400 (/4 1600)
>[724775.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4061910]
>[724776.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4061910] width 1600 pitch 6400 (/4 1600)
>[724776.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4d150]
>[724776.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4d150] width 1600 pitch 6400 (/4 1600)
>[724776.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aec70]
>[724776.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aec70] width 1600 pitch 6400 (/4 1600)
>[724776.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aec70]
>[724776.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aec70] width 1600 pitch 6400 (/4 1600)
>[724776.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4d150]
>[724776.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4d150] width 1600 pitch 6400 (/4 1600)
>[724777.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd990]
>[724777.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd990] width 1600 pitch 6400 (/4 1600)
>[724777.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28162f0]
>[724777.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28162f0] width 1600 pitch 6400 (/4 1600)
>[724796.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5010]
>[724796.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5010] width 1600 pitch 6400 (/4 1600)
>[724798.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478ca70]
>[724798.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478ca70] width 1600 pitch 6400 (/4 1600)
>[724798.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[724798.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1600 pitch 6400 (/4 1600)
>[724798.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x285fa70]
>[724798.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x285fa70] width 1600 pitch 6400 (/4 1600)
>[724798.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40395d0]
>[724798.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40395d0] width 1600 pitch 6400 (/4 1600)
>[724799.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd990]
>[724799.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd990] width 1600 pitch 6400 (/4 1600)
>[724799.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[724799.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1600 pitch 6400 (/4 1600)
>[724799.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdd990]
>[724799.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdd990] width 1600 pitch 6400 (/4 1600)
>[724799.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee6e60]
>[724799.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee6e60] width 1600 pitch 6400 (/4 1600)
>[724799.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3afcdf0]
>[724799.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3afcdf0] width 1600 pitch 6400 (/4 1600)
>[724799.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ee620]
>[724799.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ee620] width 1600 pitch 6400 (/4 1600)
>[724799.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d0e0]
>[724799.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d0e0] width 1600 pitch 6400 (/4 1600)
>[724799.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2efb4e0]
>[724799.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2efb4e0] width 1600 pitch 6400 (/4 1600)
>[724801.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595cb10]
>[724801.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595cb10] width 1600 pitch 6400 (/4 1600)
>[724801.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4d150]
>[724802.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4d150] width 1600 pitch 6400 (/4 1600)
>[725052.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5010]
>[725053.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5010] width 1600 pitch 6400 (/4 1600)
>[725053.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed5010]
>[725053.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed5010] width 1600 pitch 6400 (/4 1600)
>[725054.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5099cc0]
>[725054.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5099cc0] width 1600 pitch 6400 (/4 1600)
>[725054.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015cf0]
>[725054.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015cf0] width 1600 pitch 6400 (/4 1600)
>[725055.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d5950]
>[725055.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d5950] width 1600 pitch 6400 (/4 1600)
>[725055.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015cf0]
>[725055.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015cf0] width 1600 pitch 6400 (/4 1600)
>[725055.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015cf0]
>[725056.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015cf0] width 1600 pitch 6400 (/4 1600)
>[725056.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d5950]
>[725056.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d5950] width 1600 pitch 6400 (/4 1600)
>[725128.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2b00]
>[725128.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2b00] width 1600 pitch 6400 (/4 1600)
>[725131.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x501d650]
>[725131.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x501d650] width 1600 pitch 6400 (/4 1600)
>[725131.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[725131.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[725131.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[725131.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[725131.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[725131.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[725131.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[725131.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[725131.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[725131.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[725618.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[725618.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[725618.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[725619.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[725619.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[725619.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[725619.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[725619.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[725619.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59780]
>[725619.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59780] width 1600 pitch 6400 (/4 1600)
>[725620.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[725620.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[725620.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[725620.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[725620.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725620.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725621.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59780]
>[725621.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59780] width 1600 pitch 6400 (/4 1600)
>[725624.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725624.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725624.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59780]
>[725624.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59780] width 1600 pitch 6400 (/4 1600)
>[725624.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725624.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725624.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59780]
>[725624.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59780] width 1600 pitch 6400 (/4 1600)
>[725625.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725625.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725625.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[725625.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[725625.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59780]
>[725625.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59780] width 1600 pitch 6400 (/4 1600)
>[725626.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725626.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725626.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[725626.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[725627.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725627.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725627.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[725627.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[725627.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[725627.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[725628.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[725628.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[725628.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc940]
>[725628.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc940] width 1600 pitch 6400 (/4 1600)
>[725628.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[725628.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[725629.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbc940]
>[725629.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbc940] width 1600 pitch 6400 (/4 1600)
>[725630.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbca60]
>[725630.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbca60] width 1600 pitch 6400 (/4 1600)
>[725630.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2e960]
>[725631.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2e960] width 1600 pitch 6400 (/4 1600)
>[725631.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a15b90]
>[725631.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a15b90] width 1600 pitch 6400 (/4 1600)
>[725656.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b581a0]
>[725656.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b581a0] width 1600 pitch 6400 (/4 1600)
>[725667.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be92f0]
>[725667.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be92f0] width 1600 pitch 6400 (/4 1600)
>[725881.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a236f0]
>[725881.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a236f0] width 1600 pitch 6400 (/4 1600)
>[726008.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726008.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726008.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a67610]
>[726008.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a67610] width 1600 pitch 6400 (/4 1600)
>[726008.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726008.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726008.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a67610]
>[726009.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a67610] width 1600 pitch 6400 (/4 1600)
>[726009.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726009.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726009.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a67610]
>[726009.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a67610] width 1600 pitch 6400 (/4 1600)
>[726009.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726009.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726013.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726013.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726013.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845c00]
>[726013.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845c00] width 1600 pitch 6400 (/4 1600)
>[726013.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726013.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726013.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845c00]
>[726013.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845c00] width 1600 pitch 6400 (/4 1600)
>[726013.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726013.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726013.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845c00]
>[726013.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845c00] width 1600 pitch 6400 (/4 1600)
>[726013.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871470]
>[726013.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871470] width 1600 pitch 6400 (/4 1600)
>[726013.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6845c00]
>[726013.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6845c00] width 1600 pitch 6400 (/4 1600)
>[726259.843] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[726259.843] (II) RADEON(0): Printing DDC gathered Modelines:
>[726259.843] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[726259.843] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[726262.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726262.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726262.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5943ae0]
>[726263.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5943ae0] width 1600 pitch 6400 (/4 1600)
>[726263.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726263.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726263.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5943ae0]
>[726263.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5943ae0] width 1600 pitch 6400 (/4 1600)
>[726263.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726263.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726263.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5943ae0]
>[726263.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5943ae0] width 1600 pitch 6400 (/4 1600)
>[726263.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726263.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726267.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[726267.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1600 pitch 6400 (/4 1600)
>[726267.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726267.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726267.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[726267.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1600 pitch 6400 (/4 1600)
>[726267.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726267.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726267.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[726267.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1600 pitch 6400 (/4 1600)
>[726267.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726267.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726267.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[726267.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1600 pitch 6400 (/4 1600)
>[726267.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726267.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726277.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726277.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726278.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726278.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726282.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[726282.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[726537.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b57b80]
>[726537.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b57b80] width 1600 pitch 6400 (/4 1600)
>[726597.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86f40]
>[726597.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86f40] width 1600 pitch 6400 (/4 1600)
>[726597.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb660]
>[726597.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb660] width 1600 pitch 6400 (/4 1600)
>[726597.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479e620]
>[726597.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479e620] width 1600 pitch 6400 (/4 1600)
>[726597.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb660]
>[726597.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb660] width 1600 pitch 6400 (/4 1600)
>[726597.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479e620]
>[726597.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479e620] width 1600 pitch 6400 (/4 1600)
>[726597.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb660]
>[726597.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb660] width 1600 pitch 6400 (/4 1600)
>[726597.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479e620]
>[726597.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479e620] width 1600 pitch 6400 (/4 1600)
>[726597.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb660]
>[726597.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb660] width 1600 pitch 6400 (/4 1600)
>[726597.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479e620]
>[726598.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479e620] width 1600 pitch 6400 (/4 1600)
>[726598.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59eb660]
>[726598.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59eb660] width 1600 pitch 6400 (/4 1600)
>[727036.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68ba7e0]
>[727036.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68ba7e0] width 1600 pitch 6400 (/4 1600)
>[727360.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9da80]
>[727360.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9da80] width 1600 pitch 6400 (/4 1600)
>[727362.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[727362.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[727425.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b955d0]
>[727425.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b955d0] width 1600 pitch 6400 (/4 1600)
>[727465.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67bc0]
>[727465.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67bc0] width 1600 pitch 6400 (/4 1600)
>[727468.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b95b30]
>[727468.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b95b30] width 1600 pitch 6400 (/4 1600)
>[727538.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6ce0]
>[727538.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6ce0] width 1600 pitch 6400 (/4 1600)
>[727620.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498ec00]
>[727620.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498ec00] width 1600 pitch 6400 (/4 1600)
>[727647.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687c550]
>[727647.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687c550] width 1600 pitch 6400 (/4 1600)
>[727661.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6de0]
>[727661.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6de0] width 1600 pitch 6400 (/4 1600)
>[727662.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5103790]
>[727662.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5103790] width 1600 pitch 6400 (/4 1600)
>[727663.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[727663.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[727663.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996ef0]
>[727663.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996ef0] width 1600 pitch 6400 (/4 1600)
>[727663.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ebf70]
>[727663.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ebf70] width 1600 pitch 6400 (/4 1600)
>[727663.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996ef0]
>[727664.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996ef0] width 1600 pitch 6400 (/4 1600)
>[727664.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996ef0]
>[727664.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996ef0] width 1600 pitch 6400 (/4 1600)
>[727669.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[727669.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[727669.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c49d90]
>[727669.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c49d90] width 1600 pitch 6400 (/4 1600)
>[727669.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[727669.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[727669.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[727670.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[727670.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[727671.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[727671.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[727671.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[727671.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402cee0]
>[727671.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402cee0] width 1600 pitch 6400 (/4 1600)
>[727689.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597b2b0]
>[727689.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597b2b0] width 1600 pitch 6400 (/4 1600)
>[727691.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45450]
>[727691.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45450] width 1600 pitch 6400 (/4 1600)
>[727691.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45450]
>[727691.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45450] width 1600 pitch 6400 (/4 1600)
>[727691.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880580]
>[727691.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880580] width 1600 pitch 6400 (/4 1600)
>[727691.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a45450]
>[727691.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a45450] width 1600 pitch 6400 (/4 1600)
>[727691.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b92de0]
>[727691.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b92de0] width 1600 pitch 6400 (/4 1600)
>[727692.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be9350]
>[727692.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be9350] width 1600 pitch 6400 (/4 1600)
>[727693.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674a5d0]
>[727693.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674a5d0] width 1600 pitch 6400 (/4 1600)
>[727693.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6899d80]
>[727693.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6899d80] width 1600 pitch 6400 (/4 1600)
>[727694.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c51d50]
>[727694.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c51d50] width 1600 pitch 6400 (/4 1600)
>[727694.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6833950]
>[727694.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6833950] width 1600 pitch 6400 (/4 1600)
>[727712.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cad060]
>[727712.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cad060] width 1600 pitch 6400 (/4 1600)
>[727713.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68333e0]
>[727713.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68333e0] width 1600 pitch 6400 (/4 1600)
>[727713.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b95790]
>[727713.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b95790] width 1600 pitch 6400 (/4 1600)
>[727714.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68333e0]
>[727714.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68333e0] width 1600 pitch 6400 (/4 1600)
>[727715.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a29140]
>[727715.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a29140] width 1600 pitch 6400 (/4 1600)
>[727715.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2824a10]
>[727715.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2824a10] width 1600 pitch 6400 (/4 1600)
>[727715.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef4bb0]
>[727715.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef4bb0] width 1600 pitch 6400 (/4 1600)
>[727716.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc3ca0]
>[727716.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc3ca0] width 1600 pitch 6400 (/4 1600)
>[727716.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb520]
>[727716.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb520] width 1600 pitch 6400 (/4 1600)
>[727716.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc7af0]
>[727716.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc7af0] width 1600 pitch 6400 (/4 1600)
>[727716.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b37c90]
>[727716.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b37c90] width 1600 pitch 6400 (/4 1600)
>[727717.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a266d0]
>[727717.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a266d0] width 1600 pitch 6400 (/4 1600)
>[727717.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b95790]
>[727717.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b95790] width 1600 pitch 6400 (/4 1600)
>[727718.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[727718.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[727718.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be9b10]
>[727718.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be9b10] width 1600 pitch 6400 (/4 1600)
>[727719.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68333e0]
>[727719.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68333e0] width 1600 pitch 6400 (/4 1600)
>[727719.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b95790]
>[727719.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b95790] width 1600 pitch 6400 (/4 1600)
>[727719.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68333e0]
>[727719.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68333e0] width 1600 pitch 6400 (/4 1600)
>[727720.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08760]
>[727720.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08760] width 1600 pitch 6400 (/4 1600)
>[727720.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[727720.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[727722.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x301d1a0]
>[727722.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x301d1a0] width 1600 pitch 6400 (/4 1600)
>[727722.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[727722.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[727722.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[727722.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[727728.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dba680]
>[727728.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dba680] width 1600 pitch 6400 (/4 1600)
>[727752.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498ed30]
>[727752.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498ed30] width 1600 pitch 6400 (/4 1600)
>[727769.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6997eb0]
>[727769.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6997eb0] width 1600 pitch 6400 (/4 1600)
>[727786.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f77b00]
>[727786.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f77b00] width 1600 pitch 6400 (/4 1600)
>[727787.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[727788.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[727788.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9e4c0]
>[727788.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9e4c0] width 1600 pitch 6400 (/4 1600)
>[727790.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef4bb0]
>[727790.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef4bb0] width 1600 pitch 6400 (/4 1600)
>[727791.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x26eb520]
>[727791.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x26eb520] width 1600 pitch 6400 (/4 1600)
>[727791.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a29140]
>[727791.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a29140] width 1600 pitch 6400 (/4 1600)
>[727791.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef4bb0]
>[727791.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef4bb0] width 1600 pitch 6400 (/4 1600)
>[727791.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de3af0]
>[727792.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de3af0] width 1600 pitch 6400 (/4 1600)
>[727792.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[727792.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[727792.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[727792.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[727917.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1dd70]
>[727917.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1dd70] width 1600 pitch 6400 (/4 1600)
>[727923.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dc950]
>[727923.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dc950] width 1600 pitch 6400 (/4 1600)
>[727937.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d04b60]
>[727937.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d04b60] width 1600 pitch 6400 (/4 1600)
>[727997.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40de540]
>[727997.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40de540] width 1600 pitch 6400 (/4 1600)
>[728000.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a31a0]
>[728000.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a31a0] width 1600 pitch 6400 (/4 1600)
>[728020.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[728021.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[728021.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[728021.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[728021.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[728021.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[728022.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[728022.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[728022.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[728022.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[728022.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25c70]
>[728022.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25c70] width 1600 pitch 6400 (/4 1600)
>[728022.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[728022.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[728022.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[728022.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[728058.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25c70]
>[728059.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25c70] width 1600 pitch 6400 (/4 1600)
>[728059.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25c70]
>[728059.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25c70] width 1600 pitch 6400 (/4 1600)
>[728059.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08760]
>[728059.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08760] width 1600 pitch 6400 (/4 1600)
>[728059.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25c70]
>[728059.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25c70] width 1600 pitch 6400 (/4 1600)
>[728059.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08760]
>[728059.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08760] width 1600 pitch 6400 (/4 1600)
>[728059.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[728060.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[728060.009] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[728060.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[728060.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681d420]
>[728060.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681d420] width 1600 pitch 6400 (/4 1600)
>[728060.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3610]
>[728060.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3610] width 1600 pitch 6400 (/4 1600)
>[728060.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[728060.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[728060.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[728060.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[728060.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[728060.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[728314.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69942d0]
>[728314.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69942d0] width 1600 pitch 6400 (/4 1600)
>[728318.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d790]
>[728318.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d790] width 1600 pitch 6400 (/4 1600)
>[728414.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993da0]
>[728414.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993da0] width 1600 pitch 6400 (/4 1600)
>[728414.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bc30]
>[728414.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bc30] width 1600 pitch 6400 (/4 1600)
>[728414.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c17d70]
>[728414.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c17d70] width 1600 pitch 6400 (/4 1600)
>[728414.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5069cf0]
>[728414.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5069cf0] width 1600 pitch 6400 (/4 1600)
>[728962.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfcbb0]
>[728962.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfcbb0] width 1600 pitch 6400 (/4 1600)
>[728962.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cfcbb0]
>[728962.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cfcbb0] width 1600 pitch 6400 (/4 1600)
>[729027.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c0060]
>[729027.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c0060] width 1600 pitch 6400 (/4 1600)
>[729027.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c0060]
>[729027.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c0060] width 1600 pitch 6400 (/4 1600)
>[729114.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e34b90]
>[729114.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e34b90] width 1600 pitch 6400 (/4 1600)
>[729115.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974c90]
>[729115.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974c90] width 1600 pitch 6400 (/4 1600)
>[729135.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59edf20]
>[729135.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59edf20] width 1600 pitch 6400 (/4 1600)
>[729155.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729155.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729155.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729155.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729155.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e34b90]
>[729155.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e34b90] width 1600 pitch 6400 (/4 1600)
>[729156.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729156.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729156.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729156.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729156.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59edf20]
>[729157.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59edf20] width 1600 pitch 6400 (/4 1600)
>[729157.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729157.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729157.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729157.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729157.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bc0]
>[729157.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bc0] width 1600 pitch 6400 (/4 1600)
>[729159.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673fe30]
>[729159.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673fe30] width 1600 pitch 6400 (/4 1600)
>[729159.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d11770]
>[729160.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d11770] width 1600 pitch 6400 (/4 1600)
>[729160.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673fe30]
>[729160.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673fe30] width 1600 pitch 6400 (/4 1600)
>[729260.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68652a0]
>[729260.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68652a0] width 1600 pitch 6400 (/4 1600)
>[729261.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729261.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729261.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729261.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729261.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729261.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729358.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811240]
>[729358.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811240] width 1600 pitch 6400 (/4 1600)
>[729422.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd80a0]
>[729422.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd80a0] width 1600 pitch 6400 (/4 1600)
>[729454.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1bc30]
>[729454.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1bc30] width 1600 pitch 6400 (/4 1600)
>[729508.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921ed0]
>[729508.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921ed0] width 1600 pitch 6400 (/4 1600)
>[729520.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4a760]
>[729520.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4a760] width 1600 pitch 6400 (/4 1600)
>[729621.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f432b0]
>[729621.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f432b0] width 1600 pitch 6400 (/4 1600)
>[729637.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729637.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729840.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b59870]
>[729840.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b59870] width 1600 pitch 6400 (/4 1600)
>[729846.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729846.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729847.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594ca40]
>[729847.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594ca40] width 1600 pitch 6400 (/4 1600)
>[729847.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921e40]
>[729847.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921e40] width 1600 pitch 6400 (/4 1600)
>[729847.788] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921e40]
>[729847.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921e40] width 1600 pitch 6400 (/4 1600)
>[729859.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921e40]
>[729859.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921e40] width 1600 pitch 6400 (/4 1600)
>[729859.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[729859.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[729859.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40de410]
>[729859.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40de410] width 1600 pitch 6400 (/4 1600)
>[729859.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25310]
>[729859.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25310] width 1600 pitch 6400 (/4 1600)
>[729875.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a254c0]
>[729875.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a254c0] width 1600 pitch 6400 (/4 1600)
>[729925.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34e80]
>[729925.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34e80] width 1600 pitch 6400 (/4 1600)
>[729929.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e34c80]
>[729929.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e34c80] width 1600 pitch 6400 (/4 1600)
>[730031.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cda2e0]
>[730031.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cda2e0] width 1600 pitch 6400 (/4 1600)
>[730039.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49ae4b0]
>[730039.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49ae4b0] width 1600 pitch 6400 (/4 1600)
>[730061.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921ed0]
>[730061.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921ed0] width 1600 pitch 6400 (/4 1600)
>[730071.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddbd0]
>[730071.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddbd0] width 1600 pitch 6400 (/4 1600)
>[730078.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[730078.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[730078.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6833ae0]
>[730079.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6833ae0] width 1600 pitch 6400 (/4 1600)
>[730079.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cee420]
>[730079.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cee420] width 1600 pitch 6400 (/4 1600)
>[730080.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b65db0]
>[730080.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b65db0] width 1600 pitch 6400 (/4 1600)
>[730080.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b65db0]
>[730080.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b65db0] width 1600 pitch 6400 (/4 1600)
>[730080.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7a80]
>[730080.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7a80] width 1600 pitch 6400 (/4 1600)
>[730080.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cee420]
>[730080.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cee420] width 1600 pitch 6400 (/4 1600)
>[730081.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498ed30]
>[730081.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498ed30] width 1600 pitch 6400 (/4 1600)
>[730082.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6862b80]
>[730082.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6862b80] width 1600 pitch 6400 (/4 1600)
>[730082.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[730082.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[730252.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[730252.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[730252.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[730253.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[730253.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[730253.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[730253.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a250c0]
>[730253.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a250c0] width 1600 pitch 6400 (/4 1600)
>[730254.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[730254.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[730254.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[730254.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[730260.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[730260.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[730260.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[730260.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[730261.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687bf30]
>[730261.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687bf30] width 1600 pitch 6400 (/4 1600)
>[730262.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687bf30]
>[730262.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687bf30] width 1600 pitch 6400 (/4 1600)
>[730262.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687bf30]
>[730262.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687bf30] width 1600 pitch 6400 (/4 1600)
>[730263.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[730263.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[730266.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[730267.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[730267.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[730267.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[730267.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506ad30]
>[730267.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506ad30] width 1600 pitch 6400 (/4 1600)
>[730268.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[730268.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[730268.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[730268.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[730269.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6990ee0]
>[730269.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6990ee0] width 1600 pitch 6400 (/4 1600)
>[730271.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a5c9e0]
>[730271.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a5c9e0] width 1600 pitch 6400 (/4 1600)
>[730271.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d7a80]
>[730271.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d7a80] width 1600 pitch 6400 (/4 1600)
>[730277.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1e750]
>[730277.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1e750] width 1600 pitch 6400 (/4 1600)
>[730284.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49ae4b0]
>[730284.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49ae4b0] width 1600 pitch 6400 (/4 1600)
>[730285.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046c50]
>[730285.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046c50] width 1600 pitch 6400 (/4 1600)
>[730285.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[730285.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[730286.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046c50]
>[730286.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046c50] width 1600 pitch 6400 (/4 1600)
>[730286.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b924a0]
>[730286.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b924a0] width 1600 pitch 6400 (/4 1600)
>[730286.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498ed30]
>[730286.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498ed30] width 1600 pitch 6400 (/4 1600)
>[730321.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498ed30]
>[730321.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498ed30] width 1600 pitch 6400 (/4 1600)
>[730341.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a34f0]
>[730341.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a34f0] width 1600 pitch 6400 (/4 1600)
>[730448.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591e350]
>[730448.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591e350] width 1600 pitch 6400 (/4 1600)
>[730471.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ed660]
>[730471.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ed660] width 1600 pitch 6400 (/4 1600)
>[730632.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811b80]
>[730632.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811b80] width 1600 pitch 6400 (/4 1600)
>[730724.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748440]
>[730724.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748440] width 1600 pitch 6400 (/4 1600)
>[730800.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x506ad30]
>[730800.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x506ad30] width 1600 pitch 6400 (/4 1600)
>[730801.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6862b80]
>[730801.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6862b80] width 1600 pitch 6400 (/4 1600)
>[730801.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11070]
>[730801.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11070] width 1600 pitch 6400 (/4 1600)
>[730801.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25310]
>[730801.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25310] width 1600 pitch 6400 (/4 1600)
>[730991.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a2490]
>[730991.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a2490] width 1600 pitch 6400 (/4 1600)
>[730996.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2514a60]
>[730996.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2514a60] width 1600 pitch 6400 (/4 1600)
>[730996.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x51038f0]
>[730996.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x51038f0] width 1600 pitch 6400 (/4 1600)
>[730997.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921ef0]
>[730997.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921ef0] width 1600 pitch 6400 (/4 1600)
>[731002.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[731002.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[731190.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[731190.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[731237.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3a780]
>[731237.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3a780] width 1600 pitch 6400 (/4 1600)
>[731237.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f0daa0]
>[731237.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f0daa0] width 1600 pitch 6400 (/4 1600)
>[731237.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3a780]
>[731237.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3a780] width 1600 pitch 6400 (/4 1600)
>[731237.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970d90]
>[731238.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970d90] width 1600 pitch 6400 (/4 1600)
>[731463.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591ff10]
>[731463.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591ff10] width 1600 pitch 6400 (/4 1600)
>[731464.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d053e0]
>[731464.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d053e0] width 1600 pitch 6400 (/4 1600)
>[731464.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3a780]
>[731464.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3a780] width 1600 pitch 6400 (/4 1600)
>[731516.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e3a780]
>[731516.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e3a780] width 1600 pitch 6400 (/4 1600)
>[731517.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a451a0]
>[731517.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a451a0] width 1600 pitch 6400 (/4 1600)
>[731517.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4984f80]
>[731517.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4984f80] width 1600 pitch 6400 (/4 1600)
>[731680.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[731680.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[731680.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[731680.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[731680.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[731680.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[731680.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8ae00]
>[731680.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8ae00] width 1600 pitch 6400 (/4 1600)
>[731683.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[731683.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[731744.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5909890]
>[731744.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5909890] width 1600 pitch 6400 (/4 1600)
>[731775.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6867360]
>[731775.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6867360] width 1600 pitch 6400 (/4 1600)
>[731801.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47bf240]
>[731801.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47bf240] width 1600 pitch 6400 (/4 1600)
>[731951.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a840]
>[731951.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a840] width 1600 pitch 6400 (/4 1600)
>[731971.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6823d20]
>[731971.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6823d20] width 1600 pitch 6400 (/4 1600)
>[731972.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a840]
>[731972.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a840] width 1600 pitch 6400 (/4 1600)
>[731972.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[731972.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[732004.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732005.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732005.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732005.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732005.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951150]
>[732005.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951150] width 1600 pitch 6400 (/4 1600)
>[732005.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732005.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732161.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59103e0]
>[732161.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59103e0] width 1600 pitch 6400 (/4 1600)
>[732260.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34d70]
>[732260.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34d70] width 1600 pitch 6400 (/4 1600)
>[732260.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b96050]
>[732260.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b96050] width 1600 pitch 6400 (/4 1600)
>[732260.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d6bb0]
>[732260.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d6bb0] width 1600 pitch 6400 (/4 1600)
>[732261.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1e9e0]
>[732261.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1e9e0] width 1600 pitch 6400 (/4 1600)
>[732261.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748e20]
>[732261.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748e20] width 1600 pitch 6400 (/4 1600)
>[732261.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732262.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732262.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f200]
>[732262.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f200] width 1600 pitch 6400 (/4 1600)
>[732263.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732263.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732263.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732263.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732263.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a2490]
>[732263.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a2490] width 1600 pitch 6400 (/4 1600)
>[732264.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732264.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732265.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732265.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732265.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732265.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732278.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993a40]
>[732278.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993a40] width 1600 pitch 6400 (/4 1600)
>[732278.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993a40]
>[732278.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993a40] width 1600 pitch 6400 (/4 1600)
>[732279.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993a40]
>[732279.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993a40] width 1600 pitch 6400 (/4 1600)
>[732279.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732279.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732280.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732280.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732280.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69939a0]
>[732280.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69939a0] width 1600 pitch 6400 (/4 1600)
>[732280.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732280.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732281.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993a40]
>[732281.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993a40] width 1600 pitch 6400 (/4 1600)
>[732282.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732282.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732283.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732283.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732283.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69939a0]
>[732283.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69939a0] width 1600 pitch 6400 (/4 1600)
>[732284.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6993a40]
>[732284.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6993a40] width 1600 pitch 6400 (/4 1600)
>[732285.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732285.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732285.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5920120]
>[732285.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5920120] width 1600 pitch 6400 (/4 1600)
>[732406.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a840]
>[732406.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a840] width 1600 pitch 6400 (/4 1600)
>[732406.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a840]
>[732406.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a840] width 1600 pitch 6400 (/4 1600)
>[732406.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[732407.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[732407.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e3720]
>[732407.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e3720] width 1600 pitch 6400 (/4 1600)
>[732407.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[732407.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[732407.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732407.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732408.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732408.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732408.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732408.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732408.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880120]
>[732408.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880120] width 1600 pitch 6400 (/4 1600)
>[732409.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880120]
>[732409.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880120] width 1600 pitch 6400 (/4 1600)
>[732409.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2a020]
>[732409.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2a020] width 1600 pitch 6400 (/4 1600)
>[732409.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732409.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732410.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2a020]
>[732410.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2a020] width 1600 pitch 6400 (/4 1600)
>[732410.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ffa0]
>[732410.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ffa0] width 1600 pitch 6400 (/4 1600)
>[732410.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a840]
>[732410.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a840] width 1600 pitch 6400 (/4 1600)
>[732410.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x395d6f0]
>[732410.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x395d6f0] width 1600 pitch 6400 (/4 1600)
>[732411.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ffa0]
>[732411.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ffa0] width 1600 pitch 6400 (/4 1600)
>[732411.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b4610]
>[732411.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b4610] width 1600 pitch 6400 (/4 1600)
>[732411.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ffa0]
>[732411.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ffa0] width 1600 pitch 6400 (/4 1600)
>[732463.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014c80]
>[732463.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014c80] width 1600 pitch 6400 (/4 1600)
>[732463.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ffa0]
>[732463.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ffa0] width 1600 pitch 6400 (/4 1600)
>[732464.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014c80]
>[732464.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014c80] width 1600 pitch 6400 (/4 1600)
>[732464.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ffa0]
>[732464.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ffa0] width 1600 pitch 6400 (/4 1600)
>[732464.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7bf30]
>[732464.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7bf30] width 1600 pitch 6400 (/4 1600)
>[732501.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38de150]
>[732501.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38de150] width 1600 pitch 6400 (/4 1600)
>[732503.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b96010]
>[732503.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b96010] width 1600 pitch 6400 (/4 1600)
>[732503.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014c80]
>[732503.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014c80] width 1600 pitch 6400 (/4 1600)
>[732503.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5014c80]
>[732503.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5014c80] width 1600 pitch 6400 (/4 1600)
>[732520.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6747d60]
>[732520.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6747d60] width 1600 pitch 6400 (/4 1600)
>[732542.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732542.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732584.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f1c0]
>[732584.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f1c0] width 1600 pitch 6400 (/4 1600)
>[732584.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[732584.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[732584.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a253b0]
>[732584.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a253b0] width 1600 pitch 6400 (/4 1600)
>[732584.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f1c0]
>[732584.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f1c0] width 1600 pitch 6400 (/4 1600)
>[732584.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a253b0]
>[732584.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a253b0] width 1600 pitch 6400 (/4 1600)
>[732584.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f1c0]
>[732584.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f1c0] width 1600 pitch 6400 (/4 1600)
>[732584.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a253b0]
>[732584.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a253b0] width 1600 pitch 6400 (/4 1600)
>[732584.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f1c0]
>[732584.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f1c0] width 1600 pitch 6400 (/4 1600)
>[732586.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687d860]
>[732586.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687d860] width 1600 pitch 6400 (/4 1600)
>[732587.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687d860]
>[732587.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687d860] width 1600 pitch 6400 (/4 1600)
>[732588.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8f1c0]
>[732588.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8f1c0] width 1600 pitch 6400 (/4 1600)
>[732588.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687d860]
>[732588.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687d860] width 1600 pitch 6400 (/4 1600)
>[732589.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[732589.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[732589.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a253b0]
>[732589.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a253b0] width 1600 pitch 6400 (/4 1600)
>[732593.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732593.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732598.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732599.072] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732599.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44630]
>[732599.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44630] width 1600 pitch 6400 (/4 1600)
>[732599.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732599.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732599.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732600.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732600.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d73f0]
>[732600.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d73f0] width 1600 pitch 6400 (/4 1600)
>[732600.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732600.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732601.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732601.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732601.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732601.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732601.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732601.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732602.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732602.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732603.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732603.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732603.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732603.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732603.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732603.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732604.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e355c0]
>[732604.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e355c0] width 1600 pitch 6400 (/4 1600)
>[732604.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e355c0]
>[732604.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e355c0] width 1600 pitch 6400 (/4 1600)
>[732605.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4982e00]
>[732605.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4982e00] width 1600 pitch 6400 (/4 1600)
>[732606.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e355c0]
>[732606.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e355c0] width 1600 pitch 6400 (/4 1600)
>[732606.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4982e00]
>[732606.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4982e00] width 1600 pitch 6400 (/4 1600)
>[732606.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ef4bb0]
>[732606.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ef4bb0] width 1600 pitch 6400 (/4 1600)
>[732606.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4780310]
>[732606.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4780310] width 1600 pitch 6400 (/4 1600)
>[732606.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08760]
>[732606.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08760] width 1600 pitch 6400 (/4 1600)
>[732607.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d08760]
>[732607.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d08760] width 1600 pitch 6400 (/4 1600)
>[732608.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732608.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732609.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2a020]
>[732609.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2a020] width 1600 pitch 6400 (/4 1600)
>[732619.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687eab0]
>[732619.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687eab0] width 1600 pitch 6400 (/4 1600)
>[732619.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732619.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732621.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687eab0]
>[732621.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687eab0] width 1600 pitch 6400 (/4 1600)
>[732621.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732621.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732621.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732622.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732623.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732623.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732623.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[732624.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[732624.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732624.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732625.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[732625.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[732625.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732625.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732625.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef3e0]
>[732625.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef3e0] width 1600 pitch 6400 (/4 1600)
>[732627.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcf470]
>[732627.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcf470] width 1600 pitch 6400 (/4 1600)
>[732629.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732629.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732629.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732629.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732629.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef3e0]
>[732629.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef3e0] width 1600 pitch 6400 (/4 1600)
>[732629.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d11640]
>[732629.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d11640] width 1600 pitch 6400 (/4 1600)
>[732629.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811ca0]
>[732629.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811ca0] width 1600 pitch 6400 (/4 1600)
>[732629.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d11640]
>[732629.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d11640] width 1600 pitch 6400 (/4 1600)
>[732630.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c27f0]
>[732630.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c27f0] width 1600 pitch 6400 (/4 1600)
>[732630.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d05d50]
>[732630.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d05d50] width 1600 pitch 6400 (/4 1600)
>[732630.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811ca0]
>[732630.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811ca0] width 1600 pitch 6400 (/4 1600)
>[732630.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[732630.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[732630.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732630.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732630.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732630.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732630.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x595b260]
>[732630.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x595b260] width 1600 pitch 6400 (/4 1600)
>[732630.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732630.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732631.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732632.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732693.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce80]
>[732693.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce80] width 1600 pitch 6400 (/4 1600)
>[732693.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d05d50]
>[732693.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d05d50] width 1600 pitch 6400 (/4 1600)
>[732693.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588af10]
>[732693.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588af10] width 1600 pitch 6400 (/4 1600)
>[732693.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d4790]
>[732693.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d4790] width 1600 pitch 6400 (/4 1600)
>[732696.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34d70]
>[732696.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34d70] width 1600 pitch 6400 (/4 1600)
>[732696.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59205f0]
>[732696.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59205f0] width 1600 pitch 6400 (/4 1600)
>[732708.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732708.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732711.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749060]
>[732712.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749060] width 1600 pitch 6400 (/4 1600)
>[732712.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6876bc0]
>[732712.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6876bc0] width 1600 pitch 6400 (/4 1600)
>[732720.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731350]
>[732720.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731350] width 1600 pitch 6400 (/4 1600)
>[732728.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687bf30]
>[732728.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687bf30] width 1600 pitch 6400 (/4 1600)
>[732728.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[732728.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[732728.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6880120]
>[732728.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6880120] width 1600 pitch 6400 (/4 1600)
>[732728.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee9540]
>[732728.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee9540] width 1600 pitch 6400 (/4 1600)
>[732728.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[732728.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[732728.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2a020]
>[732728.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2a020] width 1600 pitch 6400 (/4 1600)
>[732728.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748e20]
>[732728.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748e20] width 1600 pitch 6400 (/4 1600)
>[732729.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732729.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732729.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732730.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732730.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748e20]
>[732730.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748e20] width 1600 pitch 6400 (/4 1600)
>[732730.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811ca0]
>[732730.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811ca0] width 1600 pitch 6400 (/4 1600)
>[732730.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748e20]
>[732730.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748e20] width 1600 pitch 6400 (/4 1600)
>[732730.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5811ca0]
>[732730.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5811ca0] width 1600 pitch 6400 (/4 1600)
>[732730.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748e20]
>[732730.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748e20] width 1600 pitch 6400 (/4 1600)
>[732749.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732749.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732749.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732750.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732750.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732750.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732750.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732750.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732750.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732750.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732750.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732750.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732750.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732750.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732750.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732750.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732754.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732754.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732754.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732754.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732754.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732754.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732754.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732754.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732754.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732754.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732754.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732754.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732754.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732754.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732754.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732754.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732763.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732763.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732763.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732763.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732763.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732763.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732763.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732763.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732763.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732763.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732763.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732763.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732763.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732763.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732763.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732763.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732767.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732767.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732767.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732767.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732767.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732767.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732767.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732767.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732767.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732767.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732767.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732767.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732767.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732767.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732800.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732800.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732800.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee9540]
>[732800.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee9540] width 1600 pitch 6400 (/4 1600)
>[732800.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732800.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732800.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee9540]
>[732800.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee9540] width 1600 pitch 6400 (/4 1600)
>[732800.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732800.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732800.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee9540]
>[732800.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee9540] width 1600 pitch 6400 (/4 1600)
>[732800.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732800.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732804.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732805.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732805.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732805.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732805.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732805.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732805.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732805.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732805.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732805.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732805.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732805.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732805.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673fbb0]
>[732805.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673fbb0] width 1600 pitch 6400 (/4 1600)
>[732805.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732805.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732806.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d87c0]
>[732806.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d87c0] width 1600 pitch 6400 (/4 1600)
>[732806.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5ee9540]
>[732806.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5ee9540] width 1600 pitch 6400 (/4 1600)
>[732807.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732807.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732807.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[732807.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[732808.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732808.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732810.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40d3b20]
>[732810.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40d3b20] width 1600 pitch 6400 (/4 1600)
>[732810.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732810.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732825.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8b8a0]
>[732825.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8b8a0] width 1600 pitch 6400 (/4 1600)
>[732826.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951010]
>[732826.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951010] width 1600 pitch 6400 (/4 1600)
>[732827.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8b8a0]
>[732827.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8b8a0] width 1600 pitch 6400 (/4 1600)
>[732827.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8b8a0]
>[732827.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8b8a0] width 1600 pitch 6400 (/4 1600)
>[732827.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732828.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732828.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732828.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732828.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732828.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732828.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44630]
>[732828.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44630] width 1600 pitch 6400 (/4 1600)
>[732829.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732829.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732829.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[732829.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[732829.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8b8a0]
>[732830.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8b8a0] width 1600 pitch 6400 (/4 1600)
>[732830.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[732830.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[732830.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44630]
>[732830.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44630] width 1600 pitch 6400 (/4 1600)
>[732831.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c60]
>[732831.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c60] width 1600 pitch 6400 (/4 1600)
>[732833.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732834.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732834.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[732834.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[732855.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a46830]
>[732855.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a46830] width 1600 pitch 6400 (/4 1600)
>[732855.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732855.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732856.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732856.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732856.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732856.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732858.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22b00]
>[732858.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22b00] width 1600 pitch 6400 (/4 1600)
>[732859.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403c390]
>[732859.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403c390] width 1600 pitch 6400 (/4 1600)
>[732860.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d05d50]
>[732860.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d05d50] width 1600 pitch 6400 (/4 1600)
>[732860.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732860.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732892.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732892.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732892.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732892.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732892.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732892.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732892.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732892.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732892.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732892.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732892.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732892.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732892.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732892.423] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732892.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732892.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732896.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024070]
>[732896.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024070] width 1600 pitch 6400 (/4 1600)
>[732896.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22b00]
>[732896.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22b00] width 1600 pitch 6400 (/4 1600)
>[732896.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024070]
>[732896.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024070] width 1600 pitch 6400 (/4 1600)
>[732896.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22b00]
>[732896.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22b00] width 1600 pitch 6400 (/4 1600)
>[732896.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024070]
>[732896.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024070] width 1600 pitch 6400 (/4 1600)
>[732896.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22b00]
>[732896.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22b00] width 1600 pitch 6400 (/4 1600)
>[732896.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3024070]
>[732896.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3024070] width 1600 pitch 6400 (/4 1600)
>[732896.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b22b00]
>[732896.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b22b00] width 1600 pitch 6400 (/4 1600)
>[732933.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732933.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732933.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732933.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732933.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732933.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732933.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732934.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732934.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732934.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732934.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732934.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732938.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67337b0]
>[732938.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67337b0] width 1600 pitch 6400 (/4 1600)
>[732938.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732938.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732938.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ec650]
>[732938.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ec650] width 1600 pitch 6400 (/4 1600)
>[732938.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732938.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732938.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732938.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732938.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732938.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732938.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732938.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732940.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732940.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732940.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[732940.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[732940.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732940.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732940.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[732940.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[732940.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732940.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732940.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[732940.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[732940.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f22d0]
>[732940.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f22d0] width 1600 pitch 6400 (/4 1600)
>[732940.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[732940.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[732944.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732944.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732944.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732944.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732944.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732944.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732944.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1dc40]
>[732944.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1dc40] width 1600 pitch 6400 (/4 1600)
>[732944.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732944.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732950.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860a90]
>[732950.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860a90] width 1600 pitch 6400 (/4 1600)
>[732950.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ec650]
>[732950.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ec650] width 1600 pitch 6400 (/4 1600)
>[732950.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732950.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732950.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40ddc60]
>[732951.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40ddc60] width 1600 pitch 6400 (/4 1600)
>[732951.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732951.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732951.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860a90]
>[732951.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860a90] width 1600 pitch 6400 (/4 1600)
>[732955.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865040]
>[732955.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865040] width 1600 pitch 6400 (/4 1600)
>[732955.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732955.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732955.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732955.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732955.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5a90]
>[732955.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5a90] width 1600 pitch 6400 (/4 1600)
>[732955.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c054e0]
>[732955.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c054e0] width 1600 pitch 6400 (/4 1600)
>[732964.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732964.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732964.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732964.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732964.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04670]
>[732964.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04670] width 1600 pitch 6400 (/4 1600)
>[732964.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67337b0]
>[732964.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67337b0] width 1600 pitch 6400 (/4 1600)
>[732964.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ec650]
>[732964.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ec650] width 1600 pitch 6400 (/4 1600)
>[732964.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67337b0]
>[732964.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67337b0] width 1600 pitch 6400 (/4 1600)
>[732968.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860a90]
>[732968.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860a90] width 1600 pitch 6400 (/4 1600)
>[732968.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733a60]
>[732968.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733a60] width 1600 pitch 6400 (/4 1600)
>[732968.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732968.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732968.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67337b0]
>[732968.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67337b0] width 1600 pitch 6400 (/4 1600)
>[732968.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b67510]
>[732968.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b67510] width 1600 pitch 6400 (/4 1600)
>[732968.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732968.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732972.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732973.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732973.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ec650]
>[732973.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ec650] width 1600 pitch 6400 (/4 1600)
>[732973.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5860a90]
>[732973.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5860a90] width 1600 pitch 6400 (/4 1600)
>[732973.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[732973.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[732973.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b1f0]
>[732973.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b1f0] width 1600 pitch 6400 (/4 1600)
>[732973.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2b500]
>[732973.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2b500] width 1600 pitch 6400 (/4 1600)
>[732973.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b1f0]
>[732973.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b1f0] width 1600 pitch 6400 (/4 1600)
>[732975.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732975.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732975.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732975.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732975.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732975.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732975.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732975.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732975.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732975.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732975.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732975.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732975.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d2e0]
>[732975.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d2e0] width 1600 pitch 6400 (/4 1600)
>[732975.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732975.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732979.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732979.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732979.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732979.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732979.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732979.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732979.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732979.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732979.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732979.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732979.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732979.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[732979.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ef7fc0]
>[732979.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ef7fc0] width 1600 pitch 6400 (/4 1600)
>[732979.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674d090]
>[732979.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674d090] width 1600 pitch 6400 (/4 1600)
>[733045.430] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[733045.430] (II) RADEON(0): Printing DDC gathered Modelines:
>[733045.430] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[733045.430] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[733045.847] (II) RADEON(0): Allocate new frame buffer 1920x1080 stride 1920
>[733045.950] (II) RADEON(0): VRAM usage limit set to 221119K
>[733050.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ab9c0]
>[733050.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ab9c0] width 1920 pitch 7680 (/4 1920)
>[733064.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4972d60]
>[733064.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4972d60] width 1920 pitch 7680 (/4 1920)
>[733068.276] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event6)
>[733068.419] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[733068.419] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[733068.419] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[733068.419] 	Option "XkbRules" "evdev"
>[733068.419] 	Option "XkbModel" "pc105+inet"
>[733068.419] 	Option "XkbLayout" "us"
>[733068.419] 	Option "_source" "server/udev"
>[733068.419] 	Option "name" "USB USB Keykoard"
>[733068.419] 	Option "path" "/dev/input/event6"
>[733068.419] 	Option "device" "/dev/input/event6"
>[733068.419] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input40/event6"
>[733068.419] 	Option "driver" "evdev"
>[733068.419] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[733068.419] (**) USB USB Keykoard: always reports core events
>[733068.419] (**) evdev: USB USB Keykoard: Device: "/dev/input/event6"
>[733068.419] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[733068.419] (--) evdev: USB USB Keykoard: Found keys
>[733068.419] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[733068.419] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input40/event6"
>[733068.419] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 9)
>[733068.419] (**) Option "xkb_rules" "evdev"
>[733068.419] (**) Option "xkb_model" "pc105+inet"
>[733068.419] (**) Option "xkb_layout" "us"
>[733068.419] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[733068.419] (II) XKB: Reusing cached keymap
>[733068.422] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse2)
>[733068.422] (II) No input driver specified, ignoring this device.
>[733068.422] (II) This device may have been added with another device file.
>[733068.423] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event7)
>[733068.423] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[733068.423] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[733068.423] 	Option "XkbRules" "evdev"
>[733068.423] 	Option "XkbModel" "evdev"
>[733068.423] 	Option "XkbLayout" "us"
>[733068.423] 	Option "_source" "server/udev"
>[733068.423] 	Option "name" "Logitech USB Optical Mouse"
>[733068.423] 	Option "path" "/dev/input/event7"
>[733068.423] 	Option "device" "/dev/input/event7"
>[733068.423] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input41/event7"
>[733068.423] 	Option "driver" "evdev"
>[733068.423] (**) Logitech USB Optical Mouse: always reports core events
>[733068.423] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event7"
>[733068.423] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[733068.423] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[733068.423] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[733068.423] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[733068.423] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[733068.423] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[733068.423] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[733068.423] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[733068.423] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[733068.423] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input41/event7"
>[733068.423] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 10)
>[733068.485] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[733068.486] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[733068.486] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[733068.486] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[733068.486] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[733069.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f6fff0]
>[733069.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f6fff0] width 1920 pitch 7680 (/4 1920)
>[733070.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5949d70]
>[733070.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5949d70] width 1920 pitch 7680 (/4 1920)
>[733303.225] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[733303.225] (II) RADEON(0): Printing DDC gathered Modelines:
>[733303.225] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[733303.225] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[733393.786] (II) RADEON(0): RADEONSaveScreen(2)
>[733393.791] (II) RADEON(0): RADEONSaveScreen(0)
>[775945.081] (II) RADEON(0): RADEONSaveScreen(1)
>[775951.454] (II) config/udev: removing device USB USB Keykoard
>[775951.454] (II) evdev: USB USB Keykoard: Close
>[775951.597] (II) UnloadModule: "evdev"
>[775951.999] (II) config/udev: removing device Logitech USB Optical Mouse
>[775951.999] (II) evdev: Logitech USB Optical Mouse: Close
>[775951.999] (II) UnloadModule: "evdev"
>[775952.600] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event6)
>[775952.600] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[775952.600] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[775952.600] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[775952.600] 	Option "XkbRules" "evdev"
>[775952.600] 	Option "XkbModel" "pc105+inet"
>[775952.600] 	Option "XkbLayout" "us"
>[775952.600] 	Option "_source" "server/udev"
>[775952.600] 	Option "name" "USB USB Keykoard"
>[775952.600] 	Option "path" "/dev/input/event6"
>[775952.600] 	Option "device" "/dev/input/event6"
>[775952.600] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input42/event6"
>[775952.600] 	Option "driver" "evdev"
>[775952.600] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[775952.600] (**) USB USB Keykoard: always reports core events
>[775952.600] (**) evdev: USB USB Keykoard: Device: "/dev/input/event6"
>[775952.600] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[775952.600] (--) evdev: USB USB Keykoard: Found keys
>[775952.600] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[775952.600] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input42/event6"
>[775952.600] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 9)
>[775952.600] (**) Option "xkb_rules" "evdev"
>[775952.600] (**) Option "xkb_model" "pc105+inet"
>[775952.600] (**) Option "xkb_layout" "us"
>[775952.600] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[775952.600] (II) XKB: Reusing cached keymap
>[775952.625] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event8)
>[775952.625] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[775952.625] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[775952.625] 	Option "XkbRules" "evdev"
>[775952.625] 	Option "XkbModel" "evdev"
>[775952.625] 	Option "XkbLayout" "us"
>[775952.625] 	Option "_source" "server/udev"
>[775952.625] 	Option "name" "Logitech USB Optical Mouse"
>[775952.625] 	Option "path" "/dev/input/event8"
>[775952.625] 	Option "device" "/dev/input/event8"
>[775952.625] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input44/event8"
>[775952.625] 	Option "driver" "evdev"
>[775952.625] (**) Logitech USB Optical Mouse: always reports core events
>[775952.625] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event8"
>[775952.625] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[775952.625] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[775952.625] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[775952.625] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[775952.625] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[775952.625] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[775952.625] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[775952.625] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[775952.625] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[775952.625] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input44/event8"
>[775952.625] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 10)
>[775952.626] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[775952.626] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[775952.626] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[775952.626] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[775952.626] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[775952.627] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse2)
>[775952.627] (II) No input driver specified, ignoring this device.
>[775952.627] (II) This device may have been added with another device file.
>[775952.636] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event7)
>[775952.636] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[775952.636] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[775952.636] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[775952.636] 	Option "XkbRules" "evdev"
>[775952.636] 	Option "XkbModel" "pc105+inet"
>[775952.636] 	Option "XkbLayout" "us"
>[775952.636] 	Option "_source" "server/udev"
>[775952.636] 	Option "name" "USB USB Keykoard"
>[775952.636] 	Option "path" "/dev/input/event7"
>[775952.636] 	Option "device" "/dev/input/event7"
>[775952.636] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input43/event7"
>[775952.636] 	Option "driver" "evdev"
>[775952.636] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[775952.636] (**) USB USB Keykoard: always reports core events
>[775952.636] (**) evdev: USB USB Keykoard: Device: "/dev/input/event7"
>[775952.636] (--) evdev: USB USB Keykoard: absolute axis 0x20 [572..0]
>[775952.636] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[775952.636] (--) evdev: USB USB Keykoard: Found 1 mouse buttons
>[775952.636] (--) evdev: USB USB Keykoard: Found scroll wheel(s)
>[775952.636] (--) evdev: USB USB Keykoard: Found relative axes
>[775952.636] (II) evdev: USB USB Keykoard: Forcing relative x/y axes to exist.
>[775952.636] (--) evdev: USB USB Keykoard: Found absolute axes
>[775952.636] (II) evdev: USB USB Keykoard: Forcing absolute x/y axes to exist.
>[775952.636] (--) evdev: USB USB Keykoard: Found keys
>[775952.636] (II) evdev: USB USB Keykoard: Configuring as mouse
>[775952.636] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[775952.636] (II) evdev: USB USB Keykoard: Adding scrollwheel support
>[775952.636] (**) evdev: USB USB Keykoard: YAxisMapping: buttons 4 and 5
>[775952.636] (**) evdev: USB USB Keykoard: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[775952.637] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.1/input/input43/event7"
>[775952.637] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 11)
>[775952.637] (**) Option "xkb_rules" "evdev"
>[775952.637] (**) Option "xkb_model" "pc105+inet"
>[775952.637] (**) Option "xkb_layout" "us"
>[775952.637] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[775952.637] (II) XKB: Reusing cached keymap
>[775952.637] (II) evdev: USB USB Keykoard: initialized for relative axes.
>[775952.637] (WW) evdev: USB USB Keykoard: ignoring absolute axes.
>[775952.637] (**) USB USB Keykoard: (accel) keeping acceleration scheme 1
>[775952.637] (**) USB USB Keykoard: (accel) acceleration profile 0
>[775952.637] (**) USB USB Keykoard: (accel) acceleration factor: 2.000
>[775952.637] (**) USB USB Keykoard: (accel) acceleration threshold: 4
>[775955.048] (II) config/udev: removing device USB USB Keykoard
>[775955.048] (II) evdev: USB USB Keykoard: Close
>[775955.049] (II) UnloadModule: "evdev"
>[775955.067] (II) config/udev: removing device USB USB Keykoard
>[775955.071] (II) evdev: USB USB Keykoard: Close
>[775955.072] (II) UnloadModule: "evdev"
>[775955.089] (II) config/udev: removing device Logitech USB Optical Mouse
>[775955.090] (II) evdev: Logitech USB Optical Mouse: Close
>[775955.090] (II) UnloadModule: "evdev"
>[776016.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cdf0]
>[776016.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cdf0] width 1920 pitch 7680 (/4 1920)
>[776016.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b68e0]
>[776016.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b68e0] width 1920 pitch 7680 (/4 1920)
>[776016.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a46770]
>[776016.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a46770] width 1920 pitch 7680 (/4 1920)
>[776016.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1340]
>[776016.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1340] width 1920 pitch 7680 (/4 1920)
>[776016.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x685f5c0]
>[776016.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x685f5c0] width 1920 pitch 7680 (/4 1920)
>[776016.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865400]
>[776016.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865400] width 1920 pitch 7680 (/4 1920)
>[776016.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cdf0]
>[776016.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cdf0] width 1920 pitch 7680 (/4 1920)
>[776016.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776017.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1920 pitch 7680 (/4 1920)
>[776017.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b68e0]
>[776017.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b68e0] width 1920 pitch 7680 (/4 1920)
>[776017.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a46770]
>[776017.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a46770] width 1920 pitch 7680 (/4 1920)
>[776017.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1340]
>[776017.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1340] width 1920 pitch 7680 (/4 1920)
>[776017.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x685f5c0]
>[776017.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x685f5c0] width 1920 pitch 7680 (/4 1920)
>[776017.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865400]
>[776017.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865400] width 1920 pitch 7680 (/4 1920)
>[776017.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cdf0]
>[776017.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cdf0] width 1920 pitch 7680 (/4 1920)
>[776017.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776017.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1920 pitch 7680 (/4 1920)
>[776017.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b68e0]
>[776017.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b68e0] width 1920 pitch 7680 (/4 1920)
>[776017.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a46770]
>[776017.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a46770] width 1920 pitch 7680 (/4 1920)
>[776017.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x685f5c0]
>[776017.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x685f5c0] width 1920 pitch 7680 (/4 1920)
>[776017.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865400]
>[776017.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865400] width 1920 pitch 7680 (/4 1920)
>[776024.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776024.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1920 pitch 7680 (/4 1920)
>[776024.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6865400]
>[776024.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6865400] width 1920 pitch 7680 (/4 1920)
>[776025.319] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[776025.320] (II) RADEON(0): VRAM usage limit set to 223324K
>[776028.860] [mi] EQ overflowing.  Additional events will be discarded until existing events are processed.
>[776028.867] 
>[776028.867] Backtrace:
>[776029.134] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[776029.134] 1: /usr/bin/Xorg (mieqEnqueue+0x26b) [0x55155b]
>[776029.134] 2: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22]
>[776029.134] 3: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900f0]
>[776029.150] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x5085) [0x7f6753ed1085]
>[776029.150] 5: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[776029.150] 6: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[776029.150] 7: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[776029.150] 8: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[776029.150] 9: /usr/bin/Xorg (0x400000+0x6ac20) [0x46ac20]
>[776029.150] 10: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[776029.150] 11: /lib64/libc.so.6 (0x3171e00000+0x144a4b) [0x3171f44a4b]
>[776029.150] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc7d) [0x7f6754826c7d]
>[776029.150] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[776029.150] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x806a) [0x7f6753b0b06a]
>[776029.150] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5021) [0x7f6753b08021]
>[776029.150] 16: /usr/bin/Xorg (0x400000+0xc9abf) [0x4c9abf]
>[776029.150] 17: /usr/bin/Xorg (ChangeWindowAttributes+0x279) [0x4601a9]
>[776029.150] 18: /usr/bin/Xorg (0x400000+0x2e97d) [0x42e97d]
>[776029.150] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[776029.150] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[776029.150] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[776029.150] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[776029.150] 
>[776029.150] [mi] These backtraces from mieqEnqueue may point to a culprit higher up the stack.
>[776029.150] [mi] mieq is *NOT* the cause.  It is a victim.
>[776029.888] [mi] EQ overflow continuing.  100 events have been dropped.
>[776029.888] 
>[776029.888] Backtrace:
>[776029.888] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[776029.888] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22]
>[776029.888] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900f0]
>[776029.888] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x5085) [0x7f6753ed1085]
>[776029.888] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[776029.888] 5: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[776029.888] 6: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[776029.888] 7: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[776029.888] 8: /usr/bin/Xorg (0x400000+0x6ac20) [0x46ac20]
>[776029.888] 9: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[776029.888] 10: /lib64/libc.so.6 (0x3171e00000+0x144a4b) [0x3171f44a4b]
>[776029.888] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc7d) [0x7f6754826c7d]
>[776029.888] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[776029.888] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x806a) [0x7f6753b0b06a]
>[776029.888] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5021) [0x7f6753b08021]
>[776029.888] 15: /usr/bin/Xorg (0x400000+0xc9abf) [0x4c9abf]
>[776029.888] 16: /usr/bin/Xorg (ChangeWindowAttributes+0x279) [0x4601a9]
>[776029.888] 17: /usr/bin/Xorg (0x400000+0x2e97d) [0x42e97d]
>[776029.888] 18: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[776029.888] 19: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[776029.888] 20: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[776029.888] 21: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[776029.888] 
>[776031.099] [mi] EQ overflow continuing.  200 events have been dropped.
>[776031.099] 
>[776031.099] Backtrace:
>[776031.099] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[776031.099] 1: /usr/bin/Xorg (0x400000+0x47f22) [0x447f22]
>[776031.099] 2: /usr/bin/Xorg (xf86PostMotionEvent+0xd0) [0x4900f0]
>[776031.099] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x5085) [0x7f6753ed1085]
>[776031.099] 4: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[776031.099] 5: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[776031.099] 6: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[776031.099] 7: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[776031.099] 8: /lib64/libc.so.6 (0x3171e00000+0x144a4b) [0x3171f44a4b]
>[776031.099] 9: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc7d) [0x7f6754826c7d]
>[776031.099] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[776031.099] 11: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x806a) [0x7f6753b0b06a]
>[776031.099] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5021) [0x7f6753b08021]
>[776031.099] 13: /usr/bin/Xorg (0x400000+0xc9abf) [0x4c9abf]
>[776031.099] 14: /usr/bin/Xorg (ChangeWindowAttributes+0x279) [0x4601a9]
>[776031.099] 15: /usr/bin/Xorg (0x400000+0x2e97d) [0x42e97d]
>[776031.099] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[776031.099] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[776031.099] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[776031.099] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[776031.099] 
>[776031.671] [mi] Increasing EQ size to 512 to prevent dropped events.
>[776031.682] [mi] EQ processing has resumed after 223 dropped events.
>[776031.682] [mi] This may be caused my a misbehaving driver monopolizing the server's resources.
>[776031.783] (II) AIGLX: Suspending AIGLX clients for VT switch
>[776031.783] (II) RADEON(0): RADEONLeaveVT_KMS
>[776031.783] (II) RADEON(0): Ok, leaving now...
>[776040.219] (II) AIGLX: Resuming AIGLX clients after VT switch
>[776040.281] (II) RADEON(0): RADEONEnterVT_KMS
>[776041.215] (II) RADEON(0): RADEONSaveScreen(2)
>[776041.619] (**) Option "Device" "/dev/input/event5"
>[776041.619] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[776066.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977a60]
>[776066.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977a60] width 1600 pitch 6400 (/4 1600)
>[776066.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[776066.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1600 pitch 6400 (/4 1600)
>[776066.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776066.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776066.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x491fa70]
>[776066.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x491fa70] width 1600 pitch 6400 (/4 1600)
>[776066.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[776066.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1600 pitch 6400 (/4 1600)
>[776066.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6868960]
>[776066.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6868960] width 1600 pitch 6400 (/4 1600)
>[776066.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c1c0]
>[776066.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c1c0] width 1600 pitch 6400 (/4 1600)
>[776068.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977a60]
>[776068.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977a60] width 1600 pitch 6400 (/4 1600)
>[776070.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977a60]
>[776070.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977a60] width 1600 pitch 6400 (/4 1600)
>[776070.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776070.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776070.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f0f560]
>[776070.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f0f560] width 1600 pitch 6400 (/4 1600)
>[776071.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776071.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[776074.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977410]
>[776074.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977410] width 1600 pitch 6400 (/4 1600)
>[776075.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776075.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776075.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x491fa70]
>[776075.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x491fa70] width 1600 pitch 6400 (/4 1600)
>[776078.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x491fa70]
>[776078.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x491fa70] width 1600 pitch 6400 (/4 1600)
>[776079.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[776079.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[776080.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776080.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776080.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b67510]
>[776080.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b67510] width 1600 pitch 6400 (/4 1600)
>[776081.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776081.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[776081.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[776081.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[776082.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f94d0]
>[776082.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f94d0] width 1600 pitch 6400 (/4 1600)
>[776082.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591fae0]
>[776082.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591fae0] width 1600 pitch 6400 (/4 1600)
>[776083.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e28a90]
>[776083.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e28a90] width 1600 pitch 6400 (/4 1600)
>[776085.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8c2c0]
>[776085.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8c2c0] width 1600 pitch 6400 (/4 1600)
>[776087.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47888b0]
>[776087.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47888b0] width 1600 pitch 6400 (/4 1600)
>[776088.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28519d0]
>[776088.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28519d0] width 1600 pitch 6400 (/4 1600)
>[776091.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776091.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776091.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776091.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776091.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776092.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776092.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776092.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776094.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776094.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776094.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776094.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776094.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776094.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776095.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776095.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776095.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776095.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776097.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776097.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776097.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776097.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776098.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776098.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776098.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[776098.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[776098.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776098.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776099.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[776099.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[776099.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776099.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776099.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[776099.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[776099.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[776099.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[776099.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[776100.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[776100.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[776100.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[776100.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[776100.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[776100.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[776100.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[776100.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[776100.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[776102.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[776102.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[776102.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39fbec0]
>[776102.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39fbec0] width 1600 pitch 6400 (/4 1600)
>[776102.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[776102.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[776102.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ac010]
>[776102.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ac010] width 1600 pitch 6400 (/4 1600)
>[776102.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996520]
>[776102.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996520] width 1600 pitch 6400 (/4 1600)
>[776104.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[776104.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[776104.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[776104.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[776105.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b67510]
>[776105.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b67510] width 1600 pitch 6400 (/4 1600)
>[776105.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977a60]
>[776105.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977a60] width 1600 pitch 6400 (/4 1600)
>[776106.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[776106.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[776106.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[776106.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[776298.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[776298.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[776299.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d3f0]
>[776299.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d3f0] width 1600 pitch 6400 (/4 1600)
>[776299.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c60]
>[776299.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c60] width 1600 pitch 6400 (/4 1600)
>[776299.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d3f0]
>[776299.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d3f0] width 1600 pitch 6400 (/4 1600)
>[776300.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[776300.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[776300.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[776300.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[776300.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977a60]
>[776300.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977a60] width 1600 pitch 6400 (/4 1600)
>[776301.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[776301.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[776301.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776301.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[776302.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c60]
>[776302.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c60] width 1600 pitch 6400 (/4 1600)
>[776302.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3940]
>[776302.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3940] width 1600 pitch 6400 (/4 1600)
>[776303.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[776303.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[776304.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776304.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[776304.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[776304.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[776304.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[776304.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[776304.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[776304.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[776305.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[776305.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[776305.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[776305.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[776306.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[776306.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[776309.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776309.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776310.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[776310.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[776310.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776310.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776311.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[776311.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[776311.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776311.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776312.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[776312.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[776314.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776314.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776314.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[776314.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[776315.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[776315.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[776316.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[776316.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[776316.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[776317.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[776443.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[776443.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[776459.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[776459.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[776459.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[776459.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[776459.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[776459.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[776459.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[776459.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[776459.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[776459.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[776459.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[776459.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[776459.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[776459.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[776459.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[776459.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[776466.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4875450]
>[776466.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4875450] width 1600 pitch 6400 (/4 1600)
>[776466.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[776466.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[776466.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[776466.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[776466.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[776466.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[776466.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[776466.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[776466.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[776466.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[776466.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[776466.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[776466.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[776466.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[776466.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[776466.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[776747.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2dc90]
>[776747.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2dc90] width 1600 pitch 6400 (/4 1600)
>[776781.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496ff40]
>[776781.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496ff40] width 1600 pitch 6400 (/4 1600)
>[776923.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f8ea80]
>[776923.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f8ea80] width 1600 pitch 6400 (/4 1600)
>[777097.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591fa10]
>[777097.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591fa10] width 1600 pitch 6400 (/4 1600)
>[777323.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d3940]
>[777323.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d3940] width 1600 pitch 6400 (/4 1600)
>[777331.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[777331.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[777332.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[777332.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[777332.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3eb0]
>[777332.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3eb0] width 1600 pitch 6400 (/4 1600)
>[777332.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777332.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777332.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[777332.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[777332.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[777332.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[777332.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777332.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777394.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b52e80]
>[777394.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b52e80] width 1600 pitch 6400 (/4 1600)
>[777399.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[777399.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[777399.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[777399.145] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[777399.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777399.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777399.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[777399.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[777399.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c60]
>[777399.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c60] width 1600 pitch 6400 (/4 1600)
>[777399.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0cd30]
>[777399.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0cd30] width 1600 pitch 6400 (/4 1600)
>[777402.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[777402.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[777402.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[777402.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[777402.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[777402.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[777402.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777402.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777402.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[777402.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[777402.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777402.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777402.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[777402.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[777402.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[777402.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[777402.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[777402.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[777440.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd4c0]
>[777440.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd4c0] width 1600 pitch 6400 (/4 1600)
>[777450.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[777450.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[777450.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[777450.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[777450.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[777450.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[777450.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[777450.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[777450.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[777450.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[777450.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[777450.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[777450.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[777450.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[777451.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[777451.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[777451.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[777451.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[777451.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777451.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777451.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777451.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777451.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cee570]
>[777451.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cee570] width 1600 pitch 6400 (/4 1600)
>[777451.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[777451.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[777451.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[777451.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[777451.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[777451.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[777610.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777610.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777610.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49700b0]
>[777610.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49700b0] width 1600 pitch 6400 (/4 1600)
>[777611.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777611.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777611.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49700b0]
>[777611.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49700b0] width 1600 pitch 6400 (/4 1600)
>[777647.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f770]
>[777647.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f770] width 1600 pitch 6400 (/4 1600)
>[777664.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4970430]
>[777664.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4970430] width 1600 pitch 6400 (/4 1600)
>[777666.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777666.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777666.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[777666.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[777666.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777666.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777666.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[777666.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[777666.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[777666.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[777666.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[777666.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[777670.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[777670.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[777670.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4041590]
>[777670.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4041590] width 1600 pitch 6400 (/4 1600)
>[777670.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777670.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777670.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[777670.483] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[777670.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777670.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777670.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[777670.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[777670.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777670.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777670.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777670.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777670.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[777670.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[777720.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580ee10]
>[777720.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580ee10] width 1600 pitch 6400 (/4 1600)
>[777724.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f1e20]
>[777724.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f1e20] width 1600 pitch 6400 (/4 1600)
>[777808.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bec080]
>[777808.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bec080] width 1600 pitch 6400 (/4 1600)
>[777811.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777811.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777811.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[777811.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[777811.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[777811.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[777811.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b0cd30]
>[777811.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b0cd30] width 1600 pitch 6400 (/4 1600)
>[777811.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58098b0]
>[777811.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58098b0] width 1600 pitch 6400 (/4 1600)
>[777811.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[777811.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[777811.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777811.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777823.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[777823.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[777823.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777823.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777823.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777823.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777823.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777823.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777823.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777823.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777823.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777823.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777823.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777823.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777823.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[777823.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[777837.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b533a0]
>[777837.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b533a0] width 1600 pitch 6400 (/4 1600)
>[777851.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[777851.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[777851.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[777851.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[777851.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[777851.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[777851.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[777851.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[777851.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777851.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777851.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[777851.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[777851.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[777851.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[777868.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777868.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777868.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[777869.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[777869.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777869.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777869.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[777869.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[777869.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777869.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777869.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[777869.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[777869.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777869.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777869.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[777869.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[777869.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[777869.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[777997.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d5f10]
>[777997.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d5f10] width 1600 pitch 6400 (/4 1600)
>[778065.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d069e0]
>[778065.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d069e0] width 1600 pitch 6400 (/4 1600)
>[778076.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c25d0]
>[778076.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c25d0] width 1600 pitch 6400 (/4 1600)
>[778078.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cee570]
>[778078.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cee570] width 1600 pitch 6400 (/4 1600)
>[778078.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[778078.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[778078.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[778078.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[778078.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[778078.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[778078.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778078.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778078.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778078.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778078.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778078.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778094.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778094.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778094.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778094.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778094.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778094.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778094.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778094.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778094.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778094.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778094.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778094.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778094.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778094.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778094.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778101.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f245f0]
>[778101.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f245f0] width 1600 pitch 6400 (/4 1600)
>[778239.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5889970]
>[778239.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5889970] width 1600 pitch 6400 (/4 1600)
>[778243.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67312d0]
>[778244.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67312d0] width 1600 pitch 6400 (/4 1600)
>[778244.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[778244.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[778245.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[778245.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[778245.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[778245.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[778246.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951a30]
>[778246.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951a30] width 1600 pitch 6400 (/4 1600)
>[778246.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9dd80]
>[778246.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9dd80] width 1600 pitch 6400 (/4 1600)
>[778246.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951a30]
>[778246.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951a30] width 1600 pitch 6400 (/4 1600)
>[778247.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d8270]
>[778248.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d8270] width 1600 pitch 6400 (/4 1600)
>[778248.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672cb70]
>[778248.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672cb70] width 1600 pitch 6400 (/4 1600)
>[778248.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[778248.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[778248.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672cb70]
>[778249.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672cb70] width 1600 pitch 6400 (/4 1600)
>[778249.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672cb70]
>[778249.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672cb70] width 1600 pitch 6400 (/4 1600)
>[778249.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672cb70]
>[778249.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672cb70] width 1600 pitch 6400 (/4 1600)
>[778250.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f800]
>[778250.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f800] width 1600 pitch 6400 (/4 1600)
>[778250.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f381d0]
>[778250.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f381d0] width 1600 pitch 6400 (/4 1600)
>[778250.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2dde0]
>[778250.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2dde0] width 1600 pitch 6400 (/4 1600)
>[778251.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49533c0]
>[778251.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49533c0] width 1600 pitch 6400 (/4 1600)
>[778251.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d8240]
>[778251.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d8240] width 1600 pitch 6400 (/4 1600)
>[778251.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f381d0]
>[778251.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f381d0] width 1600 pitch 6400 (/4 1600)
>[778252.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f381d0]
>[778252.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f381d0] width 1600 pitch 6400 (/4 1600)
>[778252.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58831a0]
>[778252.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58831a0] width 1600 pitch 6400 (/4 1600)
>[778253.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f381d0]
>[778253.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f381d0] width 1600 pitch 6400 (/4 1600)
>[778253.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883300]
>[778253.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883300] width 1600 pitch 6400 (/4 1600)
>[778255.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f400]
>[778255.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f400] width 1600 pitch 6400 (/4 1600)
>[778255.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[778255.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[778255.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e4f260]
>[778255.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e4f260] width 1600 pitch 6400 (/4 1600)
>[778256.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f1b10]
>[778256.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f1b10] width 1600 pitch 6400 (/4 1600)
>[778258.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778258.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778259.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778259.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778260.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[778260.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[778260.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b338b0]
>[778260.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b338b0] width 1600 pitch 6400 (/4 1600)
>[778322.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f33f30]
>[778322.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f33f30] width 1600 pitch 6400 (/4 1600)
>[778323.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f33f30]
>[778323.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f33f30] width 1600 pitch 6400 (/4 1600)
>[778323.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496dd10]
>[778323.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496dd10] width 1600 pitch 6400 (/4 1600)
>[778324.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778324.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778324.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496dd10]
>[778324.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496dd10] width 1600 pitch 6400 (/4 1600)
>[778324.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778325.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778325.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778325.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778325.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a1940]
>[778325.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a1940] width 1600 pitch 6400 (/4 1600)
>[778328.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778328.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778328.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f00]
>[778328.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f00] width 1600 pitch 6400 (/4 1600)
>[778328.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65f0]
>[778328.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65f0] width 1600 pitch 6400 (/4 1600)
>[778328.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f00]
>[778328.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f00] width 1600 pitch 6400 (/4 1600)
>[778330.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996c80]
>[778330.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996c80] width 1600 pitch 6400 (/4 1600)
>[778358.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cee570]
>[778358.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cee570] width 1600 pitch 6400 (/4 1600)
>[778358.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[778358.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[778359.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[778359.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[778359.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778359.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778359.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[778360.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[778360.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f00]
>[778360.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f00] width 1600 pitch 6400 (/4 1600)
>[778360.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778360.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778442.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778442.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778442.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4976c70]
>[778442.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4976c70] width 1600 pitch 6400 (/4 1600)
>[778443.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778443.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778443.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778443.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778443.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778443.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778444.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778444.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778444.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778444.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778445.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778445.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778445.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778445.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778446.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778446.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778447.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778447.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778447.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778447.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778447.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778447.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778447.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778447.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778448.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778448.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778448.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[778448.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[778449.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778449.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778449.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778450.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778450.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8c680]
>[778450.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8c680] width 1600 pitch 6400 (/4 1600)
>[778450.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e70400]
>[778450.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e70400] width 1600 pitch 6400 (/4 1600)
>[778456.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db450]
>[778456.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db450] width 1600 pitch 6400 (/4 1600)
>[778467.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681c400]
>[778467.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681c400] width 1600 pitch 6400 (/4 1600)
>[778467.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49515b0]
>[778467.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49515b0] width 1600 pitch 6400 (/4 1600)
>[778467.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[778467.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[778467.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[778467.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[778467.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[778467.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[778467.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[778467.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[778467.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[778467.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[778468.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[778468.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[778468.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[778468.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[778468.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f2350]
>[778468.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f2350] width 1600 pitch 6400 (/4 1600)
>[778468.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[778468.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[778468.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3eb0]
>[778468.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3eb0] width 1600 pitch 6400 (/4 1600)
>[778468.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[778468.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[778468.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[778468.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[778468.511] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c6680]
>[778468.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c6680] width 1600 pitch 6400 (/4 1600)
>[778516.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67810]
>[778516.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67810] width 1600 pitch 6400 (/4 1600)
>[778517.850] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778517.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778517.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[778517.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[778517.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[778517.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[778517.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778518.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778518.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681c400]
>[778518.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681c400] width 1600 pitch 6400 (/4 1600)
>[778518.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[778518.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[778518.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[778518.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[778518.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778518.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778518.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c6680]
>[778518.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c6680] width 1600 pitch 6400 (/4 1600)
>[778518.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[778518.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[778518.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681c400]
>[778518.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681c400] width 1600 pitch 6400 (/4 1600)
>[778518.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[778518.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[778518.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[778518.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[778518.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[778518.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[778587.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b67ed0]
>[778587.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b67ed0] width 1600 pitch 6400 (/4 1600)
>[778588.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[778588.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[778588.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x681c400]
>[778588.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x681c400] width 1600 pitch 6400 (/4 1600)
>[778588.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[778588.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[778588.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[778588.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[778588.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[778588.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[778616.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[778616.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[778616.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778616.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778616.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778616.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778616.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778617.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778617.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778617.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778617.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778617.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778617.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778617.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778617.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[778617.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[778617.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[778617.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[778652.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673ff50]
>[778652.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673ff50] width 1600 pitch 6400 (/4 1600)
>[778835.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588aab0]
>[778835.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588aab0] width 1600 pitch 6400 (/4 1600)
>[779046.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991600]
>[779046.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991600] width 1600 pitch 6400 (/4 1600)
>[779052.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[779052.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[779052.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[779052.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[779052.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[779052.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[779052.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed6510]
>[779052.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed6510] width 1600 pitch 6400 (/4 1600)
>[779052.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49515b0]
>[779052.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49515b0] width 1600 pitch 6400 (/4 1600)
>[779052.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990480]
>[779053.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990480] width 1600 pitch 6400 (/4 1600)
>[779054.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[779054.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[779054.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed6510]
>[779054.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed6510] width 1600 pitch 6400 (/4 1600)
>[779054.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779054.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779054.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779054.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779054.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[779054.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[779054.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779054.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779054.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[779054.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[779054.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779054.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779381.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[779381.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[779479.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[779479.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[779479.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[779479.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[779479.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779479.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779479.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[779479.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[779479.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[779479.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[779479.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c60]
>[779480.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c60] width 1600 pitch 6400 (/4 1600)
>[779480.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[779480.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[779480.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779480.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779480.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[779480.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[779481.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779481.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779481.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[779481.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[779481.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779481.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779481.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[779481.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[779481.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779481.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779481.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[779481.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[779524.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[779524.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[779527.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[779527.256] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[779527.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779527.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779527.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[779527.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[779527.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[779527.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[779527.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[779527.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[779527.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779527.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779527.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779527.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779528.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[779528.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[779528.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f00]
>[779528.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f00] width 1600 pitch 6400 (/4 1600)
>[779528.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6d80]
>[779528.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6d80] width 1600 pitch 6400 (/4 1600)
>[779528.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991880]
>[779528.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991880] width 1600 pitch 6400 (/4 1600)
>[779528.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[779528.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[779528.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779528.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779528.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[779528.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[779530.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cee570]
>[779530.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cee570] width 1600 pitch 6400 (/4 1600)
>[779530.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c6680]
>[779531.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c6680] width 1600 pitch 6400 (/4 1600)
>[779531.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcc890]
>[779531.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcc890] width 1600 pitch 6400 (/4 1600)
>[779531.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[779531.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[779531.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f00]
>[779531.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f00] width 1600 pitch 6400 (/4 1600)
>[779531.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[779531.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[779531.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[779531.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[779531.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[779531.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[779531.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b380b0]
>[779531.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b380b0] width 1600 pitch 6400 (/4 1600)
>[779531.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[779531.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[779531.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[779531.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[779531.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779531.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779531.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[779532.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[779532.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[779532.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[779532.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779532.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779537.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2f540]
>[779537.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2f540] width 1600 pitch 6400 (/4 1600)
>[779539.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779539.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779539.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779539.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779539.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[779539.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[779539.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497d530]
>[779539.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497d530] width 1600 pitch 6400 (/4 1600)
>[779539.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6734690]
>[779539.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6734690] width 1600 pitch 6400 (/4 1600)
>[779539.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[779539.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[779539.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[779540.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[779541.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991880]
>[779541.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991880] width 1600 pitch 6400 (/4 1600)
>[779541.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[779541.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[779541.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[779541.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[779541.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[779541.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[779541.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779541.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779541.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779541.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779541.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779541.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779563.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[779563.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[779563.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db450]
>[779564.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db450] width 1600 pitch 6400 (/4 1600)
>[779564.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[779564.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[779564.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858db0]
>[779564.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858db0] width 1600 pitch 6400 (/4 1600)
>[779565.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779565.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779565.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779565.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779567.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[779567.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[779567.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779567.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779567.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[779567.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[779567.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779567.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779567.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad6510]
>[779567.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad6510] width 1600 pitch 6400 (/4 1600)
>[779568.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779568.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779568.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740350]
>[779568.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740350] width 1600 pitch 6400 (/4 1600)
>[779568.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58098b0]
>[779568.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58098b0] width 1600 pitch 6400 (/4 1600)
>[779569.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[779569.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[779569.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[779569.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[779569.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779569.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779569.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da08b0]
>[779570.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da08b0] width 1600 pitch 6400 (/4 1600)
>[779570.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779570.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779602.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5895be0]
>[779602.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5895be0] width 1600 pitch 6400 (/4 1600)
>[779602.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779603.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779603.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47abb40]
>[779603.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47abb40] width 1600 pitch 6400 (/4 1600)
>[779603.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779603.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779603.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779604.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779604.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779604.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779605.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47abb40]
>[779605.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47abb40] width 1600 pitch 6400 (/4 1600)
>[779605.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4546680]
>[779605.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4546680] width 1600 pitch 6400 (/4 1600)
>[779605.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779605.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779605.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0120]
>[779605.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0120] width 1600 pitch 6400 (/4 1600)
>[779606.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47abb40]
>[779606.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47abb40] width 1600 pitch 6400 (/4 1600)
>[779606.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db95e0]
>[779606.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db95e0] width 1600 pitch 6400 (/4 1600)
>[779607.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d04c40]
>[779607.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d04c40] width 1600 pitch 6400 (/4 1600)
>[779607.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39458e0]
>[779607.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39458e0] width 1600 pitch 6400 (/4 1600)
>[779607.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47abb40]
>[779607.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47abb40] width 1600 pitch 6400 (/4 1600)
>[779608.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73ad0]
>[779608.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73ad0] width 1600 pitch 6400 (/4 1600)
>[779608.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5895be0]
>[779608.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5895be0] width 1600 pitch 6400 (/4 1600)
>[779608.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67403d0]
>[779609.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67403d0] width 1600 pitch 6400 (/4 1600)
>[779609.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f73ad0]
>[779609.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f73ad0] width 1600 pitch 6400 (/4 1600)
>[779609.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67403d0]
>[779609.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67403d0] width 1600 pitch 6400 (/4 1600)
>[779775.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23e00]
>[779775.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23e00] width 1600 pitch 6400 (/4 1600)
>[779780.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbdd20]
>[779780.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbdd20] width 1600 pitch 6400 (/4 1600)
>[779780.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[779780.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[779780.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[779780.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[779780.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f37f90]
>[779780.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f37f90] width 1600 pitch 6400 (/4 1600)
>[779780.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779780.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779780.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[779780.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[779782.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779782.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779782.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779782.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779782.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779782.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779782.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779782.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779782.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779782.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779782.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779782.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779782.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779782.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779782.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58098b0]
>[779782.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58098b0] width 1600 pitch 6400 (/4 1600)
>[779784.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09b00]
>[779784.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09b00] width 1600 pitch 6400 (/4 1600)
>[779787.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09f50]
>[779787.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09f50] width 1600 pitch 6400 (/4 1600)
>[779787.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d9a0]
>[779787.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d9a0] width 1600 pitch 6400 (/4 1600)
>[779787.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09b00]
>[779787.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09b00] width 1600 pitch 6400 (/4 1600)
>[779788.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779788.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779788.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09b00]
>[779788.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09b00] width 1600 pitch 6400 (/4 1600)
>[779788.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfca0]
>[779788.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfca0] width 1600 pitch 6400 (/4 1600)
>[779788.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfca0]
>[779789.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfca0] width 1600 pitch 6400 (/4 1600)
>[779789.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5971960]
>[779789.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5971960] width 1600 pitch 6400 (/4 1600)
>[779789.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4883b70]
>[779789.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4883b70] width 1600 pitch 6400 (/4 1600)
>[779790.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d9a0]
>[779790.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d9a0] width 1600 pitch 6400 (/4 1600)
>[779790.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4c30]
>[779790.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4c30] width 1600 pitch 6400 (/4 1600)
>[779790.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779790.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779792.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402a480]
>[779793.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402a480] width 1600 pitch 6400 (/4 1600)
>[779793.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d9a0]
>[779793.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d9a0] width 1600 pitch 6400 (/4 1600)
>[779793.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5917910]
>[779793.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5917910] width 1600 pitch 6400 (/4 1600)
>[779793.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5954240]
>[779794.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5954240] width 1600 pitch 6400 (/4 1600)
>[779794.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779794.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779794.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779794.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779795.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9b10]
>[779795.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9b10] width 1600 pitch 6400 (/4 1600)
>[779795.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c5c00]
>[779795.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c5c00] width 1600 pitch 6400 (/4 1600)
>[779795.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbe240]
>[779795.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbe240] width 1600 pitch 6400 (/4 1600)
>[779796.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd9b10]
>[779796.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd9b10] width 1600 pitch 6400 (/4 1600)
>[779797.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09b00]
>[779797.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09b00] width 1600 pitch 6400 (/4 1600)
>[779797.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39458e0]
>[779797.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39458e0] width 1600 pitch 6400 (/4 1600)
>[779848.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e9660]
>[779848.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e9660] width 1600 pitch 6400 (/4 1600)
>[779848.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c608b0]
>[779848.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c608b0] width 1600 pitch 6400 (/4 1600)
>[779849.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d063b0]
>[779849.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d063b0] width 1600 pitch 6400 (/4 1600)
>[779849.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b65eb0]
>[779849.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b65eb0] width 1600 pitch 6400 (/4 1600)
>[779850.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a2130]
>[779850.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a2130] width 1600 pitch 6400 (/4 1600)
>[779850.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c5fd0]
>[779850.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c5fd0] width 1600 pitch 6400 (/4 1600)
>[779854.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c5fd0]
>[779854.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c5fd0] width 1600 pitch 6400 (/4 1600)
>[779855.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4530]
>[779855.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4530] width 1600 pitch 6400 (/4 1600)
>[779855.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c5fd0]
>[779855.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c5fd0] width 1600 pitch 6400 (/4 1600)
>[779855.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4530]
>[779855.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4530] width 1600 pitch 6400 (/4 1600)
>[779856.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4530]
>[779856.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4530] width 1600 pitch 6400 (/4 1600)
>[779856.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef330]
>[779856.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef330] width 1600 pitch 6400 (/4 1600)
>[779867.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779867.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779867.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779867.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779868.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779868.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779868.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e17e0]
>[779868.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e17e0] width 1600 pitch 6400 (/4 1600)
>[779868.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779868.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779868.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0040]
>[779868.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0040] width 1600 pitch 6400 (/4 1600)
>[779868.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0040]
>[779869.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0040] width 1600 pitch 6400 (/4 1600)
>[779871.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfe50]
>[779871.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfe50] width 1600 pitch 6400 (/4 1600)
>[779871.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779871.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779873.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779873.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779873.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfe50]
>[779873.710] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfe50] width 1600 pitch 6400 (/4 1600)
>[779873.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40db450]
>[779873.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40db450] width 1600 pitch 6400 (/4 1600)
>[779873.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[779873.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[779873.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[779873.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[779873.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[779873.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[779878.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9c0c0]
>[779878.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9c0c0] width 1600 pitch 6400 (/4 1600)
>[779878.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58098b0]
>[779878.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58098b0] width 1600 pitch 6400 (/4 1600)
>[779878.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[779878.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[779878.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[779878.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[779878.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779878.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779878.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779878.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779878.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779878.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779878.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779878.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779878.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58636e0]
>[779878.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58636e0] width 1600 pitch 6400 (/4 1600)
>[779892.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49828b0]
>[779892.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49828b0] width 1600 pitch 6400 (/4 1600)
>[779896.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[779896.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[779896.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[779896.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[779896.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9ee60]
>[779896.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9ee60] width 1600 pitch 6400 (/4 1600)
>[779896.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779896.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779896.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[779896.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[779896.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f37f90]
>[779896.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f37f90] width 1600 pitch 6400 (/4 1600)
>[779896.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d13550]
>[779897.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d13550] width 1600 pitch 6400 (/4 1600)
>[779897.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9c0c0]
>[779897.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9c0c0] width 1600 pitch 6400 (/4 1600)
>[779897.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[779897.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[779897.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[779897.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[779897.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1da70]
>[779897.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1da70] width 1600 pitch 6400 (/4 1600)
>[779897.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[779897.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[779897.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[779897.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[779897.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[779897.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[779900.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[779900.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[779906.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597eb30]
>[779906.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597eb30] width 1600 pitch 6400 (/4 1600)
>[779906.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[779906.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[779906.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f37f90]
>[779906.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f37f90] width 1600 pitch 6400 (/4 1600)
>[779906.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[779906.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[779906.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779906.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779906.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6745f10]
>[779906.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6745f10] width 1600 pitch 6400 (/4 1600)
>[779907.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c6680]
>[779907.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c6680] width 1600 pitch 6400 (/4 1600)
>[779907.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6734690]
>[779907.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6734690] width 1600 pitch 6400 (/4 1600)
>[779907.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5918180]
>[779907.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5918180] width 1600 pitch 6400 (/4 1600)
>[779907.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e9c0c0]
>[779907.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e9c0c0] width 1600 pitch 6400 (/4 1600)
>[779907.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6734690]
>[779907.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6734690] width 1600 pitch 6400 (/4 1600)
>[779907.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5095b00]
>[779907.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5095b00] width 1600 pitch 6400 (/4 1600)
>[779907.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6734690]
>[779907.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6734690] width 1600 pitch 6400 (/4 1600)
>[779948.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d050]
>[779948.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d050] width 1600 pitch 6400 (/4 1600)
>[779950.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b2b0]
>[779950.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b2b0] width 1600 pitch 6400 (/4 1600)
>[779950.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[779950.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[779950.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[779950.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[779950.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f37f90]
>[779950.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f37f90] width 1600 pitch 6400 (/4 1600)
>[779950.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a779a0]
>[779950.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a779a0] width 1600 pitch 6400 (/4 1600)
>[779950.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597eb30]
>[779950.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597eb30] width 1600 pitch 6400 (/4 1600)
>[779950.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[779950.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[779950.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[779950.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[779992.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5917ac0]
>[779992.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5917ac0] width 1600 pitch 6400 (/4 1600)
>[779992.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779992.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779992.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5918180]
>[779992.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5918180] width 1600 pitch 6400 (/4 1600)
>[779992.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779993.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779993.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5918180]
>[779993.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5918180] width 1600 pitch 6400 (/4 1600)
>[779993.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779993.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779993.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5918180]
>[779993.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5918180] width 1600 pitch 6400 (/4 1600)
>[779993.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[779993.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[779997.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[779997.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[779997.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39458e0]
>[779997.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39458e0] width 1600 pitch 6400 (/4 1600)
>[779997.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e152b0]
>[779997.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e152b0] width 1600 pitch 6400 (/4 1600)
>[779997.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[779998.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[779998.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779998.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[779998.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498f710]
>[779998.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498f710] width 1600 pitch 6400 (/4 1600)
>[780000.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58098b0]
>[780000.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58098b0] width 1600 pitch 6400 (/4 1600)
>[780000.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a32f0]
>[780000.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a32f0] width 1600 pitch 6400 (/4 1600)
>[780000.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa2e0]
>[780000.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa2e0] width 1600 pitch 6400 (/4 1600)
>[780012.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48725b0]
>[780012.613] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48725b0] width 1600 pitch 6400 (/4 1600)
>[780171.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[780171.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[780172.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811fd0]
>[780172.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811fd0] width 1600 pitch 6400 (/4 1600)
>[780172.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780172.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780250.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5975640]
>[780250.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5975640] width 1600 pitch 6400 (/4 1600)
>[780252.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c3320]
>[780252.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c3320] width 1600 pitch 6400 (/4 1600)
>[780252.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b23800]
>[780252.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b23800] width 1600 pitch 6400 (/4 1600)
>[780253.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496dff0]
>[780253.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496dff0] width 1600 pitch 6400 (/4 1600)
>[780253.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[780253.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[780253.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590f360]
>[780253.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590f360] width 1600 pitch 6400 (/4 1600)
>[780254.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[780254.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[780256.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991490]
>[780256.687] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991490] width 1600 pitch 6400 (/4 1600)
>[780256.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5897430]
>[780256.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5897430] width 1600 pitch 6400 (/4 1600)
>[780257.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991490]
>[780257.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991490] width 1600 pitch 6400 (/4 1600)
>[780257.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740e90]
>[780257.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740e90] width 1600 pitch 6400 (/4 1600)
>[780257.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a7be0]
>[780257.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a7be0] width 1600 pitch 6400 (/4 1600)
>[780258.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a7be0]
>[780258.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a7be0] width 1600 pitch 6400 (/4 1600)
>[780262.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[780262.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[780262.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[780262.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[780262.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[780262.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[780262.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1da70]
>[780262.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1da70] width 1600 pitch 6400 (/4 1600)
>[780262.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780262.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780262.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e900]
>[780262.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e900] width 1600 pitch 6400 (/4 1600)
>[780262.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678cc10]
>[780262.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678cc10] width 1600 pitch 6400 (/4 1600)
>[780262.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[780262.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1600 pitch 6400 (/4 1600)
>[780263.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[780263.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[780263.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3eb0]
>[780263.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3eb0] width 1600 pitch 6400 (/4 1600)
>[780263.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[780263.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[780263.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780263.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780263.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4994b10]
>[780263.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4994b10] width 1600 pitch 6400 (/4 1600)
>[780263.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f930]
>[780263.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f930] width 1600 pitch 6400 (/4 1600)
>[780263.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597ead0]
>[780263.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597ead0] width 1600 pitch 6400 (/4 1600)
>[780263.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597ead0]
>[780263.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597ead0] width 1600 pitch 6400 (/4 1600)
>[780263.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597ead0]
>[780263.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597ead0] width 1600 pitch 6400 (/4 1600)
>[780271.260] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a43c0]
>[780271.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a43c0] width 1600 pitch 6400 (/4 1600)
>[780359.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e35430]
>[780359.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e35430] width 1600 pitch 6400 (/4 1600)
>[780372.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a76c0]
>[780372.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a76c0] width 1600 pitch 6400 (/4 1600)
>[780372.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780372.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780372.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[780372.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[780372.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[780372.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[780372.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780372.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780372.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e35430]
>[780372.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e35430] width 1600 pitch 6400 (/4 1600)
>[780372.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[780372.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[780373.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3eb0]
>[780374.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3eb0] width 1600 pitch 6400 (/4 1600)
>[780374.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780374.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780374.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e35430]
>[780374.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e35430] width 1600 pitch 6400 (/4 1600)
>[780374.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780374.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780374.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e35430]
>[780374.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e35430] width 1600 pitch 6400 (/4 1600)
>[780374.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780374.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780374.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e35430]
>[780374.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e35430] width 1600 pitch 6400 (/4 1600)
>[780374.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780374.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780380.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[780380.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[780406.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4600]
>[780406.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4600] width 1600 pitch 6400 (/4 1600)
>[780407.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780407.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780407.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780407.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780407.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[780407.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8a120] width 1600 pitch 6400 (/4 1600)
>[780407.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[780407.174] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[780407.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5ed30]
>[780407.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5ed30] width 1600 pitch 6400 (/4 1600)
>[780407.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780407.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780412.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780412.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780412.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780412.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780412.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780412.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780412.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780412.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780412.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780412.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780413.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780413.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780413.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780413.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780510.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780510.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[780510.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3eb0]
>[780510.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3eb0] width 1600 pitch 6400 (/4 1600)
>[780510.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5897430]
>[780510.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5897430] width 1600 pitch 6400 (/4 1600)
>[780510.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780510.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1600 pitch 6400 (/4 1600)
>[780510.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5897430]
>[780510.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5897430] width 1600 pitch 6400 (/4 1600)
>[780510.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780510.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780510.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780510.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780514.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780514.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780514.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780514.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780514.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780514.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780514.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780514.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780514.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780514.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780514.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780514.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780514.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ab3470]
>[780515.033] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ab3470] width 1600 pitch 6400 (/4 1600)
>[780515.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f0c0]
>[780515.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f0c0] width 1600 pitch 6400 (/4 1600)
>[780515.593] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[780515.593] (II) RADEON(0): Printing DDC gathered Modelines:
>[780515.593] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[780515.593] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[780515.835] (II) RADEON(0): Allocate new frame buffer 1920x1080 stride 1920
>[780515.837] (II) RADEON(0): VRAM usage limit set to 221119K
>[780520.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e348f0]
>[780520.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e348f0] width 1920 pitch 7680 (/4 1920)
>[780528.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[780528.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1920 pitch 7680 (/4 1920)
>[780532.112] (II) config/udev: Adding input device USB USB Keykoard (/dev/input/event6)
>[780532.163] (**) USB USB Keykoard: Applying InputClass "evdev keyboard catchall"
>[780532.163] (**) USB USB Keykoard: Applying InputClass "system-setup-keyboard"
>[780532.163] (II) Using input driver 'evdev' for 'USB USB Keykoard'
>[780532.163] 	Option "XkbRules" "evdev"
>[780532.163] 	Option "XkbModel" "pc105+inet"
>[780532.163] 	Option "XkbLayout" "us"
>[780532.163] 	Option "_source" "server/udev"
>[780532.163] 	Option "name" "USB USB Keykoard"
>[780532.163] 	Option "path" "/dev/input/event6"
>[780532.163] 	Option "device" "/dev/input/event6"
>[780532.163] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input45/event6"
>[780532.163] 	Option "driver" "evdev"
>[780532.163] 	Option "XkbOptions" "terminate:ctrl_alt_bksp,"
>[780532.163] (**) USB USB Keykoard: always reports core events
>[780532.175] (**) evdev: USB USB Keykoard: Device: "/dev/input/event6"
>[780532.187] (--) evdev: USB USB Keykoard: Vendor 0x1c4f Product 0x2
>[780532.187] (--) evdev: USB USB Keykoard: Found keys
>[780532.187] (II) evdev: USB USB Keykoard: Configuring as keyboard
>[780532.187] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.1/1-1.4.2.1:1.0/input/input45/event6"
>[780532.187] (II) XINPUT: Adding extended input device "USB USB Keykoard" (type: KEYBOARD, id 9)
>[780532.187] (**) Option "xkb_rules" "evdev"
>[780532.187] (**) Option "xkb_model" "pc105+inet"
>[780532.187] (**) Option "xkb_layout" "us"
>[780532.187] (**) Option "xkb_options" "terminate:ctrl_alt_bksp,"
>[780532.200] (II) XKB: Reusing cached keymap
>[780532.208] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event7)
>[780532.208] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[780532.208] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[780532.208] 	Option "XkbRules" "evdev"
>[780532.208] 	Option "XkbModel" "evdev"
>[780532.208] 	Option "XkbLayout" "us"
>[780532.208] 	Option "_source" "server/udev"
>[780532.208] 	Option "name" "Logitech USB Optical Mouse"
>[780532.208] 	Option "path" "/dev/input/event7"
>[780532.208] 	Option "device" "/dev/input/event7"
>[780532.208] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input46/event7"
>[780532.208] 	Option "driver" "evdev"
>[780532.208] (**) Logitech USB Optical Mouse: always reports core events
>[780532.208] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event7"
>[780532.208] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[780532.208] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[780532.208] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[780532.208] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[780532.208] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[780532.208] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[780532.208] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[780532.208] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[780532.208] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[780532.208] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input46/event7"
>[780532.208] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 10)
>[780532.208] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[780532.209] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[780532.209] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[780532.209] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[780532.209] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[780532.209] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse2)
>[780532.209] (II) No input driver specified, ignoring this device.
>[780532.209] (II) This device may have been added with another device file.
>[780532.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842e90]
>[780532.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842e90] width 1920 pitch 7680 (/4 1920)
>[780533.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b67ad0]
>[780533.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b67ad0] width 1920 pitch 7680 (/4 1920)
>[780535.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780535.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780551.347] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780551.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780551.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780551.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780551.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780551.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780551.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780551.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780551.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780551.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780551.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780551.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780555.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780555.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780555.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780555.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780555.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780555.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780555.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780555.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780555.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780555.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780555.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x684a710]
>[780555.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x684a710] width 1920 pitch 7680 (/4 1920)
>[780555.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512f620]
>[780555.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512f620] width 1920 pitch 7680 (/4 1920)
>[780589.104] (II) config/udev: removing device Logitech USB Optical Mouse
>[780589.105] (II) evdev: Logitech USB Optical Mouse: Close
>[780589.105] (II) UnloadModule: "evdev"
>[780888.464] (II) RADEON(0): EDID vendor "AUO", prod id 8766
>[780888.465] (II) RADEON(0): Printing DDC gathered Modelines:
>[780888.465] (II) RADEON(0): Modeline "1600x900"x0.0  107.80  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (54.7 kHz eP)
>[780888.465] (II) RADEON(0): Modeline "1600x900"x0.0   71.87  1600 1664 1706 1970  900 903 906 912 -hsync -vsync (36.5 kHz e)
>[780978.744] (II) RADEON(0): RADEONSaveScreen(2)
>[780978.772] (II) RADEON(0): RADEONSaveScreen(0)
>[781373.768] (II) RADEON(0): RADEONSaveScreen(1)
>[781374.145] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/mouse2)
>[781374.145] (II) No input driver specified, ignoring this device.
>[781374.145] (II) This device may have been added with another device file.
>[781374.147] (II) config/udev: Adding input device Logitech USB Optical Mouse (/dev/input/event7)
>[781374.147] (**) Logitech USB Optical Mouse: Applying InputClass "evdev pointer catchall"
>[781374.147] (II) Using input driver 'evdev' for 'Logitech USB Optical Mouse'
>[781374.147] 	Option "XkbRules" "evdev"
>[781374.147] 	Option "XkbModel" "evdev"
>[781374.147] 	Option "XkbLayout" "us"
>[781374.147] 	Option "_source" "server/udev"
>[781374.147] 	Option "name" "Logitech USB Optical Mouse"
>[781374.147] 	Option "path" "/dev/input/event7"
>[781374.147] 	Option "device" "/dev/input/event7"
>[781374.147] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input47/event7"
>[781374.147] 	Option "driver" "evdev"
>[781374.148] (**) Logitech USB Optical Mouse: always reports core events
>[781374.148] (**) evdev: Logitech USB Optical Mouse: Device: "/dev/input/event7"
>[781374.148] (--) evdev: Logitech USB Optical Mouse: Vendor 0x46d Product 0xc046
>[781374.148] (--) evdev: Logitech USB Optical Mouse: Found 12 mouse buttons
>[781374.148] (--) evdev: Logitech USB Optical Mouse: Found scroll wheel(s)
>[781374.148] (--) evdev: Logitech USB Optical Mouse: Found relative axes
>[781374.148] (--) evdev: Logitech USB Optical Mouse: Found x and y relative axes
>[781374.148] (II) evdev: Logitech USB Optical Mouse: Configuring as mouse
>[781374.148] (II) evdev: Logitech USB Optical Mouse: Adding scrollwheel support
>[781374.148] (**) evdev: Logitech USB Optical Mouse: YAxisMapping: buttons 4 and 5
>[781374.148] (**) evdev: Logitech USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[781374.148] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.4/1-1.4.2/1-1.4.2.4/1-1.4.2.4:1.0/input/input47/event7"
>[781374.148] (II) XINPUT: Adding extended input device "Logitech USB Optical Mouse" (type: MOUSE, id 10)
>[781374.148] (II) evdev: Logitech USB Optical Mouse: initialized for relative axes.
>[781374.148] (**) Logitech USB Optical Mouse: (accel) keeping acceleration scheme 1
>[781374.148] (**) Logitech USB Optical Mouse: (accel) acceleration profile 0
>[781374.148] (**) Logitech USB Optical Mouse: (accel) acceleration factor: 2.000
>[781374.148] (**) Logitech USB Optical Mouse: (accel) acceleration threshold: 4
>[781380.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781380.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781380.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781380.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781380.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781380.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781380.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781380.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781380.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781380.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781380.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781380.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781380.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781380.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781380.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781380.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781380.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781380.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781380.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781380.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781380.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781380.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781380.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781380.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781380.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781380.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781380.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781380.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781380.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781381.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781381.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781381.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781381.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781381.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781381.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781381.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781381.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781381.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781381.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781381.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781381.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781381.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781381.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781381.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781381.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781381.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781381.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781381.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781381.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781381.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781381.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781381.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781381.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781381.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781381.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781381.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781381.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781381.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781381.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781381.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781381.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781381.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781381.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781381.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781381.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781381.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781381.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781382.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781382.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781382.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781382.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781382.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781382.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781382.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781382.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781382.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781382.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781382.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781382.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781382.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781382.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781382.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781382.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781382.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781382.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb0a0]
>[781382.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb0a0] width 1920 pitch 7680 (/4 1920)
>[781382.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad55f0]
>[781382.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad55f0] width 1920 pitch 7680 (/4 1920)
>[781383.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2d70]
>[781383.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2d70] width 1920 pitch 7680 (/4 1920)
>[781383.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd2d70]
>[781383.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd2d70] width 1920 pitch 7680 (/4 1920)
>[781397.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d89050]
>[781397.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d89050] width 1920 pitch 7680 (/4 1920)
>[781397.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781397.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781397.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781397.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781397.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad55f0]
>[781397.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad55f0] width 1920 pitch 7680 (/4 1920)
>[781401.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781401.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781401.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781401.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781401.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781401.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781401.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781401.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781401.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781401.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781401.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781402.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781402.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781402.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781402.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781402.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781402.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781402.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781402.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781402.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781402.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781402.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781402.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781403.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781403.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781403.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781403.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781403.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781403.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781403.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781403.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad55f0]
>[781403.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad55f0] width 1920 pitch 7680 (/4 1920)
>[781403.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781403.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781403.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781403.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781403.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781403.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781403.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781403.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781403.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a4af0]
>[781403.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a4af0] width 1920 pitch 7680 (/4 1920)
>[781403.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad55f0]
>[781403.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad55f0] width 1920 pitch 7680 (/4 1920)
>[781403.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781403.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad55f0]
>[781403.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad55f0] width 1920 pitch 7680 (/4 1920)
>[781403.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781403.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781408.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476c5f0]
>[781408.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476c5f0] width 1920 pitch 7680 (/4 1920)
>[781408.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c3580]
>[781408.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c3580] width 1920 pitch 7680 (/4 1920)
>[781414.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476ac20]
>[781414.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476ac20] width 1920 pitch 7680 (/4 1920)
>[781414.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[781414.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1920 pitch 7680 (/4 1920)
>[781415.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df0e0]
>[781415.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df0e0] width 1920 pitch 7680 (/4 1920)
>[781415.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f756e0]
>[781415.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f756e0] width 1920 pitch 7680 (/4 1920)
>[781415.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[781415.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1920 pitch 7680 (/4 1920)
>[781415.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[781415.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1920 pitch 7680 (/4 1920)
>[781416.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[781416.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1920 pitch 7680 (/4 1920)
>[781416.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[781416.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1920 pitch 7680 (/4 1920)
>[781416.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[781417.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1920 pitch 7680 (/4 1920)
>[781417.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[781417.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1920 pitch 7680 (/4 1920)
>[781417.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[781417.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1920 pitch 7680 (/4 1920)
>[781420.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75fa0]
>[781420.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75fa0] width 1920 pitch 7680 (/4 1920)
>[781420.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78420]
>[781420.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78420] width 1920 pitch 7680 (/4 1920)
>[781420.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ef60]
>[781420.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ef60] width 1920 pitch 7680 (/4 1920)
>[781423.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36433b0]
>[781423.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36433b0] width 1920 pitch 7680 (/4 1920)
>[781423.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781423.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781423.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781423.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781423.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781423.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781423.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781423.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781423.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36426d0]
>[781423.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36426d0] width 1920 pitch 7680 (/4 1920)
>[781423.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781423.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781423.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781423.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781423.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781423.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781423.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781424.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781424.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781424.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781424.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781424.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781424.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781424.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781424.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36426d0]
>[781424.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36426d0] width 1920 pitch 7680 (/4 1920)
>[781424.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781424.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781424.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781424.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781424.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.671] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781424.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781424.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781424.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781424.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781424.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781424.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781425.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781425.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781425.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781425.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781425.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781425.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781425.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781425.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781425.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781425.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781425.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781425.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781425.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781425.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781425.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781425.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781425.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781425.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.271] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36436f0]
>[781426.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36436f0] width 1920 pitch 7680 (/4 1920)
>[781426.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781426.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781426.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781426.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781426.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781426.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781426.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781427.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781427.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781427.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781427.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781427.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781427.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.469] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781428.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781428.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781428.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781428.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781428.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781428.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781429.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781429.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781429.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781429.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781429.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781429.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f773f0]
>[781430.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f773f0] width 1920 pitch 7680 (/4 1920)
>[781430.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5d60]
>[781430.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5d60] width 1920 pitch 7680 (/4 1920)
>[781430.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768440]
>[781430.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768440] width 1920 pitch 7680 (/4 1920)
>[781430.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ea70]
>[781430.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ea70] width 1920 pitch 7680 (/4 1920)
>[781430.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ef30]
>[781430.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ef30] width 1920 pitch 7680 (/4 1920)
>[781430.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ef30]
>[781431.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ef30] width 1920 pitch 7680 (/4 1920)
>[781431.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ef30]
>[781431.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ef30] width 1920 pitch 7680 (/4 1920)
>[781431.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f77870]
>[781431.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f77870] width 1920 pitch 7680 (/4 1920)
>[781431.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ad600]
>[781431.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ad600] width 1920 pitch 7680 (/4 1920)
>[781431.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588ef30]
>[781431.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588ef30] width 1920 pitch 7680 (/4 1920)
>[781433.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f77870]
>[781433.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f77870] width 1920 pitch 7680 (/4 1920)
>[781433.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f77870]
>[781434.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f77870] width 1920 pitch 7680 (/4 1920)
>[781434.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f77870]
>[781434.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f77870] width 1920 pitch 7680 (/4 1920)
>[781440.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0e60]
>[781440.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0e60] width 1920 pitch 7680 (/4 1920)
>[781441.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48aaba0]
>[781441.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48aaba0] width 1920 pitch 7680 (/4 1920)
>[781442.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3642820]
>[781442.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3642820] width 1920 pitch 7680 (/4 1920)
>[781442.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781442.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781446.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48aaba0]
>[781446.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48aaba0] width 1920 pitch 7680 (/4 1920)
>[781446.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48aaba0]
>[781446.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48aaba0] width 1920 pitch 7680 (/4 1920)
>[781446.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888940]
>[781446.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888940] width 1920 pitch 7680 (/4 1920)
>[781534.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c5110]
>[781534.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c5110] width 1920 pitch 7680 (/4 1920)
>[781535.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584e7e0]
>[781535.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584e7e0] width 1920 pitch 7680 (/4 1920)
>[781535.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ee94c0]
>[781535.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ee94c0] width 1920 pitch 7680 (/4 1920)
>[781539.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4795bc0]
>[781539.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4795bc0] width 1920 pitch 7680 (/4 1920)
>[781539.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a9c30]
>[781539.598] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a9c30] width 1920 pitch 7680 (/4 1920)
>[781539.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a9c00]
>[781539.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a9c00] width 1920 pitch 7680 (/4 1920)
>[781539.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898710]
>[781539.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898710] width 1920 pitch 7680 (/4 1920)
>[781539.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38986b0]
>[781539.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38986b0] width 1920 pitch 7680 (/4 1920)
>[781539.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4795bb0]
>[781539.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4795bb0] width 1920 pitch 7680 (/4 1920)
>[781539.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a9c50]
>[781539.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a9c50] width 1920 pitch 7680 (/4 1920)
>[781539.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898610]
>[781539.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898610] width 1920 pitch 7680 (/4 1920)
>[781539.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[781539.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1920 pitch 7680 (/4 1920)
>[781549.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c600]
>[781549.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c600] width 1920 pitch 7680 (/4 1920)
>[781549.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b98c60]
>[781549.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b98c60] width 1920 pitch 7680 (/4 1920)
>[781549.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df0e0]
>[781549.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df0e0] width 1920 pitch 7680 (/4 1920)
>[781549.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b98c60]
>[781549.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b98c60] width 1920 pitch 7680 (/4 1920)
>[781549.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df0e0]
>[781549.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df0e0] width 1920 pitch 7680 (/4 1920)
>[781549.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b98c60]
>[781549.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b98c60] width 1920 pitch 7680 (/4 1920)
>[781549.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59df0e0]
>[781549.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59df0e0] width 1920 pitch 7680 (/4 1920)
>[781553.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781553.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781553.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x363c600]
>[781554.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x363c600] width 1920 pitch 7680 (/4 1920)
>[781554.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781554.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781554.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781554.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781554.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781554.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781554.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781554.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781554.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9150]
>[781554.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9150] width 1920 pitch 7680 (/4 1920)
>[781554.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478f530]
>[781554.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478f530] width 1920 pitch 7680 (/4 1920)
>[781558.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc9fa0]
>[781558.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc9fa0] width 1920 pitch 7680 (/4 1920)
>[781558.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733ca0]
>[781558.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733ca0] width 1920 pitch 7680 (/4 1920)
>[781558.337] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3809db0]
>[781558.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3809db0] width 1920 pitch 7680 (/4 1920)
>[781558.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6732020]
>[781558.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6732020] width 1920 pitch 7680 (/4 1920)
>[781558.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6732020]
>[781558.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6732020] width 1920 pitch 7680 (/4 1920)
>[781558.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35e4e60]
>[781558.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35e4e60] width 1920 pitch 7680 (/4 1920)
>[781564.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781564.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781564.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6973250]
>[781564.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6973250] width 1920 pitch 7680 (/4 1920)
>[781564.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781564.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781564.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781564.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781564.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015500]
>[781564.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015500] width 1920 pitch 7680 (/4 1920)
>[781564.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781564.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781565.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781566.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781566.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781566.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781566.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781566.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781566.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015520]
>[781566.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015520] width 1920 pitch 7680 (/4 1920)
>[781567.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821450]
>[781567.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821450] width 1920 pitch 7680 (/4 1920)
>[781567.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015520]
>[781567.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015520] width 1920 pitch 7680 (/4 1920)
>[781567.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768880]
>[781567.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768880] width 1920 pitch 7680 (/4 1920)
>[781567.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015520]
>[781567.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015520] width 1920 pitch 7680 (/4 1920)
>[781567.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768880]
>[781567.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768880] width 1920 pitch 7680 (/4 1920)
>[781567.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781567.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781567.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781567.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781567.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768880]
>[781567.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768880] width 1920 pitch 7680 (/4 1920)
>[781567.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d441f0]
>[781567.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d441f0] width 1920 pitch 7680 (/4 1920)
>[781590.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781590.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781590.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4797070]
>[781590.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4797070] width 1920 pitch 7680 (/4 1920)
>[781591.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f73c10]
>[781591.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f73c10] width 1920 pitch 7680 (/4 1920)
>[781591.301] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781591.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781591.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781591.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781591.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781591.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781591.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781591.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781591.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781591.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781592.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584be40]
>[781592.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584be40] width 1920 pitch 7680 (/4 1920)
>[781592.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584be40]
>[781592.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584be40] width 1920 pitch 7680 (/4 1920)
>[781592.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781592.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781592.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584be40]
>[781592.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584be40] width 1920 pitch 7680 (/4 1920)
>[781592.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781592.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781592.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584be40]
>[781592.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584be40] width 1920 pitch 7680 (/4 1920)
>[781592.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781592.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781592.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584be40]
>[781592.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584be40] width 1920 pitch 7680 (/4 1920)
>[781592.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781592.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781592.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781592.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781592.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5821450]
>[781593.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5821450] width 1920 pitch 7680 (/4 1920)
>[781593.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768880]
>[781593.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768880] width 1920 pitch 7680 (/4 1920)
>[781593.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781593.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781593.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781593.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781593.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4768880]
>[781593.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4768880] width 1920 pitch 7680 (/4 1920)
>[781615.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781615.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781615.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781615.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781615.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2da0]
>[781615.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2da0] width 1920 pitch 7680 (/4 1920)
>[781615.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380ffc0]
>[781615.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380ffc0] width 1920 pitch 7680 (/4 1920)
>[781615.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781615.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781615.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781615.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781615.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781615.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781621.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781621.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781621.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781622.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781622.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5720]
>[781622.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5720] width 1920 pitch 7680 (/4 1920)
>[781622.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2da0]
>[781622.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2da0] width 1920 pitch 7680 (/4 1920)
>[781622.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5720]
>[781622.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5720] width 1920 pitch 7680 (/4 1920)
>[781626.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781626.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781629.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0ef0]
>[781629.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0ef0] width 1920 pitch 7680 (/4 1920)
>[781630.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0ef0]
>[781630.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0ef0] width 1920 pitch 7680 (/4 1920)
>[781633.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781633.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781633.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781633.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781633.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0b10]
>[781633.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0b10] width 1920 pitch 7680 (/4 1920)
>[781633.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0b10]
>[781633.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0b10] width 1920 pitch 7680 (/4 1920)
>[781633.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f74480]
>[781633.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f74480] width 1920 pitch 7680 (/4 1920)
>[781633.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67530]
>[781634.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67530] width 1920 pitch 7680 (/4 1920)
>[781635.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781635.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781636.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c56c0]
>[781636.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c56c0] width 1920 pitch 7680 (/4 1920)
>[781636.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781636.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781636.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f74480]
>[781636.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f74480] width 1920 pitch 7680 (/4 1920)
>[781636.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3646140]
>[781636.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3646140] width 1920 pitch 7680 (/4 1920)
>[781641.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649f70]
>[781641.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649f70] width 1920 pitch 7680 (/4 1920)
>[781641.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48ab180]
>[781642.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48ab180] width 1920 pitch 7680 (/4 1920)
>[781648.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c5660]
>[781648.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c5660] width 1920 pitch 7680 (/4 1920)
>[781648.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3644000]
>[781648.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3644000] width 1920 pitch 7680 (/4 1920)
>[781648.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67530]
>[781648.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67530] width 1920 pitch 7680 (/4 1920)
>[781648.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3655850]
>[781648.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3655850] width 1920 pitch 7680 (/4 1920)
>[781649.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3646140]
>[781649.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3646140] width 1920 pitch 7680 (/4 1920)
>[781649.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[781649.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[781649.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3655850]
>[781649.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3655850] width 1920 pitch 7680 (/4 1920)
>[781649.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[781649.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[781649.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f74480]
>[781649.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f74480] width 1920 pitch 7680 (/4 1920)
>[781649.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364a620]
>[781649.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364a620] width 1920 pitch 7680 (/4 1920)
>[781650.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781650.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781650.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781650.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781651.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781651.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781651.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57afc30]
>[781651.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57afc30] width 1920 pitch 7680 (/4 1920)
>[781651.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781652.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781652.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781652.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781652.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2670]
>[781652.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2670] width 1920 pitch 7680 (/4 1920)
>[781652.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781652.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781652.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57afc30]
>[781652.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57afc30] width 1920 pitch 7680 (/4 1920)
>[781652.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364a2f0]
>[781652.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364a2f0] width 1920 pitch 7680 (/4 1920)
>[781652.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364a2f0]
>[781652.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364a2f0] width 1920 pitch 7680 (/4 1920)
>[781653.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2670]
>[781653.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2670] width 1920 pitch 7680 (/4 1920)
>[781653.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781653.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781653.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f74480]
>[781653.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f74480] width 1920 pitch 7680 (/4 1920)
>[781653.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811ed0]
>[781653.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811ed0] width 1920 pitch 7680 (/4 1920)
>[781653.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57afc30]
>[781653.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57afc30] width 1920 pitch 7680 (/4 1920)
>[781653.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781653.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781653.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781653.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781653.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478f010]
>[781653.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478f010] width 1920 pitch 7680 (/4 1920)
>[781653.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67530]
>[781653.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67530] width 1920 pitch 7680 (/4 1920)
>[781653.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781653.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781653.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781654.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781654.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781654.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781654.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781654.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781654.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478f010]
>[781654.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478f010] width 1920 pitch 7680 (/4 1920)
>[781654.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4979690]
>[781654.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4979690] width 1920 pitch 7680 (/4 1920)
>[781654.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2670]
>[781654.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2670] width 1920 pitch 7680 (/4 1920)
>[781654.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[781654.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[781655.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a28e10]
>[781655.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a28e10] width 1920 pitch 7680 (/4 1920)
>[781655.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c67530]
>[781655.615] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c67530] width 1920 pitch 7680 (/4 1920)
>[781655.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f740e0]
>[781655.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f740e0] width 1920 pitch 7680 (/4 1920)
>[781655.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f740e0]
>[781656.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f740e0] width 1920 pitch 7680 (/4 1920)
>[781656.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781656.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781656.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec5560]
>[781656.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec5560] width 1920 pitch 7680 (/4 1920)
>[781656.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3631570]
>[781656.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3631570] width 1920 pitch 7680 (/4 1920)
>[781656.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cee7c0]
>[781656.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cee7c0] width 1920 pitch 7680 (/4 1920)
>[781656.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f740e0]
>[781656.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f740e0] width 1920 pitch 7680 (/4 1920)
>[781656.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781656.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781656.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec5560]
>[781656.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec5560] width 1920 pitch 7680 (/4 1920)
>[781656.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3658550]
>[781656.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3658550] width 1920 pitch 7680 (/4 1920)
>[781658.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585fe00]
>[781658.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585fe00] width 1920 pitch 7680 (/4 1920)
>[781658.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c37a0]
>[781658.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c37a0] width 1920 pitch 7680 (/4 1920)
>[781660.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585fe00]
>[781660.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585fe00] width 1920 pitch 7680 (/4 1920)
>[781660.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687cc00]
>[781661.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687cc00] width 1920 pitch 7680 (/4 1920)
>[781661.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687cc00]
>[781661.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687cc00] width 1920 pitch 7680 (/4 1920)
>[781661.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a9a70]
>[781661.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a9a70] width 1920 pitch 7680 (/4 1920)
>[781661.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687cc00]
>[781661.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687cc00] width 1920 pitch 7680 (/4 1920)
>[781661.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a9a70]
>[781661.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a9a70] width 1920 pitch 7680 (/4 1920)
>[781661.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687cc00]
>[781661.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687cc00] width 1920 pitch 7680 (/4 1920)
>[781661.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a9a70]
>[781661.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a9a70] width 1920 pitch 7680 (/4 1920)
>[781663.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f740e0]
>[781663.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f740e0] width 1920 pitch 7680 (/4 1920)
>[781663.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f740e0]
>[781663.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f740e0] width 1920 pitch 7680 (/4 1920)
>[781663.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632460]
>[781663.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632460] width 1920 pitch 7680 (/4 1920)
>[781663.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57afc30]
>[781663.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57afc30] width 1920 pitch 7680 (/4 1920)
>[781663.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec5560]
>[781663.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec5560] width 1920 pitch 7680 (/4 1920)
>[781675.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0bd0]
>[781675.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0bd0] width 1920 pitch 7680 (/4 1920)
>[781675.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0d20]
>[781675.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0d20] width 1920 pitch 7680 (/4 1920)
>[781688.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f6e6b0]
>[781688.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f6e6b0] width 1920 pitch 7680 (/4 1920)
>[781703.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe4040]
>[781703.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe4040] width 1920 pitch 7680 (/4 1920)
>[781703.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0030]
>[781703.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0030] width 1920 pitch 7680 (/4 1920)
>[781703.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781703.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781710.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ddc80]
>[781710.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ddc80] width 1920 pitch 7680 (/4 1920)
>[781713.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dd770]
>[781713.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dd770] width 1920 pitch 7680 (/4 1920)
>[781721.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781721.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781721.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0b10]
>[781721.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0b10] width 1920 pitch 7680 (/4 1920)
>[781723.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0d20]
>[781724.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0d20] width 1920 pitch 7680 (/4 1920)
>[781724.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0b10]
>[781724.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0b10] width 1920 pitch 7680 (/4 1920)
>[781724.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40aa0]
>[781724.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40aa0] width 1920 pitch 7680 (/4 1920)
>[781724.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781724.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781725.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40aa0]
>[781725.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40aa0] width 1920 pitch 7680 (/4 1920)
>[781725.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781725.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781725.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47683e0]
>[781725.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47683e0] width 1920 pitch 7680 (/4 1920)
>[781727.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0d20]
>[781727.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0d20] width 1920 pitch 7680 (/4 1920)
>[781727.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0b10]
>[781727.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0b10] width 1920 pitch 7680 (/4 1920)
>[781727.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0d20]
>[781727.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0d20] width 1920 pitch 7680 (/4 1920)
>[781727.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f40aa0]
>[781727.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f40aa0] width 1920 pitch 7680 (/4 1920)
>[781727.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781727.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781731.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e03e0]
>[781731.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e03e0] width 1920 pitch 7680 (/4 1920)
>[781733.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d9d0]
>[781733.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d9d0] width 1920 pitch 7680 (/4 1920)
>[781733.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1cb0]
>[781733.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1cb0] width 1920 pitch 7680 (/4 1920)
>[781733.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4e350]
>[781733.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4e350] width 1920 pitch 7680 (/4 1920)
>[781733.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2da0]
>[781733.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2da0] width 1920 pitch 7680 (/4 1920)
>[781733.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476d9d0]
>[781733.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476d9d0] width 1920 pitch 7680 (/4 1920)
>[781733.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781733.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781735.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3778b00]
>[781735.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3778b00] width 1920 pitch 7680 (/4 1920)
>[781736.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2da0]
>[781736.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2da0] width 1920 pitch 7680 (/4 1920)
>[781737.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37781a0]
>[781737.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37781a0] width 1920 pitch 7680 (/4 1920)
>[781758.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[781758.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1920 pitch 7680 (/4 1920)
>[781758.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e0af0]
>[781758.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e0af0] width 1920 pitch 7680 (/4 1920)
>[781758.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749d50]
>[781758.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749d50] width 1920 pitch 7680 (/4 1920)
>[781765.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33e50]
>[781765.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33e50] width 1920 pitch 7680 (/4 1920)
>[781765.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d43f20]
>[781765.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d43f20] width 1920 pitch 7680 (/4 1920)
>[781766.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749d50]
>[781766.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749d50] width 1920 pitch 7680 (/4 1920)
>[781766.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c57f0]
>[781766.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c57f0] width 1920 pitch 7680 (/4 1920)
>[781766.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781766.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781766.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d9090]
>[781766.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d9090] width 1920 pitch 7680 (/4 1920)
>[781766.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1cb0]
>[781766.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1cb0] width 1920 pitch 7680 (/4 1920)
>[781766.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2170]
>[781766.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2170] width 1920 pitch 7680 (/4 1920)
>[781766.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781766.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781766.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781766.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781766.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39631c0]
>[781766.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39631c0] width 1920 pitch 7680 (/4 1920)
>[781775.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0030]
>[781775.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0030] width 1920 pitch 7680 (/4 1920)
>[781775.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476bb80]
>[781775.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476bb80] width 1920 pitch 7680 (/4 1920)
>[781775.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33e50]
>[781775.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33e50] width 1920 pitch 7680 (/4 1920)
>[781775.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781776.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781776.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d310]
>[781776.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d310] width 1920 pitch 7680 (/4 1920)
>[781776.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b7710]
>[781776.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b7710] width 1920 pitch 7680 (/4 1920)
>[781776.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781776.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781776.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476b8b0]
>[781776.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476b8b0] width 1920 pitch 7680 (/4 1920)
>[781776.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0bd0]
>[781776.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0bd0] width 1920 pitch 7680 (/4 1920)
>[781776.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d9090]
>[781776.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d9090] width 1920 pitch 7680 (/4 1920)
>[781776.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2170]
>[781776.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2170] width 1920 pitch 7680 (/4 1920)
>[781776.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731040]
>[781776.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731040] width 1920 pitch 7680 (/4 1920)
>[781776.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781776.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781776.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781776.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781776.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39631c0]
>[781776.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39631c0] width 1920 pitch 7680 (/4 1920)
>[781776.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781776.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781776.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781776.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781776.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584d2c0]
>[781776.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584d2c0] width 1920 pitch 7680 (/4 1920)
>[781776.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781776.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781776.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749d50]
>[781777.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749d50] width 1920 pitch 7680 (/4 1920)
>[781777.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6c50]
>[781777.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6c50] width 1920 pitch 7680 (/4 1920)
>[781777.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe4040]
>[781777.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe4040] width 1920 pitch 7680 (/4 1920)
>[781777.149] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669150]
>[781777.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669150] width 1920 pitch 7680 (/4 1920)
>[781777.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[781777.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1920 pitch 7680 (/4 1920)
>[781777.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ea2da0]
>[781777.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ea2da0] width 1920 pitch 7680 (/4 1920)
>[781777.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf560]
>[781777.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf560] width 1920 pitch 7680 (/4 1920)
>[781777.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1cb0]
>[781777.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1cb0] width 1920 pitch 7680 (/4 1920)
>[781777.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b238c0]
>[781777.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b238c0] width 1920 pitch 7680 (/4 1920)
>[781777.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c57f0]
>[781777.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c57f0] width 1920 pitch 7680 (/4 1920)
>[781777.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0030]
>[781777.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0030] width 1920 pitch 7680 (/4 1920)
>[781777.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476bb80]
>[781777.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476bb80] width 1920 pitch 7680 (/4 1920)
>[781777.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33e50]
>[781777.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33e50] width 1920 pitch 7680 (/4 1920)
>[781777.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781777.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781777.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f29090]
>[781777.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f29090] width 1920 pitch 7680 (/4 1920)
>[781777.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d310]
>[781777.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d310] width 1920 pitch 7680 (/4 1920)
>[781777.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b7710]
>[781777.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b7710] width 1920 pitch 7680 (/4 1920)
>[781777.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496e090]
>[781777.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496e090] width 1920 pitch 7680 (/4 1920)
>[781777.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476b8b0]
>[781777.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476b8b0] width 1920 pitch 7680 (/4 1920)
>[781777.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d0bd0]
>[781778.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d0bd0] width 1920 pitch 7680 (/4 1920)
>[781778.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d9090]
>[781778.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d9090] width 1920 pitch 7680 (/4 1920)
>[781778.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2170]
>[781778.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2170] width 1920 pitch 7680 (/4 1920)
>[781778.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731040]
>[781778.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731040] width 1920 pitch 7680 (/4 1920)
>[781778.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584eb90]
>[781778.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584eb90] width 1920 pitch 7680 (/4 1920)
>[781778.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecaf30]
>[781778.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecaf30] width 1920 pitch 7680 (/4 1920)
>[781778.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39631c0]
>[781778.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39631c0] width 1920 pitch 7680 (/4 1920)
>[781778.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781778.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781778.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f78480]
>[781778.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f78480] width 1920 pitch 7680 (/4 1920)
>[781778.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584d2c0]
>[781778.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584d2c0] width 1920 pitch 7680 (/4 1920)
>[781778.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781778.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781778.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6749d50]
>[781778.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6749d50] width 1920 pitch 7680 (/4 1920)
>[781778.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cc6c50]
>[781778.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cc6c50] width 1920 pitch 7680 (/4 1920)
>[781778.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fe4040]
>[781778.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fe4040] width 1920 pitch 7680 (/4 1920)
>[781778.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3669150]
>[781778.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3669150] width 1920 pitch 7680 (/4 1920)
>[781778.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f19650]
>[781778.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f19650] width 1920 pitch 7680 (/4 1920)
>[781787.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5245120]
>[781787.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5245120] width 1920 pitch 7680 (/4 1920)
>[781790.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38142b0]
>[781790.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38142b0] width 1920 pitch 7680 (/4 1920)
>[781790.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f29090]
>[781790.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f29090] width 1920 pitch 7680 (/4 1920)
>[781790.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781790.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781790.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476bb80]
>[781790.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476bb80] width 1920 pitch 7680 (/4 1920)
>[781790.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0030]
>[781790.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0030] width 1920 pitch 7680 (/4 1920)
>[781790.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b1cb0]
>[781790.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b1cb0] width 1920 pitch 7680 (/4 1920)
>[781790.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4888ee0]
>[781790.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4888ee0] width 1920 pitch 7680 (/4 1920)
>[781790.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48895a0]
>[781790.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48895a0] width 1920 pitch 7680 (/4 1920)
>[781790.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b4beb0]
>[781790.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b4beb0] width 1920 pitch 7680 (/4 1920)
>[781790.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b0030]
>[781790.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b0030] width 1920 pitch 7680 (/4 1920)
>[781790.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476bb80]
>[781790.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476bb80] width 1920 pitch 7680 (/4 1920)
>[781790.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6731040]
>[781790.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6731040] width 1920 pitch 7680 (/4 1920)
>[781790.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9a20]
>[781791.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9a20] width 1920 pitch 7680 (/4 1920)
>[781796.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27be0]
>[781796.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27be0] width 1920 pitch 7680 (/4 1920)
>[781797.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a7400]
>[781797.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a7400] width 1920 pitch 7680 (/4 1920)
>[781799.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3775c80]
>[781799.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3775c80] width 1920 pitch 7680 (/4 1920)
>[781816.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781816.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781816.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377afa0]
>[781816.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377afa0] width 1920 pitch 7680 (/4 1920)
>[781816.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33e50]
>[781817.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33e50] width 1920 pitch 7680 (/4 1920)
>[781817.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a4520]
>[781817.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a4520] width 1920 pitch 7680 (/4 1920)
>[781817.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781817.127] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781817.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377afa0]
>[781817.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377afa0] width 1920 pitch 7680 (/4 1920)
>[781817.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c33e50]
>[781817.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c33e50] width 1920 pitch 7680 (/4 1920)
>[781817.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781817.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781854.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d7470]
>[781854.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d7470] width 1920 pitch 7680 (/4 1920)
>[781854.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[781854.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1920 pitch 7680 (/4 1920)
>[781855.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364a2f0]
>[781855.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364a2f0] width 1920 pitch 7680 (/4 1920)
>[781855.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4979690]
>[781855.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4979690] width 1920 pitch 7680 (/4 1920)
>[781855.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781855.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781855.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811ed0]
>[781855.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811ed0] width 1920 pitch 7680 (/4 1920)
>[781855.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781855.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781856.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57dbbf0]
>[781856.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57dbbf0] width 1920 pitch 7680 (/4 1920)
>[781856.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811ed0]
>[781856.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811ed0] width 1920 pitch 7680 (/4 1920)
>[781856.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2670]
>[781856.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2670] width 1920 pitch 7680 (/4 1920)
>[781856.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781856.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781856.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48b3850]
>[781856.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48b3850] width 1920 pitch 7680 (/4 1920)
>[781856.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781857.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781857.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811ed0]
>[781857.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811ed0] width 1920 pitch 7680 (/4 1920)
>[781857.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781857.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781857.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[781857.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1920 pitch 7680 (/4 1920)
>[781857.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[781857.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[781857.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[781857.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1920 pitch 7680 (/4 1920)
>[781857.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e78c0]
>[781857.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e78c0] width 1920 pitch 7680 (/4 1920)
>[781857.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781857.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781857.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781857.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781860.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[781860.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1920 pitch 7680 (/4 1920)
>[781860.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[781861.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1920 pitch 7680 (/4 1920)
>[781861.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478f010]
>[781861.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478f010] width 1920 pitch 7680 (/4 1920)
>[781861.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[781861.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1920 pitch 7680 (/4 1920)
>[781861.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3811ed0]
>[781861.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3811ed0] width 1920 pitch 7680 (/4 1920)
>[781864.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[781864.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[781864.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dece00]
>[781864.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dece00] width 1920 pitch 7680 (/4 1920)
>[781865.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[781865.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1920 pitch 7680 (/4 1920)
>[781865.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e282a0]
>[781865.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e282a0] width 1920 pitch 7680 (/4 1920)
>[781865.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[781865.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1920 pitch 7680 (/4 1920)
>[781866.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[781866.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[781866.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364a2f0]
>[781866.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364a2f0] width 1920 pitch 7680 (/4 1920)
>[781867.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[781867.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1920 pitch 7680 (/4 1920)
>[781867.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811fd0]
>[781868.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811fd0] width 1920 pitch 7680 (/4 1920)
>[781868.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[781868.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1920 pitch 7680 (/4 1920)
>[781869.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[781869.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1920 pitch 7680 (/4 1920)
>[781869.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781869.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781869.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[781869.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1920 pitch 7680 (/4 1920)
>[781869.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781869.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781869.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781869.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781870.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584e780]
>[781870.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584e780] width 1920 pitch 7680 (/4 1920)
>[781870.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781870.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781870.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781871.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781871.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781871.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781872.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781872.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781873.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e91cb0]
>[781873.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e91cb0] width 1920 pitch 7680 (/4 1920)
>[781873.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781873.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781873.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x242f1a0]
>[781873.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x242f1a0] width 1920 pitch 7680 (/4 1920)
>[781880.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3697030]
>[781880.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3697030] width 1920 pitch 7680 (/4 1920)
>[781880.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ecf10]
>[781880.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ecf10] width 1920 pitch 7680 (/4 1920)
>[781880.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ecf10]
>[781880.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ecf10] width 1920 pitch 7680 (/4 1920)
>[781880.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630700]
>[781880.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630700] width 1920 pitch 7680 (/4 1920)
>[781900.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3630700]
>[781900.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3630700] width 1920 pitch 7680 (/4 1920)
>[781900.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57c86d0]
>[781900.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57c86d0] width 1920 pitch 7680 (/4 1920)
>[781965.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36952b0]
>[781965.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36952b0] width 1920 pitch 7680 (/4 1920)
>[781965.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d7420]
>[781965.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d7420] width 1920 pitch 7680 (/4 1920)
>[781966.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36952b0]
>[781966.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36952b0] width 1920 pitch 7680 (/4 1920)
>[781966.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36952b0]
>[781966.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36952b0] width 1920 pitch 7680 (/4 1920)
>[781966.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3789410]
>[781966.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3789410] width 1920 pitch 7680 (/4 1920)
>[781967.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36952b0]
>[781967.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36952b0] width 1920 pitch 7680 (/4 1920)
>[781967.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f048c0]
>[781967.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f048c0] width 1920 pitch 7680 (/4 1920)
>[781967.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[781968.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[781968.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f048c0]
>[781968.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f048c0] width 1920 pitch 7680 (/4 1920)
>[781968.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36952b0]
>[781968.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36952b0] width 1920 pitch 7680 (/4 1920)
>[781969.313] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[781969.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[781969.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[781969.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[781988.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ecf10]
>[781988.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ecf10] width 1920 pitch 7680 (/4 1920)
>[781988.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378cf70]
>[781988.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378cf70] width 1920 pitch 7680 (/4 1920)
>[781989.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37893b0]
>[781989.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37893b0] width 1920 pitch 7680 (/4 1920)
>[781989.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ecf10]
>[781990.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ecf10] width 1920 pitch 7680 (/4 1920)
>[781990.179] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781990.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781990.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[781990.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1920 pitch 7680 (/4 1920)
>[781990.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781990.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781991.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781991.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781991.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[781991.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1920 pitch 7680 (/4 1920)
>[781991.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781991.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781992.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781992.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781999.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781999.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[781999.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[781999.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[782000.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[782000.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1920 pitch 7680 (/4 1920)
>[782000.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2811fd0]
>[782000.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2811fd0] width 1920 pitch 7680 (/4 1920)
>[782000.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37893b0]
>[782000.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37893b0] width 1920 pitch 7680 (/4 1920)
>[782000.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[782000.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1920 pitch 7680 (/4 1920)
>[782000.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[782000.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1920 pitch 7680 (/4 1920)
>[782001.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[782001.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[782001.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37efb70]
>[782001.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37efb70] width 1920 pitch 7680 (/4 1920)
>[782001.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6520]
>[782001.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6520] width 1920 pitch 7680 (/4 1920)
>[782001.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd6520]
>[782001.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd6520] width 1920 pitch 7680 (/4 1920)
>[782001.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4979690]
>[782001.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4979690] width 1920 pitch 7680 (/4 1920)
>[782008.591] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b53a0]
>[782008.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b53a0] width 1920 pitch 7680 (/4 1920)
>[782011.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[782011.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1920 pitch 7680 (/4 1920)
>[782011.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[782011.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[782012.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[782012.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[782311.759] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[782311.759] (II) RADEON(0): Using hsync ranges from config file
>[782311.759] (II) RADEON(0): Using vrefresh ranges from config file
>[782311.759] (II) RADEON(0): Printing DDC gathered Modelines:
>[782311.759] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[782311.759] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[782311.759] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[782311.759] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[782311.759] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[782311.759] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[782311.759] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[782311.759] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[782311.759] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[782311.759] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[782311.759] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[782391.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[782391.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1920 pitch 7680 (/4 1920)
>[782391.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[782391.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[782391.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782391.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782391.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[782391.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1920 pitch 7680 (/4 1920)
>[782392.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584e780]
>[782392.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584e780] width 1920 pitch 7680 (/4 1920)
>[782392.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[782392.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1920 pitch 7680 (/4 1920)
>[782392.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782392.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782393.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[782393.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1920 pitch 7680 (/4 1920)
>[782393.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[782393.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[782393.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[782393.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1920 pitch 7680 (/4 1920)
>[782393.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57db650]
>[782393.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57db650] width 1920 pitch 7680 (/4 1920)
>[782393.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[782393.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1920 pitch 7680 (/4 1920)
>[782393.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[782393.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1920 pitch 7680 (/4 1920)
>[782393.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584e780]
>[782393.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584e780] width 1920 pitch 7680 (/4 1920)
>[782393.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[782394.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[782394.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[782394.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1920 pitch 7680 (/4 1920)
>[782394.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364ad40]
>[782394.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364ad40] width 1920 pitch 7680 (/4 1920)
>[782394.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[782394.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1920 pitch 7680 (/4 1920)
>[782394.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[782394.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1920 pitch 7680 (/4 1920)
>[782394.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782394.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782395.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[782395.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1920 pitch 7680 (/4 1920)
>[782395.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[782395.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1920 pitch 7680 (/4 1920)
>[782398.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[782398.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1920 pitch 7680 (/4 1920)
>[782398.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[782398.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1920 pitch 7680 (/4 1920)
>[782399.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782399.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782400.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[782400.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1920 pitch 7680 (/4 1920)
>[782400.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782400.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782400.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782400.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782401.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed4600]
>[782401.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed4600] width 1920 pitch 7680 (/4 1920)
>[782401.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[782401.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1920 pitch 7680 (/4 1920)
>[782402.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476e720]
>[782402.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476e720] width 1920 pitch 7680 (/4 1920)
>[782402.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[782402.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1920 pitch 7680 (/4 1920)
>[782707.050] (II) RADEON(0): EDID vendor "SAM", prod id 1399
>[782707.050] (II) RADEON(0): Using hsync ranges from config file
>[782707.050] (II) RADEON(0): Using vrefresh ranges from config file
>[782707.050] (II) RADEON(0): Printing DDC gathered Modelines:
>[782707.050] (II) RADEON(0): Modeline "1920x1080"x0.0  148.50  1920 2008 2052 2200  1080 1084 1089 1125 +hsync +vsync (67.5 kHz eP)
>[782707.050] (II) RADEON(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz e)
>[782707.050] (II) RADEON(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz e)
>[782707.050] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz e)
>[782707.050] (II) RADEON(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz e)
>[782707.050] (II) RADEON(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz e)
>[782707.050] (II) RADEON(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz e)
>[782707.051] (II) RADEON(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz e)
>[782707.051] (II) RADEON(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz e)
>[782707.051] (II) RADEON(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz e)
>[782707.051] (II) RADEON(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1280x800"x0.0   83.50  1280 1352 1480 1680  800 803 809 831 -hsync +vsync (49.7 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1280x960"x0.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1440x900"x0.0  106.50  1440 1520 1672 1904  900 903 909 934 -hsync +vsync (55.9 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1600x1200"x0.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz e)
>[782707.051] (II) RADEON(0): Modeline "1680x1050"x0.0  146.25  1680 1784 1960 2240  1050 1053 1059 1089 -hsync +vsync (65.3 kHz e)
>[782797.759] (II) RADEON(0): RADEONSaveScreen(2)
>[782797.760] (II) RADEON(0): RADEONSaveScreen(0)
>[783209.933] (II) RADEON(0): RADEONSaveScreen(1)
>[783221.863] (II) config/udev: removing device Logitech USB Optical Mouse
>[783222.053] (II) evdev: Logitech USB Optical Mouse: Close
>[783222.071] (II) UnloadModule: "evdev"
>[783222.071] (II) config/udev: removing device USB USB Keykoard
>[783222.072] (II) evdev: USB USB Keykoard: Close
>[783222.086] (II) UnloadModule: "evdev"
>[783306.045] (II) AIGLX: Suspending AIGLX clients for VT switch
>[783306.055] (II) RADEON(0): RADEONLeaveVT_KMS
>[783306.055] (II) RADEON(0): Ok, leaving now...
>[783317.195] (II) AIGLX: Resuming AIGLX clients after VT switch
>[783317.195] (II) RADEON(0): RADEONEnterVT_KMS
>[783317.697] (II) RADEON(0): RADEONSaveScreen(2)
>[783317.698] (**) Option "Device" "/dev/input/event5"
>[783317.698] (--) synaptics: SynPS/2 Synaptics TouchPad: touchpad found
>[783318.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8a120]
>[783318.800] (WW) RADEON(0): flip queue failed: Device or resource busy
>[783318.800] (WW) RADEON(0): Page flip failed: Device or resource busy
>[783320.451] (II) RADEON(0): Allocate new frame buffer 1600x904 stride 1600
>[783320.451] (II) RADEON(0): VRAM usage limit set to 223324K
>[783323.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783323.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783323.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783323.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783323.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c1d050]
>[783323.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c1d050] width 1600 pitch 6400 (/4 1600)
>[783323.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783323.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783323.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783323.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783324.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783324.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783324.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783324.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783324.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783324.303] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783327.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783327.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783327.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783327.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783327.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783327.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783329.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783329.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783330.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783330.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783330.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783330.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783330.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783330.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783330.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783330.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783330.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783330.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783330.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783330.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783330.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[783330.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[783330.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783331.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783331.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783331.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783331.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783331.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783331.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783331.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783331.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783331.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783331.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783331.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783331.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783332.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783332.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783332.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783332.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783332.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783332.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783332.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783332.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783332.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783332.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783332.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783332.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783332.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783332.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783332.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783332.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783332.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783332.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783332.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783332.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783332.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783332.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783332.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783332.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783332.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783332.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783332.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783332.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783332.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783332.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783332.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783332.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783332.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783332.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783332.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783332.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783332.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783332.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783332.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783332.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783332.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783332.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783332.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783332.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783333.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783333.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783333.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783333.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783333.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783333.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783333.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783333.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783333.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783333.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783333.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783333.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783333.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783333.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783333.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783333.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783333.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783333.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783333.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783333.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783333.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783333.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783333.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783333.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783333.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783333.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783333.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783333.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783333.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783333.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783333.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783333.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783333.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783333.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783333.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783333.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783333.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783333.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783333.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783333.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783333.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783333.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783334.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783334.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783334.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783334.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783334.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783334.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783334.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783334.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783334.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783334.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783334.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783334.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783334.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783334.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783334.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783334.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783334.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783334.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783334.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783334.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783334.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783334.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783334.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783334.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783334.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783334.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783334.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783334.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783334.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783334.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783334.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783334.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783334.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783334.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783334.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783334.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783334.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783334.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783334.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783334.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783334.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783334.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783335.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783335.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783335.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783335.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783335.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783335.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783335.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783335.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783335.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783335.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783335.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783335.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783335.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783335.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783335.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783335.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783335.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783335.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783335.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783335.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783335.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783335.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783335.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783335.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783335.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783335.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783335.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783335.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783335.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783335.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783335.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783335.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783335.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783335.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783335.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783335.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783335.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783335.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783335.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783335.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783335.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783335.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783336.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783336.019] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783336.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783336.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783336.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783336.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783336.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783336.119] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783336.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783336.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783336.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783336.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783336.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783336.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783336.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783336.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783336.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783336.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783336.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783336.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783336.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783336.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783336.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783336.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783336.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783336.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783336.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783336.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783336.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783336.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783336.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783336.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783336.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783336.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783336.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783336.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783336.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783336.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783336.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783336.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783336.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783336.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783336.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783336.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783337.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783337.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783337.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783337.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783337.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783337.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783337.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783337.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783337.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783337.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783337.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783337.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783337.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783337.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783337.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783337.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783337.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783337.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783337.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783337.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783337.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783337.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783337.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783337.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783337.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783337.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783337.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783337.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783337.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783337.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783337.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783337.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783337.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783337.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783337.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783337.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783337.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783337.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783338.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783338.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783338.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783338.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783338.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783338.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783338.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783338.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783338.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783338.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783338.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783338.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783338.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783338.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783338.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783338.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783338.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783338.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783338.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783338.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783338.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783338.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783338.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783338.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783338.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783338.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783338.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783338.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783338.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783338.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783338.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783338.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783338.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783338.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783338.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783338.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783338.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783338.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783338.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783338.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783338.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783338.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783339.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783339.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783339.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783339.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783339.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783339.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783339.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783339.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783339.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783339.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783339.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783339.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783339.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783339.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783339.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783339.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783339.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783339.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783339.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783339.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783339.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783339.528] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783339.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783339.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783339.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783339.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783339.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783339.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783339.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783339.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783339.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783339.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783339.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783339.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783339.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783339.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783339.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783339.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3220]
>[783339.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3220] width 1600 pitch 6400 (/4 1600)
>[783339.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783340.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783340.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783340.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783340.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783340.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783340.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783340.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783340.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783340.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783340.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783340.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783340.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783340.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783340.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[783340.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[783340.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783340.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783340.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[783340.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[783340.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783340.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783340.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b34740]
>[783340.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b34740] width 1600 pitch 6400 (/4 1600)
>[783340.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783340.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783340.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783340.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783340.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783340.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783340.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783340.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783340.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783340.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783340.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783340.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783343.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783343.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783343.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783343.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783343.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783343.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783343.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[783343.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[783380.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783380.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783380.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783380.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783380.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783380.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783380.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783380.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783398.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783398.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783399.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b50]
>[783399.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b50] width 1600 pitch 6400 (/4 1600)
>[783399.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1210]
>[783399.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1210] width 1600 pitch 6400 (/4 1600)
>[783403.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b50]
>[783404.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b50] width 1600 pitch 6400 (/4 1600)
>[783404.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3aad0]
>[783404.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3aad0] width 1600 pitch 6400 (/4 1600)
>[783405.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b50]
>[783406.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b50] width 1600 pitch 6400 (/4 1600)
>[783406.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b50]
>[783406.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b50] width 1600 pitch 6400 (/4 1600)
>[783406.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3aad0]
>[783406.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3aad0] width 1600 pitch 6400 (/4 1600)
>[783406.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783406.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783406.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a5b50]
>[783406.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a5b50] width 1600 pitch 6400 (/4 1600)
>[783407.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67e00]
>[783407.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67e00] width 1600 pitch 6400 (/4 1600)
>[783408.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67e00]
>[783408.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67e00] width 1600 pitch 6400 (/4 1600)
>[783408.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67e00]
>[783408.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67e00] width 1600 pitch 6400 (/4 1600)
>[783408.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783408.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783408.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67e00]
>[783408.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67e00] width 1600 pitch 6400 (/4 1600)
>[783421.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4984f90]
>[783421.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4984f90] width 1600 pitch 6400 (/4 1600)
>[783421.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783422.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783422.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fb3200]
>[783422.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fb3200] width 1600 pitch 6400 (/4 1600)
>[783422.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783422.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783422.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585dfe0]
>[783422.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585dfe0] width 1600 pitch 6400 (/4 1600)
>[783424.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783424.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783425.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783425.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783425.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783425.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783426.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783426.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783426.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783426.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783432.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783432.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783436.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783436.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783439.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783439.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783440.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783440.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783441.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783441.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783442.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[783442.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[783442.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783442.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783442.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783442.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783442.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783442.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783446.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3780d20]
>[783446.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3780d20] width 1600 pitch 6400 (/4 1600)
>[783446.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783446.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783446.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[783447.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[783447.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3780d20]
>[783447.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3780d20] width 1600 pitch 6400 (/4 1600)
>[783447.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6736830]
>[783447.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6736830] width 1600 pitch 6400 (/4 1600)
>[783447.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[783447.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[783448.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783448.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783449.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd99f0]
>[783449.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd99f0] width 1600 pitch 6400 (/4 1600)
>[783450.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783450.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783450.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364ad40]
>[783450.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364ad40] width 1600 pitch 6400 (/4 1600)
>[783450.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783450.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783450.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378cf70]
>[783450.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378cf70] width 1600 pitch 6400 (/4 1600)
>[783450.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364ad40]
>[783450.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364ad40] width 1600 pitch 6400 (/4 1600)
>[783450.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783450.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783450.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[783450.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[783450.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[783450.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[783451.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37893b0]
>[783451.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37893b0] width 1600 pitch 6400 (/4 1600)
>[783451.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783451.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783452.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804cd0]
>[783452.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804cd0] width 1600 pitch 6400 (/4 1600)
>[783453.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378cf70]
>[783453.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378cf70] width 1600 pitch 6400 (/4 1600)
>[783453.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783453.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783453.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[783453.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[783453.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4972d00]
>[783453.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4972d00] width 1600 pitch 6400 (/4 1600)
>[783454.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783454.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783454.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[783454.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[783454.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd99f0]
>[783454.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd99f0] width 1600 pitch 6400 (/4 1600)
>[783454.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378cf70]
>[783454.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378cf70] width 1600 pitch 6400 (/4 1600)
>[783454.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[783454.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[783454.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3925920]
>[783454.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3925920] width 1600 pitch 6400 (/4 1600)
>[783454.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x362e270]
>[783454.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x362e270] width 1600 pitch 6400 (/4 1600)
>[783454.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783454.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783454.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783454.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783454.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4972d00]
>[783454.728] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4972d00] width 1600 pitch 6400 (/4 1600)
>[783454.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7ef40]
>[783454.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7ef40] width 1600 pitch 6400 (/4 1600)
>[783454.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783454.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783454.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bfa60]
>[783454.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bfa60] width 1600 pitch 6400 (/4 1600)
>[783454.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de90e0]
>[783454.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de90e0] width 1600 pitch 6400 (/4 1600)
>[783454.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783454.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783454.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x378cf70]
>[783455.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x378cf70] width 1600 pitch 6400 (/4 1600)
>[783455.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783455.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783455.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd99f0]
>[783455.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd99f0] width 1600 pitch 6400 (/4 1600)
>[783455.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804cd0]
>[783455.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804cd0] width 1600 pitch 6400 (/4 1600)
>[783455.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c020]
>[783455.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c020] width 1600 pitch 6400 (/4 1600)
>[783455.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783455.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783455.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783455.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783455.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3944bc0]
>[783455.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3944bc0] width 1600 pitch 6400 (/4 1600)
>[783455.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4972d00]
>[783455.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4972d00] width 1600 pitch 6400 (/4 1600)
>[783455.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364ad40]
>[783455.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364ad40] width 1600 pitch 6400 (/4 1600)
>[783455.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f76f30]
>[783455.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f76f30] width 1600 pitch 6400 (/4 1600)
>[783455.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804cd0]
>[783455.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804cd0] width 1600 pitch 6400 (/4 1600)
>[783455.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd99f0]
>[783455.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd99f0] width 1600 pitch 6400 (/4 1600)
>[783455.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[783455.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[783455.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[783455.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[783455.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783455.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783455.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[783455.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[783696.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[783697.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[783697.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[783697.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[783697.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783697.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783699.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783699.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783699.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[783699.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[783700.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377bb10]
>[783700.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377bb10] width 1600 pitch 6400 (/4 1600)
>[783700.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b490]
>[783700.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b490] width 1600 pitch 6400 (/4 1600)
>[783701.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783701.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783701.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[783701.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[783702.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[783702.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[783702.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[783702.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[783799.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5857d60]
>[783799.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5857d60] width 1600 pitch 6400 (/4 1600)
>[783799.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[783799.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[783799.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783799.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783799.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[783799.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[783800.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[783800.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[783800.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[783800.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[783800.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[783800.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[783801.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dcd20]
>[783801.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dcd20] width 1600 pitch 6400 (/4 1600)
>[783801.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783801.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783801.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[783801.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[783801.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6b490]
>[783801.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6b490] width 1600 pitch 6400 (/4 1600)
>[783801.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[783801.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[783801.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[783801.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[783802.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5857d60]
>[783802.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5857d60] width 1600 pitch 6400 (/4 1600)
>[783802.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783802.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783802.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[783802.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[783802.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[783802.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[783802.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783802.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783802.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[783803.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[783803.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[783803.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[783803.581] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de6a10]
>[783803.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de6a10] width 1600 pitch 6400 (/4 1600)
>[783804.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[783804.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[783804.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[783804.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[783804.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783804.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783805.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[783805.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[783805.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d0d0]
>[783805.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d0d0] width 1600 pitch 6400 (/4 1600)
>[783805.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632e20]
>[783805.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632e20] width 1600 pitch 6400 (/4 1600)
>[783805.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[783805.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[783805.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[783805.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[783806.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5857d60]
>[783806.130] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5857d60] width 1600 pitch 6400 (/4 1600)
>[783806.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dcd20]
>[783806.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dcd20] width 1600 pitch 6400 (/4 1600)
>[783806.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d0d0]
>[783806.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d0d0] width 1600 pitch 6400 (/4 1600)
>[783806.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[783807.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[783807.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[783808.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[783808.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[783808.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[783808.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[783808.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[783808.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x586d0d0]
>[783808.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x586d0d0] width 1600 pitch 6400 (/4 1600)
>[783808.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632e20]
>[783808.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632e20] width 1600 pitch 6400 (/4 1600)
>[783808.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[783808.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[783808.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[783808.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[783808.961] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[783809.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[784045.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784045.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784045.720] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784045.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784046.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784046.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784046.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784047.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784047.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784047.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784047.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a9280]
>[784047.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a9280] width 1600 pitch 6400 (/4 1600)
>[784047.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784047.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784047.817] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[784047.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[784048.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a9280]
>[784048.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a9280] width 1600 pitch 6400 (/4 1600)
>[784048.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784048.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784048.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[784048.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[784050.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784050.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784050.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5894450]
>[784050.949] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5894450] width 1600 pitch 6400 (/4 1600)
>[784051.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[784051.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[784051.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[784051.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[784059.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a9d610]
>[784059.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a9d610] width 1600 pitch 6400 (/4 1600)
>[784067.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784067.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784067.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ea8b0]
>[784067.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ea8b0] width 1600 pitch 6400 (/4 1600)
>[784067.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5857d60]
>[784067.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5857d60] width 1600 pitch 6400 (/4 1600)
>[784067.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[784067.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[784068.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784068.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784068.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8bd10]
>[784068.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8bd10] width 1600 pitch 6400 (/4 1600)
>[784068.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784068.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784068.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8bd10]
>[784068.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8bd10] width 1600 pitch 6400 (/4 1600)
>[784068.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784068.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784068.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784068.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784096.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784096.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784096.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784096.670] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784097.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784097.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784097.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784097.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784097.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784097.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784097.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da6bb0]
>[784097.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da6bb0] width 1600 pitch 6400 (/4 1600)
>[784097.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784097.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784097.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784098.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784098.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b1200]
>[784098.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b1200] width 1600 pitch 6400 (/4 1600)
>[784098.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5857d60]
>[784098.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5857d60] width 1600 pitch 6400 (/4 1600)
>[784098.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[784099.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[784099.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c756d0]
>[784099.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c756d0] width 1600 pitch 6400 (/4 1600)
>[784099.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec9aa0]
>[784099.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec9aa0] width 1600 pitch 6400 (/4 1600)
>[784099.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784100.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784100.180] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784100.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784100.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784100.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784100.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784100.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784102.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[784102.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[784102.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784102.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784102.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb4eb0]
>[784102.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb4eb0] width 1600 pitch 6400 (/4 1600)
>[784102.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d1290]
>[784103.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d1290] width 1600 pitch 6400 (/4 1600)
>[784450.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ea7b0]
>[784450.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ea7b0] width 1600 pitch 6400 (/4 1600)
>[784450.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[784450.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[784450.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[784450.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[784455.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4995c20]
>[784455.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4995c20] width 1600 pitch 6400 (/4 1600)
>[784455.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784455.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784455.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0280]
>[784456.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0280] width 1600 pitch 6400 (/4 1600)
>[784456.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[784456.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[784456.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784456.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784457.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0280]
>[784457.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0280] width 1600 pitch 6400 (/4 1600)
>[784457.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[784457.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[784458.072] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784458.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784458.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0280]
>[784458.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0280] width 1600 pitch 6400 (/4 1600)
>[784458.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784458.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784458.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0280]
>[784458.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0280] width 1600 pitch 6400 (/4 1600)
>[784458.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784458.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784458.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fa9640]
>[784458.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fa9640] width 1600 pitch 6400 (/4 1600)
>[784459.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[784459.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[784468.370] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784468.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784468.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x369e030]
>[784468.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x369e030] width 1600 pitch 6400 (/4 1600)
>[784469.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57cf5c0]
>[784469.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57cf5c0] width 1600 pitch 6400 (/4 1600)
>[784469.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[784469.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[784469.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784469.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784469.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[784469.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[784470.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[784470.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[784470.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784470.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784471.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784471.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784471.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784471.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50495b0]
>[784471.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50495b0] width 1600 pitch 6400 (/4 1600)
>[784471.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784471.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784471.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784472.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784472.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784472.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784472.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784472.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784472.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784472.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784472.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48676b0]
>[784472.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48676b0] width 1600 pitch 6400 (/4 1600)
>[784476.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[784476.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[784477.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[784477.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[784478.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5850de0]
>[784478.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5850de0] width 1600 pitch 6400 (/4 1600)
>[784478.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584cef0]
>[784478.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584cef0] width 1600 pitch 6400 (/4 1600)
>[784480.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[784480.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[784481.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3e60]
>[784481.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3e60] width 1600 pitch 6400 (/4 1600)
>[784481.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[784481.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[784481.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3e60]
>[784482.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3e60] width 1600 pitch 6400 (/4 1600)
>[784482.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[784482.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[784482.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[784482.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[784482.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[784483.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[784483.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d5bb0]
>[784483.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d5bb0] width 1600 pitch 6400 (/4 1600)
>[784483.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[784483.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[784484.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[784484.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[784484.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a4e0]
>[784484.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a4e0] width 1600 pitch 6400 (/4 1600)
>[784484.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[784484.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[784550.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784550.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784552.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[784552.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[784552.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3e60]
>[784552.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3e60] width 1600 pitch 6400 (/4 1600)
>[784566.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[784566.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[784566.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[784566.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[784567.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[784567.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[784568.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784568.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784568.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784568.317] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784568.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784568.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784568.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784568.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784568.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a2b0]
>[784568.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a2b0] width 1600 pitch 6400 (/4 1600)
>[784568.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784568.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784568.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784568.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784569.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[784569.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[784570.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784570.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784573.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a2b0]
>[784573.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a2b0] width 1600 pitch 6400 (/4 1600)
>[784573.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784573.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784573.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784573.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784573.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784573.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784573.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784573.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784573.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784573.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784573.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593a610]
>[784573.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593a610] width 1600 pitch 6400 (/4 1600)
>[784574.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784574.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784574.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784574.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784574.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784574.426] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784574.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593a610]
>[784574.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593a610] width 1600 pitch 6400 (/4 1600)
>[784574.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784574.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784577.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784577.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784577.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x593a610]
>[784577.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x593a610] width 1600 pitch 6400 (/4 1600)
>[784577.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a2b0]
>[784578.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a2b0] width 1600 pitch 6400 (/4 1600)
>[784578.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784578.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784578.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a2b0]
>[784578.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a2b0] width 1600 pitch 6400 (/4 1600)
>[784578.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784578.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784578.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784578.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784578.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784578.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784598.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951780]
>[784598.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951780] width 1600 pitch 6400 (/4 1600)
>[784662.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x364c7a0]
>[784662.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x364c7a0] width 1600 pitch 6400 (/4 1600)
>[784664.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784664.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784664.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784664.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784664.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398a2b0]
>[784664.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398a2b0] width 1600 pitch 6400 (/4 1600)
>[784664.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784664.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784664.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[784664.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[784664.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784664.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784664.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784665.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784665.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951820]
>[784665.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951820] width 1600 pitch 6400 (/4 1600)
>[784665.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[784665.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[784665.501] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784665.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784665.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784665.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784665.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784665.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784665.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784665.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784665.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784665.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784665.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951820]
>[784665.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951820] width 1600 pitch 6400 (/4 1600)
>[784665.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[784665.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[784666.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[784666.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[784700.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[784701.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[784701.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784701.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784701.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784701.696] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784701.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784702.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784702.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[784702.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[784702.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37fdd20]
>[784702.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37fdd20] width 1600 pitch 6400 (/4 1600)
>[784702.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784702.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784702.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784702.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784702.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[784703.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[784703.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x597e910]
>[784703.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x597e910] width 1600 pitch 6400 (/4 1600)
>[784703.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784703.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784704.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[784704.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[784704.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784704.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784704.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784704.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784704.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[784704.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[784704.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784704.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784704.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784704.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784705.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784705.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784705.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[784705.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[784705.318] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784705.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784705.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[784705.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[784705.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[784705.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[784705.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784705.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784705.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[784705.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[784705.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[784705.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[784706.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[784706.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[784707.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784707.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784707.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[784707.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[784708.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b673c0]
>[784708.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b673c0] width 1600 pitch 6400 (/4 1600)
>[784708.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ec1d00]
>[784709.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ec1d00] width 1600 pitch 6400 (/4 1600)
>[784709.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[784709.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[784709.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ac66b0]
>[784709.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ac66b0] width 1600 pitch 6400 (/4 1600)
>[784709.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed680]
>[784709.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed680] width 1600 pitch 6400 (/4 1600)
>[784709.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x263f800]
>[784709.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x263f800] width 1600 pitch 6400 (/4 1600)
>[784709.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d96630]
>[784709.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d96630] width 1600 pitch 6400 (/4 1600)
>[784709.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6821df0]
>[784709.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6821df0] width 1600 pitch 6400 (/4 1600)
>[784710.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f367e0]
>[784710.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f367e0] width 1600 pitch 6400 (/4 1600)
>[784710.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6dce0]
>[784710.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6dce0] width 1600 pitch 6400 (/4 1600)
>[784710.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c50f50]
>[784710.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c50f50] width 1600 pitch 6400 (/4 1600)
>[784710.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3809760]
>[784710.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3809760] width 1600 pitch 6400 (/4 1600)
>[784835.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[784835.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[784835.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd78d0]
>[784835.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd78d0] width 1600 pitch 6400 (/4 1600)
>[784836.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804dd0]
>[784836.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804dd0] width 1600 pitch 6400 (/4 1600)
>[784836.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804dd0]
>[784836.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804dd0] width 1600 pitch 6400 (/4 1600)
>[784836.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804dd0]
>[784836.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804dd0] width 1600 pitch 6400 (/4 1600)
>[784837.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804dd0]
>[784837.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804dd0] width 1600 pitch 6400 (/4 1600)
>[784837.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784838.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784838.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784838.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784838.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784838.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784838.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[784838.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[784839.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784839.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784839.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784839.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784840.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3804dd0]
>[784840.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3804dd0] width 1600 pitch 6400 (/4 1600)
>[784840.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c20ef0]
>[784840.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c20ef0] width 1600 pitch 6400 (/4 1600)
>[784840.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[784840.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[784841.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd78d0]
>[784841.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd78d0] width 1600 pitch 6400 (/4 1600)
>[784842.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48896d0]
>[784842.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48896d0] width 1600 pitch 6400 (/4 1600)
>[784842.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883520]
>[784842.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883520] width 1600 pitch 6400 (/4 1600)
>[784843.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f771f0]
>[784843.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f771f0] width 1600 pitch 6400 (/4 1600)
>[784843.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b3e8b0]
>[784843.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b3e8b0] width 1600 pitch 6400 (/4 1600)
>[784844.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35de7f0]
>[784844.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35de7f0] width 1600 pitch 6400 (/4 1600)
>[784844.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ab7a0]
>[784844.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ab7a0] width 1600 pitch 6400 (/4 1600)
>[784844.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f73dd0]
>[784844.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f73dd0] width 1600 pitch 6400 (/4 1600)
>[784844.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f73dd0]
>[784844.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f73dd0] width 1600 pitch 6400 (/4 1600)
>[784847.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f73dd0]
>[784847.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f73dd0] width 1600 pitch 6400 (/4 1600)
>[784847.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f046a0]
>[784847.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f046a0] width 1600 pitch 6400 (/4 1600)
>[784850.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[784850.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[784850.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[784851.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[784851.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784851.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784851.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[784851.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[784854.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[784854.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[784854.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[784854.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[784854.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784854.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784854.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784854.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784858.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[784858.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[784883.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b74b0]
>[784883.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b74b0] width 1600 pitch 6400 (/4 1600)
>[784891.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784891.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784891.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b24250]
>[784891.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b24250] width 1600 pitch 6400 (/4 1600)
>[784891.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784891.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784891.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784891.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784892.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[784892.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[784892.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951820]
>[784892.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951820] width 1600 pitch 6400 (/4 1600)
>[784892.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784892.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784892.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b5c0]
>[784892.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b5c0] width 1600 pitch 6400 (/4 1600)
>[784892.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[784892.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[784892.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4b5c0]
>[784892.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4b5c0] width 1600 pitch 6400 (/4 1600)
>[784892.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a7c0]
>[784892.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a7c0] width 1600 pitch 6400 (/4 1600)
>[784893.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48afb20]
>[784893.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48afb20] width 1600 pitch 6400 (/4 1600)
>[784893.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59af8b0]
>[784893.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59af8b0] width 1600 pitch 6400 (/4 1600)
>[784893.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4865f90]
>[784893.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4865f90] width 1600 pitch 6400 (/4 1600)
>[784893.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951820]
>[784893.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951820] width 1600 pitch 6400 (/4 1600)
>[784893.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[784893.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[784893.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[784893.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[784893.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a87f0]
>[784893.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a87f0] width 1600 pitch 6400 (/4 1600)
>[785230.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785230.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785230.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[785230.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[785231.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785231.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785231.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785231.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785231.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785231.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785231.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785231.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785231.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785231.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785231.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785232.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785232.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785232.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785232.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785232.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785232.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785232.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785233.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785233.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785233.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785233.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785234.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[785234.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[785234.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785234.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785234.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785234.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785234.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[785234.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[785234.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ea5870]
>[785235.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ea5870] width 1600 pitch 6400 (/4 1600)
>[785235.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785235.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785235.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x477fcf0]
>[785235.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x477fcf0] width 1600 pitch 6400 (/4 1600)
>[785236.078] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785236.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785236.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785236.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785236.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785236.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785238.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785238.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785238.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785238.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785238.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a24690]
>[785238.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a24690] width 1600 pitch 6400 (/4 1600)
>[785238.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd53b0]
>[785238.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd53b0] width 1600 pitch 6400 (/4 1600)
>[785238.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785238.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785238.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785238.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785238.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785238.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785238.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd53b0]
>[785238.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd53b0] width 1600 pitch 6400 (/4 1600)
>[785253.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785253.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785253.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785253.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785253.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3e60]
>[785253.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3e60] width 1600 pitch 6400 (/4 1600)
>[785253.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785253.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785253.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f3e60]
>[785253.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f3e60] width 1600 pitch 6400 (/4 1600)
>[785256.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[785256.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1600 pitch 6400 (/4 1600)
>[785257.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785257.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785258.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785258.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785258.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785258.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785258.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785258.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785258.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785258.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785259.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a49e0]
>[785259.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a49e0] width 1600 pitch 6400 (/4 1600)
>[785259.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785259.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785259.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[785259.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[785259.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785259.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785259.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785259.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785259.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38f5e30]
>[785259.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38f5e30] width 1600 pitch 6400 (/4 1600)
>[785272.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785272.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785272.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785272.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785272.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785273.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785273.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785273.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785273.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f046a0]
>[785273.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f046a0] width 1600 pitch 6400 (/4 1600)
>[785273.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785273.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785295.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[785296.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1600 pitch 6400 (/4 1600)
>[785296.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785296.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785296.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785296.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785297.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785297.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785297.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785297.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785297.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785297.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785298.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37a49e0]
>[785298.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37a49e0] width 1600 pitch 6400 (/4 1600)
>[785298.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785298.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785299.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785299.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785299.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785299.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785299.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785300.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785300.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785300.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785300.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[785300.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[785301.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785301.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785301.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785301.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785301.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785301.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785302.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[785302.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[785302.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[785302.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[785302.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785302.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785303.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785303.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785304.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785304.475] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785304.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785304.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785362.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd01a0]
>[785362.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd01a0] width 1600 pitch 6400 (/4 1600)
>[785363.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785363.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785363.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785363.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785363.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785363.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785363.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785363.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785363.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785363.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785365.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785365.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785365.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785365.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785365.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785365.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785365.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785365.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785366.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa50]
>[785366.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa50] width 1600 pitch 6400 (/4 1600)
>[785366.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[785366.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[785366.479] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bfb0]
>[785366.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bfb0] width 1600 pitch 6400 (/4 1600)
>[785366.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785366.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785375.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785375.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785375.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785375.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785375.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785375.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785375.487] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785375.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785375.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496d820]
>[785375.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496d820] width 1600 pitch 6400 (/4 1600)
>[785375.601] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785375.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785375.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496d820]
>[785375.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496d820] width 1600 pitch 6400 (/4 1600)
>[785375.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785375.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785384.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785384.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785384.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785384.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785384.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785384.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785384.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785384.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785384.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785384.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785384.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d9fa50]
>[785384.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d9fa50] width 1600 pitch 6400 (/4 1600)
>[785384.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57aee90]
>[785384.650] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57aee90] width 1600 pitch 6400 (/4 1600)
>[785388.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585eb40]
>[785388.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585eb40] width 1600 pitch 6400 (/4 1600)
>[785388.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57aee90]
>[785388.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57aee90] width 1600 pitch 6400 (/4 1600)
>[785388.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585eb40]
>[785388.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585eb40] width 1600 pitch 6400 (/4 1600)
>[785388.369] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57aee90]
>[785388.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57aee90] width 1600 pitch 6400 (/4 1600)
>[785388.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585eb40]
>[785388.431] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585eb40] width 1600 pitch 6400 (/4 1600)
>[785388.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57aee90]
>[785388.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57aee90] width 1600 pitch 6400 (/4 1600)
>[785388.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x585eb40]
>[785388.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x585eb40] width 1600 pitch 6400 (/4 1600)
>[785388.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57aee90]
>[785388.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57aee90] width 1600 pitch 6400 (/4 1600)
>[785392.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785392.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785392.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd01a0]
>[785392.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd01a0] width 1600 pitch 6400 (/4 1600)
>[785392.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785392.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785392.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785392.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785392.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785392.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785392.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785392.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785395.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785395.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785396.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785396.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785396.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785396.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785396.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785396.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785396.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785396.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785396.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[785396.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[785396.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785396.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785396.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785396.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785396.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785396.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785397.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785397.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785397.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785397.141] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785398.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785398.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785398.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785398.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785398.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785398.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785398.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785398.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785398.843] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[785398.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[785398.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785398.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785398.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[785399.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[785403.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785403.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785403.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785403.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785403.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785404.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785404.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[785404.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[785404.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785404.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785404.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[785404.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[785404.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785404.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785404.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[785404.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[785404.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[785404.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[785404.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388b890]
>[785404.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388b890] width 1600 pitch 6400 (/4 1600)
>[785465.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[785466.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[785466.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[785466.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[785466.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785466.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785466.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785466.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785466.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785466.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785466.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785467.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785467.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785467.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785467.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785467.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785467.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785467.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785468.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785468.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785468.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785468.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785468.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785468.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785483.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[785483.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[785483.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785483.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785484.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc4ad0]
>[785484.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc4ad0] width 1600 pitch 6400 (/4 1600)
>[785484.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785484.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785484.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[785484.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1600 pitch 6400 (/4 1600)
>[785484.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785485.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785485.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e757e0]
>[785485.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e757e0] width 1600 pitch 6400 (/4 1600)
>[785485.530] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35de7f0]
>[785485.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35de7f0] width 1600 pitch 6400 (/4 1600)
>[785485.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785485.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785485.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[785485.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[785485.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785486.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785486.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785486.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785486.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785486.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785487.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785487.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785488.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785488.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785488.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785488.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785488.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785488.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785488.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[785488.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[785488.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785488.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785488.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388b890]
>[785489.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388b890] width 1600 pitch 6400 (/4 1600)
>[785494.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785494.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785494.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785494.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785494.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785494.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785494.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785495.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785495.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785495.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785495.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785495.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785495.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785495.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785495.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[785495.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[785496.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785496.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785496.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd01a0]
>[785496.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd01a0] width 1600 pitch 6400 (/4 1600)
>[785496.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785496.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785496.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[785496.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1600 pitch 6400 (/4 1600)
>[785496.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785496.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785496.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e757e0]
>[785496.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e757e0] width 1600 pitch 6400 (/4 1600)
>[785497.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785497.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785497.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd78d0]
>[785497.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd78d0] width 1600 pitch 6400 (/4 1600)
>[785497.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[785498.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[785541.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785541.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785541.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785541.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785541.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785541.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785541.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785541.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785541.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785541.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785541.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785541.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785541.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[785542.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[785542.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785542.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785542.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785542.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785542.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785542.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785542.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785542.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785542.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785542.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785542.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785542.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785542.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785542.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785542.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[785542.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[785542.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785542.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785542.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785542.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785542.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785542.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785543.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785543.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785543.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785543.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785543.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785543.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785544.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785544.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785544.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785544.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785544.467] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785544.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785544.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785544.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785544.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785544.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785545.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785545.065] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785545.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785545.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785545.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785545.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785558.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785558.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785558.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df45f0]
>[785558.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df45f0] width 1600 pitch 6400 (/4 1600)
>[785558.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785559.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785559.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785559.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785559.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df45f0]
>[785559.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df45f0] width 1600 pitch 6400 (/4 1600)
>[785559.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58360]
>[785559.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58360] width 1600 pitch 6400 (/4 1600)
>[785559.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785559.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785559.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58360]
>[785559.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58360] width 1600 pitch 6400 (/4 1600)
>[785559.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785559.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785559.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b58360]
>[785559.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b58360] width 1600 pitch 6400 (/4 1600)
>[785559.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785559.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785559.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785559.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785559.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785559.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785560.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785560.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785560.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785560.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785576.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785576.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785576.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785576.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785576.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785576.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785576.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785577.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785577.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[785577.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[785577.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785577.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785577.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785577.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785577.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785577.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785583.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785583.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785583.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785583.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785583.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785583.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785583.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785583.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785583.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785583.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785583.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785583.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785587.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785587.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785587.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785587.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785587.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785587.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785587.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785587.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785587.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785587.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785587.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785587.945] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785588.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785588.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785588.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785588.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785588.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785588.430] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785592.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785592.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785592.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785593.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785593.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785593.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785593.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785593.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785597.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785597.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785597.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[785598.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[785598.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785598.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785598.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785598.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785598.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785598.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785603.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785603.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785603.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785603.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785603.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785603.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785603.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785603.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785603.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785603.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785603.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785603.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785608.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[785608.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[785608.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785608.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785608.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785608.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785608.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785608.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785613.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785614.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785614.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785614.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785614.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785614.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785614.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785614.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785614.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785614.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785614.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785614.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785615.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785615.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785615.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785615.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785615.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[785615.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[785615.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785615.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785615.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785615.837] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785615.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785616.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785616.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785616.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785616.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785616.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785616.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785616.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785619.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785619.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785619.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785619.647] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785619.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785619.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785619.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785619.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785620.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785620.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785620.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785620.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785620.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785620.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785620.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785620.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785621.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785621.184] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785621.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785621.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785621.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785621.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785621.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785621.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785621.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785621.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785623.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785623.643] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785624.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785624.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785624.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785624.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785624.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785624.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785624.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785624.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785624.672] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785624.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785627.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785627.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785627.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785627.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785627.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785627.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785627.482] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785627.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785627.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785627.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785627.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785627.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785627.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785627.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785627.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785627.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785630.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785630.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785630.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785630.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785631.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785631.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785631.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785631.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785631.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785631.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785631.314] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785631.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785633.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b673c0]
>[785633.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b673c0] width 1600 pitch 6400 (/4 1600)
>[785633.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785633.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785633.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785634.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785634.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785634.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785634.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785634.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785634.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785634.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785634.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785634.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785634.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785634.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785635.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785635.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785635.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785635.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785635.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785635.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785635.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e757e0]
>[785635.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e757e0] width 1600 pitch 6400 (/4 1600)
>[785635.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785635.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785635.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[785635.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[785636.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b673c0]
>[785636.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b673c0] width 1600 pitch 6400 (/4 1600)
>[785636.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785636.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785636.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785636.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785636.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785636.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785636.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785636.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785637.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[785637.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[785637.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785637.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785637.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785637.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785637.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785637.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785637.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785637.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785637.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785637.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785638.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785638.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785638.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785638.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785644.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785644.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785644.451] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785644.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785644.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785644.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785644.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785644.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785644.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785645.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785645.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785645.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785645.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785645.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785645.473] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785645.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785645.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785645.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785645.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785645.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785645.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785645.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785645.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785645.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785646.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785646.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785646.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785646.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785646.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785646.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785646.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785646.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785646.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785646.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785646.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785647.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785647.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785647.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785647.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785647.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785648.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785648.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785648.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785648.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785648.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785648.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785648.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785648.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785648.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785648.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785648.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785648.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785648.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785648.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785648.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785648.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785648.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785648.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785650.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785650.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785650.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[785650.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[785650.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785650.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785650.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785650.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785651.018] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785651.063] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785651.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785651.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785651.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785651.264] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785651.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785651.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785651.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785651.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785651.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785651.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785653.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785653.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785653.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785653.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785654.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785654.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785654.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785654.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785654.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785654.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785654.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785654.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785654.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785654.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785654.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785654.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785656.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785656.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785656.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785656.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785656.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785657.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785657.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785657.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785657.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785657.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785664.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785664.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785664.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[785664.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[785670.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785670.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785670.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785670.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785670.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785670.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785670.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785670.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785670.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785670.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785670.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785670.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785671.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785671.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785671.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785671.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785671.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785671.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785671.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785671.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785671.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785671.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785672.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785672.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785672.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785672.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785672.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785672.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785679.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785679.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785689.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785689.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785689.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785689.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785689.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785689.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785690.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785690.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785690.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785690.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785690.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785690.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785690.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785690.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785690.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785690.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785690.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785690.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785690.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785690.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785706.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785707.029] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785707.032] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785707.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785707.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785707.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785707.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785707.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785707.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785707.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785707.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785707.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785713.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785713.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785713.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785713.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785713.868] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785713.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785713.901] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785713.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785713.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[785713.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[785714.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785714.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785714.112] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785714.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785714.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785714.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785734.858] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785734.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785734.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785734.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785734.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785735.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785735.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785735.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785735.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785735.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785735.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785735.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785737.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785737.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785738.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785738.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785738.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785738.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785751.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785751.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785751.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[785751.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[785751.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785751.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785751.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785751.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785751.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785751.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785751.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785751.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785752.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785752.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785752.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[785752.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[785752.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785752.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785752.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785752.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785752.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785752.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785752.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785752.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785753.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785753.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785753.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e757e0]
>[785753.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e757e0] width 1600 pitch 6400 (/4 1600)
>[785753.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785753.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785753.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[785753.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[785753.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[785753.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[785753.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[785754.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[785754.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[785754.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[785754.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785754.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785754.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785754.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785754.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785754.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785755.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785755.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785755.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785755.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785755.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[785755.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[785755.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785755.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785755.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785755.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785755.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785755.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785755.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785755.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785755.999] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785756.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785756.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785756.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785756.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785756.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785756.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785756.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785757.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[785757.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[785757.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785757.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785757.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785757.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785757.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785757.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785757.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785758.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785758.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785758.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785758.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785758.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785758.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785758.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785758.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785758.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785758.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b30ef0]
>[785758.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b30ef0] width 1600 pitch 6400 (/4 1600)
>[785758.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785758.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785758.452] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785758.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785759.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785759.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785759.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785759.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785759.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785759.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785759.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785759.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785759.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785759.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785759.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785759.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785760.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785760.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785760.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785760.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785760.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785760.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785760.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785760.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785760.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[785760.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[785760.661] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785760.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785760.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be20d0]
>[785760.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be20d0] width 1600 pitch 6400 (/4 1600)
>[785760.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[785760.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[785760.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b673c0]
>[785760.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b673c0] width 1600 pitch 6400 (/4 1600)
>[785760.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[785761.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[785761.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[785761.190] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[785761.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785761.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785761.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[785761.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[785761.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785761.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785761.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785761.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785761.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785761.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785761.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785761.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785761.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785761.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785761.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785761.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785761.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785761.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785762.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785762.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785762.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[785762.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[785762.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[785762.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[785762.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785762.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785762.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785762.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785762.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[785762.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[785762.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785762.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785762.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785762.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785763.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785763.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785763.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[785763.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[785763.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785763.513] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785763.645] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785763.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785763.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[785763.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[785763.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785763.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785764.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[785764.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[785764.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785764.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785764.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785764.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785764.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785764.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785764.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785764.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785764.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785764.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785764.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785764.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785764.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785764.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785766.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[785766.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[785766.910] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785766.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785766.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[785767.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[785767.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785767.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785767.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[785767.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[785767.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[785767.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[785767.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785767.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785767.399] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785767.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785767.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785767.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785767.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785767.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785806.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[785806.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[785806.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785807.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785807.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6879120]
>[785807.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6879120] width 1600 pitch 6400 (/4 1600)
>[785807.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785807.196] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785811.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x24e6b50]
>[785811.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x24e6b50] width 1600 pitch 6400 (/4 1600)
>[785811.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785811.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785811.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785811.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785811.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785811.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785811.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785811.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785811.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785811.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785812.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785812.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785812.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785812.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785812.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785812.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785812.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785812.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785812.414] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785812.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785816.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785816.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785816.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785816.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785816.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785816.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785816.609] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[785816.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[785816.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b48d0]
>[785816.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b48d0] width 1600 pitch 6400 (/4 1600)
>[785821.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[785821.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[785821.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785821.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785821.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[785821.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[785821.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785821.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785825.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785825.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785826.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[785826.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[785826.107] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[785826.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[785826.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6735fa0]
>[785826.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6735fa0] width 1600 pitch 6400 (/4 1600)
>[785826.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85bb0]
>[785826.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85bb0] width 1600 pitch 6400 (/4 1600)
>[785826.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[785826.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[785826.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d9f770]
>[785826.731] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d9f770] width 1600 pitch 6400 (/4 1600)
>[785829.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[785829.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[785829.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[785829.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[785829.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785829.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785829.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785829.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785829.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785829.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785830.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x287f210]
>[785830.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x287f210] width 1600 pitch 6400 (/4 1600)
>[785830.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785830.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785830.740] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[785830.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[785830.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497cf00]
>[785831.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497cf00] width 1600 pitch 6400 (/4 1600)
>[785831.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[785831.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[785913.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[785914.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[785914.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785914.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785914.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[785914.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[785915.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[785915.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[785915.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785915.768] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785916.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[785916.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[785916.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[785916.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[785916.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[785916.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[785916.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785916.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785916.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[785916.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[785916.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[785916.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[785916.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[785916.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[785916.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[785916.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[785916.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785916.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[785916.860] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785916.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785916.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785916.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785916.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[785916.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[785917.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[785917.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[785917.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[785917.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[785917.229] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[785917.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[785917.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[785917.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[785917.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785917.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785918.010] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[785918.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[785952.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[785952.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[785952.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a2ac0]
>[785952.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a2ac0] width 1600 pitch 6400 (/4 1600)
>[785967.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[785967.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[785967.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[785967.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[785975.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2859570]
>[785975.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2859570] width 1600 pitch 6400 (/4 1600)
>[785975.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[785975.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[785985.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bfb0]
>[785985.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bfb0] width 1600 pitch 6400 (/4 1600)
>[785985.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a622a0]
>[785985.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a622a0] width 1600 pitch 6400 (/4 1600)
>[786057.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[786057.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[786057.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[786057.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[786057.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[786057.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[786057.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[786058.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[786058.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[786058.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[786058.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[786058.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[786058.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[786058.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[786058.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[786058.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[786058.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59ee9a0]
>[786058.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59ee9a0] width 1600 pitch 6400 (/4 1600)
>[786058.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[786058.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[786058.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[786058.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[786058.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[786058.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[786058.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x512e5a0]
>[786058.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x512e5a0] width 1600 pitch 6400 (/4 1600)
>[786058.762] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36d71f0]
>[786058.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36d71f0] width 1600 pitch 6400 (/4 1600)
>[786058.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786059.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786065.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[786065.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[786065.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[786065.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[786065.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[786065.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[786065.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[786065.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[786065.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[786065.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[786065.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[786065.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[786066.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[786066.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[786067.027] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d6230]
>[786067.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d6230] width 1600 pitch 6400 (/4 1600)
>[786067.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[786067.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[786067.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[786067.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[786067.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[786067.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[786067.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786067.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786067.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[786067.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[786067.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786067.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786067.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[786067.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[786067.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[786067.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[786067.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[786067.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[786067.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786067.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786067.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[786067.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[786067.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[786067.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[786067.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[786067.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[786067.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786067.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786067.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[786067.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[786067.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786068.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786068.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[786068.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[786068.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786068.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786068.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[786068.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[786068.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[786068.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[786069.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[786069.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[786069.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[786069.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[786069.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786069.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786084.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[786084.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[786093.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[786093.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[786093.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f217d0]
>[786093.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f217d0] width 1600 pitch 6400 (/4 1600)
>[786111.516] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3632500]
>[786111.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3632500] width 1600 pitch 6400 (/4 1600)
>[786111.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[786111.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[786111.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388b890]
>[786111.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388b890] width 1600 pitch 6400 (/4 1600)
>[786111.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[786111.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[786112.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[786112.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[786112.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786112.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786112.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[786112.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[786112.781] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a0270]
>[786112.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a0270] width 1600 pitch 6400 (/4 1600)
>[786112.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58987c0]
>[786112.910] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58987c0] width 1600 pitch 6400 (/4 1600)
>[786112.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eccd50]
>[786112.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eccd50] width 1600 pitch 6400 (/4 1600)
>[786113.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786113.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786113.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[786113.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[786113.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786113.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786113.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[786113.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[786113.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786113.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786113.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[786113.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[786114.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[786114.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[786114.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[786115.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[786115.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786115.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786115.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[786115.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[786149.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786149.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786149.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[786149.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[786149.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786149.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786149.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf1a10]
>[786149.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf1a10] width 1600 pitch 6400 (/4 1600)
>[786150.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[786150.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[786150.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[786151.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[786151.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[786151.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[786151.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786151.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786151.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[786151.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[786151.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786151.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786151.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49725d0]
>[786151.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49725d0] width 1600 pitch 6400 (/4 1600)
>[786151.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[786151.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[786152.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f1a980]
>[786152.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f1a980] width 1600 pitch 6400 (/4 1600)
>[786152.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786152.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786152.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786152.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786152.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786152.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786152.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[786152.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[786152.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[786152.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[786153.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bfb0]
>[786153.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bfb0] width 1600 pitch 6400 (/4 1600)
>[786153.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786153.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786153.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[786153.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[786153.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f21ed0]
>[786153.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f21ed0] width 1600 pitch 6400 (/4 1600)
>[786155.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3774f10]
>[786155.397] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3774f10] width 1600 pitch 6400 (/4 1600)
>[786155.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[786155.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[786155.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92c50]
>[786155.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92c50] width 1600 pitch 6400 (/4 1600)
>[786155.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786155.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786155.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786155.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786155.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[786155.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[786155.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786155.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786156.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b12e0]
>[786156.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b12e0] width 1600 pitch 6400 (/4 1600)
>[786156.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[786156.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[786156.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bfb0]
>[786156.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bfb0] width 1600 pitch 6400 (/4 1600)
>[786156.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786156.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786156.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[786157.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[786157.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[786157.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[786157.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92c50]
>[786157.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92c50] width 1600 pitch 6400 (/4 1600)
>[786157.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786157.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786158.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[786158.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[786158.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786159.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786159.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e92c50]
>[786159.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e92c50] width 1600 pitch 6400 (/4 1600)
>[786161.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[786161.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[786161.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[786161.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[786162.859] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588cd70]
>[786162.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588cd70] width 1600 pitch 6400 (/4 1600)
>[786163.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786163.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786163.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[786163.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[786163.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eccd50]
>[786163.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eccd50] width 1600 pitch 6400 (/4 1600)
>[786164.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f112f0]
>[786164.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f112f0] width 1600 pitch 6400 (/4 1600)
>[786165.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[786165.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[786165.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a84a0]
>[786165.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a84a0] width 1600 pitch 6400 (/4 1600)
>[786166.211] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[786166.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[786166.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[786166.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[786166.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58ca460]
>[786166.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58ca460] width 1600 pitch 6400 (/4 1600)
>[786166.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388b890]
>[786166.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388b890] width 1600 pitch 6400 (/4 1600)
>[786166.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4964510]
>[786166.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4964510] width 1600 pitch 6400 (/4 1600)
>[786166.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786166.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786166.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[786166.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[786166.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786166.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786166.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786167.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786167.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786167.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786167.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786167.121] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786171.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[786171.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[786171.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[786171.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1600 pitch 6400 (/4 1600)
>[786171.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786171.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786171.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[786171.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1600 pitch 6400 (/4 1600)
>[786171.270] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786171.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786171.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786171.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786171.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786171.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786171.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786171.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786171.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9c60]
>[786171.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9c60] width 1600 pitch 6400 (/4 1600)
>[786171.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[786171.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[786171.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b3bfb0]
>[786172.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b3bfb0] width 1600 pitch 6400 (/4 1600)
>[786172.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[786172.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[786172.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2ba10]
>[786172.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2ba10] width 1600 pitch 6400 (/4 1600)
>[786172.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[786172.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[786176.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786176.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786176.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[786176.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[786176.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786176.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786176.298] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[786176.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[786176.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786176.412] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786176.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786176.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786176.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786176.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786176.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786176.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786179.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786179.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786179.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786179.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786179.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf2a60]
>[786179.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf2a60] width 1600 pitch 6400 (/4 1600)
>[786179.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786179.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786180.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[786180.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[786180.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[786180.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[786180.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[786180.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[786180.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[786180.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[786180.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786180.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786180.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[786180.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[786187.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[786187.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[786187.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786187.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786526.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786527.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786527.052] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c19950]
>[786527.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c19950] width 1600 pitch 6400 (/4 1600)
>[786527.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786527.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786527.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786527.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786527.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9e10]
>[786527.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9e10] width 1600 pitch 6400 (/4 1600)
>[786527.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[786527.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[786527.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672bf00]
>[786527.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672bf00] width 1600 pitch 6400 (/4 1600)
>[786527.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5918180]
>[786527.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5918180] width 1600 pitch 6400 (/4 1600)
>[786527.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[786527.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[786527.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786527.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786527.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4e30]
>[786527.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4e30] width 1600 pitch 6400 (/4 1600)
>[786527.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786527.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786527.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786527.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786527.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[786528.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[786528.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[786528.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[786528.098] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958430]
>[786528.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958430] width 1600 pitch 6400 (/4 1600)
>[786528.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[786528.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[786528.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[786528.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[786528.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786528.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786528.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786528.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786528.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786528.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786528.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043c70]
>[786528.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043c70] width 1600 pitch 6400 (/4 1600)
>[786528.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786528.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786528.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786528.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786528.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786528.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786528.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3645eb0]
>[786529.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3645eb0] width 1600 pitch 6400 (/4 1600)
>[786532.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[786532.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[786533.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786533.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786533.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[786533.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[786534.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786534.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786534.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4e30]
>[786534.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4e30] width 1600 pitch 6400 (/4 1600)
>[786534.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786534.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786534.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4e30]
>[786534.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4e30] width 1600 pitch 6400 (/4 1600)
>[786534.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49730a0]
>[786534.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49730a0] width 1600 pitch 6400 (/4 1600)
>[786534.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4e30]
>[786534.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4e30] width 1600 pitch 6400 (/4 1600)
>[786534.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958430]
>[786534.469] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958430] width 1600 pitch 6400 (/4 1600)
>[786534.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[786534.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[786534.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786534.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786534.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786535.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786535.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786535.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786535.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7940]
>[786535.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7940] width 1600 pitch 6400 (/4 1600)
>[786535.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[786535.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1600 pitch 6400 (/4 1600)
>[786535.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x25d3f20]
>[786535.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x25d3f20] width 1600 pitch 6400 (/4 1600)
>[786535.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[786535.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[786536.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3015cf0]
>[786536.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3015cf0] width 1600 pitch 6400 (/4 1600)
>[786536.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[786536.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[786536.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[786536.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[786536.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[786536.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[786536.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786536.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786536.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38eeeb0]
>[786537.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38eeeb0] width 1600 pitch 6400 (/4 1600)
>[786537.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[786537.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[786537.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786537.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786537.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786537.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786537.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786537.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786661.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dfd5c0]
>[786661.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dfd5c0] width 1600 pitch 6400 (/4 1600)
>[786661.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26ff0]
>[786661.457] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26ff0] width 1600 pitch 6400 (/4 1600)
>[786661.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590ecc0]
>[786661.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590ecc0] width 1600 pitch 6400 (/4 1600)
>[786661.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5c60]
>[786661.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5c60] width 1600 pitch 6400 (/4 1600)
>[786661.586] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[786661.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[786661.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786661.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786661.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[786661.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[786661.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786661.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786661.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[786661.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[786661.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786661.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786661.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[786662.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[786662.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[786662.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[786662.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[786662.109] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[786663.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786663.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786664.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786664.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786664.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x398bb80]
>[786664.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x398bb80] width 1600 pitch 6400 (/4 1600)
>[786664.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[786664.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[786664.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786664.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786671.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7940]
>[786671.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7940] width 1600 pitch 6400 (/4 1600)
>[786671.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786671.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786671.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[786671.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1600 pitch 6400 (/4 1600)
>[786677.836] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[786677.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[786677.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786677.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786678.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[786678.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[786678.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786678.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786678.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[786678.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[786678.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786678.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786678.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786678.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786679.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e32dd0]
>[786679.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e32dd0] width 1600 pitch 6400 (/4 1600)
>[786679.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[786679.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[786679.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7940]
>[786679.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7940] width 1600 pitch 6400 (/4 1600)
>[786679.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786679.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786679.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc0a60]
>[786679.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc0a60] width 1600 pitch 6400 (/4 1600)
>[786679.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c52c00]
>[786679.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c52c00] width 1600 pitch 6400 (/4 1600)
>[786679.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[786679.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[786686.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786686.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786686.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[786686.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[786686.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786687.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786687.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9c40]
>[786687.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9c40] width 1600 pitch 6400 (/4 1600)
>[786687.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3efe360]
>[786687.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3efe360] width 1600 pitch 6400 (/4 1600)
>[786687.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[786687.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[786687.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786687.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786687.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786687.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786688.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786688.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786688.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9c40]
>[786688.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9c40] width 1600 pitch 6400 (/4 1600)
>[786688.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[786688.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[786688.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043c70]
>[786688.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043c70] width 1600 pitch 6400 (/4 1600)
>[786688.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39774e0]
>[786688.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39774e0] width 1600 pitch 6400 (/4 1600)
>[786688.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786689.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786692.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786692.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786692.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786692.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786692.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[786693.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[786693.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[786693.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1600 pitch 6400 (/4 1600)
>[786693.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300ad60]
>[786693.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300ad60] width 1600 pitch 6400 (/4 1600)
>[786693.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c47270]
>[786693.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c47270] width 1600 pitch 6400 (/4 1600)
>[786701.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc500]
>[786701.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc500] width 1600 pitch 6400 (/4 1600)
>[786701.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[786701.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[786701.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786701.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786702.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7c540]
>[786702.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7c540] width 1600 pitch 6400 (/4 1600)
>[786702.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786702.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786702.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7c540]
>[786702.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7c540] width 1600 pitch 6400 (/4 1600)
>[786702.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf1ed0]
>[786702.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf1ed0] width 1600 pitch 6400 (/4 1600)
>[786706.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786706.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786706.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786706.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786706.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786706.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786706.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786706.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786717.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786717.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786717.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786717.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786717.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786717.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786717.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786717.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786717.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786717.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786717.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7c540]
>[786717.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7c540] width 1600 pitch 6400 (/4 1600)
>[786721.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786721.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786721.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786721.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786721.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786721.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786721.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786721.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786721.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786721.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786721.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786721.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786721.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786721.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786721.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786721.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786721.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786721.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786722.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786722.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786722.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786722.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786722.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786722.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786722.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786722.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786722.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786722.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786722.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786722.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786723.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786723.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786723.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786723.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786723.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786723.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786723.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786723.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786723.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786723.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786723.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786724.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786724.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786724.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786724.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786724.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786724.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786724.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786724.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786724.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786724.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786724.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786725.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786725.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786725.261] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786725.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786725.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786725.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786725.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786725.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786725.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786725.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786725.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786726.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786726.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786726.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786726.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786726.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786726.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786726.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786726.709] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786726.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786726.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786726.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786726.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786726.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786727.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786727.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786727.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786727.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786727.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786727.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786727.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786727.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786727.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786727.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786727.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786727.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786727.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786728.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786728.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786728.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786728.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786728.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786728.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786728.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786728.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786728.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786728.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786728.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786729.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786729.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786729.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786729.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786729.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786729.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786729.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786729.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786729.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786729.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786729.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786730.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786730.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786730.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786730.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786730.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786730.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786730.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786730.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786730.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786730.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786730.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786731.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786731.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786731.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786731.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786731.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786731.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786731.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786731.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786731.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786731.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786731.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786732.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786732.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786732.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786732.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786732.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786732.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786732.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786732.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786732.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786732.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6877090]
>[786732.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6877090] width 1600 pitch 6400 (/4 1600)
>[786733.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786733.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786733.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786733.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786733.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786733.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786733.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786733.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786733.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786733.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786733.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786734.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786734.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786734.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786734.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e020]
>[786734.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e020] width 1600 pitch 6400 (/4 1600)
>[786734.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786734.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786734.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786734.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786734.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df7800]
>[786734.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df7800] width 1600 pitch 6400 (/4 1600)
>[786735.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786735.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786735.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786735.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786735.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786735.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786735.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786735.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786735.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402db60]
>[786735.838] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402db60] width 1600 pitch 6400 (/4 1600)
>[786735.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786736.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786736.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786736.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786736.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786736.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786736.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786736.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786736.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786736.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786736.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786736.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786737.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786737.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786737.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786737.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786737.409] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786737.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786737.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786737.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786737.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786737.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786737.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786738.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786738.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[786738.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[786738.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786738.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786738.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786738.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786738.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786738.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786738.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786738.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786739.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786739.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786739.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e020]
>[786739.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e020] width 1600 pitch 6400 (/4 1600)
>[786739.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786739.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786739.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786739.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786739.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df7800]
>[786739.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df7800] width 1600 pitch 6400 (/4 1600)
>[786739.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786740.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786740.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786740.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786740.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786740.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786740.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786740.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786740.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402db60]
>[786740.734] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402db60] width 1600 pitch 6400 (/4 1600)
>[786740.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786740.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786741.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786741.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786741.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786741.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786741.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786741.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786741.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786741.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786741.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786741.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786741.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786742.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786742.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786742.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786768.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786768.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786768.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786768.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786768.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786768.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786768.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786769.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786769.028] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786769.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786769.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786769.093] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786769.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786769.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786769.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786769.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786769.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[786769.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[786769.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786769.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786769.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[786769.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[786773.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786773.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786773.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786773.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786773.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786773.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786773.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786773.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786773.458] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786773.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786773.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786773.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786773.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786773.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786773.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786773.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786773.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786773.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786773.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786773.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786774.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786774.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786774.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786774.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786774.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786774.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786774.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786774.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786774.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786774.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786774.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786775.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786775.155] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786775.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786775.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786775.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786775.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[786775.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[786775.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786775.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786775.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786775.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786776.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786776.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786776.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786776.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786776.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786776.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786776.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786776.664] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786776.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786776.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786776.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786777.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786777.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786777.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786777.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786777.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786777.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786777.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786777.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786777.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786777.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402db60]
>[786777.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402db60] width 1600 pitch 6400 (/4 1600)
>[786778.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786778.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786778.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786778.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786778.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786778.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786778.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786778.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786778.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786778.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786778.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786779.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786779.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786779.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786779.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786779.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786779.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786779.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786779.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786779.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786779.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786779.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786780.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786780.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786780.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786780.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786780.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[786780.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[786780.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786780.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786780.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786780.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786780.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786781.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786781.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786781.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786781.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786781.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786781.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786781.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786781.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786781.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786781.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786781.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786782.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786782.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786782.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786782.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786782.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786782.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786782.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786782.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786782.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402db60]
>[786782.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402db60] width 1600 pitch 6400 (/4 1600)
>[786782.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786783.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786783.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786783.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786783.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786783.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786783.495] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e649d0]
>[786783.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e649d0] width 1600 pitch 6400 (/4 1600)
>[786783.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786783.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786783.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786783.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786784.036] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786784.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786784.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd9d40]
>[786784.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd9d40] width 1600 pitch 6400 (/4 1600)
>[786784.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786784.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786784.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786784.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786784.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786784.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786784.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786784.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786784.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786785.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786785.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786785.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786785.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786785.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786785.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786785.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786785.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786785.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786785.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a25e20]
>[786785.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a25e20] width 1600 pitch 6400 (/4 1600)
>[786785.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786785.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786785.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786785.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786785.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786785.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786785.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[786785.988] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[786785.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786786.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786786.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786786.106] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786786.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786786.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786786.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786786.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786786.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786786.456] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786786.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786786.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786786.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786786.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786786.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786786.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786787.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786787.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786790.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786790.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786790.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786790.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786790.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786790.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786790.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786790.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786790.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786790.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786790.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786790.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786790.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786790.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786790.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df7800]
>[786790.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df7800] width 1600 pitch 6400 (/4 1600)
>[786790.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786790.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786857.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786857.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786857.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786857.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786857.967] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786857.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786858.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786858.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786858.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786858.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786858.118] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786858.147] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786858.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[786858.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[786858.425] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786858.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786858.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786858.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786858.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786858.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786861.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2e020]
>[786861.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2e020] width 1600 pitch 6400 (/4 1600)
>[786862.219] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786862.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786862.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786862.342] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786884.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786884.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786884.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[786884.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[786884.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786884.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786884.558] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786884.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786884.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786884.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786897.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786897.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786897.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786897.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786897.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786897.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786897.519] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786897.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786897.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28532f0]
>[786897.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28532f0] width 1600 pitch 6400 (/4 1600)
>[786897.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786897.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786897.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786897.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786897.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786897.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786898.017] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786898.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786898.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786898.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786898.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786898.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786898.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786898.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786898.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786898.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786898.303] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786898.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786898.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786898.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786898.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786898.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786898.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d974d0]
>[786898.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d974d0] width 1600 pitch 6400 (/4 1600)
>[786898.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786898.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786898.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786898.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786898.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786898.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786898.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786898.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786898.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786898.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786898.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786898.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786899.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[786899.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[786899.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f00f40]
>[786899.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f00f40] width 1600 pitch 6400 (/4 1600)
>[786899.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786899.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786899.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786899.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786899.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786899.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786899.981] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786900.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786900.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786900.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786900.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dffd80]
>[786900.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dffd80] width 1600 pitch 6400 (/4 1600)
>[786900.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786900.577] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786900.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786900.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786900.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786900.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786901.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786901.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786901.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[786901.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[786901.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786901.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786901.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786901.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786901.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786901.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786901.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786902.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786902.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786902.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786902.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786902.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786902.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786902.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786902.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786902.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786902.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786902.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786903.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786903.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786903.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786903.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786903.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786903.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786903.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786903.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786903.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[786903.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[786903.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786904.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786904.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786904.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786904.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786904.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786904.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786904.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786904.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786904.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786904.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786904.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786905.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786905.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786905.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786905.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786905.413] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786905.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786905.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4871340]
>[786905.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4871340] width 1600 pitch 6400 (/4 1600)
>[786905.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786905.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786905.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786906.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786906.147] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786906.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786906.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[786906.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[786906.507] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786906.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786906.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786906.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786906.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[786906.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[786907.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786907.111] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786907.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786907.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786907.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786907.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786907.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786907.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786907.775] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786907.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786907.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38efc70]
>[786908.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38efc70] width 1600 pitch 6400 (/4 1600)
>[786909.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bac100]
>[786909.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bac100] width 1600 pitch 6400 (/4 1600)
>[786909.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786909.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786915.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786915.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786916.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[786916.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[786916.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[786917.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[786917.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786917.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786917.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786917.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786917.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[786917.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[786917.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786917.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786917.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786917.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786917.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786917.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786917.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e2060]
>[786917.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e2060] width 1600 pitch 6400 (/4 1600)
>[786917.395] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bd5c60]
>[786917.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bd5c60] width 1600 pitch 6400 (/4 1600)
>[786917.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786917.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786917.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x686a4a0]
>[786917.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x686a4a0] width 1600 pitch 6400 (/4 1600)
>[786917.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786918.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786918.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[786918.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[786918.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[786918.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[786918.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[786918.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[786918.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388ae30]
>[786918.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388ae30] width 1600 pitch 6400 (/4 1600)
>[786918.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59dfe80]
>[786918.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59dfe80] width 1600 pitch 6400 (/4 1600)
>[786919.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf7280]
>[786919.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf7280] width 1600 pitch 6400 (/4 1600)
>[786919.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9490]
>[786919.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9490] width 1600 pitch 6400 (/4 1600)
>[786919.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786919.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786919.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[786919.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[786927.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[786927.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[786927.419] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[786927.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[786927.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50fc500]
>[786927.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50fc500] width 1600 pitch 6400 (/4 1600)
>[786927.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a1b440]
>[786927.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a1b440] width 1600 pitch 6400 (/4 1600)
>[786928.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786928.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786928.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786928.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786929.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f649d0]
>[786929.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f649d0] width 1600 pitch 6400 (/4 1600)
>[786929.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2eb0bf0]
>[786929.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2eb0bf0] width 1600 pitch 6400 (/4 1600)
>[786929.650] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[786929.720] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[786929.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[786929.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[786930.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fc65b0]
>[786930.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fc65b0] width 1600 pitch 6400 (/4 1600)
>[786930.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786930.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786930.585] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786930.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786930.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[786930.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[786930.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[786930.722] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[786930.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498d170]
>[786930.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498d170] width 1600 pitch 6400 (/4 1600)
>[786931.190] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ace020]
>[786931.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ace020] width 1600 pitch 6400 (/4 1600)
>[786936.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42860]
>[786936.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42860] width 1600 pitch 6400 (/4 1600)
>[786938.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5971280]
>[786938.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5971280] width 1600 pitch 6400 (/4 1600)
>[786938.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f99f80]
>[786938.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f99f80] width 1600 pitch 6400 (/4 1600)
>[786939.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a26d0]
>[786940.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a26d0] width 1600 pitch 6400 (/4 1600)
>[786940.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[786940.181] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[786940.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa60e0]
>[786940.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa60e0] width 1600 pitch 6400 (/4 1600)
>[786940.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[786940.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[786941.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef9f0]
>[786941.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef9f0] width 1600 pitch 6400 (/4 1600)
>[786941.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6c9b0]
>[786941.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6c9b0] width 1600 pitch 6400 (/4 1600)
>[786941.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[786942.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[786942.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f42860]
>[786942.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f42860] width 1600 pitch 6400 (/4 1600)
>[786945.589] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f206d0]
>[786945.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f206d0] width 1600 pitch 6400 (/4 1600)
>[786945.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[786945.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[786945.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e11370]
>[786945.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e11370] width 1600 pitch 6400 (/4 1600)
>[786946.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50ef9f0]
>[786946.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50ef9f0] width 1600 pitch 6400 (/4 1600)
>[786947.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c00]
>[786947.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c00] width 1600 pitch 6400 (/4 1600)
>[786947.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[786947.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[786947.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ec2580]
>[786947.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ec2580] width 1600 pitch 6400 (/4 1600)
>[786947.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a60e10]
>[786947.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a60e10] width 1600 pitch 6400 (/4 1600)
>[786947.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50eae70]
>[786948.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50eae70] width 1600 pitch 6400 (/4 1600)
>[786948.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c86dc0]
>[786948.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c86dc0] width 1600 pitch 6400 (/4 1600)
>[786949.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d16f0]
>[786949.231] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d16f0] width 1600 pitch 6400 (/4 1600)
>[786949.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c422c0]
>[786949.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c422c0] width 1600 pitch 6400 (/4 1600)
>[786949.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786949.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786949.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d3b0]
>[786949.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d3b0] width 1600 pitch 6400 (/4 1600)
>[786949.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786949.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786950.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786950.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786950.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786950.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786950.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.798] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786950.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786950.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4df1c20]
>[786950.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4df1c20] width 1600 pitch 6400 (/4 1600)
>[786950.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786950.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786950.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786951.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786951.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b4770]
>[786951.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b4770] width 1600 pitch 6400 (/4 1600)
>[786955.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7f40]
>[786955.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7f40] width 1600 pitch 6400 (/4 1600)
>[786957.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730d50]
>[786957.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730d50] width 1600 pitch 6400 (/4 1600)
>[786957.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786957.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786957.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730d50]
>[786958.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730d50] width 1600 pitch 6400 (/4 1600)
>[786958.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4889290]
>[786958.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4889290] width 1600 pitch 6400 (/4 1600)
>[786958.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786958.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786959.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730d50]
>[786959.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730d50] width 1600 pitch 6400 (/4 1600)
>[786959.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786959.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786959.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730d50]
>[786960.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730d50] width 1600 pitch 6400 (/4 1600)
>[786960.237] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786960.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786961.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786961.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786961.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786961.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786961.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6730d50]
>[786961.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6730d50] width 1600 pitch 6400 (/4 1600)
>[786961.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499a4d0]
>[786961.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499a4d0] width 1600 pitch 6400 (/4 1600)
>[786963.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[786963.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[786963.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0910]
>[786964.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0910] width 1600 pitch 6400 (/4 1600)
>[786964.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[786964.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[786964.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec83c0]
>[786964.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec83c0] width 1600 pitch 6400 (/4 1600)
>[786964.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0910]
>[786964.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0910] width 1600 pitch 6400 (/4 1600)
>[786965.309] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bab6d0]
>[786965.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bab6d0] width 1600 pitch 6400 (/4 1600)
>[786965.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886600]
>[786965.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886600] width 1600 pitch 6400 (/4 1600)
>[786966.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d7fa0]
>[786966.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d7fa0] width 1600 pitch 6400 (/4 1600)
>[786966.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[786966.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[786967.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d7fa0]
>[786967.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d7fa0] width 1600 pitch 6400 (/4 1600)
>[786967.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e07d0]
>[786967.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e07d0] width 1600 pitch 6400 (/4 1600)
>[786967.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59d7fa0]
>[786967.237] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59d7fa0] width 1600 pitch 6400 (/4 1600)
>[786967.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[786967.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[786967.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e07d0]
>[786967.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e07d0] width 1600 pitch 6400 (/4 1600)
>[787064.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec8110]
>[787064.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec8110] width 1600 pitch 6400 (/4 1600)
>[787064.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787064.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787065.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787065.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787065.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787065.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787065.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787065.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787066.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787066.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787066.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787066.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787066.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787066.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787066.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787066.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787066.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787067.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787067.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787067.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787067.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787067.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787067.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787068.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787068.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787068.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787068.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787068.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787069.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787069.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787069.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787088.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787088.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787088.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787088.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787088.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787088.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787088.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5360]
>[787088.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5360] width 1600 pitch 6400 (/4 1600)
>[787088.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787088.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787088.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc5360]
>[787088.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc5360] width 1600 pitch 6400 (/4 1600)
>[787088.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[787088.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[787088.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787088.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787088.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787088.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787091.776] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[787091.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[787091.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[787091.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[787093.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[787093.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[787093.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787093.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787094.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787094.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787094.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787094.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787095.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[787095.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[787095.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea9d20]
>[787095.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea9d20] width 1600 pitch 6400 (/4 1600)
>[787095.870] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787095.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787096.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023bb0]
>[787096.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023bb0] width 1600 pitch 6400 (/4 1600)
>[787096.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787096.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787096.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2fe20]
>[787096.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2fe20] width 1600 pitch 6400 (/4 1600)
>[787097.044] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[787097.099] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[787097.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e10480]
>[787097.182] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e10480] width 1600 pitch 6400 (/4 1600)
>[787097.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787097.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787097.418] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787097.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787100.979] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787101.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787101.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e10480]
>[787101.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e10480] width 1600 pitch 6400 (/4 1600)
>[787102.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787102.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787102.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0b7c0]
>[787102.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0b7c0] width 1600 pitch 6400 (/4 1600)
>[787103.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787103.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787103.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd2a00]
>[787103.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd2a00] width 1600 pitch 6400 (/4 1600)
>[787103.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36432e0]
>[787104.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36432e0] width 1600 pitch 6400 (/4 1600)
>[787104.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x498fa20]
>[787104.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x498fa20] width 1600 pitch 6400 (/4 1600)
>[787104.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3802220]
>[787104.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3802220] width 1600 pitch 6400 (/4 1600)
>[787104.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[787104.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[787104.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787104.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787104.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787104.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787104.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e940]
>[787104.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e940] width 1600 pitch 6400 (/4 1600)
>[787104.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49592c0]
>[787104.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49592c0] width 1600 pitch 6400 (/4 1600)
>[787104.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6e940]
>[787104.479] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6e940] width 1600 pitch 6400 (/4 1600)
>[787104.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787104.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787104.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[787104.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[787104.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787104.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787104.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4991800]
>[787104.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4991800] width 1600 pitch 6400 (/4 1600)
>[787104.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x377af40]
>[787104.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x377af40] width 1600 pitch 6400 (/4 1600)
>[787193.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28668d0]
>[787193.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28668d0] width 1600 pitch 6400 (/4 1600)
>[787193.667] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787193.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787195.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bba50]
>[787195.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bba50] width 1600 pitch 6400 (/4 1600)
>[787195.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bba50]
>[787195.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bba50] width 1600 pitch 6400 (/4 1600)
>[787195.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bba50]
>[787195.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bba50] width 1600 pitch 6400 (/4 1600)
>[787305.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787306.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787306.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787306.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787307.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787307.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787307.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787307.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787307.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380fc30]
>[787307.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380fc30] width 1600 pitch 6400 (/4 1600)
>[787308.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787308.194] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787308.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787308.261] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787308.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787308.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787313.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787313.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787313.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787313.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787314.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[787314.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[787315.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787315.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787315.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787315.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787315.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787315.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787316.124] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787316.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787316.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787316.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787316.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[787316.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[787316.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787316.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787316.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x284a940]
>[787316.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x284a940] width 1600 pitch 6400 (/4 1600)
>[787316.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787316.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787316.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787316.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787316.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787316.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787316.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[787316.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[787316.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787316.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787316.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787316.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787317.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787317.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787317.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[787317.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[787317.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787317.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787317.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787317.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787317.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787317.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787317.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787317.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787317.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787317.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787317.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68c9970]
>[787318.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68c9970] width 1600 pitch 6400 (/4 1600)
>[787318.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd1910]
>[787318.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd1910] width 1600 pitch 6400 (/4 1600)
>[787318.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea6280]
>[787319.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea6280] width 1600 pitch 6400 (/4 1600)
>[787319.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[787319.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[787319.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5886f30]
>[787319.707] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5886f30] width 1600 pitch 6400 (/4 1600)
>[787322.731] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49758c0]
>[787322.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49758c0] width 1600 pitch 6400 (/4 1600)
>[787324.460] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x678c060]
>[787324.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x678c060] width 1600 pitch 6400 (/4 1600)
>[787324.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efc0f0]
>[787324.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efc0f0] width 1600 pitch 6400 (/4 1600)
>[787335.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787335.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787335.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787335.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787335.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787335.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787335.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787335.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787335.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787335.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787335.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787335.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787335.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787335.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787335.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787335.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787335.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787335.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787335.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787335.900] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787335.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787336.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787336.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787336.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787336.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787336.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787336.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787336.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787336.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787336.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787336.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787336.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787336.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787336.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787336.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787336.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787336.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787336.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787337.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.141] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787337.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787337.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787337.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787337.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787337.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787337.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787337.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787337.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787338.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787338.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787338.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787338.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787338.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787338.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787338.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787338.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787338.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787338.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787338.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787338.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787338.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787338.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787338.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787338.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787338.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787339.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787339.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787339.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787339.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787339.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5340]
>[787339.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5340] width 1600 pitch 6400 (/4 1600)
>[787339.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787339.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787339.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f91a50]
>[787339.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f91a50] width 1600 pitch 6400 (/4 1600)
>[787347.000] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd360]
>[787347.062] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd360] width 1600 pitch 6400 (/4 1600)
>[787355.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x475df70]
>[787355.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x475df70] width 1600 pitch 6400 (/4 1600)
>[787367.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bbfe0]
>[787367.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bbfe0] width 1600 pitch 6400 (/4 1600)
>[787367.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d06c50]
>[787367.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d06c50] width 1600 pitch 6400 (/4 1600)
>[787367.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x476f390]
>[787367.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x476f390] width 1600 pitch 6400 (/4 1600)
>[787367.689] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787367.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787367.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0c90]
>[787367.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0c90] width 1600 pitch 6400 (/4 1600)
>[787367.770] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c3810]
>[787367.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c3810] width 1600 pitch 6400 (/4 1600)
>[787367.839] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e0c90]
>[787367.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e0c90] width 1600 pitch 6400 (/4 1600)
>[787367.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c3810]
>[787368.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c3810] width 1600 pitch 6400 (/4 1600)
>[787368.140] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c3810]
>[787368.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c3810] width 1600 pitch 6400 (/4 1600)
>[787368.191] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787368.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787368.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c3810]
>[787368.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c3810] width 1600 pitch 6400 (/4 1600)
>[787368.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4953cb0]
>[787368.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4953cb0] width 1600 pitch 6400 (/4 1600)
>[787368.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787368.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787368.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787368.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787369.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[787369.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[787369.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787369.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787369.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505d850]
>[787369.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505d850] width 1600 pitch 6400 (/4 1600)
>[787369.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787369.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787370.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787370.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787370.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787370.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787370.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787370.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787372.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787372.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787372.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787372.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787378.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740620]
>[787378.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740620] width 1600 pitch 6400 (/4 1600)
>[787380.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787380.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787380.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11f70]
>[787380.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11f70] width 1600 pitch 6400 (/4 1600)
>[787380.299] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fec30]
>[787380.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fec30] width 1600 pitch 6400 (/4 1600)
>[787380.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787380.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787380.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787380.653] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787380.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787380.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787380.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787380.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787380.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787380.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787380.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11f70]
>[787380.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11f70] width 1600 pitch 6400 (/4 1600)
>[787380.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787380.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787381.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fec30]
>[787381.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fec30] width 1600 pitch 6400 (/4 1600)
>[787381.352] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11f70]
>[787381.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11f70] width 1600 pitch 6400 (/4 1600)
>[787381.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fec30]
>[787381.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fec30] width 1600 pitch 6400 (/4 1600)
>[787381.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787381.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787381.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787381.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787381.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787381.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787381.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787381.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787381.660] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787381.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787381.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787381.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787381.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787381.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787381.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787381.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787382.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787382.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787382.401] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787382.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787382.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787382.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787382.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787382.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787382.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787382.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787382.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787382.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787382.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787382.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787383.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787383.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787383.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787383.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787383.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787383.343] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787383.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787383.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787383.474] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942e20]
>[787383.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942e20] width 1600 pitch 6400 (/4 1600)
>[787383.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942e20]
>[787383.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942e20] width 1600 pitch 6400 (/4 1600)
>[787383.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787383.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787383.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787383.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787385.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787385.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787385.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787385.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787385.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787385.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787385.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787385.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787385.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787385.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787385.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787385.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787385.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787385.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787385.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787385.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a85a70]
>[787385.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a85a70] width 1600 pitch 6400 (/4 1600)
>[787385.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787385.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787385.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787385.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787385.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787386.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787386.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787386.067] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787386.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787386.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787386.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787386.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787398.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787398.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787398.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787398.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787398.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[787398.300] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[787398.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787398.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787398.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942e20]
>[787398.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942e20] width 1600 pitch 6400 (/4 1600)
>[787398.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787398.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787398.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787398.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787398.702] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787398.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787398.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787398.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787399.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787399.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787399.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787399.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787399.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787399.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787399.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[787399.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[787399.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787399.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787399.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787399.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787400.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11f70]
>[787400.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11f70] width 1600 pitch 6400 (/4 1600)
>[787400.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787400.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787400.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787400.155] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787400.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787400.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787400.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787400.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787400.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787400.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787400.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787400.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787400.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787400.573] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787400.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787400.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787400.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787400.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787400.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787400.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787400.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787400.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787401.117] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787401.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787401.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787401.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787401.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787401.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787401.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787401.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787401.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740620]
>[787401.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740620] width 1600 pitch 6400 (/4 1600)
>[787401.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787401.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787401.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787401.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787401.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5773fc0]
>[787402.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5773fc0] width 1600 pitch 6400 (/4 1600)
>[787410.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787410.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787410.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787410.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787410.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787410.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787410.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787410.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787410.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787410.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787411.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787411.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787411.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787411.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787411.308] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787411.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787411.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787411.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787411.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787411.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787411.598] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787411.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787411.732] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787411.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787411.787] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787411.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787411.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787412.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787412.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787412.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787412.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787412.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787412.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787412.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787412.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787412.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787412.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787412.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787412.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787412.738] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787412.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787412.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787412.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787412.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787413.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fddd0]
>[787413.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fddd0] width 1600 pitch 6400 (/4 1600)
>[787413.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787413.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787415.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787415.241] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787415.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b11f70]
>[787415.378] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b11f70] width 1600 pitch 6400 (/4 1600)
>[787415.381] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787415.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787415.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787415.512] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787415.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[787415.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[787415.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787415.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787415.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787415.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787415.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787415.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787415.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787415.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787415.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[787415.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[787415.819] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6740620]
>[787415.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6740620] width 1600 pitch 6400 (/4 1600)
>[787415.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[787416.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[787420.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787420.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787420.571] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ce460]
>[787420.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ce460] width 1600 pitch 6400 (/4 1600)
>[787420.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[787420.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[787421.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787421.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787421.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787421.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787421.866] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787421.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787421.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787421.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787422.105] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787422.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787422.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787422.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787422.286] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787422.347] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787422.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787422.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787422.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787422.715] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787422.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787422.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787422.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787422.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787422.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787422.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787422.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787422.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787423.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bd180]
>[787423.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bd180] width 1600 pitch 6400 (/4 1600)
>[787423.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787423.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787423.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787423.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787423.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787423.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787423.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787423.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787423.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787423.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787423.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787423.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787423.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787423.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787424.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787424.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787424.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787424.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787424.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787424.280] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787424.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787424.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787424.457] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787424.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787424.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787424.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787424.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787424.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787424.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787424.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787424.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787424.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787425.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787425.071] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787425.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787425.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787425.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787425.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787425.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[787425.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[787425.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787425.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787425.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787425.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787425.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787425.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787425.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f4b2a0]
>[787425.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f4b2a0] width 1600 pitch 6400 (/4 1600)
>[787425.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27d90]
>[787425.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27d90] width 1600 pitch 6400 (/4 1600)
>[787425.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[787425.990] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[787426.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59bb930]
>[787426.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59bb930] width 1600 pitch 6400 (/4 1600)
>[787701.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787702.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787702.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[787702.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[787702.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[787702.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[787702.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787702.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787704.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[787705.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[787705.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787705.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787705.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26720]
>[787705.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26720] width 1600 pitch 6400 (/4 1600)
>[787705.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787705.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787706.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[787706.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[787706.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[787706.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[787707.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787707.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787707.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787708.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787708.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787708.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787710.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[787710.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[787711.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787711.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787711.037] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[787711.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[787711.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787712.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787712.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787712.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787712.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787712.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787712.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[787712.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[787712.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[787712.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[787712.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[787712.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[787713.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e0d0]
>[787713.655] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e0d0] width 1600 pitch 6400 (/4 1600)
>[787714.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[787714.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[787714.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787714.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787714.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[787714.608] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[787714.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787714.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787714.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5979280]
>[787714.821] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5979280] width 1600 pitch 6400 (/4 1600)
>[787714.838] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[787714.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[787715.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[787715.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[787715.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26720]
>[787715.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26720] width 1600 pitch 6400 (/4 1600)
>[787715.197] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[787715.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[787715.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7c70]
>[787715.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7c70] width 1600 pitch 6400 (/4 1600)
>[787715.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787715.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787715.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787715.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787715.729] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787715.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787715.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[787715.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[787715.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787715.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787715.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787715.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787716.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26720]
>[787716.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26720] width 1600 pitch 6400 (/4 1600)
>[787721.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787721.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787721.365] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d67e00]
>[787721.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d67e00] width 1600 pitch 6400 (/4 1600)
>[787721.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787721.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787721.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787721.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787721.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787721.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787721.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[787721.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[787721.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b26720]
>[787721.967] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b26720] width 1600 pitch 6400 (/4 1600)
>[787721.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787722.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787778.950] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[787778.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[787779.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787779.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787779.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787779.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787779.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787779.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787779.231] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[787779.296] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[787783.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[787783.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[787783.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787783.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787783.348] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787783.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787783.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[787783.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[787783.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[787783.507] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[787783.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[787783.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[787786.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787786.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787786.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[787786.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[787786.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787786.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787786.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[787786.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[787786.436] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787786.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787786.490] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[787786.549] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[787786.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787786.599] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787786.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787786.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787786.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[787786.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[787786.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7c70]
>[787786.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7c70] width 1600 pitch 6400 (/4 1600)
>[787786.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787786.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787787.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787787.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787787.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[787787.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[787787.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787787.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787787.258] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[787787.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[787787.307] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[787787.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[787787.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[787787.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[787787.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[787787.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[787787.912] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[787787.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[787787.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[787788.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[787788.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e0d0]
>[787788.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e0d0] width 1600 pitch 6400 (/4 1600)
>[787788.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[787788.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[787788.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787788.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787788.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be5540]
>[787788.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be5540] width 1600 pitch 6400 (/4 1600)
>[787788.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[787788.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[787788.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[787788.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[787788.565] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787788.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787788.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[787788.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[787788.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x507e250]
>[787788.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x507e250] width 1600 pitch 6400 (/4 1600)
>[787789.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4baaba0]
>[787789.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4baaba0] width 1600 pitch 6400 (/4 1600)
>[787789.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e0d0]
>[787789.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e0d0] width 1600 pitch 6400 (/4 1600)
>[787789.944] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787790.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787815.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38fdea0]
>[787815.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38fdea0] width 1600 pitch 6400 (/4 1600)
>[787815.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[787815.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[787815.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebd00]
>[787815.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebd00] width 1600 pitch 6400 (/4 1600)
>[787816.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[787816.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[787816.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7c70]
>[787816.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7c70] width 1600 pitch 6400 (/4 1600)
>[787816.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[787816.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[787816.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787816.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787816.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7c70]
>[787816.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7c70] width 1600 pitch 6400 (/4 1600)
>[787816.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[787816.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[787816.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b7c70]
>[787816.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b7c70] width 1600 pitch 6400 (/4 1600)
>[787816.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[787817.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[787847.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787847.778] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787847.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787847.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787847.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787847.879] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787847.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787847.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787847.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787847.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787848.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787848.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787848.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[787848.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[787848.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787848.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787848.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a28640]
>[787848.498] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a28640] width 1600 pitch 6400 (/4 1600)
>[787848.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d8f4b0]
>[787848.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d8f4b0] width 1600 pitch 6400 (/4 1600)
>[787848.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5888eb0]
>[787848.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5888eb0] width 1600 pitch 6400 (/4 1600)
>[787852.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5921e00]
>[787852.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5921e00] width 1600 pitch 6400 (/4 1600)
>[787853.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5888eb0]
>[787853.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5888eb0] width 1600 pitch 6400 (/4 1600)
>[787853.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ca60]
>[787853.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ca60] width 1600 pitch 6400 (/4 1600)
>[787853.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48ad2f0]
>[787853.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48ad2f0] width 1600 pitch 6400 (/4 1600)
>[787853.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5888eb0]
>[787853.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5888eb0] width 1600 pitch 6400 (/4 1600)
>[787853.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402ca60]
>[787853.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402ca60] width 1600 pitch 6400 (/4 1600)
>[787854.123] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x67d61c0]
>[787854.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x67d61c0] width 1600 pitch 6400 (/4 1600)
>[787854.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5888eb0]
>[787854.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5888eb0] width 1600 pitch 6400 (/4 1600)
>[787854.291] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787854.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787854.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787854.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787854.477] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787854.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787854.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787854.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787854.739] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787854.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787854.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787854.914] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787854.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787854.997] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787855.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787855.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787855.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787855.265] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787855.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787855.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787855.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787855.449] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787855.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787855.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787855.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787855.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787855.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6dce0]
>[787855.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6dce0] width 1600 pitch 6400 (/4 1600)
>[787855.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787855.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787855.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6dce0]
>[787856.000] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6dce0] width 1600 pitch 6400 (/4 1600)
>[787862.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787862.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787862.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787862.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787862.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd4260]
>[787862.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd4260] width 1600 pitch 6400 (/4 1600)
>[787862.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787862.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787862.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787862.826] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787862.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787862.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787862.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787862.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787863.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787863.069] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787863.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[787863.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[787905.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787905.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787905.417] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787905.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787905.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787905.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787905.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[787905.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[787905.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787905.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787905.815] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787905.865] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787905.869] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787905.899] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787905.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787905.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787905.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787905.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787905.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787906.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787906.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787906.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787906.088] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787906.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787906.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787906.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787916.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787916.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787916.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787916.727] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787916.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787916.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787916.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787916.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787916.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787916.894] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787916.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787916.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787916.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787917.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787917.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787917.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787917.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787917.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787917.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787917.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787917.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787917.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787917.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787917.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787917.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787918.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787918.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787918.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[787918.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787918.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787918.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787918.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787918.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787918.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787918.884] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787918.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787919.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787919.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787919.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787919.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787919.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787919.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787919.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787919.669] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787919.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787919.853] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[787919.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787920.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787920.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787920.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787920.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787920.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787920.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787920.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787920.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787920.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787920.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787921.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787921.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787921.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787921.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787921.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787921.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787921.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787921.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf96c0]
>[787921.324] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf96c0] width 1600 pitch 6400 (/4 1600)
>[787921.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787921.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787921.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787921.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787921.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[787921.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[787921.785] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787921.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787921.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787922.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787922.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf96c0]
>[787922.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf96c0] width 1600 pitch 6400 (/4 1600)
>[787922.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[787922.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[787922.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787922.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787965.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787965.497] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787965.746] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[787965.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[787965.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787966.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787969.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787969.985] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787969.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787970.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787970.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787970.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787970.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787970.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787970.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787970.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787970.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787970.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787970.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787970.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787970.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787970.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787971.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787971.489] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787971.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[787971.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[787971.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787971.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787971.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787971.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787971.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787971.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787971.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787971.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787971.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787971.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787971.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787971.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787971.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787971.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787972.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[787972.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[787972.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787972.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[787972.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[787972.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[787972.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[787972.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[787972.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787972.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[787973.008] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[787973.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[787973.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf96c0]
>[787973.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf96c0] width 1600 pitch 6400 (/4 1600)
>[787973.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[787973.428] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[787973.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787973.611] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787973.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[787973.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[787974.199] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787974.247] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[787974.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[787974.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[787974.827] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[787974.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788026.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788026.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788026.925] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788026.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788027.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788027.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788027.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788027.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788027.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788027.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788027.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[788027.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[788030.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788030.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788030.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788030.612] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788030.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788030.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788030.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788030.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788030.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788030.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788030.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788030.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788032.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788032.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788033.011] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788033.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788033.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788033.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788033.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788033.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788033.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788033.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788033.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788033.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788033.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788033.888] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788034.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788034.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788039.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788039.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788039.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788039.536] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788039.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788039.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788039.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788039.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788039.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788040.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788040.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788040.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788040.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788040.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788040.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788040.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788040.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788040.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788040.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788040.956] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788041.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788041.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788041.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788041.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788041.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788041.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788052.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[788052.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[788052.758] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788052.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788052.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788052.938] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788053.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788053.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788053.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788053.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788053.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788053.473] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788053.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788053.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788053.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788053.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788053.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788054.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788054.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788054.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788054.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788054.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788054.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788054.559] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788054.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788054.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788054.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788054.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788055.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788055.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788064.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788064.937] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788065.172] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788065.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788065.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788065.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788065.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4955710]
>[788065.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4955710] width 1600 pitch 6400 (/4 1600)
>[788065.459] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788065.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788065.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788065.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788065.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788065.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788071.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[788071.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[788071.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788071.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788073.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[788073.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[788073.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788073.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788073.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788073.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788073.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788073.978] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788074.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788074.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788074.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788074.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788074.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788074.529] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788074.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788074.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788074.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788074.880] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788075.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788075.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788075.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788075.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788075.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788075.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788075.556] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788075.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788075.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788075.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788075.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788075.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788076.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788076.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788076.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788076.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788076.465] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788076.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788076.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788076.701] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788076.826] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b4910]
>[788076.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b4910] width 1600 pitch 6400 (/4 1600)
>[788079.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841a10]
>[788079.659] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841a10] width 1600 pitch 6400 (/4 1600)
>[788079.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788079.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788090.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[788091.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[788091.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[788091.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[788092.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788092.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788092.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788092.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788092.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[788092.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[788092.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2d2a0]
>[788092.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2d2a0] width 1600 pitch 6400 (/4 1600)
>[788100.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[788100.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[788100.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[788100.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[788101.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788101.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788102.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f957d0]
>[788102.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f957d0] width 1600 pitch 6400 (/4 1600)
>[788102.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788102.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788102.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c57fe0]
>[788102.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c57fe0] width 1600 pitch 6400 (/4 1600)
>[788102.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d5090]
>[788102.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d5090] width 1600 pitch 6400 (/4 1600)
>[788102.957] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788102.979] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788103.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788103.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788103.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788103.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788103.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788103.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788103.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788103.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788103.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788103.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788104.674] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788104.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788104.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788104.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788104.848] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788104.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788104.896] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788104.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788106.091] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788106.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788106.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788106.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788108.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788108.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788108.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788108.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788108.537] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788108.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788108.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788108.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788108.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788108.903] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788108.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788108.970] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788108.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788109.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788109.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788109.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788109.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3fc3990]
>[788109.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3fc3990] width 1600 pitch 6400 (/4 1600)
>[788109.188] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511f870]
>[788109.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511f870] width 1600 pitch 6400 (/4 1600)
>[788115.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788115.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788115.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788115.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788115.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788115.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788115.810] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e2df50]
>[788115.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e2df50] width 1600 pitch 6400 (/4 1600)
>[788115.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[788115.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[788115.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478dfa0]
>[788115.971] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478dfa0] width 1600 pitch 6400 (/4 1600)
>[788115.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788116.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788116.060] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478dfa0]
>[788116.105] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478dfa0] width 1600 pitch 6400 (/4 1600)
>[788116.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x478df40]
>[788116.156] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x478df40] width 1600 pitch 6400 (/4 1600)
>[788116.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x479a8f0]
>[788116.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x479a8f0] width 1600 pitch 6400 (/4 1600)
>[788116.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a346c0]
>[788116.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a346c0] width 1600 pitch 6400 (/4 1600)
>[788117.222] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b16c0]
>[788117.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b16c0] width 1600 pitch 6400 (/4 1600)
>[788118.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788118.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788118.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788118.365] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788118.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788118.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788138.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788138.382] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788138.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788138.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788138.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788138.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788138.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788138.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788138.705] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788138.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788139.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788139.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788139.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788139.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788139.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788139.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788139.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788139.819] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788139.842] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788139.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788139.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788140.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788140.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788140.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788140.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48c2e20]
>[788140.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48c2e20] width 1600 pitch 6400 (/4 1600)
>[788140.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788140.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788141.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788141.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788141.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788141.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788141.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788141.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788141.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788141.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788156.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788156.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788156.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788156.847] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788156.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788156.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788156.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788157.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788157.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788157.197] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788157.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788157.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788157.642] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788157.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788157.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788157.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788157.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788157.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788157.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788158.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788171.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788171.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788171.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788171.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788171.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788171.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788171.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788171.569] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788171.602] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788171.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788172.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788172.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788172.430] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788172.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788172.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788172.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788172.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788172.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788172.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788172.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788172.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788172.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788172.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788172.822] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788172.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788172.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788172.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788173.006] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788173.033] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788173.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788173.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788173.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788173.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788173.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788173.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788173.290] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788173.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788173.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788173.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788173.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788173.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788173.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788173.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788173.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788173.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788173.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788173.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788173.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788173.835] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788173.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788174.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788174.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788174.213] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788174.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788174.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788174.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788174.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788174.460] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788174.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788174.510] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788174.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788174.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788174.599] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788174.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788174.748] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788174.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788174.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788174.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788175.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788175.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788175.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788175.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788175.321] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788175.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788175.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788175.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788175.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788175.915] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788176.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788176.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788176.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c49e90]
>[788176.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c49e90] width 1600 pitch 6400 (/4 1600)
>[788176.973] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788177.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788177.043] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788177.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788177.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788177.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788177.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788177.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788177.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788177.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788177.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788177.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788177.647] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788177.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788177.766] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d5390]
>[788178.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d5390] width 1600 pitch 6400 (/4 1600)
>[788178.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788178.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788191.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788191.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788191.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788191.272] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788191.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3beaaf0]
>[788191.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3beaaf0] width 1600 pitch 6400 (/4 1600)
>[788191.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788191.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788191.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4992480]
>[788191.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4992480] width 1600 pitch 6400 (/4 1600)
>[788191.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788191.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788191.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788192.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788192.100] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788192.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788192.228] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788192.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788192.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4958690]
>[788192.358] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4958690] width 1600 pitch 6400 (/4 1600)
>[788195.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788195.251] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788195.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788195.733] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788195.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788195.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788197.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788197.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788197.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788197.656] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788197.658] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788197.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788197.737] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788197.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788197.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788197.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788198.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788198.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788198.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49632a0]
>[788198.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49632a0] width 1600 pitch 6400 (/4 1600)
>[788198.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788198.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788198.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788198.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788201.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788201.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788201.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788201.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788201.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788201.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788201.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788201.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788222.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788222.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788222.619] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788222.965] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788223.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788223.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788223.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788223.972] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788223.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788224.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788224.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788224.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788224.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788224.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788224.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac870]
>[788224.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac870] width 1600 pitch 6400 (/4 1600)
>[788224.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788224.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788224.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac870]
>[788224.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac870] width 1600 pitch 6400 (/4 1600)
>[788224.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788224.409] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788224.518] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788224.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788225.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788226.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788226.034] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788226.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788226.478] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788226.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788226.555] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788226.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788226.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788226.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788226.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788226.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788226.916] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788226.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788230.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788230.977] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788230.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788231.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788231.031] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788231.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788231.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788231.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788231.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788231.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788231.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788231.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788231.349] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788231.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788289.620] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788289.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788289.691] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788289.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788289.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788289.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788289.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788289.868] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788289.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858c80]
>[788289.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858c80] width 1600 pitch 6400 (/4 1600)
>[788289.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2f710]
>[788289.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2f710] width 1600 pitch 6400 (/4 1600)
>[788293.871] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788294.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788294.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788294.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788294.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788294.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788294.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788294.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788294.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788294.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788294.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892a30]
>[788294.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892a30] width 1600 pitch 6400 (/4 1600)
>[788294.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[788295.031] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[788295.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788295.214] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788295.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788295.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788295.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788295.398] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788295.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788295.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788295.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788295.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788295.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788295.816] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788295.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858c80]
>[788295.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858c80] width 1600 pitch 6400 (/4 1600)
>[788296.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788296.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788296.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788296.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788296.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788296.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788296.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d329f0]
>[788296.485] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d329f0] width 1600 pitch 6400 (/4 1600)
>[788296.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788296.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788296.743] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788296.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788296.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788296.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788296.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788297.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788297.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788297.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788297.242] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788297.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788297.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788297.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788297.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788297.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788297.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788297.755] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788297.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788297.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788297.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788297.939] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788298.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788298.122] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788298.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788298.306] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788298.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788298.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788298.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2f710]
>[788298.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2f710] width 1600 pitch 6400 (/4 1600)
>[788298.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788298.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788298.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4780]
>[788298.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4780] width 1600 pitch 6400 (/4 1600)
>[788298.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788298.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788298.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788299.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788299.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788299.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788299.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788299.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788299.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788299.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788299.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788299.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788299.685] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892a30]
>[788299.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892a30] width 1600 pitch 6400 (/4 1600)
>[788299.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788299.810] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788299.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[788299.927] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[788319.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788320.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788320.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788320.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788320.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788320.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788320.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788320.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788321.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788321.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788321.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[788321.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[788321.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788321.368] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788321.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d8230]
>[788321.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d8230] width 1600 pitch 6400 (/4 1600)
>[788321.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788321.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788321.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d8230]
>[788321.631] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d8230] width 1600 pitch 6400 (/4 1600)
>[788321.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788321.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788321.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788321.719] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788321.722] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788321.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788321.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788321.786] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788321.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788321.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788322.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788322.053] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788322.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788322.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788328.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788329.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788329.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788329.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788329.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788329.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788329.968] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788330.057] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788330.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788330.124] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788330.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788330.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788333.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788334.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788334.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788334.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788334.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788334.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788334.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788334.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788334.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788334.235] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788334.239] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788334.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788334.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788334.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788334.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788334.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788334.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788334.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788334.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788334.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788334.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788334.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788334.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788334.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788334.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788334.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788335.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788335.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788335.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788335.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788335.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788335.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788335.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788335.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788335.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788335.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788335.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788335.799] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788335.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788335.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788335.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788336.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788336.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788336.224] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788336.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788336.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788336.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4780]
>[788336.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4780] width 1600 pitch 6400 (/4 1600)
>[788336.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788336.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788336.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788336.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788336.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788336.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788336.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788336.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788337.071] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788337.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788337.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788337.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788337.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788337.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788337.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788337.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788337.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788337.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788337.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788337.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788337.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788338.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788338.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788338.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788338.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788338.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788338.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788338.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788338.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788338.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788338.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4780]
>[788338.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4780] width 1600 pitch 6400 (/4 1600)
>[788338.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d329f0]
>[788338.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d329f0] width 1600 pitch 6400 (/4 1600)
>[788338.887] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788338.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788339.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788339.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788339.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892a30]
>[788339.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892a30] width 1600 pitch 6400 (/4 1600)
>[788339.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788339.349] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788339.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788339.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788339.630] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788339.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788339.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788339.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788339.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788339.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788339.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788340.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788340.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788340.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788340.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788340.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788340.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788340.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788340.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788340.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788340.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788340.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788340.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788340.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788340.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788340.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788341.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd4780]
>[788341.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd4780] width 1600 pitch 6400 (/4 1600)
>[788341.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788341.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788341.435] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788341.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788341.616] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892a30]
>[788341.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892a30] width 1600 pitch 6400 (/4 1600)
>[788341.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788341.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788341.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788341.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788341.982] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788342.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788346.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788346.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788346.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788346.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788349.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38121d0]
>[788349.814] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38121d0] width 1600 pitch 6400 (/4 1600)
>[788349.818] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788349.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788349.921] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788350.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788350.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788350.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788350.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788350.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788350.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788350.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788350.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788350.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788350.659] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788350.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788350.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788350.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788350.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788350.829] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788350.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858c80]
>[788350.912] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858c80] width 1600 pitch 6400 (/4 1600)
>[788350.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788350.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788350.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6858c80]
>[788351.013] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6858c80] width 1600 pitch 6400 (/4 1600)
>[788351.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788351.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788351.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788351.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788351.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788351.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788351.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788351.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788351.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788351.380] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788351.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[788351.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[788351.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788351.531] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788351.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788351.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788352.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788352.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788352.198] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788352.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788352.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788352.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788352.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788352.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788352.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788352.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788352.406] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788352.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788352.509] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788352.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788352.687] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974b60]
>[788352.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974b60] width 1600 pitch 6400 (/4 1600)
>[788352.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788352.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788352.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788352.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788353.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788353.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788353.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[788353.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[788353.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788353.904] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788353.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788354.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788354.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788354.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788354.252] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788354.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788354.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788354.372] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788354.497] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788354.556] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788354.682] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788354.739] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788354.753] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788354.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788354.865] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788354.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788355.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788355.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788355.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788355.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788355.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788355.341] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788355.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788355.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788355.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788355.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788355.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[788355.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[788356.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37d8170]
>[788356.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37d8170] width 1600 pitch 6400 (/4 1600)
>[788356.389] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788356.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788356.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d329f0]
>[788356.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d329f0] width 1600 pitch 6400 (/4 1600)
>[788357.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788357.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788358.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788358.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788358.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788358.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788358.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788358.800] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788375.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d04080]
>[788375.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d04080] width 1600 pitch 6400 (/4 1600)
>[788376.051] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788376.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788376.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788376.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788376.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788376.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788377.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788377.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788377.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788377.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788377.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788377.547] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788378.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788378.419] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788378.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d329f0]
>[788378.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d329f0] width 1600 pitch 6400 (/4 1600)
>[788378.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788378.603] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788378.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788378.703] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788378.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788378.805] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788378.808] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788378.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788385.283] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788385.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788385.796] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788385.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788386.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788386.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788386.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[788386.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[788386.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788386.921] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788387.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788387.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788387.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49635b0]
>[788387.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49635b0] width 1600 pitch 6400 (/4 1600)
>[788389.697] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788389.749] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788389.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788389.833] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788389.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788389.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788389.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788390.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788390.070] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788390.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788390.125] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788390.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788390.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788390.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788390.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788390.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788390.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788390.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788390.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788390.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788390.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788390.501] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788390.541] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788390.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788390.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788390.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788390.675] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[788390.702] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[788390.738] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788390.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788390.832] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788390.852] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788390.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788390.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788390.947] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d329f0]
>[788390.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d329f0] width 1600 pitch 6400 (/4 1600)
>[788391.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c55b10]
>[788391.036] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c55b10] width 1600 pitch 6400 (/4 1600)
>[788391.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788391.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788391.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788391.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788391.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788391.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788391.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788391.353] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788391.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788391.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788391.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788391.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788391.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788391.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788391.631] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788391.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788391.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788391.721] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788391.751] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788391.771] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788392.759] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788392.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788392.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e1ecf0]
>[788392.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e1ecf0] width 1600 pitch 6400 (/4 1600)
>[788392.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788392.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788392.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788392.958] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788392.988] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788393.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788393.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788393.198] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788393.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788393.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788393.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5ba00]
>[788393.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5ba00] width 1600 pitch 6400 (/4 1600)
>[788393.627] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788393.693] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788393.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[788393.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[788393.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788393.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788410.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788410.421] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788410.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788410.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788410.499] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788410.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788411.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788411.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788411.378] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788411.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788411.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788411.526] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788411.553] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788411.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788411.629] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788411.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788411.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788411.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788411.728] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788411.772] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788411.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788411.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788411.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788411.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788411.919] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788412.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788412.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788412.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788412.701] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788412.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788412.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788412.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788412.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788413.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788413.383] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788413.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788413.588] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788413.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788413.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788413.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788413.750] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788413.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788413.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788413.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788414.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788414.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788414.235] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788414.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788414.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788414.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788414.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788414.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788414.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788414.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788414.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788414.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788414.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788414.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788443.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788443.960] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788443.962] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788444.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788444.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788444.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788444.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788444.110] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788444.177] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788444.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788444.249] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788444.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788444.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788444.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788444.432] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788444.461] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788444.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788444.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788444.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974b60]
>[788444.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974b60] width 1600 pitch 6400 (/4 1600)
>[788444.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788444.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788444.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974b60]
>[788444.726] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974b60] width 1600 pitch 6400 (/4 1600)
>[788445.992] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788446.012] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788446.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788446.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788446.539] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788446.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788446.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788446.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788446.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788446.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788446.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788446.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788447.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788447.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788447.268] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788447.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788447.341] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788447.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788447.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788447.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788447.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788447.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788447.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a455a0]
>[788447.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a455a0] width 1600 pitch 6400 (/4 1600)
>[788447.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788447.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788447.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788448.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788448.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788448.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788448.253] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788448.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788448.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788448.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788448.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974b60]
>[788448.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974b60] width 1600 pitch 6400 (/4 1600)
>[788448.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788448.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788448.778] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788448.823] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788448.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788448.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788449.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788449.140] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788449.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495c810]
>[788449.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495c810] width 1600 pitch 6400 (/4 1600)
>[788449.329] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788449.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788449.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788449.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788461.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788461.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788461.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788461.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788461.879] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788461.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788462.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788462.082] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788462.207] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788462.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788462.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788462.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788466.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7ce60]
>[788466.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7ce60] width 1600 pitch 6400 (/4 1600)
>[788466.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3808f20]
>[788466.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3808f20] width 1600 pitch 6400 (/4 1600)
>[788466.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f580d0]
>[788466.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f580d0] width 1600 pitch 6400 (/4 1600)
>[788466.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788466.420] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788466.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788466.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788466.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788466.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788466.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x393dd80]
>[788466.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x393dd80] width 1600 pitch 6400 (/4 1600)
>[788466.572] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788466.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788466.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788466.754] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788466.757] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788466.787] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788507.745] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4951960]
>[788507.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4951960] width 1600 pitch 6400 (/4 1600)
>[788507.783] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788507.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788507.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788507.913] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788508.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788508.114] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788508.226] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788508.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788508.285] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788508.314] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788508.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788508.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788508.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788508.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788508.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788508.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788508.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788508.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788508.600] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c55b10]
>[788508.649] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c55b10] width 1600 pitch 6400 (/4 1600)
>[788512.579] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788512.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788512.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788512.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788512.681] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788512.709] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788512.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788512.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788512.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea14b0]
>[788512.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea14b0] width 1600 pitch 6400 (/4 1600)
>[788512.867] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918970]
>[788512.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918970] width 1600 pitch 6400 (/4 1600)
>[788512.951] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788512.993] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788512.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6864b70]
>[788513.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6864b70] width 1600 pitch 6400 (/4 1600)
>[788513.126] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788513.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788513.238] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788513.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788513.319] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2feb5d0]
>[788513.361] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2feb5d0] width 1600 pitch 6400 (/4 1600)
>[788517.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d32cd0]
>[788517.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d32cd0] width 1600 pitch 6400 (/4 1600)
>[788517.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788517.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788517.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788517.539] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788517.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788517.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788517.577] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d4cf50]
>[788517.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d4cf50] width 1600 pitch 6400 (/4 1600)
>[788517.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788517.639] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788521.597] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788521.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788521.637] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788521.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788521.670] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4990ed0]
>[788521.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4990ed0] width 1600 pitch 6400 (/4 1600)
>[788521.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788521.783] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788521.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788521.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788521.908] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788521.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788521.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788522.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788522.020] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788522.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788522.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788522.268] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788522.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6975fe0]
>[788522.301] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6975fe0] width 1600 pitch 6400 (/4 1600)
>[788522.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494d3f0]
>[788522.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494d3f0] width 1600 pitch 6400 (/4 1600)
>[788522.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788522.619] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788522.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918970]
>[788522.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918970] width 1600 pitch 6400 (/4 1600)
>[788522.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea14b0]
>[788522.836] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea14b0] width 1600 pitch 6400 (/4 1600)
>[788522.934] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788522.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788533.929] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7bcd0]
>[788533.966] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7bcd0] width 1600 pitch 6400 (/4 1600)
>[788533.970] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788534.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788534.006] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6864b70]
>[788534.083] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6864b70] width 1600 pitch 6400 (/4 1600)
>[788534.087] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788534.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788534.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6864b70]
>[788534.150] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6864b70] width 1600 pitch 6400 (/4 1600)
>[788534.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788534.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788538.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788538.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788538.181] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788538.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788538.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788538.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788538.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x28196f0]
>[788538.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x28196f0] width 1600 pitch 6400 (/4 1600)
>[788538.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788538.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788538.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788538.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788538.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6748170]
>[788538.545] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6748170] width 1600 pitch 6400 (/4 1600)
>[788538.547] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5974b60]
>[788538.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5974b60] width 1600 pitch 6400 (/4 1600)
>[788587.614] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788587.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788587.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788587.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788587.763] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f653d0]
>[788587.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f653d0] width 1600 pitch 6400 (/4 1600)
>[788587.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788587.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788587.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788587.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788591.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788591.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788591.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788592.070] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788592.090] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788592.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788592.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788592.187] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788592.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788592.221] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788592.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f94d10]
>[788592.288] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f94d10] width 1600 pitch 6400 (/4 1600)
>[788592.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5947660]
>[788592.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5947660] width 1600 pitch 6400 (/4 1600)
>[788592.449] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f653d0]
>[788592.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f653d0] width 1600 pitch 6400 (/4 1600)
>[788592.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788592.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788592.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d11b00]
>[788592.789] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d11b00] width 1600 pitch 6400 (/4 1600)
>[788592.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788592.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788612.695] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b350f0]
>[788612.725] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b350f0] width 1600 pitch 6400 (/4 1600)
>[788615.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788615.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788615.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788615.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788615.978] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495eaf0]
>[788616.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495eaf0] width 1600 pitch 6400 (/4 1600)
>[788616.538] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x689aa20]
>[788616.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x689aa20] width 1600 pitch 6400 (/4 1600)
>[788616.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd86d0]
>[788616.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd86d0] width 1600 pitch 6400 (/4 1600)
>[788616.700] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x689aa20]
>[788616.736] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x689aa20] width 1600 pitch 6400 (/4 1600)
>[788616.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a6a0]
>[788616.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a6a0] width 1600 pitch 6400 (/4 1600)
>[788617.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69a9180]
>[788617.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69a9180] width 1600 pitch 6400 (/4 1600)
>[788618.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788618.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788618.400] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[788618.458] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[788618.527] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788618.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788618.566] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94810]
>[788618.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94810] width 1600 pitch 6400 (/4 1600)
>[788618.646] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788618.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788618.679] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e94810]
>[788618.708] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e94810] width 1600 pitch 6400 (/4 1600)
>[788618.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788618.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788618.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788618.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788618.829] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788618.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788618.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788618.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788618.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40bd200]
>[788618.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40bd200] width 1600 pitch 6400 (/4 1600)
>[788618.940] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea14b0]
>[788618.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea14b0] width 1600 pitch 6400 (/4 1600)
>[788618.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[788619.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[788619.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ea14b0]
>[788619.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ea14b0] width 1600 pitch 6400 (/4 1600)
>[788619.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788619.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788619.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d5550]
>[788619.276] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d5550] width 1600 pitch 6400 (/4 1600)
>[788619.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a860b0]
>[788619.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a860b0] width 1600 pitch 6400 (/4 1600)
>[788619.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5a28630]
>[788619.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5a28630] width 1600 pitch 6400 (/4 1600)
>[788619.653] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788619.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788619.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788619.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788619.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f653d0]
>[788619.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f653d0] width 1600 pitch 6400 (/4 1600)
>[788620.025] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788620.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788620.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590a9a0]
>[788620.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590a9a0] width 1600 pitch 6400 (/4 1600)
>[788620.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cf96c0]
>[788620.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cf96c0] width 1600 pitch 6400 (/4 1600)
>[788620.393] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673a6a0]
>[788620.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673a6a0] width 1600 pitch 6400 (/4 1600)
>[788620.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4861f10]
>[788620.480] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4861f10] width 1600 pitch 6400 (/4 1600)
>[788620.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b89150]
>[788620.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b89150] width 1600 pitch 6400 (/4 1600)
>[788779.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[788780.020] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[788781.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[788781.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[788781.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[788781.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[788783.158] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788783.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788783.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11070]
>[788783.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11070] width 1600 pitch 6400 (/4 1600)
>[788783.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951030]
>[788783.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951030] width 1600 pitch 6400 (/4 1600)
>[788783.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6834ae0]
>[788783.931] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6834ae0] width 1600 pitch 6400 (/4 1600)
>[788784.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788784.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788784.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788784.299] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788784.424] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788784.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788784.606] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc83e0]
>[788784.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc83e0] width 1600 pitch 6400 (/4 1600)
>[788784.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d5550]
>[788784.850] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d5550] width 1600 pitch 6400 (/4 1600)
>[788784.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e1d50]
>[788785.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e1d50] width 1600 pitch 6400 (/4 1600)
>[788785.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09f50]
>[788785.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09f50] width 1600 pitch 6400 (/4 1600)
>[788785.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970bc0]
>[788785.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970bc0] width 1600 pitch 6400 (/4 1600)
>[788785.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788785.568] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788785.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f60]
>[788785.752] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f60] width 1600 pitch 6400 (/4 1600)
>[788785.875] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788785.936] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788786.053] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733910]
>[788786.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733910] width 1600 pitch 6400 (/4 1600)
>[788786.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[788786.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1600 pitch 6400 (/4 1600)
>[788786.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36be640]
>[788786.471] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36be640] width 1600 pitch 6400 (/4 1600)
>[788786.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b89150]
>[788786.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b89150] width 1600 pitch 6400 (/4 1600)
>[788786.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c220]
>[788786.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c220] width 1600 pitch 6400 (/4 1600)
>[788786.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a5b0]
>[788787.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a5b0] width 1600 pitch 6400 (/4 1600)
>[788787.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58940e0]
>[788787.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58940e0] width 1600 pitch 6400 (/4 1600)
>[788787.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788787.373] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788787.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x499c1f0]
>[788787.557] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x499c1f0] width 1600 pitch 6400 (/4 1600)
>[788787.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d600]
>[788787.741] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d600] width 1600 pitch 6400 (/4 1600)
>[788787.855] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e0b7a0]
>[788787.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e0b7a0] width 1600 pitch 6400 (/4 1600)
>[788788.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[788788.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[788788.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687bf30]
>[788788.292] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687bf30] width 1600 pitch 6400 (/4 1600)
>[788788.398] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[788788.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[788788.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4956ed0]
>[788788.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4956ed0] width 1600 pitch 6400 (/4 1600)
>[788788.772] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11070]
>[788788.827] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11070] width 1600 pitch 6400 (/4 1600)
>[788788.954] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951030]
>[788789.011] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951030] width 1600 pitch 6400 (/4 1600)
>[788789.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6834ae0]
>[788789.195] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6834ae0] width 1600 pitch 6400 (/4 1600)
>[788789.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788789.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788789.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[788789.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[788789.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788789.746] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788789.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc83e0]
>[788789.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc83e0] width 1600 pitch 6400 (/4 1600)
>[788790.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d5550]
>[788790.097] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d5550] width 1600 pitch 6400 (/4 1600)
>[788790.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e1d50]
>[788790.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e1d50] width 1600 pitch 6400 (/4 1600)
>[788790.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09f50]
>[788790.465] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09f50] width 1600 pitch 6400 (/4 1600)
>[788790.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5970bc0]
>[788790.665] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5970bc0] width 1600 pitch 6400 (/4 1600)
>[788790.767] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788790.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788790.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f60]
>[788791.016] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f60] width 1600 pitch 6400 (/4 1600)
>[788791.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x496a650]
>[788791.200] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x496a650] width 1600 pitch 6400 (/4 1600)
>[788791.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6733910]
>[788791.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6733910] width 1600 pitch 6400 (/4 1600)
>[788791.496] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5c780]
>[788791.551] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5c780] width 1600 pitch 6400 (/4 1600)
>[788791.683] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36be640]
>[788791.735] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36be640] width 1600 pitch 6400 (/4 1600)
>[788791.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b89150]
>[788791.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b89150] width 1600 pitch 6400 (/4 1600)
>[788816.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d11b00]
>[788816.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d11b00] width 1600 pitch 6400 (/4 1600)
>[788817.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d6a310]
>[788817.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d6a310] width 1600 pitch 6400 (/4 1600)
>[788817.442] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc83e0]
>[788817.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc83e0] width 1600 pitch 6400 (/4 1600)
>[788817.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918970]
>[788817.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918970] width 1600 pitch 6400 (/4 1600)
>[788817.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4670]
>[788817.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4670] width 1600 pitch 6400 (/4 1600)
>[788817.797] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[788817.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[788817.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a2490]
>[788818.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a2490] width 1600 pitch 6400 (/4 1600)
>[788818.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590a9a0]
>[788818.222] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590a9a0] width 1600 pitch 6400 (/4 1600)
>[788818.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674a500]
>[788818.406] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674a500] width 1600 pitch 6400 (/4 1600)
>[788818.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59870f0]
>[788818.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59870f0] width 1600 pitch 6400 (/4 1600)
>[788818.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[788818.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[788818.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa6a0]
>[788818.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa6a0] width 1600 pitch 6400 (/4 1600)
>[788819.074] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[788819.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[788819.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2f19170]
>[788819.308] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2f19170] width 1600 pitch 6400 (/4 1600)
>[788819.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x494d3f0]
>[788819.492] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x494d3f0] width 1600 pitch 6400 (/4 1600)
>[788819.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c220]
>[788819.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c220] width 1600 pitch 6400 (/4 1600)
>[788819.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ad8310]
>[788819.860] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ad8310] width 1600 pitch 6400 (/4 1600)
>[788819.969] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[788820.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[788820.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bdef20]
>[788820.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bdef20] width 1600 pitch 6400 (/4 1600)
>[788820.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f5baf0]
>[788820.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f5baf0] width 1600 pitch 6400 (/4 1600)
>[788820.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d600]
>[788820.579] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d600] width 1600 pitch 6400 (/4 1600)
>[788820.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e0b7a0]
>[788820.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e0b7a0] width 1600 pitch 6400 (/4 1600)
>[788820.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788820.946] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788821.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49acf80]
>[788821.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49acf80] width 1600 pitch 6400 (/4 1600)
>[788821.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788821.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788821.434] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788821.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788821.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11070]
>[788821.681] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11070] width 1600 pitch 6400 (/4 1600)
>[788821.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788821.849] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788821.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6834ae0]
>[788822.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6834ae0] width 1600 pitch 6400 (/4 1600)
>[788822.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788822.216] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788822.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7b240]
>[788822.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7b240] width 1600 pitch 6400 (/4 1600)
>[788822.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da27b0]
>[788822.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da27b0] width 1600 pitch 6400 (/4 1600)
>[788822.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3918970]
>[788822.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3918970] width 1600 pitch 6400 (/4 1600)
>[788822.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4670]
>[788822.935] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4670] width 1600 pitch 6400 (/4 1600)
>[788823.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[788823.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[788823.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a2490]
>[788823.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a2490] width 1600 pitch 6400 (/4 1600)
>[788823.423] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x590a9a0]
>[788823.486] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x590a9a0] width 1600 pitch 6400 (/4 1600)
>[788823.613] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x674a500]
>[788823.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x674a500] width 1600 pitch 6400 (/4 1600)
>[788823.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59870f0]
>[788823.854] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59870f0] width 1600 pitch 6400 (/4 1600)
>[788823.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[788824.038] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[788824.148] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47aa6a0]
>[788824.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47aa6a0] width 1600 pitch 6400 (/4 1600)
>[788824.210] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4861f10]
>[788824.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4861f10] width 1600 pitch 6400 (/4 1600)
>[788824.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d03990]
>[788824.407] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d03990] width 1600 pitch 6400 (/4 1600)
>[788824.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42360]
>[788824.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42360] width 1600 pitch 6400 (/4 1600)
>[788824.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046c50]
>[788824.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046c50] width 1600 pitch 6400 (/4 1600)
>[788824.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d600]
>[788824.773] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d600] width 1600 pitch 6400 (/4 1600)
>[788824.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046c50]
>[788824.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046c50] width 1600 pitch 6400 (/4 1600)
>[788824.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1d600]
>[788824.839] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1d600] width 1600 pitch 6400 (/4 1600)
>[788824.873] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e0b7a0]
>[788824.923] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e0b7a0] width 1600 pitch 6400 (/4 1600)
>[788825.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3df6170]
>[788825.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3df6170] width 1600 pitch 6400 (/4 1600)
>[788825.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49acf80]
>[788825.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49acf80] width 1600 pitch 6400 (/4 1600)
>[788825.404] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[788825.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[788825.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce8fd0]
>[788825.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce8fd0] width 1600 pitch 6400 (/4 1600)
>[788825.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11070]
>[788825.825] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11070] width 1600 pitch 6400 (/4 1600)
>[788825.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4efe310]
>[788826.026] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4efe310] width 1600 pitch 6400 (/4 1600)
>[788826.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6834ae0]
>[788826.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6834ae0] width 1600 pitch 6400 (/4 1600)
>[788826.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c0c8b0]
>[788826.377] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c0c8b0] width 1600 pitch 6400 (/4 1600)
>[788826.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7b240]
>[788826.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7b240] width 1600 pitch 6400 (/4 1600)
>[788959.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[788959.981] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[788960.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x39142d0]
>[788960.302] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x39142d0] width 1600 pitch 6400 (/4 1600)
>[788960.574] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68cb180]
>[788960.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68cb180] width 1600 pitch 6400 (/4 1600)
>[788997.536] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57810]
>[788997.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57810] width 1600 pitch 6400 (/4 1600)
>[788997.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c360]
>[788998.133] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c360] width 1600 pitch 6400 (/4 1600)
>[788998.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3841650]
>[788998.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3841650] width 1600 pitch 6400 (/4 1600)
>[788998.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x505c220]
>[788998.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x505c220] width 1600 pitch 6400 (/4 1600)
>[788998.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d190]
>[788998.668] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d190] width 1600 pitch 6400 (/4 1600)
>[788998.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[788998.835] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[788998.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68440f0]
>[788999.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68440f0] width 1600 pitch 6400 (/4 1600)
>[788999.143] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f7b240]
>[788999.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f7b240] width 1600 pitch 6400 (/4 1600)
>[788999.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c42360]
>[788999.370] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c42360] width 1600 pitch 6400 (/4 1600)
>[788999.502] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6861400]
>[788999.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6861400] width 1600 pitch 6400 (/4 1600)
>[789070.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2872d00]
>[789070.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2872d00] width 1600 pitch 6400 (/4 1600)
>[789070.923] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[789071.044] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[789071.269] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d190]
>[789071.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d190] width 1600 pitch 6400 (/4 1600)
>[789071.385] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dba760]
>[789071.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dba760] width 1600 pitch 6400 (/4 1600)
>[789071.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[789071.645] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[789071.756] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x522d8b0]
>[789071.830] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x522d8b0] width 1600 pitch 6400 (/4 1600)
>[789071.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3db3130]
>[789072.098] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3db3130] width 1600 pitch 6400 (/4 1600)
>[789072.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f1f0b0]
>[789072.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f1f0b0] width 1600 pitch 6400 (/4 1600)
>[789072.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dcbb0]
>[789072.716] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dcbb0] width 1600 pitch 6400 (/4 1600)
>[789143.654] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d64f80]
>[789143.782] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d64f80] width 1600 pitch 6400 (/4 1600)
>[789144.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d190]
>[789144.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d190] width 1600 pitch 6400 (/4 1600)
>[789144.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36be640]
>[789144.440] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36be640] width 1600 pitch 6400 (/4 1600)
>[789147.241] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2823ed0]
>[789147.495] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2823ed0] width 1600 pitch 6400 (/4 1600)
>[789147.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2517110]
>[789147.802] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2517110] width 1600 pitch 6400 (/4 1600)
>[789148.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591a630]
>[789148.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591a630] width 1600 pitch 6400 (/4 1600)
>[789744.872] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88c00]
>[789744.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88c00] width 1600 pitch 6400 (/4 1600)
>[789744.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[789744.973] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[789744.975] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[789745.007] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[789745.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[789745.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[789745.046] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[789745.089] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[789745.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269da0]
>[789745.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269da0] width 1600 pitch 6400 (/4 1600)
>[789745.162] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x265c650]
>[789745.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x265c650] width 1600 pitch 6400 (/4 1600)
>[789752.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dd0350]
>[789752.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dd0350] width 1600 pitch 6400 (/4 1600)
>[789752.416] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d0100]
>[789752.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d0100] width 1600 pitch 6400 (/4 1600)
>[789752.500] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88c00]
>[789752.543] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88c00] width 1600 pitch 6400 (/4 1600)
>[789752.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4269c40]
>[789752.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4269c40] width 1600 pitch 6400 (/4 1600)
>[789752.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88c00]
>[789752.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88c00] width 1600 pitch 6400 (/4 1600)
>[789752.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c88c00]
>[789752.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c88c00] width 1600 pitch 6400 (/4 1600)
>[789826.719] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ed8710]
>[789827.002] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ed8710] width 1600 pitch 6400 (/4 1600)
>[789827.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc83e0]
>[789827.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc83e0] width 1600 pitch 6400 (/4 1600)
>[789827.328] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3980660]
>[789827.459] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3980660] width 1600 pitch 6400 (/4 1600)
>[789832.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bc83e0]
>[789832.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bc83e0] width 1600 pitch 6400 (/4 1600)
>[789832.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[789832.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[789832.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69ac370]
>[789832.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69ac370] width 1600 pitch 6400 (/4 1600)
>[789832.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a09f50]
>[789833.058] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a09f50] width 1600 pitch 6400 (/4 1600)
>[789833.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x698e650]
>[789833.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x698e650] width 1600 pitch 6400 (/4 1600)
>[789833.371] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f6ba30]
>[789833.425] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f6ba30] width 1600 pitch 6400 (/4 1600)
>[789833.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cedfd0]
>[789833.610] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cedfd0] width 1600 pitch 6400 (/4 1600)
>[789833.730] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4029720]
>[789833.794] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4029720] width 1600 pitch 6400 (/4 1600)
>[789885.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[789885.180] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[790677.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c220]
>[790677.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c220] width 1600 pitch 6400 (/4 1600)
>[790677.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4787470]
>[790677.186] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4787470] width 1600 pitch 6400 (/4 1600)
>[790677.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c220]
>[790677.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c220] width 1600 pitch 6400 (/4 1600)
>[790677.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4787470]
>[790677.445] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4787470] width 1600 pitch 6400 (/4 1600)
>[790677.471] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c220]
>[790677.563] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c220] width 1600 pitch 6400 (/4 1600)
>[790682.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48677d0]
>[790682.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48677d0] width 1600 pitch 6400 (/4 1600)
>[790682.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842a80]
>[790683.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842a80] width 1600 pitch 6400 (/4 1600)
>[790684.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6842a80]
>[790684.840] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6842a80] width 1600 pitch 6400 (/4 1600)
>[790686.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec1910]
>[790686.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec1910] width 1600 pitch 6400 (/4 1600)
>[790782.333] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[790782.333] BUG: synaptics.c:3122 in UpdateTouchState()
>[790782.344] 
>[790782.344] Backtrace:
>[790782.362] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[790782.362] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[790782.362] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[790782.362] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[790782.362] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[790782.362] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[790782.362] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[790782.362] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[790782.362] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[790782.362] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[790782.363] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[790782.363] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[790782.363] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[790782.363] 
>[790782.394] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[790782.394] BUG: synaptics.c:3122 in UpdateTouchState()
>[790782.394] 
>[790782.394] Backtrace:
>[790782.394] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[790782.394] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[790782.394] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[790782.394] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[790782.394] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[790782.394] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[790782.394] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[790782.394] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[790782.395] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[790782.395] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[790782.395] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[790782.395] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[790782.395] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[790782.395] 
>[790794.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47b2300]
>[790794.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47b2300] width 1600 pitch 6400 (/4 1600)
>[790794.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d9e0]
>[790794.690] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d9e0] width 1600 pitch 6400 (/4 1600)
>[790794.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d710]
>[790794.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d710] width 1600 pitch 6400 (/4 1600)
>[790800.823] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[790800.823] BUG: synaptics.c:3122 in UpdateTouchState()
>[790800.823] 
>[790800.823] Backtrace:
>[790800.823] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[790800.823] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[790800.823] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[790800.823] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[790800.823] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[790800.823] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[790800.823] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[790800.823] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[790800.823] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[790800.823] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[790800.823] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[790800.823] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[790800.824] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[790800.824] 
>[790801.245] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[790801.245] BUG: synaptics.c:3122 in UpdateTouchState()
>[790801.245] 
>[790801.245] Backtrace:
>[790801.246] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[790801.246] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[790801.246] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[790801.246] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[790801.246] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[790801.246] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[790801.246] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[790801.246] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[790801.246] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[790801.246] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[790801.246] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[790801.246] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[790801.246] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[790801.246] 
>[790808.531] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x689aa40]
>[790808.604] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x689aa40] width 1600 pitch 6400 (/4 1600)
>[790808.899] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0ae0]
>[790808.917] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0ae0] width 1600 pitch 6400 (/4 1600)
>[790809.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38b5e00]
>[790809.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38b5e00] width 1600 pitch 6400 (/4 1600)
>[790814.144] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d710]
>[790814.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d710] width 1600 pitch 6400 (/4 1600)
>[790814.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dbfc0]
>[790814.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dbfc0] width 1600 pitch 6400 (/4 1600)
>[790814.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dbfc0]
>[790815.019] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dbfc0] width 1600 pitch 6400 (/4 1600)
>[790817.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d9e0]
>[790818.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d9e0] width 1600 pitch 6400 (/4 1600)
>[790818.129] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d9e0]
>[790818.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d9e0] width 1600 pitch 6400 (/4 1600)
>[790818.215] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d710]
>[790818.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d710] width 1600 pitch 6400 (/4 1600)
>[790818.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dbfc0]
>[790818.328] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dbfc0] width 1600 pitch 6400 (/4 1600)
>[790818.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d710]
>[790818.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d710] width 1600 pitch 6400 (/4 1600)
>[790822.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3895800]
>[790822.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3895800] width 1600 pitch 6400 (/4 1600)
>[790822.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c1ecc0]
>[790822.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c1ecc0] width 1600 pitch 6400 (/4 1600)
>[790823.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x402d710]
>[790823.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x402d710] width 1600 pitch 6400 (/4 1600)
>[790823.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3895800]
>[790823.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3895800] width 1600 pitch 6400 (/4 1600)
>[790823.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd7af0]
>[790824.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd7af0] width 1600 pitch 6400 (/4 1600)
>[790824.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4042040]
>[790824.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4042040] width 1600 pitch 6400 (/4 1600)
>[790825.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cd7af0]
>[790825.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cd7af0] width 1600 pitch 6400 (/4 1600)
>[790827.552] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[790827.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[790827.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[790827.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[790865.806] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495fc60]
>[790866.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495fc60] width 1600 pitch 6400 (/4 1600)
>[790866.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913d70]
>[790866.164] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913d70] width 1600 pitch 6400 (/4 1600)
>[790866.387] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913d70]
>[790866.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913d70] width 1600 pitch 6400 (/4 1600)
>[790866.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7100]
>[790866.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7100] width 1600 pitch 6400 (/4 1600)
>[790867.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7100]
>[790867.375] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7100] width 1600 pitch 6400 (/4 1600)
>[790867.582] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913d70]
>[790867.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913d70] width 1600 pitch 6400 (/4 1600)
>[790868.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dcf160]
>[790868.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dcf160] width 1600 pitch 6400 (/4 1600)
>[790868.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0ae0]
>[790868.663] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0ae0] width 1600 pitch 6400 (/4 1600)
>[790869.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0ae0]
>[790869.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0ae0] width 1600 pitch 6400 (/4 1600)
>[790869.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7830]
>[790869.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7830] width 1600 pitch 6400 (/4 1600)
>[790870.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f79020]
>[790870.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f79020] width 1600 pitch 6400 (/4 1600)
>[790870.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7830]
>[790870.149] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7830] width 1600 pitch 6400 (/4 1600)
>[790870.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7830]
>[790870.333] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7830] width 1600 pitch 6400 (/4 1600)
>[790870.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7830]
>[790870.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7830] width 1600 pitch 6400 (/4 1600)
>[790870.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f79020]
>[790870.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f79020] width 1600 pitch 6400 (/4 1600)
>[790870.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0ae0]
>[790870.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0ae0] width 1600 pitch 6400 (/4 1600)
>[790871.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7830]
>[790871.052] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7830] width 1600 pitch 6400 (/4 1600)
>[790871.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f79020]
>[790871.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f79020] width 1600 pitch 6400 (/4 1600)
>[790871.366] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f79020]
>[790871.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f79020] width 1600 pitch 6400 (/4 1600)
>[790885.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581c420]
>[790885.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581c420] width 1600 pitch 6400 (/4 1600)
>[790886.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ce9430]
>[790886.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ce9430] width 1600 pitch 6400 (/4 1600)
>[790887.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581c420]
>[790887.211] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581c420] width 1600 pitch 6400 (/4 1600)
>[790906.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8f710]
>[790906.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8f710] width 1600 pitch 6400 (/4 1600)
>[790972.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69efda0]
>[790972.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69efda0] width 1600 pitch 6400 (/4 1600)
>[790977.204] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[790977.204] BUG: synaptics.c:3122 in UpdateTouchState()
>[790977.204] 
>[790977.204] Backtrace:
>[790977.204] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[790977.204] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[790977.204] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[790977.204] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[790977.204] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[790977.204] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[790977.204] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[790977.205] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[790977.205] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[790977.205] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[790977.205] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[790977.205] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[790977.205] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[790977.205] 
>[790981.076] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979db0]
>[790981.188] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979db0] width 1600 pitch 6400 (/4 1600)
>[790981.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48619b0]
>[790981.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48619b0] width 1600 pitch 6400 (/4 1600)
>[790981.707] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a62fc0]
>[790981.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a62fc0] width 1600 pitch 6400 (/4 1600)
>[790982.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c21720]
>[790982.385] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c21720] width 1600 pitch 6400 (/4 1600)
>[790982.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40dfb40]
>[790982.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40dfb40] width 1600 pitch 6400 (/4 1600)
>[790982.807] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6886290]
>[790982.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6886290] width 1600 pitch 6400 (/4 1600)
>[790983.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3cf7100]
>[790983.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3cf7100] width 1600 pitch 6400 (/4 1600)
>[790983.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x581c420]
>[790983.151] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x581c420] width 1600 pitch 6400 (/4 1600)
>[790983.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dc93c0]
>[790983.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dc93c0] width 1600 pitch 6400 (/4 1600)
>[791033.562] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791033.562] BUG: synaptics.c:3122 in UpdateTouchState()
>[791033.562] 
>[791033.562] Backtrace:
>[791033.760] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791033.760] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791033.760] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791033.760] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791033.761] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791033.761] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791033.761] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791033.761] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791033.761] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791033.761] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791033.761] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x27c3) [0x7f67545387c3]
>[791033.761] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xd3664) [0x7f675483c664]
>[791033.761] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdfad) [0x7f6754826fad]
>[791033.761] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791033.761] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791033.761] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791033.761] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791033.761] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791033.761] 18: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[791033.761] 19: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[791033.761] 20: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791033.761] 21: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791033.761] 22: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791033.761] 23: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791033.761] 
>[791033.903] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791033.903] BUG: synaptics.c:3122 in UpdateTouchState()
>[791033.903] 
>[791033.903] Backtrace:
>[791033.988] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791033.988] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791033.988] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791033.988] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791033.988] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791033.988] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791033.988] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791033.988] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791033.988] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791033.988] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791033.988] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791033.988] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791033.989] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791033.989] 
>[791035.509] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791035.509] BUG: synaptics.c:3122 in UpdateTouchState()
>[791035.509] 
>[791035.509] Backtrace:
>[791035.509] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791035.510] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791035.510] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791035.510] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791035.510] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791035.510] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791035.510] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791035.510] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791035.510] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791035.510] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791035.510] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791035.510] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791035.510] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791035.510] 
>[791035.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8bbd0]
>[791035.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8bbd0] width 1600 pitch 6400 (/4 1600)
>[791035.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b65870]
>[791035.807] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b65870] width 1600 pitch 6400 (/4 1600)
>[791035.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791035.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791035.878] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6eb0]
>[791035.907] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6eb0] width 1600 pitch 6400 (/4 1600)
>[791035.911] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791035.940] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791035.945] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6eb0]
>[791035.983] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6eb0] width 1600 pitch 6400 (/4 1600)
>[791037.818] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791037.818] BUG: synaptics.c:3122 in UpdateTouchState()
>[791037.818] 
>[791037.818] Backtrace:
>[791037.818] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791037.818] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791037.818] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791037.819] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791037.819] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791037.819] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791037.819] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791037.819] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791037.819] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791037.819] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791037.819] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791037.819] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791037.819] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791037.819] 
>[791039.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[791039.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[791039.985] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3883250]
>[791040.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3883250] width 1600 pitch 6400 (/4 1600)
>[791040.057] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[791040.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[791040.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3883250]
>[791040.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3883250] width 1600 pitch 6400 (/4 1600)
>[791040.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[791040.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[791040.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38e9200]
>[791040.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38e9200] width 1600 pitch 6400 (/4 1600)
>[791040.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b39020]
>[791040.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b39020] width 1600 pitch 6400 (/4 1600)
>[791040.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791040.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791040.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d94650]
>[791040.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d94650] width 1600 pitch 6400 (/4 1600)
>[791040.718] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f25ae0]
>[791040.770] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f25ae0] width 1600 pitch 6400 (/4 1600)
>[791040.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3885960]
>[791040.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3885960] width 1600 pitch 6400 (/4 1600)
>[791041.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[791041.138] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[791041.160] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2c6d0]
>[791041.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2c6d0] width 1600 pitch 6400 (/4 1600)
>[791041.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6aae1f0]
>[791041.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6aae1f0] width 1600 pitch 6400 (/4 1600)
>[791041.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27013f0]
>[791041.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27013f0] width 1600 pitch 6400 (/4 1600)
>[791041.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[791041.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[791041.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x27013f0]
>[791041.388] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x27013f0] width 1600 pitch 6400 (/4 1600)
>[791041.392] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d44250]
>[791041.435] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d44250] width 1600 pitch 6400 (/4 1600)
>[791041.441] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6863f90]
>[791041.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6863f90] width 1600 pitch 6400 (/4 1600)
>[791041.492] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3883250]
>[791041.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3883250] width 1600 pitch 6400 (/4 1600)
>[791041.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b65870]
>[791041.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b65870] width 1600 pitch 6400 (/4 1600)
>[791041.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6410]
>[791041.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6410] width 1600 pitch 6400 (/4 1600)
>[791041.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ba6eb0]
>[791042.041] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ba6eb0] width 1600 pitch 6400 (/4 1600)
>[791087.363] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791087.364] BUG: synaptics.c:3122 in UpdateTouchState()
>[791087.364] 
>[791087.364] Backtrace:
>[791087.364] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791087.364] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791087.364] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791087.364] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791087.364] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791087.364] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791087.364] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791087.365] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791087.365] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791087.365] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791087.365] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791087.365] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791087.365] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791087.365] 
>[791088.913] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791088.913] BUG: synaptics.c:3122 in UpdateTouchState()
>[791088.913] 
>[791088.913] Backtrace:
>[791088.913] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791088.913] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791088.913] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791088.913] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791088.914] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791088.914] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791088.914] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791088.914] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791088.914] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791088.914] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791088.914] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791088.914] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791088.914] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791088.914] 
>[791090.072] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791090.072] BUG: synaptics.c:3122 in UpdateTouchState()
>[791090.072] 
>[791090.072] Backtrace:
>[791090.072] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791090.072] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791090.072] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791090.072] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791090.072] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791090.072] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791090.072] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791090.072] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791090.072] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791090.072] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791090.072] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791090.072] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791090.072] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791090.072] 
>[791090.838] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791090.838] BUG: synaptics.c:3122 in UpdateTouchState()
>[791090.838] 
>[791090.838] Backtrace:
>[791090.838] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791090.838] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791090.838] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791090.838] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791090.838] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791090.838] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791090.838] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791090.838] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791090.839] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791090.839] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791090.839] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791090.839] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791090.839] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791090.839] 
>[791091.797] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791091.797] BUG: synaptics.c:3122 in UpdateTouchState()
>[791091.797] 
>[791091.797] Backtrace:
>[791091.797] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791091.797] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791091.798] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791091.798] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791091.798] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791091.798] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791091.798] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791091.798] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791091.798] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791091.798] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791091.798] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791091.798] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791091.798] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791091.798] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791091.798] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791091.799] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791091.799] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791091.799] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791091.799] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791091.799] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791091.799] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791091.799] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791091.799] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791091.799] 
>[791092.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x685d590]
>[791092.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x685d590] width 1600 pitch 6400 (/4 1600)
>[791092.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791093.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791093.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5088280]
>[791093.243] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5088280] width 1600 pitch 6400 (/4 1600)
>[791093.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791093.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791097.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791097.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791097.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791097.220] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791097.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791097.253] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791097.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791097.287] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791097.292] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791097.320] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791097.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791097.404] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791097.782] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791097.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791097.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791097.922] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791097.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791098.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791098.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791098.206] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791098.333] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791098.390] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791098.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c9d990]
>[791098.574] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c9d990] width 1600 pitch 6400 (/4 1600)
>[791098.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791098.624] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791098.628] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791098.657] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791098.696] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d88360]
>[791098.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d88360] width 1600 pitch 6400 (/4 1600)
>[791133.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3883250]
>[791133.588] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3883250] width 1600 pitch 6400 (/4 1600)
>[791133.937] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f5ec50]
>[791134.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f5ec50] width 1600 pitch 6400 (/4 1600)
>[791134.851] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4956ed0]
>[791134.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4956ed0] width 1600 pitch 6400 (/4 1600)
>[791135.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584fc50]
>[791135.238] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584fc50] width 1600 pitch 6400 (/4 1600)
>[791135.462] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f72a0]
>[791135.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f72a0] width 1600 pitch 6400 (/4 1600)
>[791135.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x584fc50]
>[791135.572] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x584fc50] width 1600 pitch 6400 (/4 1600)
>[791135.706] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[791135.756] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[791136.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5868e70]
>[791136.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5868e70] width 1600 pitch 6400 (/4 1600)
>[791136.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b90b70]
>[791136.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b90b70] width 1600 pitch 6400 (/4 1600)
>[791136.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5868e70]
>[791136.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5868e70] width 1600 pitch 6400 (/4 1600)
>[791136.795] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b90b70]
>[791136.842] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b90b70] width 1600 pitch 6400 (/4 1600)
>[791137.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3788030]
>[791137.566] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3788030] width 1600 pitch 6400 (/4 1600)
>[791137.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5046c50]
>[791137.886] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5046c50] width 1600 pitch 6400 (/4 1600)
>[791138.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be0c80]
>[791138.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be0c80] width 1600 pitch 6400 (/4 1600)
>[791138.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dd27c0]
>[791138.329] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dd27c0] width 1600 pitch 6400 (/4 1600)
>[791138.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fe110]
>[791138.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fe110] width 1600 pitch 6400 (/4 1600)
>[791138.673] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0b7a0]
>[791138.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0b7a0] width 1600 pitch 6400 (/4 1600)
>[791139.040] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4dc47e0]
>[791139.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4dc47e0] width 1600 pitch 6400 (/4 1600)
>[791139.161] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4d0b7a0]
>[791139.215] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4d0b7a0] width 1600 pitch 6400 (/4 1600)
>[791139.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68bc6b0]
>[791139.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68bc6b0] width 1600 pitch 6400 (/4 1600)
>[791139.403] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36332c0]
>[791139.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36332c0] width 1600 pitch 6400 (/4 1600)
>[791139.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68b9fd0]
>[791139.666] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68b9fd0] width 1600 pitch 6400 (/4 1600)
>[791140.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dbfc0]
>[791140.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dbfc0] width 1600 pitch 6400 (/4 1600)
>[791140.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791140.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791141.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791141.337] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791141.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dbfc0]
>[791141.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dbfc0] width 1600 pitch 6400 (/4 1600)
>[791142.029] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3913ec0]
>[791142.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3913ec0] width 1600 pitch 6400 (/4 1600)
>[791142.342] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791142.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791142.608] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791142.762] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791142.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791143.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791143.085] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898690]
>[791143.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898690] width 1600 pitch 6400 (/4 1600)
>[791143.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791143.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791147.481] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791147.502] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791147.540] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791147.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791149.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f81c70]
>[791149.576] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f81c70] width 1600 pitch 6400 (/4 1600)
>[791153.011] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791153.011] BUG: synaptics.c:3122 in UpdateTouchState()
>[791153.011] 
>[791153.011] Backtrace:
>[791153.011] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791153.012] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791153.012] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791153.012] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791153.012] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791153.012] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791153.012] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791153.012] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791153.012] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791153.012] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791153.012] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791153.012] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791153.012] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791153.012] 
>[791156.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f11a20]
>[791156.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f11a20] width 1600 pitch 6400 (/4 1600)
>[791161.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7dcc0]
>[791161.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7dcc0] width 1600 pitch 6400 (/4 1600)
>[791170.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6869de0]
>[791170.532] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6869de0] width 1600 pitch 6400 (/4 1600)
>[791184.912] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791184.913] BUG: synaptics.c:3122 in UpdateTouchState()
>[791184.913] 
>[791184.913] Backtrace:
>[791184.913] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791184.913] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791184.913] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791184.913] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791184.913] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791184.913] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791184.913] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791184.913] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791184.913] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791184.913] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791184.914] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791184.914] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791184.914] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791184.914] 
>[791185.170] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791185.170] BUG: synaptics.c:3122 in UpdateTouchState()
>[791185.170] 
>[791185.170] Backtrace:
>[791185.170] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791185.170] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791185.170] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791185.170] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791185.170] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791185.170] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791185.171] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791185.171] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791185.171] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791185.171] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791185.171] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791185.171] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791185.171] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791185.171] 
>[791185.735] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791185.735] BUG: synaptics.c:3122 in UpdateTouchState()
>[791185.735] 
>[791185.735] Backtrace:
>[791185.735] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791185.735] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791185.735] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791185.735] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791185.735] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791185.735] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791185.735] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791185.735] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791185.735] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791185.735] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791185.735] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791185.735] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791185.735] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791185.735] 
>[791186.208] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791186.208] BUG: synaptics.c:3122 in UpdateTouchState()
>[791186.208] 
>[791186.208] Backtrace:
>[791186.208] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791186.208] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791186.208] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791186.208] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791186.208] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791186.208] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791186.208] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791186.209] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791186.209] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791186.209] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791186.209] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791186.209] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791186.209] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791186.209] 
>[791196.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2862020]
>[791196.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2862020] width 1600 pitch 6400 (/4 1600)
>[791197.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791197.453] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791197.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59791b0]
>[791198.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59791b0] width 1600 pitch 6400 (/4 1600)
>[791198.830] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791198.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791198.898] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[791199.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[791199.042] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d590]
>[791199.107] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d590] width 1600 pitch 6400 (/4 1600)
>[791199.741] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791199.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791199.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791199.930] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791200.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecbac0]
>[791200.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecbac0] width 1600 pitch 6400 (/4 1600)
>[791200.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[791200.291] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[791239.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37de6e0]
>[791239.584] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37de6e0] width 1600 pitch 6400 (/4 1600)
>[791252.084] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49e4590]
>[791252.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49e4590] width 1600 pitch 6400 (/4 1600)
>[791273.912] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791273.912] BUG: synaptics.c:3122 in UpdateTouchState()
>[791273.912] 
>[791273.912] Backtrace:
>[791273.912] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791273.913] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791273.913] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791273.913] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791273.913] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791273.913] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791273.913] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791273.913] 7: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x94fb) [0x7f6753b0c4fb]
>[791273.913] 8: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x9f78) [0x7f6753b0cf78]
>[791273.941] 9: /usr/bin/Xorg (miCopyRegion+0x185) [0x54f755]
>[791273.941] 10: /usr/bin/Xorg (miDoCopy+0x426) [0x54fcf6]
>[791273.941] 11: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x8706) [0x7f6753b0b706]
>[791273.941] 12: /usr/bin/Xorg (0x400000+0x10511d) [0x50511d]
>[791273.941] 13: /usr/bin/Xorg (0x400000+0xd8d8f) [0x4d8d8f]
>[791273.941] 14: /usr/bin/Xorg (0x400000+0xda275) [0x4da275]
>[791273.941] 15: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791273.941] 16: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791273.941] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791273.942] 18: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791273.942] 
>[791275.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791275.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791275.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f72a0]
>[791275.331] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f72a0] width 1600 pitch 6400 (/4 1600)
>[791275.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791275.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791275.410] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f72a0]
>[791275.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f72a0] width 1600 pitch 6400 (/4 1600)
>[791275.522] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791275.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791279.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791279.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791279.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f957d0]
>[791279.521] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f957d0] width 1600 pitch 6400 (/4 1600)
>[791279.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[791279.555] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[791279.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791279.638] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791279.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[791279.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[791279.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791279.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791329.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4758810]
>[791329.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4758810] width 1600 pitch 6400 (/4 1600)
>[791329.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[791329.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[791330.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[791330.123] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[791330.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791330.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791330.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791330.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791330.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[791331.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[791331.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e1be0]
>[791331.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e1be0] width 1600 pitch 6400 (/4 1600)
>[791331.246] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59791b0]
>[791331.309] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59791b0] width 1600 pitch 6400 (/4 1600)
>[791331.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791331.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791331.573] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791331.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791331.708] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791331.761] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791331.764] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59791b0]
>[791331.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59791b0] width 1600 pitch 6400 (/4 1600)
>[791331.847] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791331.878] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791331.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791331.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791332.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791332.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791332.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f72a0]
>[791332.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f72a0] width 1600 pitch 6400 (/4 1600)
>[791332.484] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791332.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791332.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791332.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791334.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898690]
>[791334.267] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898690] width 1600 pitch 6400 (/4 1600)
>[791334.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d590]
>[791334.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d590] width 1600 pitch 6400 (/4 1600)
>[791334.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791334.384] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791334.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791334.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791335.259] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791335.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791335.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca34f0]
>[791335.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca34f0] width 1600 pitch 6400 (/4 1600)
>[791343.058] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791343.058] BUG: synaptics.c:3122 in UpdateTouchState()
>[791343.058] 
>[791343.058] Backtrace:
>[791343.058] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791343.058] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791343.058] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791343.058] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791343.059] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791343.059] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791343.059] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791343.059] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791343.059] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791343.059] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791343.059] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791343.059] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791343.059] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791343.059] 
>[791343.399] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791343.399] BUG: synaptics.c:3122 in UpdateTouchState()
>[791343.399] 
>[791343.399] Backtrace:
>[791343.399] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791343.399] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791343.400] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791343.400] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791343.400] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791343.400] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791343.400] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791343.400] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791343.400] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791343.400] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791343.400] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791343.400] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791343.400] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791343.400] 
>[791344.186] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791344.186] BUG: synaptics.c:3122 in UpdateTouchState()
>[791344.186] 
>[791344.186] Backtrace:
>[791344.186] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791344.186] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791344.186] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791344.186] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791344.186] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791344.186] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791344.186] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791344.186] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791344.186] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791344.186] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791344.186] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791344.186] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791344.186] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791344.186] 
>[791344.456] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791344.456] BUG: synaptics.c:3122 in UpdateTouchState()
>[791344.456] 
>[791344.456] Backtrace:
>[791344.456] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791344.456] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791344.456] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791344.456] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791344.456] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791344.456] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791344.456] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791344.456] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791344.456] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791344.456] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791344.456] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791344.456] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791344.456] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791344.456] 
>[791344.730] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791344.730] BUG: synaptics.c:3122 in UpdateTouchState()
>[791344.730] 
>[791344.730] Backtrace:
>[791344.730] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791344.730] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791344.730] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791344.730] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791344.730] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791344.730] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791344.730] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791344.730] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791344.730] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791344.730] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791344.730] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791344.730] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791344.730] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791344.730] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791344.730] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791344.730] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791344.730] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791344.730] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791344.730] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791344.730] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791344.730] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791344.731] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791344.731] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791344.731] 
>[791344.933] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791344.933] BUG: synaptics.c:3122 in UpdateTouchState()
>[791344.933] 
>[791344.933] Backtrace:
>[791344.933] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791344.933] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791344.933] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791344.933] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791344.933] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791344.933] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791344.933] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791344.933] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791344.933] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791344.933] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791344.933] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791344.933] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791344.933] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791344.933] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xafaf) [0x7f6753b0dfaf]
>[791344.933] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543]
>[791344.933] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20]
>[791344.934] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8]
>[791344.934] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791344.934] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791344.934] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791344.934] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791344.934] 
>[791345.598] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791345.598] BUG: synaptics.c:3122 in UpdateTouchState()
>[791345.598] 
>[791345.598] Backtrace:
>[791345.598] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791345.598] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791345.598] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791345.598] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791345.598] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791345.599] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791345.599] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791345.599] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791345.599] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791345.599] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791345.599] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791345.599] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791345.599] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791345.599] 
>[791345.818] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791345.818] BUG: synaptics.c:3122 in UpdateTouchState()
>[791345.819] 
>[791345.819] Backtrace:
>[791345.855] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791345.855] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791345.855] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791345.855] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791345.855] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791345.855] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791345.855] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791345.855] 7: /lib64/libc.so.6 (0x3171e00000+0x7cc4f) [0x3171e7cc4f]
>[791345.855] 8: /lib64/libc.so.6 (__libc_malloc+0x63) [0x3171e7f4b3]
>[791345.855] 9: /lib64/libpixman-1.so.0 (0x317ba00000+0x4282b) [0x317ba4282b]
>[791345.855] 10: /lib64/libpixman-1.so.0 (pixman_image_create_bits+0x73) [0x317ba1c573]
>[791345.855] 11: /usr/lib64/xorg/modules/libfb.so (0x7f67538e0000+0x174c8) [0x7f67538f74c8]
>[791345.855] 12: /usr/lib64/xorg/modules/libfb.so (fbRasterizeTrapezoid+0x3a) [0x7f67538fcc0a]
>[791345.855] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf85e) [0x7f6753b1285e]
>[791345.855] 14: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[791345.855] 15: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791345.855] 16: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791345.855] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791345.855] 18: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791345.855] 
>[791346.840] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[791346.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[791346.891] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6410]
>[791346.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6410] width 1600 pitch 6400 (/4 1600)
>[791346.942] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791346.986] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791346.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791347.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791347.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58c9190]
>[791347.101] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58c9190] width 1600 pitch 6400 (/4 1600)
>[791347.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e1be0]
>[791347.134] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e1be0] width 1600 pitch 6400 (/4 1600)
>[791351.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898690]
>[791351.095] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898690] width 1600 pitch 6400 (/4 1600)
>[791351.099] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[791351.161] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[791351.163] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[791351.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[791351.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4be4fd0]
>[791351.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4be4fd0] width 1600 pitch 6400 (/4 1600)
>[791351.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6410]
>[791351.295] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6410] width 1600 pitch 6400 (/4 1600)
>[791351.305] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[791351.345] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[791387.006] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791387.006] BUG: synaptics.c:3122 in UpdateTouchState()
>[791387.006] 
>[791387.006] Backtrace:
>[791387.006] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791387.006] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791387.006] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791387.006] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791387.007] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791387.007] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791387.007] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791387.007] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791387.007] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791387.007] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791387.007] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791387.007] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791387.007] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791387.007] 
>[791387.209] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791387.210] BUG: synaptics.c:3122 in UpdateTouchState()
>[791387.210] 
>[791387.210] Backtrace:
>[791387.210] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791387.210] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791387.210] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791387.210] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791387.210] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791387.210] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791387.210] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791387.210] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791387.210] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791387.210] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791387.210] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791387.211] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791387.211] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791387.211] 
>[791388.059] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791388.059] BUG: synaptics.c:3122 in UpdateTouchState()
>[791388.059] 
>[791388.059] Backtrace:
>[791388.059] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791388.059] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791388.059] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791388.059] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791388.059] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791388.059] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791388.059] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791388.059] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791388.059] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791388.059] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791388.059] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791388.059] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791388.059] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791388.059] 
>[791388.402] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791388.402] BUG: synaptics.c:3122 in UpdateTouchState()
>[791388.402] 
>[791388.402] Backtrace:
>[791388.402] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791388.403] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791388.403] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791388.403] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791388.403] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791388.403] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791388.403] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791388.403] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791388.403] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791388.403] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791388.403] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791388.403] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791388.403] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791388.403] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xafaf) [0x7f6753b0dfaf]
>[791388.403] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543]
>[791388.403] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20]
>[791388.404] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8]
>[791388.404] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791388.404] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791388.404] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791388.404] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791388.404] 
>[791388.735] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791388.735] BUG: synaptics.c:3122 in UpdateTouchState()
>[791388.735] 
>[791388.735] Backtrace:
>[791388.735] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791388.735] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791388.735] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791388.735] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791388.736] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791388.736] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791388.736] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791388.736] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791388.736] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791388.736] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791388.736] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791388.736] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791388.736] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791388.736] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xafaf) [0x7f6753b0dfaf]
>[791388.736] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543]
>[791388.736] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20]
>[791388.736] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8]
>[791388.736] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791388.737] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791388.737] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791388.737] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791388.737] 
>[791389.226] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791389.226] BUG: synaptics.c:3122 in UpdateTouchState()
>[791389.226] 
>[791389.226] Backtrace:
>[791389.226] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791389.226] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791389.226] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791389.227] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791389.227] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791389.227] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791389.227] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791389.227] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791389.227] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791389.227] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791389.227] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791389.227] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791389.227] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791389.227] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xafaf) [0x7f6753b0dfaf]
>[791389.227] 14: /usr/bin/Xorg (0x400000+0x160543) [0x560543]
>[791389.227] 15: /usr/bin/Xorg (0x400000+0xc9c20) [0x4c9c20]
>[791389.227] 16: /usr/bin/Xorg (0x400000+0xfa7d8) [0x4fa7d8]
>[791389.227] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791389.228] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791389.228] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791389.228] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791389.228] 
>[791389.579] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791389.579] BUG: synaptics.c:3122 in UpdateTouchState()
>[791389.579] 
>[791389.579] Backtrace:
>[791389.579] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791389.579] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791389.579] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791389.579] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791389.579] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791389.579] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791389.579] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791389.579] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791389.579] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791389.579] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791389.580] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791389.580] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791389.580] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791389.580] 
>[791390.166] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791390.167] BUG: synaptics.c:3122 in UpdateTouchState()
>[791390.167] 
>[791390.167] Backtrace:
>[791390.167] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791390.167] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791390.167] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791390.167] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791390.167] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791390.167] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791390.167] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791390.167] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791390.167] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791390.167] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791390.167] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791390.167] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791390.167] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791390.167] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791390.167] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791390.167] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791390.167] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791390.167] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791390.167] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791390.167] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791390.167] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791390.167] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791390.167] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791390.167] 
>[791390.764] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791390.764] BUG: synaptics.c:3122 in UpdateTouchState()
>[791390.764] 
>[791390.764] Backtrace:
>[791390.764] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791390.764] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791390.764] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791390.764] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791390.765] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791390.765] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791390.765] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791390.765] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791390.765] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791390.765] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791390.765] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791390.765] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791390.765] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791390.765] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791390.765] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791390.765] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791390.765] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791390.765] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791390.765] 18: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[791390.765] 19: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[791390.765] 20: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791390.766] 21: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791390.766] 22: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791390.766] 23: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791390.766] 
>[791396.472] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791396.472] BUG: synaptics.c:3122 in UpdateTouchState()
>[791396.472] 
>[791396.472] Backtrace:
>[791396.472] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791396.472] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791396.472] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791396.472] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791396.472] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791396.472] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791396.472] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791396.473] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791396.473] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791396.473] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791396.473] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791396.473] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791396.473] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791396.473] 
>[791403.240] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791403.240] BUG: synaptics.c:3122 in UpdateTouchState()
>[791403.240] 
>[791403.240] Backtrace:
>[791403.240] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791403.240] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791403.241] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791403.241] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791403.241] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791403.241] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791403.241] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791403.241] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791403.241] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791403.241] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791403.241] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791403.241] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791403.241] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791403.241] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791403.241] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791403.241] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791403.241] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791403.241] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791403.241] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791403.241] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791403.242] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791403.242] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791403.242] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791403.242] 
>[791414.622] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791414.623] BUG: synaptics.c:3122 in UpdateTouchState()
>[791414.623] 
>[791414.623] Backtrace:
>[791414.623] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791414.623] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791414.623] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791414.623] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791414.623] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791414.623] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791414.623] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791414.623] 7: /usr/bin/Xorg (0x400000+0x6ac20) [0x46ac20]
>[791414.623] 8: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791414.623] 9: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791414.623] 10: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791414.623] 11: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791414.623] 12: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791414.623] 13: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791414.623] 14: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791414.623] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791414.623] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791414.623] 17: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791414.623] 18: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791414.623] 19: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791414.623] 20: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[791414.623] 21: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[791414.623] 22: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791414.623] 23: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791414.623] 24: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791414.623] 25: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791414.623] 
>[791414.960] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791414.960] BUG: synaptics.c:3122 in UpdateTouchState()
>[791414.960] 
>[791414.960] Backtrace:
>[791414.960] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791414.960] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791414.960] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791414.960] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791414.961] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791414.961] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791414.961] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791414.961] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791414.961] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791414.961] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791414.961] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x215c) [0x7f675453815c]
>[791414.961] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbe24f) [0x7f675482724f]
>[791414.961] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xbbf5) [0x7f6753b0ebf5]
>[791414.961] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xc36b) [0x7f6753b0f36b]
>[791414.961] 14: /usr/bin/Xorg (0x400000+0x1022a1) [0x5022a1]
>[791414.961] 15: /usr/bin/Xorg (0x400000+0xfb486) [0x4fb486]
>[791414.961] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791414.961] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791414.961] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791414.961] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791414.962] 
>[791415.917] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d3ac0]
>[791415.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d3ac0] width 1600 pitch 6400 (/4 1600)
>[791415.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[791416.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[791416.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d3ac0]
>[791416.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d3ac0] width 1600 pitch 6400 (/4 1600)
>[791416.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[791416.103] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[791416.109] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d07990]
>[791416.168] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d07990] width 1600 pitch 6400 (/4 1600)
>[791416.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x594e590]
>[791416.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x594e590] width 1600 pitch 6400 (/4 1600)
>[791416.570] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791416.570] BUG: synaptics.c:3122 in UpdateTouchState()
>[791416.570] 
>[791416.570] Backtrace:
>[791416.570] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791416.570] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791416.570] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791416.570] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791416.570] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791416.570] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791416.570] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791416.570] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791416.570] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791416.570] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791416.570] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791416.570] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791416.570] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791416.570] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791416.570] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791416.570] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791416.570] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791416.570] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791416.570] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791416.570] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791416.570] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791416.570] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791416.570] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791416.570] 
>[791417.053] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791417.053] BUG: synaptics.c:3122 in UpdateTouchState()
>[791417.053] 
>[791417.053] Backtrace:
>[791417.053] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791417.053] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791417.053] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791417.053] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791417.053] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791417.053] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791417.053] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791417.053] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791417.053] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791417.053] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791417.053] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791417.053] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791417.053] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791417.053] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791417.053] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791417.053] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791417.053] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791417.053] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791417.053] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791417.053] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791417.054] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791417.054] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791417.054] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791417.054] 
>[791419.770] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791419.770] BUG: synaptics.c:3122 in UpdateTouchState()
>[791419.770] 
>[791419.770] Backtrace:
>[791419.770] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791419.770] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791419.770] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791419.770] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791419.770] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791419.770] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791419.770] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791419.770] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791419.771] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791419.771] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791419.771] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791419.771] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791419.771] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791419.771] 
>[791420.175] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898690]
>[791420.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898690] width 1600 pitch 6400 (/4 1600)
>[791420.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240]
>[791420.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1600 pitch 6400 (/4 1600)
>[791420.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[791420.346] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1600 pitch 6400 (/4 1600)
>[791420.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791420.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791420.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e234e0]
>[791420.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e234e0] width 1600 pitch 6400 (/4 1600)
>[791420.420] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[791420.463] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[791420.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591f830]
>[791420.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591f830] width 1600 pitch 6400 (/4 1600)
>[791420.548] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d3ac0]
>[791420.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d3ac0] width 1600 pitch 6400 (/4 1600)
>[791420.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c186d0]
>[791420.697] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c186d0] width 1600 pitch 6400 (/4 1600)
>[791420.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50e6410]
>[791420.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50e6410] width 1600 pitch 6400 (/4 1600)
>[791421.012] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f35240]
>[791421.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f35240] width 1600 pitch 6400 (/4 1600)
>[791421.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[791421.248] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[791421.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b64b20]
>[791421.432] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b64b20] width 1600 pitch 6400 (/4 1600)
>[791421.953] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791421.953] BUG: synaptics.c:3122 in UpdateTouchState()
>[791421.953] 
>[791421.953] Backtrace:
>[791421.953] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791421.953] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791421.953] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791421.953] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791421.953] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791421.954] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791421.954] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791421.954] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791421.954] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791421.954] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791421.954] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791421.954] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791421.954] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791421.954] 
>[791423.856] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791423.856] BUG: synaptics.c:3122 in UpdateTouchState()
>[791423.856] 
>[791423.856] Backtrace:
>[791423.857] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791423.857] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791423.857] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791423.857] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791423.857] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791423.857] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791423.857] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791423.857] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791423.857] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791423.857] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791423.857] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791423.857] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791423.857] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791423.858] 
>[791470.152] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791470.152] BUG: synaptics.c:3122 in UpdateTouchState()
>[791470.152] 
>[791470.152] Backtrace:
>[791470.152] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791470.152] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791470.152] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791470.152] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791470.152] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791470.153] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791470.153] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791470.153] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791470.153] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791470.153] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791470.153] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791470.153] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791470.153] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[791470.153] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[791470.153] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[791470.153] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[791470.153] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[791470.153] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[791470.153] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[791470.153] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791470.153] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791470.153] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791470.154] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791470.154] 
>[791474.459] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791474.459] BUG: synaptics.c:3122 in UpdateTouchState()
>[791474.459] 
>[791474.459] Backtrace:
>[791474.460] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791474.460] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791474.460] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791474.460] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791474.460] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791474.460] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791474.460] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791474.460] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791474.460] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791474.460] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791474.460] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791474.461] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791474.461] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791474.461] 
>[791538.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3898950]
>[791538.561] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3898950] width 1600 pitch 6400 (/4 1600)
>[791543.234] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x591fc20]
>[791543.298] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x591fc20] width 1600 pitch 6400 (/4 1600)
>[791543.300] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[791543.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[791543.463] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[791543.490] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[791543.491] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791543.607] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791543.612] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791543.640] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791543.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[791543.724] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[791543.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791543.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791547.760] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e9ffa0]
>[791547.818] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e9ffa0] width 1600 pitch 6400 (/4 1600)
>[791547.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[791547.906] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[791547.941] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[791548.293] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[791548.331] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48a24c0]
>[791548.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48a24c0] width 1600 pitch 6400 (/4 1600)
>[791586.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791586.957] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791587.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f1960]
>[791587.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f1960] width 1600 pitch 6400 (/4 1600)
>[791587.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791587.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791587.230] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[791587.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[791587.311] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791587.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791587.412] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791587.474] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791587.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[791587.658] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[791587.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791587.824] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791587.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791588.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791588.150] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[791588.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[791588.322] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791588.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791588.489] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791588.560] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791588.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[791588.744] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[791588.856] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791588.911] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791589.045] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791589.094] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791589.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[791589.278] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[791589.405] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791589.462] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791601.422] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[791601.537] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[791601.590] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791601.627] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791601.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791601.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791607.066] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791607.066] BUG: synaptics.c:3122 in UpdateTouchState()
>[791607.066] 
>[791607.066] Backtrace:
>[791607.066] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791607.066] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791607.066] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791607.066] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791607.066] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791607.067] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791607.067] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791607.067] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791607.067] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791607.067] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791607.067] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791607.067] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791607.067] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791607.067] 
>[791607.547] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791607.547] BUG: synaptics.c:3122 in UpdateTouchState()
>[791607.547] 
>[791607.547] Backtrace:
>[791607.547] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791607.547] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791607.547] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791607.547] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791607.547] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791607.547] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791607.547] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791607.547] 7: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xc177b) [0x7f675482a77b]
>[791607.547] 8: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbed0c) [0x7f6754827d0c]
>[791607.547] 9: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x9074) [0x7f6753b0c074]
>[791607.547] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xaad9) [0x7f6753b0dad9]
>[791607.547] 11: /usr/bin/Xorg (0x400000+0x10354d) [0x50354d]
>[791607.547] 12: /usr/bin/Xorg (0x400000+0xf32f8) [0x4f32f8]
>[791607.547] 13: /usr/bin/Xorg (miCompositeRects+0x8b) [0x4f33fb]
>[791607.547] 14: /usr/bin/Xorg (0x400000+0xfb035) [0x4fb035]
>[791607.547] 15: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791607.547] 16: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791607.547] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791607.547] 18: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791607.547] 
>[791608.072] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791608.072] BUG: synaptics.c:3122 in UpdateTouchState()
>[791608.072] 
>[791608.072] Backtrace:
>[791608.072] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791608.072] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791608.072] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791608.072] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791608.072] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791608.072] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791608.072] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791608.074] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791608.074] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791608.074] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791608.074] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x27c3) [0x7f67545387c3]
>[791608.074] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xd3664) [0x7f675483c664]
>[791608.074] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xc71f0) [0x7f67548301f0]
>[791608.074] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x8a6b) [0x7f6753b0ba6b]
>[791608.074] 14: /usr/bin/Xorg (miFillGeneralPoly+0x338) [0x55ce28]
>[791608.074] 15: /usr/bin/Xorg (0x400000+0x1037e3) [0x5037e3]
>[791608.074] 16: /usr/bin/Xorg (0x400000+0x30cca) [0x430cca]
>[791608.074] 17: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791608.074] 18: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791608.074] 19: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791608.074] 20: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791608.074] 
>[791608.508] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[791608.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[791608.551] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791608.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791608.638] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791608.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791608.703] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791608.747] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791608.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791608.757] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791608.757] BUG: synaptics.c:3122 in UpdateTouchState()
>[791608.757] 
>[791608.757] Backtrace:
>[791608.757] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791608.757] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791608.757] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791608.757] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791608.757] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791608.757] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791608.757] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791608.757] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791608.757] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791608.758] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791608.758] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791608.758] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791608.758] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791608.758] 
>[791608.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791609.255] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791609.255] BUG: synaptics.c:3122 in UpdateTouchState()
>[791609.255] 
>[791609.255] Backtrace:
>[791609.255] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791609.255] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791609.256] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791609.256] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791609.256] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791609.256] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791609.256] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791609.256] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791609.256] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791609.256] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791609.257] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791609.257] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791609.257] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791609.257] 
>[791610.499] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791610.499] BUG: synaptics.c:3122 in UpdateTouchState()
>[791610.499] 
>[791610.499] Backtrace:
>[791610.499] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791610.499] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791610.499] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791610.499] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791610.499] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791610.499] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791610.499] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791610.499] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791610.499] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791610.500] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791610.500] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791610.500] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791610.500] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791610.500] 
>[791611.971] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791611.971] BUG: synaptics.c:3122 in UpdateTouchState()
>[791611.971] 
>[791611.971] Backtrace:
>[791611.971] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791611.971] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791611.971] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791611.971] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791611.972] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791611.972] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791611.972] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791611.972] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791611.972] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791611.972] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791611.972] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791611.972] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791611.972] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791611.972] 
>[791612.628] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791612.628] BUG: synaptics.c:3122 in UpdateTouchState()
>[791612.628] 
>[791612.628] Backtrace:
>[791612.628] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791612.628] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791612.628] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791612.628] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791612.628] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791612.628] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791612.628] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791612.628] 7: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xc08c9) [0x7f67548298c9]
>[791612.628] 8: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbed0c) [0x7f6754827d0c]
>[791612.628] 9: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x9074) [0x7f6753b0c074]
>[791612.628] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xaad9) [0x7f6753b0dad9]
>[791612.628] 11: /usr/bin/Xorg (0x400000+0x10354d) [0x50354d]
>[791612.628] 12: /usr/bin/Xorg (0x400000+0xf32f8) [0x4f32f8]
>[791612.628] 13: /usr/bin/Xorg (miCompositeRects+0x8b) [0x4f33fb]
>[791612.628] 14: /usr/bin/Xorg (0x400000+0xfb035) [0x4fb035]
>[791612.628] 15: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791612.628] 16: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791612.628] 17: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791612.628] 18: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791612.628] 
>[791612.946] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[791612.991] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[791616.079] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791616.079] BUG: synaptics.c:3122 in UpdateTouchState()
>[791616.079] 
>[791616.079] Backtrace:
>[791616.079] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791616.079] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791616.079] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791616.079] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791616.079] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791616.079] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791616.079] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791616.079] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[791616.079] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[791616.079] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[791616.079] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[791616.079] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[791616.079] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xd91b5) [0x7f67548421b5]
>[791616.079] 13: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbee72) [0x7f6754827e72]
>[791616.079] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x9074) [0x7f6753b0c074]
>[791616.079] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xaad9) [0x7f6753b0dad9]
>[791616.079] 16: /usr/bin/Xorg (0x400000+0x10354d) [0x50354d]
>[791616.079] 17: /usr/bin/Xorg (0x400000+0xf32f8) [0x4f32f8]
>[791616.079] 18: /usr/bin/Xorg (miCompositeRects+0x8b) [0x4f33fb]
>[791616.079] 19: /usr/bin/Xorg (0x400000+0xfb035) [0x4fb035]
>[791616.079] 20: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[791616.079] 21: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791616.079] 22: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791616.079] 23: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791616.079] 
>[791617.176] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791617.236] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791617.243] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791617.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791617.289] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791617.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791617.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791617.437] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791617.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791617.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791617.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[791617.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[791617.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791617.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791621.615] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[791621.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[791621.652] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[791621.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[791621.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791621.765] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791621.769] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791621.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791621.803] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[791621.832] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[791621.837] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[791621.874] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[791686.080] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f21a0]
>[791686.088] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f21a0] width 1600 pitch 6400 (/4 1600)
>[791888.859] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791888.859] BUG: synaptics.c:3122 in UpdateTouchState()
>[791888.859] 
>[791888.859] Backtrace:
>[791888.860] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791888.860] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791888.860] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791888.860] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791888.860] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791888.860] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791888.860] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791888.860] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791888.860] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791888.860] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791888.860] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791888.861] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791888.861] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791888.861] 
>[791918.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2fd85f0]
>[791918.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2fd85f0] width 1600 pitch 6400 (/4 1600)
>[791972.614] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791972.614] BUG: synaptics.c:3122 in UpdateTouchState()
>[791972.614] 
>[791972.614] Backtrace:
>[791972.614] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791972.614] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791972.614] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791972.614] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791972.614] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791972.614] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791972.614] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791972.614] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791972.615] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791972.615] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791972.615] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791972.615] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791972.615] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791972.615] 
>[791973.412] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[791973.412] BUG: synaptics.c:3122 in UpdateTouchState()
>[791973.412] 
>[791973.412] Backtrace:
>[791973.412] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[791973.412] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[791973.412] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[791973.412] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[791973.412] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[791973.412] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[791973.412] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[791973.412] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[791973.412] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[791973.412] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[791973.412] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[791973.412] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[791973.412] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[791973.412] 
>[792168.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[792168.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[792168.323] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[792168.352] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[792168.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[792168.402] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[792168.407] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[792168.444] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[792168.448] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792168.519] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792168.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[792168.552] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[792168.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[792168.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[792168.824] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95860]
>[792168.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95860] width 1600 pitch 6400 (/4 1600)
>[792169.001] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[792169.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[792169.225] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792169.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792169.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[792169.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[792169.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[792169.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[792169.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[792169.455] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[792169.562] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[792169.605] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[792169.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95860]
>[792169.806] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95860] width 1600 pitch 6400 (/4 1600)
>[792169.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[792169.989] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[792170.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792170.173] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792170.206] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792170.273] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792170.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[792170.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[792170.345] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792170.374] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792170.380] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[792170.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[792170.450] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4880c10]
>[792170.491] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4880c10] width 1600 pitch 6400 (/4 1600)
>[792170.494] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[792170.541] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[792170.636] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95860]
>[792170.691] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95860] width 1600 pitch 6400 (/4 1600)
>[792170.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3004d90]
>[792170.875] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3004d90] width 1600 pitch 6400 (/4 1600)
>[792171.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[792171.059] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[792171.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[792171.226] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[792171.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f5d0]
>[792171.410] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f5d0] width 1600 pitch 6400 (/4 1600)
>[792171.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d95860]
>[792171.594] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d95860] width 1600 pitch 6400 (/4 1600)
>[792182.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4791e80]
>[792182.339] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4791e80] width 1600 pitch 6400 (/4 1600)
>[792193.152] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f3830]
>[792193.201] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f3830] width 1600 pitch 6400 (/4 1600)
>[792195.141] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792195.141] BUG: synaptics.c:3122 in UpdateTouchState()
>[792195.141] 
>[792195.141] Backtrace:
>[792195.142] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792195.142] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792195.142] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792195.142] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792195.142] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792195.142] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792195.142] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792195.142] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792195.142] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792195.142] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792195.142] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792195.142] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792195.142] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792195.142] 
>[792306.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892430]
>[792306.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892430] width 1600 pitch 6400 (/4 1600)
>[792306.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fd350]
>[792306.554] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fd350] width 1600 pitch 6400 (/4 1600)
>[792306.692] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aff0]
>[792306.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aff0] width 1600 pitch 6400 (/4 1600)
>[792307.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792307.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792307.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[792307.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[792307.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792307.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792307.794] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792307.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792307.956] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792308.008] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792308.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792308.191] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792308.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[792308.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[792308.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792308.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792308.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792308.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792308.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792308.609] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792308.710] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[792308.743] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[792308.906] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ed06f0]
>[792309.010] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ed06f0] width 1600 pitch 6400 (/4 1600)
>[792315.754] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792315.754] BUG: synaptics.c:3122 in UpdateTouchState()
>[792315.754] 
>[792315.754] Backtrace:
>[792315.754] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792315.754] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792315.754] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792315.754] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792315.754] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792315.754] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792315.754] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792315.754] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792315.754] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792315.754] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792315.754] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792315.754] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792315.754] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792315.754] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792315.754] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792315.755] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792315.755] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792315.755] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792315.755] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792315.755] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792315.755] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792315.755] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792315.755] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792315.755] 
>[792556.048] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2835c90]
>[792556.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2835c90] width 1600 pitch 6400 (/4 1600)
>[792558.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37e4e50]
>[792558.090] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37e4e50] width 1600 pitch 6400 (/4 1600)
>[792558.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3539f60]
>[792558.369] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3539f60] width 1600 pitch 6400 (/4 1600)
>[792558.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3547ec0]
>[792558.493] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3547ec0] width 1600 pitch 6400 (/4 1600)
>[792558.569] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3539f60]
>[792558.589] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3539f60] width 1600 pitch 6400 (/4 1600)
>[792620.216] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3547dc0]
>[792620.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3547dc0] width 1600 pitch 6400 (/4 1600)
>[792620.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ce740]
>[792620.389] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ce740] width 1600 pitch 6400 (/4 1600)
>[792620.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecb4c0]
>[792620.523] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecb4c0] width 1600 pitch 6400 (/4 1600)
>[792620.526] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bd4880]
>[792620.590] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bd4880] width 1600 pitch 6400 (/4 1600)
>[792620.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecb4c0]
>[792620.623] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecb4c0] width 1600 pitch 6400 (/4 1600)
>[792620.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34f1290]
>[792620.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34f1290] width 1600 pitch 6400 (/4 1600)
>[792620.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e4230]
>[792620.924] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e4230] width 1600 pitch 6400 (/4 1600)
>[792621.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[792621.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[792712.267] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792712.267] BUG: synaptics.c:3122 in UpdateTouchState()
>[792712.267] 
>[792712.267] Backtrace:
>[792712.267] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792712.267] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792712.267] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792712.267] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792712.267] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792712.267] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792712.267] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792712.268] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792712.268] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792712.268] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792712.268] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792712.268] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792712.268] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792712.268] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792712.268] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792712.268] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792712.268] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792712.268] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792712.268] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792712.268] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792712.268] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792712.268] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792712.268] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792712.268] 
>[792756.216] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792756.216] BUG: synaptics.c:3122 in UpdateTouchState()
>[792756.216] 
>[792756.216] Backtrace:
>[792756.217] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792756.217] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792756.217] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792756.217] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792756.217] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792756.217] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792756.217] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792756.217] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792756.217] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792756.217] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792756.217] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792756.217] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792756.217] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792756.217] 
>[792780.986] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792780.986] BUG: synaptics.c:3122 in UpdateTouchState()
>[792780.986] 
>[792780.986] Backtrace:
>[792780.987] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792780.987] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792780.987] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792780.987] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792780.987] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792780.987] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792780.987] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792780.987] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792780.987] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792780.987] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792780.987] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792780.987] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792780.988] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792780.988] 
>[792785.794] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792785.794] BUG: synaptics.c:3122 in UpdateTouchState()
>[792785.794] 
>[792785.794] Backtrace:
>[792785.794] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792785.794] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792785.794] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792785.794] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792785.794] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792785.795] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792785.795] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792785.795] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792785.795] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792785.795] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792785.795] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792785.795] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792785.795] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792785.795] 
>[792796.821] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792796.821] BUG: synaptics.c:3122 in UpdateTouchState()
>[792796.821] 
>[792796.821] Backtrace:
>[792796.821] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792796.821] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792796.821] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792796.821] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792796.821] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792796.821] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792796.821] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792796.821] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792796.821] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792796.821] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792796.821] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792796.821] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792796.822] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792796.822] 
>[792797.175] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792797.175] BUG: synaptics.c:3122 in UpdateTouchState()
>[792797.175] 
>[792797.175] Backtrace:
>[792797.176] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792797.176] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792797.176] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792797.176] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792797.176] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792797.176] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792797.176] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792797.176] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792797.176] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792797.176] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792797.176] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792797.176] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792797.176] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792797.176] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792797.176] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792797.176] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792797.177] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792797.177] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792797.177] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792797.177] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792797.177] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792797.177] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792797.177] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792797.177] 
>[792797.480] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792797.480] BUG: synaptics.c:3122 in UpdateTouchState()
>[792797.480] 
>[792797.480] Backtrace:
>[792797.480] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792797.480] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792797.481] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792797.481] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792797.481] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792797.481] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792797.481] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792797.481] 7: /usr/bin/Xorg (dixLookupResourceByClass+0xb0) [0x456580]
>[792797.481] 8: /usr/bin/Xorg (dixLookupDrawable+0x3c) [0x437d3c]
>[792797.481] 9: /usr/bin/Xorg (dixLookupWindow+0x11) [0x437db1]
>[792797.481] 10: /usr/bin/Xorg (0x400000+0x2e950) [0x42e950]
>[792797.481] 11: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792797.481] 12: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792797.481] 13: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792797.481] 14: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792797.481] 
>[792797.732] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792797.732] BUG: synaptics.c:3122 in UpdateTouchState()
>[792797.732] 
>[792797.732] Backtrace:
>[792797.733] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792797.733] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792797.733] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792797.733] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792797.733] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792797.733] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792797.733] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792797.733] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792797.733] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792797.733] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792797.733] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792797.733] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792797.733] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792797.733] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792797.733] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792797.733] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792797.733] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792797.733] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792797.733] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792797.734] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792797.734] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792797.734] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792797.734] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792797.734] 
>[792798.465] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792798.465] BUG: synaptics.c:3122 in UpdateTouchState()
>[792798.465] 
>[792798.465] Backtrace:
>[792798.465] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792798.465] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792798.465] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792798.465] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792798.465] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792798.465] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792798.465] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792798.465] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792798.465] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792798.466] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792798.466] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792798.466] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792798.466] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792798.466] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792798.466] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792798.466] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792798.466] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792798.466] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792798.466] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792798.466] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792798.466] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792798.466] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792798.466] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792798.466] 
>[792798.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ec52f0]
>[792798.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ec52f0] width 1600 pitch 6400 (/4 1600)
>[792798.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be7a20]
>[792798.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be7a20] width 1600 pitch 6400 (/4 1600)
>[792798.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f27d90]
>[792798.757] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792798.757] BUG: synaptics.c:3122 in UpdateTouchState()
>[792798.757] 
>[792798.757] Backtrace:
>[792798.757] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792798.757] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792798.757] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792798.757] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792798.757] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792798.757] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792798.757] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792798.757] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[792798.757] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[792798.757] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[792798.757] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[792798.757] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[792798.758] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[792798.758] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[792798.758] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[792798.758] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[792798.758] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[792798.758] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[792798.758] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[792798.758] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[792798.758] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792798.758] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792798.758] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792798.758] 
>[792798.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f27d90] width 1600 pitch 6400 (/4 1600)
>[792798.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672bf00]
>[792798.887] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672bf00] width 1600 pitch 6400 (/4 1600)
>[792802.736] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3884b40]
>[792802.792] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3884b40] width 1600 pitch 6400 (/4 1600)
>[792802.800] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50970]
>[792802.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50970] width 1600 pitch 6400 (/4 1600)
>[792802.862] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x672bf00]
>[792802.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x672bf00] width 1600 pitch 6400 (/4 1600)
>[792802.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c50970]
>[792802.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c50970] width 1600 pitch 6400 (/4 1600)
>[792802.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929e00]
>[792802.975] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929e00] width 1600 pitch 6400 (/4 1600)
>[792802.995] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[792803.075] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[792803.079] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3929e00]
>[792803.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3929e00] width 1600 pitch 6400 (/4 1600)
>[792803.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d3db0]
>[792803.209] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d3db0] width 1600 pitch 6400 (/4 1600)
>[792803.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5958e10]
>[792803.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5958e10] width 1600 pitch 6400 (/4 1600)
>[792809.603] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792809.603] BUG: synaptics.c:3122 in UpdateTouchState()
>[792809.603] 
>[792809.603] Backtrace:
>[792809.603] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792809.603] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792809.603] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792809.603] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792809.604] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792809.604] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792809.604] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792809.604] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792809.604] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792809.604] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792809.604] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792809.604] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792809.604] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792809.604] 
>[792810.096] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792810.097] BUG: synaptics.c:3122 in UpdateTouchState()
>[792810.097] 
>[792810.097] Backtrace:
>[792810.097] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792810.097] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792810.097] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792810.097] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792810.097] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792810.097] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792810.097] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792810.097] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792810.097] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792810.097] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792810.098] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792810.098] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792810.098] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792810.098] 
>[792824.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47a19e0]
>[792824.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47a19e0] width 1600 pitch 6400 (/4 1600)
>[792827.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x300f6d0]
>[792827.558] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x300f6d0] width 1600 pitch 6400 (/4 1600)
>[792827.592] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a8d900]
>[792827.675] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a8d900] width 1600 pitch 6400 (/4 1600)
>[792827.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38418f0]
>[792827.926] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38418f0] width 1600 pitch 6400 (/4 1600)
>[792827.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c9900]
>[792828.024] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c9900] width 1600 pitch 6400 (/4 1600)
>[792828.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ee1a0]
>[792828.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ee1a0] width 1600 pitch 6400 (/4 1600)
>[792900.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9e7b0]
>[792900.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9e7b0] width 1600 pitch 6400 (/4 1600)
>[792900.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f27cc0]
>[792900.335] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f27cc0] width 1600 pitch 6400 (/4 1600)
>[792900.668] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c5bb30]
>[792900.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c5bb30] width 1600 pitch 6400 (/4 1600)
>[792903.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b9e7b0]
>[792903.525] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b9e7b0] width 1600 pitch 6400 (/4 1600)
>[792903.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996c40]
>[792903.759] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996c40] width 1600 pitch 6400 (/4 1600)
>[792903.790] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996c40]
>[792903.843] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996c40] width 1600 pitch 6400 (/4 1600)
>[792903.849] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36830]
>[792903.893] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36830] width 1600 pitch 6400 (/4 1600)
>[792903.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[792904.027] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[792904.151] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d0d0]
>[792904.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d0d0] width 1600 pitch 6400 (/4 1600)
>[792904.332] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bed780]
>[792904.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bed780] width 1600 pitch 6400 (/4 1600)
>[792904.513] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x699cd20]
>[792904.562] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x699cd20] width 1600 pitch 6400 (/4 1600)
>[792904.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[792904.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[792904.882] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6c7f0]
>[792904.929] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6c7f0] width 1600 pitch 6400 (/4 1600)
>[792905.062] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57d3db0]
>[792905.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57d3db0] width 1600 pitch 6400 (/4 1600)
>[792905.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3649c40]
>[792905.297] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3649c40] width 1600 pitch 6400 (/4 1600)
>[792905.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68822a0]
>[792905.481] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68822a0] width 1600 pitch 6400 (/4 1600)
>[792905.595] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4b40dd0]
>[792905.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4b40dd0] width 1600 pitch 6400 (/4 1600)
>[792905.786] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4996c40]
>[792905.848] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4996c40] width 1600 pitch 6400 (/4 1600)
>[792905.963] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c316b0]
>[792906.015] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c316b0] width 1600 pitch 6400 (/4 1600)
>[792906.146] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bebb70]
>[792906.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bebb70] width 1600 pitch 6400 (/4 1600)
>[792906.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bed780]
>[792906.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bed780] width 1600 pitch 6400 (/4 1600)
>[792906.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e6c7f0]
>[792906.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e6c7f0] width 1600 pitch 6400 (/4 1600)
>[792906.694] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c6d80]
>[792906.751] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c6d80] width 1600 pitch 6400 (/4 1600)
>[792906.874] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x281d0d0]
>[792906.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x281d0d0] width 1600 pitch 6400 (/4 1600)
>[792907.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49907f0]
>[792907.102] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49907f0] width 1600 pitch 6400 (/4 1600)
>[792917.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792917.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792917.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57f1870]
>[792917.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57f1870] width 1600 pitch 6400 (/4 1600)
>[792917.965] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cef0]
>[792918.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cef0] width 1600 pitch 6400 (/4 1600)
>[792925.170] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792925.170] BUG: synaptics.c:3122 in UpdateTouchState()
>[792925.170] 
>[792925.170] Backtrace:
>[792925.170] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792925.170] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792925.170] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792925.170] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792925.170] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792925.170] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792925.170] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792925.171] 7: /usr/bin/Xorg (0x400000+0x344cc) [0x4344cc]
>[792925.171] 8: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792925.171] 9: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792925.171] 10: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792925.171] 
>[792925.758] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[792925.758] BUG: synaptics.c:3122 in UpdateTouchState()
>[792925.758] 
>[792925.758] Backtrace:
>[792925.758] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[792925.758] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[792925.758] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[792925.758] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[792925.758] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[792925.758] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[792925.758] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[792925.758] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[792925.758] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[792925.758] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[792925.758] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[792925.758] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[792925.759] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[792925.759] 
>[792927.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3548550]
>[792927.289] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3548550] width 1600 pitch 6400 (/4 1600)
>[792927.306] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5887e80]
>[792927.376] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5887e80] width 1600 pitch 6400 (/4 1600)
>[792927.388] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8f10]
>[792927.439] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8f10] width 1600 pitch 6400 (/4 1600)
>[792930.287] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50f8f10]
>[792930.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50f8f10] width 1600 pitch 6400 (/4 1600)
>[792930.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x34ecd80]
>[792930.548] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x34ecd80] width 1600 pitch 6400 (/4 1600)
>[792930.677] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a2daf0]
>[792930.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a2daf0] width 1600 pitch 6400 (/4 1600)
>[792931.325] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b8c00]
>[792931.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b8c00] width 1600 pitch 6400 (/4 1600)
>[792931.368] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e53b00]
>[792931.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e53b00] width 1600 pitch 6400 (/4 1600)
>[792931.437] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b8c00]
>[792931.466] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b8c00] width 1600 pitch 6400 (/4 1600)
>[792931.470] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792931.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792931.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef82d0]
>[792931.583] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef82d0] width 1600 pitch 6400 (/4 1600)
>[792931.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b974a0]
>[792931.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b974a0] width 1600 pitch 6400 (/4 1600)
>[792931.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef82d0]
>[792931.723] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef82d0] width 1600 pitch 6400 (/4 1600)
>[792931.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cef0]
>[792931.801] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cef0] width 1600 pitch 6400 (/4 1600)
>[792940.780] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47c6d80]
>[792940.841] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47c6d80] width 1600 pitch 6400 (/4 1600)
>[792940.845] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ef91a0]
>[792940.908] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ef91a0] width 1600 pitch 6400 (/4 1600)
>[792940.928] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cef0]
>[792941.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cef0] width 1600 pitch 6400 (/4 1600)
>[792941.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeea90]
>[792941.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeea90] width 1600 pitch 6400 (/4 1600)
>[792941.247] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792941.326] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792941.350] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57a10]
>[792941.393] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57a10] width 1600 pitch 6400 (/4 1600)
>[792941.397] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590070]
>[792941.443] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590070] width 1600 pitch 6400 (/4 1600)
>[792941.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f0cef0]
>[792941.593] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f0cef0] width 1600 pitch 6400 (/4 1600)
>[792941.713] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792941.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792941.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590070]
>[792941.944] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590070] width 1600 pitch 6400 (/4 1600)
>[792942.075] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792942.128] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792942.255] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590070]
>[792942.312] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590070] width 1600 pitch 6400 (/4 1600)
>[792942.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ead70]
>[792942.496] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ead70] width 1600 pitch 6400 (/4 1600)
>[792942.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3590070]
>[792942.679] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3590070] width 1600 pitch 6400 (/4 1600)
>[792942.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5043c70]
>[792942.863] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5043c70] width 1600 pitch 6400 (/4 1600)
>[792942.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57a10]
>[792943.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57a10] width 1600 pitch 6400 (/4 1600)
>[792945.809] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eeea90]
>[792945.905] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eeea90] width 1600 pitch 6400 (/4 1600)
>[792945.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d57a70]
>[792946.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d57a70] width 1600 pitch 6400 (/4 1600)
>[792946.136] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e53b00]
>[792946.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e53b00] width 1600 pitch 6400 (/4 1600)
>[793001.746] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793001.746] BUG: synaptics.c:3122 in UpdateTouchState()
>[793001.746] 
>[793001.746] Backtrace:
>[793001.747] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793001.747] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793001.747] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793001.747] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793001.747] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793001.747] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793001.747] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793001.747] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793001.747] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793001.748] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793001.748] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793001.748] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793001.748] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793001.748] 
>[793036.690] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793036.690] BUG: synaptics.c:3122 in UpdateTouchState()
>[793036.690] 
>[793036.690] Backtrace:
>[793036.690] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793036.690] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793036.690] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793036.690] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793036.690] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793036.690] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793036.690] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793036.691] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793036.691] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793036.691] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793036.691] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793036.691] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793036.691] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793036.691] 
>[793086.399] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793086.399] BUG: synaptics.c:3122 in UpdateTouchState()
>[793086.399] 
>[793086.399] Backtrace:
>[793086.399] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793086.400] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793086.400] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793086.400] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793086.400] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793086.400] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793086.400] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793086.400] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793086.400] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793086.400] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793086.400] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793086.400] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793086.400] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793086.400] 
>[793098.710] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793098.710] BUG: synaptics.c:3122 in UpdateTouchState()
>[793098.710] 
>[793098.710] Backtrace:
>[793098.710] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793098.710] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793098.710] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793098.710] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793098.710] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793098.710] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793098.710] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793098.710] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[793098.710] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[793098.711] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[793098.711] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[793098.711] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[793098.711] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[793098.711] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[793098.711] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[793098.711] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[793098.711] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[793098.711] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[793098.711] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[793098.711] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793098.711] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793098.711] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793098.711] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793098.711] 
>[793104.920] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[793105.014] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[793105.506] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca9020]
>[793105.630] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca9020] width 1600 pitch 6400 (/4 1600)
>[793105.633] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892430]
>[793105.730] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892430] width 1600 pitch 6400 (/4 1600)
>[793105.733] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ca9020]
>[793105.795] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ca9020] width 1600 pitch 6400 (/4 1600)
>[793105.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892430]
>[793105.864] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892430] width 1600 pitch 6400 (/4 1600)
>[793105.980] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5892430]
>[793106.047] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5892430] width 1600 pitch 6400 (/4 1600)
>[793106.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d04e70]
>[793106.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d04e70] width 1600 pitch 6400 (/4 1600)
>[793106.294] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x388b890]
>[793106.542] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x388b890] width 1600 pitch 6400 (/4 1600)
>[793106.774] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c51f10]
>[793106.916] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c51f10] width 1600 pitch 6400 (/4 1600)
>[793106.918] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac950]
>[793106.995] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac950] width 1600 pitch 6400 (/4 1600)
>[793238.494] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793238.494] BUG: synaptics.c:3122 in UpdateTouchState()
>[793238.494] 
>[793238.494] Backtrace:
>[793238.494] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793238.494] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793238.494] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793238.494] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793238.494] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793238.494] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793238.494] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793238.494] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793238.494] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793238.494] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793238.495] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793238.495] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793238.495] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793238.495] 
>[793238.694] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793238.694] BUG: synaptics.c:3122 in UpdateTouchState()
>[793238.694] 
>[793238.694] Backtrace:
>[793238.694] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793238.694] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793238.694] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793238.694] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793238.694] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793238.694] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793238.694] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793238.694] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793238.694] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793238.694] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793238.694] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793238.694] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793238.694] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793238.694] 
>[793243.678] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793243.678] BUG: synaptics.c:3122 in UpdateTouchState()
>[793243.678] 
>[793243.678] Backtrace:
>[793243.678] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793243.678] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793243.678] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793243.678] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793243.678] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793243.678] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793243.678] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793243.678] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793243.678] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793243.678] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793243.678] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793243.678] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793243.678] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793243.678] 
>[793252.188] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793252.188] BUG: synaptics.c:3122 in UpdateTouchState()
>[793252.188] 
>[793252.188] Backtrace:
>[793252.188] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793252.188] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793252.188] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793252.188] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793252.188] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793252.188] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793252.188] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793252.188] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[793252.188] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[793252.188] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[793252.188] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[793252.188] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[793252.189] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[793252.189] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[793252.189] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[793252.189] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[793252.189] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[793252.189] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[793252.189] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[793252.189] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793252.189] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793252.189] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793252.189] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793252.189] 
>[793252.532] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793252.532] BUG: synaptics.c:3122 in UpdateTouchState()
>[793252.532] 
>[793252.532] Backtrace:
>[793252.532] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793252.532] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793252.532] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793252.532] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793252.532] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793252.532] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793252.532] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793252.532] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[793252.532] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[793252.532] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[793252.532] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[793252.532] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[793252.532] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[793252.532] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[793252.532] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[793252.532] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[793252.532] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[793252.532] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[793252.532] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[793252.532] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793252.532] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793252.532] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793252.532] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793252.532] 
>[793252.809] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793252.809] BUG: synaptics.c:3122 in UpdateTouchState()
>[793252.809] 
>[793252.809] Backtrace:
>[793252.809] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793252.809] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793252.809] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793252.809] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793252.809] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793252.810] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793252.810] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793252.810] 7: /usr/bin/Xorg (WaitForSomething+0x808) [0x462f18]
>[793252.810] 8: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793252.810] 9: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793252.810] 10: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793252.810] 11: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793252.810] 
>[793253.755] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793253.791] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793253.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dcbb0]
>[793253.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dcbb0] width 1600 pitch 6400 (/4 1600)
>[793253.861] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793253.892] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793253.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673c360]
>[793253.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673c360] width 1600 pitch 6400 (/4 1600)
>[793253.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[793254.072] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793254.072] BUG: synaptics.c:3122 in UpdateTouchState()
>[793254.072] 
>[793254.072] Backtrace:
>[793254.073] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793254.073] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793254.073] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793254.073] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793254.073] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793254.073] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793254.073] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793254.073] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[793254.073] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[793254.073] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[793254.073] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[793254.073] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[793254.073] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[793254.073] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[793254.073] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[793254.073] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[793254.073] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[793254.073] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[793254.074] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[793254.074] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793254.074] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793254.074] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793254.074] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793254.074] 
>[793254.108] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[793254.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e230]
>[793254.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e230] width 1600 pitch 6400 (/4 1600)
>[793258.041] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x48dcbb0]
>[793258.085] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x48dcbb0] width 1600 pitch 6400 (/4 1600)
>[793258.089] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36dcf50]
>[793258.119] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36dcf50] width 1600 pitch 6400 (/4 1600)
>[793258.121] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[793258.169] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[793258.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6861400]
>[793258.219] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6861400] width 1600 pitch 6400 (/4 1600)
>[793258.223] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[793258.252] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[793258.256] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6861400]
>[793258.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6861400] width 1600 pitch 6400 (/4 1600)
>[793258.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[793258.319] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[793258.320] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c75c60]
>[793258.403] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c75c60] width 1600 pitch 6400 (/4 1600)
>[793290.510] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793290.511] BUG: synaptics.c:3122 in UpdateTouchState()
>[793290.511] 
>[793290.511] Backtrace:
>[793290.511] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793290.511] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793290.511] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793290.511] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793290.511] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793290.511] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793290.511] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793290.511] 7: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0x15580) [0x7f675477e580]
>[793290.511] 8: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbe38a) [0x7f675482738a]
>[793290.511] 9: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xbbf5) [0x7f6753b0ebf5]
>[793290.511] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xc36b) [0x7f6753b0f36b]
>[793290.511] 11: /usr/bin/Xorg (0x400000+0x1022a1) [0x5022a1]
>[793290.511] 12: /usr/bin/Xorg (0x400000+0xfb486) [0x4fb486]
>[793290.512] 13: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793290.512] 14: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793290.512] 15: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793290.512] 16: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793290.512] 
>[793291.793] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793291.858] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793291.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793291.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793291.998] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793292.042] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793292.047] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3980660]
>[793292.084] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3980660] width 1600 pitch 6400 (/4 1600)
>[793296.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4029720]
>[793296.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4029720] width 1600 pitch 6400 (/4 1600)
>[793296.077] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9aa10]
>[793296.136] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9aa10] width 1600 pitch 6400 (/4 1600)
>[793296.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e230]
>[793296.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e230] width 1600 pitch 6400 (/4 1600)
>[793296.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f9aa10]
>[793296.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f9aa10] width 1600 pitch 6400 (/4 1600)
>[793296.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[793296.354] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[793296.358] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793296.387] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793296.391] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x580f180]
>[793296.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x580f180] width 1600 pitch 6400 (/4 1600)
>[793296.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[793296.504] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[793296.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e230]
>[793296.688] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e230] width 1600 pitch 6400 (/4 1600)
>[793296.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4029720]
>[793296.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4029720] width 1600 pitch 6400 (/4 1600)
>[793354.110] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36960]
>[793354.170] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36960] width 1600 pitch 6400 (/4 1600)
>[793354.280] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b8ab30]
>[793354.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b8ab30] width 1600 pitch 6400 (/4 1600)
>[793354.669] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793354.776] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793362.297] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793362.323] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793362.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793362.797] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793363.054] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x394d870]
>[793363.091] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x394d870] width 1600 pitch 6400 (/4 1600)
>[793363.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[793363.165] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[793363.276] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef290]
>[793363.332] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef290] width 1600 pitch 6400 (/4 1600)
>[793363.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e7e230]
>[793363.516] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e7e230] width 1600 pitch 6400 (/4 1600)
>[793363.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[793363.700] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[793376.647] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793376.647] BUG: synaptics.c:3122 in UpdateTouchState()
>[793376.647] 
>[793376.648] Backtrace:
>[793376.648] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793376.648] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793376.648] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793376.648] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793376.648] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793376.648] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793376.648] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793376.648] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793376.648] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793376.648] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793376.648] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793376.648] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793376.648] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793376.648] 
>[793376.733] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793376.733] BUG: synaptics.c:3122 in UpdateTouchState()
>[793376.733] 
>[793376.733] Backtrace:
>[793376.733] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793376.733] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793376.733] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793376.733] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793376.733] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793376.733] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793376.733] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793376.733] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793376.733] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793376.733] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793376.733] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793376.733] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793376.734] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793376.734] 
>[793380.835] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793380.835] BUG: synaptics.c:3122 in UpdateTouchState()
>[793380.835] 
>[793380.835] Backtrace:
>[793380.835] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793380.835] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793380.835] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793380.835] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793380.835] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793380.836] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793380.836] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793380.836] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793380.836] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793380.836] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793380.836] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793380.836] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793380.836] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793380.836] 
>[793397.882] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793397.882] BUG: synaptics.c:3122 in UpdateTouchState()
>[793397.883] 
>[793397.883] Backtrace:
>[793397.883] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793397.883] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793397.883] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793397.883] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793397.883] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793397.883] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793397.883] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793397.883] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793397.883] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793397.883] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793397.884] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793397.884] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793397.884] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793397.884] 
>[793398.063] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793398.063] BUG: synaptics.c:3122 in UpdateTouchState()
>[793398.063] 
>[793398.063] Backtrace:
>[793398.063] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793398.063] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793398.063] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793398.063] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793398.063] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793398.063] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793398.063] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793398.063] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793398.063] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793398.063] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793398.063] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793398.063] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793398.063] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793398.063] 
>[793444.955] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x68609e0]
>[793445.255] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x68609e0] width 1600 pitch 6400 (/4 1600)
>[793445.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4898440]
>[793445.454] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4898440] width 1600 pitch 6400 (/4 1600)
>[793445.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793445.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793462.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793462.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793463.344] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[793463.364] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[793463.690] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[793463.732] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[793463.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793463.882] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793464.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1cc0]
>[793464.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1cc0] width 1600 pitch 6400 (/4 1600)
>[793464.185] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4898440]
>[793464.250] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4898440] width 1600 pitch 6400 (/4 1600)
>[793464.367] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793464.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793464.554] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793464.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793464.734] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793464.785] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793464.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac950]
>[793464.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac950] width 1600 pitch 6400 (/4 1600)
>[793465.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793465.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793465.274] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36960]
>[793465.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36960] width 1600 pitch 6400 (/4 1600)
>[793465.472] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef290]
>[793465.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef290] width 1600 pitch 6400 (/4 1600)
>[793472.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793473.266] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793473.374] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793473.394] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793473.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793473.742] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793474.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[793475.003] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[793475.214] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef290]
>[793475.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef290] width 1600 pitch 6400 (/4 1600)
>[793475.594] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[793475.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[793475.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4cef290]
>[793475.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4cef290] width 1600 pitch 6400 (/4 1600)
>[793477.068] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3662f40]
>[793477.087] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3662f40] width 1600 pitch 6400 (/4 1600)
>[793477.505] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793477.553] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793477.711] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1cc0]
>[793477.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1cc0] width 1600 pitch 6400 (/4 1600)
>[793477.761] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793477.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793477.960] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e1cc0]
>[793478.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e1cc0] width 1600 pitch 6400 (/4 1600)
>[793478.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38ee2e0]
>[793478.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38ee2e0] width 1600 pitch 6400 (/4 1600)
>[793478.618] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x673dcf0]
>[793478.676] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x673dcf0] width 1600 pitch 6400 (/4 1600)
>[793479.686] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793479.760] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793479.773] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942e00]
>[793479.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942e00] width 1600 pitch 6400 (/4 1600)
>[793480.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[793481.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[793481.178] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793481.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793481.504] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[793481.634] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[793481.853] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3662f40]
>[793481.920] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3662f40] width 1600 pitch 6400 (/4 1600)
>[793482.195] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793482.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793482.515] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793482.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793482.583] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793482.616] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793534.498] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793534.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793534.639] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793534.654] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793537.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793537.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793538.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793538.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793586.132] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793586.189] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793586.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793587.043] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793587.067] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793587.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793587.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793587.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793587.265] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793587.327] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793587.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793587.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793587.622] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793587.678] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793587.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793587.862] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793587.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793588.046] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793588.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793588.230] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793588.351] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793588.414] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793588.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793588.597] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793588.724] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793588.781] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793588.892] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793588.948] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793589.065] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793589.132] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793589.248] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793589.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793589.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793589.500] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793589.610] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793589.667] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793590.986] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793591.021] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793591.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793591.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793591.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793591.137] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793591.139] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793591.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793591.187] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793591.254] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793591.275] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793591.371] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793591.376] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793591.405] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793591.427] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793591.488] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793591.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793591.672] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793591.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793591.856] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793591.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c5d0]
>[793592.023] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c5d0] width 1600 pitch 6400 (/4 1600)
>[793592.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793592.207] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793592.334] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793592.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793592.525] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793592.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793592.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793592.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793592.885] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c5d0]
>[793592.942] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c5d0] width 1600 pitch 6400 (/4 1600)
>[793593.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793593.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793593.240] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793593.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793593.429] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793593.477] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793593.611] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793593.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793593.791] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c5d0]
>[793593.845] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c5d0] width 1600 pitch 6400 (/4 1600)
>[793593.974] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793594.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793594.156] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793594.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793594.340] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793594.396] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793594.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793594.581] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793705.990] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793706.076] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793706.096] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793706.175] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793706.202] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c5d0]
>[793706.260] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c5d0] width 1600 pitch 6400 (/4 1600)
>[793706.266] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793706.311] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793710.227] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793710.271] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793710.278] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793710.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793710.324] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793710.355] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793710.359] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793710.438] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793710.443] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793710.472] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793710.475] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793710.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793710.510] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c16600]
>[793710.538] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c16600] width 1600 pitch 6400 (/4 1600)
>[793710.542] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793710.622] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793770.157] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793770.245] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793770.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793770.415] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793770.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c720]
>[793770.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c720] width 1600 pitch 6400 (/4 1600)
>[793771.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38675c0]
>[793771.774] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38675c0] width 1600 pitch 6400 (/4 1600)
>[793772.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49721a0]
>[793772.286] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49721a0] width 1600 pitch 6400 (/4 1600)
>[793772.428] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36960]
>[793772.470] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36960] width 1600 pitch 6400 (/4 1600)
>[793772.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793772.587] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793772.725] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36960]
>[793772.788] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36960] width 1600 pitch 6400 (/4 1600)
>[793772.902] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793772.955] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793772.958] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793773.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793773.024] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793773.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793773.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793773.139] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793773.273] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793773.322] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793773.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793773.506] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793773.625] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793773.673] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793773.805] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793773.857] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793773.983] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[793774.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[793774.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793774.225] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793774.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793774.408] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793775.208] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c720]
>[793775.379] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c720] width 1600 pitch 6400 (/4 1600)
>[793775.587] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b80]
>[793775.617] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b80] width 1600 pitch 6400 (/4 1600)
>[793775.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793775.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793787.657] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942e00]
>[793787.660] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942e00] width 1600 pitch 6400 (/4 1600)
>[793787.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793788.032] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793788.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[793788.446] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[793788.544] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793788.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793788.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b0df0]
>[793788.780] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b0df0] width 1600 pitch 6400 (/4 1600)
>[793788.914] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793788.964] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793789.086] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793789.148] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793789.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36b0df0]
>[793789.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36b0df0] width 1600 pitch 6400 (/4 1600)
>[793789.461] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3023ec0]
>[793789.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3023ec0] width 1600 pitch 6400 (/4 1600)
>[793789.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793789.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793789.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793789.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793789.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e36960]
>[793790.050] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e36960] width 1600 pitch 6400 (/4 1600)
>[793790.171] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793790.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793790.361] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793790.417] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793796.425] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793796.425] BUG: synaptics.c:3122 in UpdateTouchState()
>[793796.425] 
>[793796.425] Backtrace:
>[793796.425] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793796.425] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793796.425] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793796.425] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793796.425] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793796.425] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793796.425] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793796.425] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[793796.426] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[793796.426] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[793796.426] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793796.426] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793796.426] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793796.426] 
>[793796.667] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[793796.667] BUG: synaptics.c:3122 in UpdateTouchState()
>[793796.667] 
>[793796.668] Backtrace:
>[793796.668] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[793796.668] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[793796.668] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[793796.668] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[793796.668] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[793796.668] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[793796.668] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[793796.668] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[793796.668] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[793796.668] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[793796.668] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[793796.668] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[793796.668] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[793796.668] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[793796.668] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[793796.668] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[793796.668] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[793796.669] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[793796.669] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[793796.669] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[793796.669] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[793796.669] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[793796.669] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[793796.669] 
>[793869.559] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793869.628] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793869.678] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[793869.745] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[793870.002] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793870.037] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793870.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793870.096] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793870.138] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793870.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793870.221] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793870.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793870.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793870.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793870.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793870.464] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793870.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793870.648] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793870.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793870.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793870.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793870.831] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793870.877] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793870.898] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793870.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793870.998] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793871.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793871.049] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793871.142] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793871.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793871.316] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793871.366] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793871.411] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793871.433] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793871.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793871.550] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793871.605] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793871.633] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793871.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793871.684] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793871.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793871.750] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793871.754] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793871.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793871.789] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793871.817] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793871.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793871.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793871.852] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793871.934] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793871.938] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793871.968] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793871.972] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793872.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793872.005] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793872.035] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793872.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793872.118] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793872.122] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793872.152] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793872.224] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793872.285] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793872.396] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793872.452] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793872.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793872.636] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793872.765] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793872.820] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793872.943] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793873.004] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793873.115] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[793873.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[793883.831] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793883.889] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793883.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793883.933] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793883.936] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793883.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793883.989] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793884.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793884.055] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793884.167] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793884.169] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793884.217] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793884.220] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793884.334] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793884.338] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793884.367] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793884.375] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793884.451] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793884.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793884.484] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793884.488] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793884.518] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793884.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793884.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793884.603] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[793884.635] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[793884.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793884.685] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793887.290] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793887.400] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793887.935] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793888.001] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793888.007] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793888.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793888.194] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793888.262] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793888.379] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793888.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793888.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793888.629] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793888.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793888.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793888.915] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793888.980] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793889.097] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793889.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793889.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793889.348] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793889.456] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793889.515] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793889.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793889.699] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793889.811] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793889.883] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793890.003] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793890.066] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793890.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793890.233] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793890.373] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793890.434] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793890.545] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793890.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793890.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793890.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793890.913] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793890.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793891.094] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793891.153] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793891.277] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793891.336] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793891.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793891.520] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793891.643] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793891.704] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793891.812] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793891.871] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793891.994] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793892.055] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793892.182] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793892.239] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793892.364] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793892.422] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793892.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793892.606] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793892.727] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793892.790] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793892.907] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793892.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793893.102] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793893.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793893.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793893.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793893.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793893.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793893.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793893.692] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793893.823] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793893.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793893.997] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793894.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793894.186] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793894.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793894.357] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793894.411] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793894.546] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793894.595] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793894.726] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793894.779] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793894.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793894.962] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793895.101] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793895.146] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793895.264] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793895.330] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793895.455] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793895.514] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793895.635] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793895.698] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793895.813] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793895.881] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793895.996] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793896.048] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793896.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793896.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793896.356] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793896.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793896.543] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793896.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793896.712] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793896.784] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793896.889] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793896.951] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793897.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793897.135] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793897.257] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793897.318] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793897.438] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793897.503] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793897.621] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793897.686] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793897.799] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793897.870] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793897.991] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793898.054] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793902.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793902.064] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793902.069] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793902.115] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793902.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793902.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793902.168] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793902.232] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793902.236] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793902.282] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793902.343] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793902.399] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793902.524] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e645b0]
>[793902.582] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e645b0] width 1600 pitch 6400 (/4 1600)
>[793902.714] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793902.766] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793902.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793902.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793903.064] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793903.117] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793912.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793912.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793912.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[793912.258] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[793912.281] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[793912.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[793912.327] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793912.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793912.447] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793912.509] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793912.512] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793912.592] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793912.596] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793912.642] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793912.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793912.869] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793912.893] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793912.943] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793913.030] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793913.077] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793913.081] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793913.144] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793913.245] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793913.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793913.415] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793913.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793913.604] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793913.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793913.784] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793913.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793913.964] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793914.030] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793914.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[793914.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[793914.326] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793914.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793914.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793914.564] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793914.693] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793914.748] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793914.876] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793914.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793915.056] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793915.116] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793915.137] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793915.199] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793915.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793915.249] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793915.251] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793915.316] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793915.402] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793915.467] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793915.593] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[793915.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[793915.777] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793915.834] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793915.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793916.018] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793916.145] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793916.202] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793916.317] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793916.386] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793916.503] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793916.570] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793916.680] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793916.737] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793916.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793916.932] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793921.676] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[793921.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[793921.721] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793921.767] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793921.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793921.851] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793921.854] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793921.901] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793921.905] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793921.950] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793921.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793922.017] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793922.022] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793922.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793922.135] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793922.185] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793925.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[793925.092] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[793925.095] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793925.143] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793925.159] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793925.193] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793925.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793925.313] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793925.315] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793925.427] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793925.431] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793925.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793925.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793925.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793925.584] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793925.644] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793925.649] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793925.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793925.699] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793925.758] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793925.771] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793925.828] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793931.567] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793931.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793931.641] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793931.677] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793931.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793931.777] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793931.779] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793931.877] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793931.881] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793931.961] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793931.966] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793932.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793932.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793932.113] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793932.120] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793932.178] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793932.183] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793932.228] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793932.233] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793932.294] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793932.304] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793932.362] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793932.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793932.546] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793932.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793932.729] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793932.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[793932.897] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[793933.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[793933.081] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[793933.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a03340]
>[793933.281] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a03340] width 1600 pitch 6400 (/4 1600)
>[793933.394] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49a1b50]
>[793933.448] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49a1b50] width 1600 pitch 6400 (/4 1600)
>[793933.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793933.632] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793933.749] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc11f0]
>[793933.815] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc11f0] width 1600 pitch 6400 (/4 1600)
>[793933.931] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[793933.999] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[793934.131] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793934.183] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793934.293] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[793934.351] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[793934.485] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[793934.534] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[793934.560] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793934.601] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793934.662] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e645b0]
>[793934.718] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e645b0] width 1600 pitch 6400 (/4 1600)
>[793934.846] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793934.902] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793935.026] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793935.086] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793935.201] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793935.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793935.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793935.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793935.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793935.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793935.747] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[793935.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[793935.949] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793936.005] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793936.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793936.172] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793936.296] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793936.356] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793936.486] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793936.540] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793936.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793936.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793936.834] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793936.891] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793937.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793937.074] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793937.200] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793937.275] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793937.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793937.442] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793937.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793937.626] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793937.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793937.793] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793937.933] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793937.994] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793938.106] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e645b0]
>[793938.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e645b0] width 1600 pitch 6400 (/4 1600)
>[793938.295] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793938.344] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793938.466] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793938.528] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793938.656] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793938.712] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793938.833] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793938.896] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793939.014] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793939.080] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793939.196] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[793939.263] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[793939.382] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793939.447] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793939.561] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793939.614] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793939.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793939.798] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793939.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793939.982] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793940.113] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793940.166] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793940.284] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793940.350] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793940.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793940.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793940.655] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793940.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793940.828] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[793940.885] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[793941.016] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[793941.068] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[793941.205] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[793941.269] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[793941.377] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793941.436] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793941.557] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e645b0]
>[793941.620] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e645b0] width 1600 pitch 6400 (/4 1600)
>[793941.735] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5883b70]
>[793941.804] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5883b70] width 1600 pitch 6400 (/4 1600)
>[793941.926] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[793941.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[793942.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x495afd0]
>[793942.171] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x495afd0] width 1600 pitch 6400 (/4 1600)
>[793942.282] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ecca70]
>[793942.338] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ecca70] width 1600 pitch 6400 (/4 1600)
>[793942.464] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36de870]
>[793942.522] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36de870] width 1600 pitch 6400 (/4 1600)
>[793942.644] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[793942.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[793942.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793942.890] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793943.013] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793943.073] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793943.193] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4fa9080]
>[793943.257] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4fa9080] width 1600 pitch 6400 (/4 1600)
>[793943.372] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793943.441] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793943.563] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793943.625] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[793943.744] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[793943.809] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[793943.922] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40e0ed0]
>[793943.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40e0ed0] width 1600 pitch 6400 (/4 1600)
>[793944.103] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[793944.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[793988.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793988.227] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793988.232] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[793988.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[793988.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[793988.969] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[793988.987] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793989.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793989.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793989.213] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793989.217] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[793989.246] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[793989.250] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e8e110]
>[793989.283] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e8e110] width 1600 pitch 6400 (/4 1600)
>[793989.288] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[793989.363] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[793989.483] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[793989.530] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[793989.663] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[793989.714] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[794040.061] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[794040.104] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[794040.173] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59f6b20]
>[794040.192] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59f6b20] width 1600 pitch 6400 (/4 1600)
>[794040.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x69accf0]
>[794040.270] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x69accf0] width 1600 pitch 6400 (/4 1600)
>[794040.272] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[794040.383] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[794040.386] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[794040.450] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[794040.454] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c1a00]
>[794040.517] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c1a00] width 1600 pitch 6400 (/4 1600)
>[794040.520] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ac60]
>[794040.567] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ac60] width 1600 pitch 6400 (/4 1600)
>[794040.570] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c1a00]
>[794040.600] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c1a00] width 1600 pitch 6400 (/4 1600)
>[794040.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794040.717] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794040.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[794040.813] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[794040.820] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977ef0]
>[794040.884] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977ef0] width 1600 pitch 6400 (/4 1600)
>[794040.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[794040.918] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[794044.857] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794044.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794044.900] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[794044.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[794044.930] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794044.976] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794044.977] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c1a00]
>[794045.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c1a00] width 1600 pitch 6400 (/4 1600)
>[794045.049] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794045.079] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794045.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x72c1a00]
>[794045.112] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x72c1a00] width 1600 pitch 6400 (/4 1600)
>[794045.114] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794045.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794045.170] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794045.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794045.339] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[794045.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[794045.533] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[794045.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[794045.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[794045.646] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[794045.651] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[794045.680] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[794045.684] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[794045.713] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[794045.717] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83370]
>[794045.796] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83370] width 1600 pitch 6400 (/4 1600)
>[794045.890] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4dd0]
>[794045.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4dd0] width 1600 pitch 6400 (/4 1600)
>[794045.953] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb3010]
>[794045.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb3010] width 1600 pitch 6400 (/4 1600)
>[794046.354] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[794046.381] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[794046.426] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[794046.482] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[794046.517] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83370]
>[794046.533] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83370] width 1600 pitch 6400 (/4 1600)
>[794046.640] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac950]
>[794046.682] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac950] width 1600 pitch 6400 (/4 1600)
>[794046.822] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4795710]
>[794046.866] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4795710] width 1600 pitch 6400 (/4 1600)
>[794047.021] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[794047.051] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[794047.082] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3c74560]
>[794047.100] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3c74560] width 1600 pitch 6400 (/4 1600)
>[794047.127] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[794047.159] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[794047.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57fb220]
>[794047.234] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57fb220] width 1600 pitch 6400 (/4 1600)
>[794047.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[794047.284] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[794047.390] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[794047.418] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[794047.446] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[794047.468] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[794047.521] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794047.535] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794047.575] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794047.602] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794047.632] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794047.652] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794047.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[794047.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[794047.888] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5948ee0]
>[794047.952] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5948ee0] width 1600 pitch 6400 (/4 1600)
>[794048.111] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4dd0]
>[794048.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4dd0] width 1600 pitch 6400 (/4 1600)
>[794048.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5067c70]
>[794048.637] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5067c70] width 1600 pitch 6400 (/4 1600)
>[794048.648] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[794048.705] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[794048.801] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977ef0]
>[794048.872] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977ef0] width 1600 pitch 6400 (/4 1600)
>[794048.971] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e2f0]
>[794049.022] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e2f0] width 1600 pitch 6400 (/4 1600)
>[794049.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58cf8f0]
>[794049.984] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58cf8f0] width 1600 pitch 6400 (/4 1600)
>[794050.015] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ac60]
>[794050.125] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ac60] width 1600 pitch 6400 (/4 1600)
>[794050.130] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794050.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794050.212] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ac60]
>[794050.242] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ac60] width 1600 pitch 6400 (/4 1600)
>[794050.244] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[794050.325] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[794050.330] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687ac60]
>[794050.359] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687ac60] width 1600 pitch 6400 (/4 1600)
>[794050.363] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[794050.392] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[794050.421] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4977ef0]
>[794050.476] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4977ef0] width 1600 pitch 6400 (/4 1600)
>[794182.218] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57ac950]
>[794182.259] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57ac950] width 1600 pitch 6400 (/4 1600)
>[794182.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3eb3010]
>[794182.305] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3eb3010] width 1600 pitch 6400 (/4 1600)
>[794182.310] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dad930]
>[794182.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dad930] width 1600 pitch 6400 (/4 1600)
>[794182.768] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[794182.811] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[794182.825] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4f708c0]
>[794182.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4f708c0] width 1600 pitch 6400 (/4 1600)
>[794183.038] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d190]
>[794183.061] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d190] width 1600 pitch 6400 (/4 1600)
>[794183.164] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b4990]
>[794183.179] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b4990] width 1600 pitch 6400 (/4 1600)
>[794185.903] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c10]
>[794185.963] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c10] width 1600 pitch 6400 (/4 1600)
>[794186.493] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x58d0f60]
>[794186.571] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x58d0f60] width 1600 pitch 6400 (/4 1600)
>[794186.576] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7aed0]
>[794186.621] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7aed0] width 1600 pitch 6400 (/4 1600)
>[794195.134] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a25350]
>[794195.177] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a25350] width 1600 pitch 6400 (/4 1600)
>[794195.204] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83370]
>[794195.277] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83370] width 1600 pitch 6400 (/4 1600)
>[794195.360] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e0960]
>[794195.416] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e0960] width 1600 pitch 6400 (/4 1600)
>[794195.468] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ababc0]
>[794195.578] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ababc0] width 1600 pitch 6400 (/4 1600)
>[794195.580] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[794195.662] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[794195.666] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x35dcd20]
>[794195.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x35dcd20] width 1600 pitch 6400 (/4 1600)
>[794195.698] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f65fb0]
>[794195.740] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f65fb0] width 1600 pitch 6400 (/4 1600)
>[794195.742] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3dad930]
>[794195.812] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3dad930] width 1600 pitch 6400 (/4 1600)
>[794195.927] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3534220]
>[794195.996] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3534220] width 1600 pitch 6400 (/4 1600)
>[794196.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d02d30]
>[794196.163] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d02d30] width 1600 pitch 6400 (/4 1600)
>[794248.108] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[794248.203] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[794248.564] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6862110]
>[794248.586] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6862110] width 1600 pitch 6400 (/4 1600)
>[794248.894] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[794248.954] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[794249.189] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794249.210] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794249.578] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50c7020]
>[794249.706] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50c7020] width 1600 pitch 6400 (/4 1600)
>[794249.864] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c3f0]
>[794249.919] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c3f0] width 1600 pitch 6400 (/4 1600)
>[794249.924] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3945af0]
>[794249.974] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3945af0] width 1600 pitch 6400 (/4 1600)
>[794250.104] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794250.157] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794267.948] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5869230]
>[794268.040] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5869230] width 1600 pitch 6400 (/4 1600)
>[794268.063] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[794268.208] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[794268.550] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x57b3cc0]
>[794268.674] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x57b3cc0] width 1600 pitch 6400 (/4 1600)
>[794269.083] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x511d730]
>[794269.158] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x511d730] width 1600 pitch 6400 (/4 1600)
>[794269.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041fa0]
>[794269.508] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041fa0] width 1600 pitch 6400 (/4 1600)
>[794269.821] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[794269.876] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[794269.880] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e09f0]
>[794269.909] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e09f0] width 1600 pitch 6400 (/4 1600)
>[794270.004] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[794270.060] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[794270.192] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d190]
>[794270.244] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d190] width 1600 pitch 6400 (/4 1600)
>[794270.408] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4959d40]
>[794270.651] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4959d40] width 1600 pitch 6400 (/4 1600)
>[794270.841] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59791b0]
>[794270.846] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59791b0] width 1600 pitch 6400 (/4 1600)
>[794271.050] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[794271.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[794273.058] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3800970]
>[794273.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3800970] width 1600 pitch 6400 (/4 1600)
>[794273.336] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3979c10]
>[794273.357] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3979c10] width 1600 pitch 6400 (/4 1600)
>[794273.909] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3b2c520]
>[794273.987] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3b2c520] width 1600 pitch 6400 (/4 1600)
>[794274.093] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3884b40]
>[794274.154] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3884b40] width 1600 pitch 6400 (/4 1600)
>[794274.267] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bb5a20]
>[794274.321] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bb5a20] width 1600 pitch 6400 (/4 1600)
>[794274.453] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d9530]
>[794274.505] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d9530] width 1600 pitch 6400 (/4 1600)
>[794274.626] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee020]
>[794274.689] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee020] width 1600 pitch 6400 (/4 1600)
>[794274.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[794274.873] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[794274.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bbbb00]
>[794275.056] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bbbb00] width 1600 pitch 6400 (/4 1600)
>[794275.184] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5951030]
>[794275.240] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5951030] width 1600 pitch 6400 (/4 1600)
>[794275.362] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[794275.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[794275.535] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3938610]
>[794275.591] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3938610] width 1600 pitch 6400 (/4 1600)
>[794275.723] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[794275.775] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[794275.904] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x36e09f0]
>[794275.959] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x36e09f0] width 1600 pitch 6400 (/4 1600)
>[794276.092] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2e9d1a0]
>[794276.142] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2e9d1a0] width 1600 pitch 6400 (/4 1600)
>[794276.262] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6862110]
>[794276.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6862110] width 1600 pitch 6400 (/4 1600)
>[794276.445] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794276.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794276.634] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3800970]
>[794276.694] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3800970] width 1600 pitch 6400 (/4 1600)
>[794276.814] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[794276.861] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[794276.993] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x37ed240]
>[794277.045] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x37ed240] width 1600 pitch 6400 (/4 1600)
>[794277.174] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f42f00]
>[794277.229] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f42f00] width 1600 pitch 6400 (/4 1600)
>[794277.353] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50b7940]
>[794277.413] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50b7940] width 1600 pitch 6400 (/4 1600)
>[794277.532] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50580c0]
>[794277.596] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50580c0] width 1600 pitch 6400 (/4 1600)
>[794277.716] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4959d40]
>[794277.764] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4959d40] width 1600 pitch 6400 (/4 1600)
>[794277.895] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7aed0]
>[794277.947] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7aed0] width 1600 pitch 6400 (/4 1600)
>[794278.073] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x2ebf550]
>[794278.131] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x2ebf550] width 1600 pitch 6400 (/4 1600)
>[794278.263] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3f737c0]
>[794278.315] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3f737c0] width 1600 pitch 6400 (/4 1600)
>[794278.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e3e340]
>[794278.499] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e3e340] width 1600 pitch 6400 (/4 1600)
>[794278.617] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[794278.683] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[794278.804] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4898440]
>[794278.867] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4898440] width 1600 pitch 6400 (/4 1600)
>[794278.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c5d0]
>[794279.034] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c5d0] width 1600 pitch 6400 (/4 1600)
>[794279.166] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a3c720]
>[794279.218] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a3c720] width 1600 pitch 6400 (/4 1600)
>[794279.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x50455a0]
>[794279.401] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x50455a0] width 1600 pitch 6400 (/4 1600)
>[794279.534] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6ad4e30]
>[794279.585] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6ad4e30] width 1600 pitch 6400 (/4 1600)
>[794279.715] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59e3530]
>[794279.769] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59e3530] width 1600 pitch 6400 (/4 1600)
>[794279.886] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4da05a0]
>[794279.953] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4da05a0] width 1600 pitch 6400 (/4 1600)
>[794280.066] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3d50220]
>[794280.120] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3d50220] width 1600 pitch 6400 (/4 1600)
>[794280.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x685dba0]
>[794280.304] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x685dba0] width 1600 pitch 6400 (/4 1600)
>[794280.444] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecb4c0]
>[794280.486] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794280.486] BUG: synaptics.c:3122 in UpdateTouchState()
>[794280.486] 
>[794280.486] Backtrace:
>[794280.486] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794280.486] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794280.486] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794280.486] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794280.486] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794280.486] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794280.486] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794280.486] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794280.486] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794280.486] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794280.486] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794280.486] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794280.486] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794280.486] 
>[794280.487] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecb4c0] width 1600 pitch 6400 (/4 1600)
>[794280.624] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c2d590]
>[794280.671] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c2d590] width 1600 pitch 6400 (/4 1600)
>[794280.802] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5866d20]
>[794280.855] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5866d20] width 1600 pitch 6400 (/4 1600)
>[794280.984] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x40a4dd0]
>[794281.039] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x40a4dd0] width 1600 pitch 6400 (/4 1600)
>[794281.165] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[794281.223] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[794281.346] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4ed7d70]
>[794281.391] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4ed7d70] width 1600 pitch 6400 (/4 1600)
>[794281.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e600]
>[794281.575] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e600] width 1600 pitch 6400 (/4 1600)
>[794281.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3de8d50]
>[794281.757] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3de8d50] width 1600 pitch 6400 (/4 1600)
>[794281.883] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4c4a510]
>[794281.941] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4c4a510] width 1600 pitch 6400 (/4 1600)
>[794282.059] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[794282.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[794282.254] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26b40]
>[794282.310] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26b40] width 1600 pitch 6400 (/4 1600)
>[794282.433] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3a63700]
>[794282.494] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3a63700] width 1600 pitch 6400 (/4 1600)
>[794282.607] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bcafb0]
>[794282.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bcafb0] width 1600 pitch 6400 (/4 1600)
>[794282.792] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[794282.844] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[794282.976] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38be670]
>[794283.028] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38be670] width 1600 pitch 6400 (/4 1600)
>[794283.153] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4de6ba0]
>[794283.212] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4de6ba0] width 1600 pitch 6400 (/4 1600)
>[794283.335] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59b4990]
>[794283.395] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59b4990] width 1600 pitch 6400 (/4 1600)
>[794283.523] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a901f0]
>[794283.580] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a901f0] width 1600 pitch 6400 (/4 1600)
>[794283.704] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[794283.763] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[794294.429] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794294.429] BUG: synaptics.c:3122 in UpdateTouchState()
>[794294.429] 
>[794294.429] Backtrace:
>[794294.429] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794294.429] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794294.429] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794294.429] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794294.429] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794294.429] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794294.429] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794294.430] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794294.430] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794294.430] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794294.430] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794294.430] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794294.430] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794294.430] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794294.430] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794294.430] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794294.430] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794294.430] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794294.430] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794294.430] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794294.430] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794294.430] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794294.430] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794294.430] 
>[794295.171] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794295.171] BUG: synaptics.c:3122 in UpdateTouchState()
>[794295.171] 
>[794295.171] Backtrace:
>[794295.172] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794295.172] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794295.172] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794295.172] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794295.172] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794295.172] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794295.172] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794295.172] 7: /lib64/libc.so.6 (0x3171e00000+0x1449c4) [0x3171f449c4]
>[794295.172] 8: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbe407) [0x7f6754827407]
>[794295.172] 9: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794295.172] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7c75) [0x7f6753b0ac75]
>[794295.172] 11: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe0ed) [0x7f6753b110ed]
>[794295.172] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xeaaa) [0x7f6753b11aaa]
>[794295.172] 13: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794295.172] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[794295.172] 15: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[794295.172] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794295.173] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794295.173] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794295.173] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794295.173] 
>[794295.897] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e600]
>[794295.928] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e600] width 1600 pitch 6400 (/4 1600)
>[794295.952] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be8e80]
>[794296.025] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be8e80] width 1600 pitch 6400 (/4 1600)
>[794296.039] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26b40]
>[794296.129] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26b40] width 1600 pitch 6400 (/4 1600)
>[794296.133] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x588b250]
>[794296.162] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x588b250] width 1600 pitch 6400 (/4 1600)
>[794296.167] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26b40]
>[794296.205] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26b40] width 1600 pitch 6400 (/4 1600)
>[794296.384] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794296.384] BUG: synaptics.c:3122 in UpdateTouchState()
>[794296.384] 
>[794296.384] Backtrace:
>[794296.384] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794296.384] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794296.384] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794296.384] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794296.384] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794296.384] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794296.384] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794296.384] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794296.385] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794296.385] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794296.385] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794296.385] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794296.385] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794296.385] 
>[794296.713] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794296.713] BUG: synaptics.c:3122 in UpdateTouchState()
>[794296.713] 
>[794296.713] Backtrace:
>[794296.713] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794296.713] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794296.713] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794296.713] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794296.714] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794296.714] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794296.714] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794296.714] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794296.714] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794296.714] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794296.714] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794296.714] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794296.714] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794296.714] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794296.714] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794296.714] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794296.714] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794296.714] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794296.714] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794296.714] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794296.714] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794296.715] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794296.715] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794296.715] 
>[794300.154] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x380d190]
>[794300.204] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x380d190] width 1600 pitch 6400 (/4 1600)
>[794300.209] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ca030]
>[794300.274] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ca030] width 1600 pitch 6400 (/4 1600)
>[794300.279] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[794300.307] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[794300.312] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x47ca030]
>[794300.340] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x47ca030] width 1600 pitch 6400 (/4 1600)
>[794300.355] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[794300.424] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[794300.440] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38951f0]
>[794300.524] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38951f0] width 1600 pitch 6400 (/4 1600)
>[794300.529] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f75cc0]
>[794300.565] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f75cc0] width 1600 pitch 6400 (/4 1600)
>[794300.568] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecf070]
>[794300.641] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecf070] width 1600 pitch 6400 (/4 1600)
>[794300.752] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3942af0]
>[794300.808] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3942af0] width 1600 pitch 6400 (/4 1600)
>[794300.932] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a83df0]
>[794300.992] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a83df0] width 1600 pitch 6400 (/4 1600)
>[794301.116] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4962040]
>[794301.176] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4962040] width 1600 pitch 6400 (/4 1600)
>[794301.302] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f2afd0]
>[794301.360] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f2afd0] width 1600 pitch 6400 (/4 1600)
>[794301.476] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3e7aed0]
>[794301.527] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3e7aed0] width 1600 pitch 6400 (/4 1600)
>[794301.665] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x38d1cb0]
>[794301.711] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x38d1cb0] width 1600 pitch 6400 (/4 1600)
>[794301.844] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3bc74c0]
>[794301.895] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3bc74c0] width 1600 pitch 6400 (/4 1600)
>[794302.023] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x6a25350]
>[794302.078] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x6a25350] width 1600 pitch 6400 (/4 1600)
>[794302.203] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x486e0d0]
>[794302.279] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x486e0d0] width 1600 pitch 6400 (/4 1600)
>[794302.384] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5f07450]
>[794302.429] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5f07450] width 1600 pitch 6400 (/4 1600)
>[794313.093] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794313.093] BUG: synaptics.c:3122 in UpdateTouchState()
>[794313.093] 
>[794313.093] Backtrace:
>[794313.093] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794313.093] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794313.093] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794313.093] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794313.093] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794313.093] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794313.093] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794313.093] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794313.093] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794313.093] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794313.093] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794313.093] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794313.093] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794313.093] 
>[794313.831] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794313.831] BUG: synaptics.c:3122 in UpdateTouchState()
>[794313.831] 
>[794313.831] Backtrace:
>[794313.832] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794313.832] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794313.832] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794313.832] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794313.832] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794313.832] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794313.832] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794313.832] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794313.832] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794313.832] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794313.832] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794313.832] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794313.832] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794313.832] 
>[794328.061] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794328.061] BUG: synaptics.c:3122 in UpdateTouchState()
>[794328.061] 
>[794328.061] Backtrace:
>[794328.061] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794328.061] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794328.061] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794328.061] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794328.061] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794328.062] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794328.062] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794328.062] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794328.062] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794328.062] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794328.062] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794328.062] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794328.062] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794328.062] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794328.062] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794328.062] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794328.062] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794328.062] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794328.062] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794328.062] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794328.062] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794328.062] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794328.062] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794328.062] 
>[794328.593] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794328.593] BUG: synaptics.c:3122 in UpdateTouchState()
>[794328.593] 
>[794328.593] Backtrace:
>[794328.593] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794328.593] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794328.593] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794328.593] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794328.593] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794328.594] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794328.594] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794328.594] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794328.594] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794328.594] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794328.594] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794328.594] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794328.594] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794328.594] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794328.594] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794328.594] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794328.594] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794328.594] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794328.594] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794328.594] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794328.594] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794328.594] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794328.594] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794328.595] 
>[794336.104] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794336.104] BUG: synaptics.c:3122 in UpdateTouchState()
>[794336.104] 
>[794336.104] Backtrace:
>[794336.104] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794336.104] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794336.104] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794336.105] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794336.105] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794336.105] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794336.105] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794336.105] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794336.105] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794336.105] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794336.105] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794336.105] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794336.105] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794336.105] 
>[794336.905] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794336.905] BUG: synaptics.c:3122 in UpdateTouchState()
>[794336.905] 
>[794336.905] Backtrace:
>[794336.905] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794336.905] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794336.905] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794336.905] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794336.906] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794336.906] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794336.906] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794336.906] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794336.906] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794336.906] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794336.906] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794336.906] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794336.906] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794336.906] 
>[794337.563] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794337.563] BUG: synaptics.c:3122 in UpdateTouchState()
>[794337.563] 
>[794337.563] Backtrace:
>[794337.563] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794337.563] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794337.563] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794337.563] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794337.563] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794337.564] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794337.564] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794337.564] 7: /lib64/libpixman-1.so.0 (pixman_region_union+0xa) [0x317ba47cda]
>[794337.564] 8: /usr/bin/Xorg (DamageReportDamage+0x122) [0x501272]
>[794337.564] 9: /usr/bin/Xorg (0x400000+0x101a87) [0x501a87]
>[794337.564] 10: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x382a) [0x7f6753b0682a]
>[794337.564] 11: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7faf) [0x7f6753b0afaf]
>[794337.564] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11164) [0x7f6753b14164]
>[794337.564] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xd625) [0x7f6753b10625]
>[794337.564] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf804) [0x7f6753b12804]
>[794337.564] 15: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[794337.564] 16: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794337.564] 17: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794337.564] 18: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794337.564] 19: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794337.564] 
>[794337.825] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794337.825] BUG: synaptics.c:3122 in UpdateTouchState()
>[794337.825] 
>[794337.825] Backtrace:
>[794337.825] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794337.825] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794337.825] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794337.825] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794337.825] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794337.825] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794337.825] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794337.825] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794337.825] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794337.825] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794337.826] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794337.826] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794337.826] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794337.826] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794337.826] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794337.826] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794337.826] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794337.826] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794337.826] 18: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794337.826] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794337.826] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794337.826] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794337.826] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794337.826] 
>[794337.929] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794337.929] BUG: synaptics.c:3122 in UpdateTouchState()
>[794337.929] 
>[794337.929] Backtrace:
>[794337.960] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794337.960] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794337.960] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794337.960] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794337.960] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794337.960] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794337.960] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794337.960] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794337.960] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794337.960] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794337.960] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x215c) [0x7f675453815c]
>[794337.960] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0x99036) [0x7f6754802036]
>[794337.960] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7ac3) [0x7f6753b0aac3]
>[794337.960] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7cb8) [0x7f6753b0acb8]
>[794337.960] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe0ed) [0x7f6753b110ed]
>[794337.960] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xeaaa) [0x7f6753b11aaa]
>[794337.960] 16: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794337.960] 17: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[794337.960] 18: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[794337.960] 19: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794337.960] 20: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794337.960] 21: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794337.960] 22: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794337.960] 
>[794338.152] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794338.152] BUG: synaptics.c:3122 in UpdateTouchState()
>[794338.152] 
>[794338.152] Backtrace:
>[794338.152] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794338.152] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794338.152] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794338.152] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794338.152] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794338.152] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794338.152] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794338.152] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794338.152] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794338.152] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794338.152] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x215c) [0x7f675453815c]
>[794338.152] 11: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdd48) [0x7f6754826d48]
>[794338.152] 12: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794338.152] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794338.152] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794338.152] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794338.153] 16: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794338.153] 17: /usr/bin/Xorg (0x400000+0xfaf74) [0x4faf74]
>[794338.153] 18: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794338.153] 19: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794338.153] 20: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794338.153] 21: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794338.153] 
>[794339.439] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4bec7c0]
>[794339.478] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4bec7c0] width 1600 pitch 6400 (/4 1600)
>[794339.480] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3be13c0]
>[794339.511] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3be13c0] width 1600 pitch 6400 (/4 1600)
>[794339.514] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x5041fa0]
>[794339.544] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x5041fa0] width 1600 pitch 6400 (/4 1600)
>[794339.549] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x687e600]
>[794339.618] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x687e600] width 1600 pitch 6400 (/4 1600)
>[794339.623] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4e26b40]
>[794339.661] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4e26b40] width 1600 pitch 6400 (/4 1600)
>[794339.664] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x403f380]
>[794339.695] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x403f380] width 1600 pitch 6400 (/4 1600)
>[794339.786] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794339.786] BUG: synaptics.c:3122 in UpdateTouchState()
>[794339.786] 
>[794339.786] Backtrace:
>[794339.786] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794339.786] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794339.786] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794339.786] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794339.786] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794339.786] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794339.786] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794339.786] 7: /lib64/libc.so.6 (ioctl+0x7) [0x3171eea307]
>[794339.787] 8: /lib64/libdrm.so.2 (drmIoctl+0x28) [0x3180e03658]
>[794339.787] 9: /lib64/libdrm.so.2 (drmCommandWriteRead+0x1c) [0x3180e058cc]
>[794339.787] 10: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2009) [0x7f6754538009]
>[794339.787] 11: /lib64/libdrm_radeon.so.1 (0x7f6754536000+0x2234) [0x7f6754538234]
>[794339.787] 12: /usr/lib64/xorg/modules/drivers/radeon_drv.so (0x7f6754769000+0xbdc2b) [0x7f6754826c2b]
>[794339.787] 13: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x5a7b) [0x7f6753b08a7b]
>[794339.787] 14: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x7f30) [0x7f6753b0af30]
>[794339.787] 15: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0x11ed8) [0x7f6753b14ed8]
>[794339.787] 16: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xe828) [0x7f6753b11828]
>[794339.787] 17: /usr/bin/Xorg (0x400000+0x102019) [0x502019]
>[794339.787] 18: /usr/lib64/xorg/modules/libexa.so (0x7f6753b03000+0xf8ef) [0x7f6753b128ef]
>[794339.787] 19: /usr/bin/Xorg (0x400000+0xfbb4b) [0x4fbb4b]
>[794339.787] 20: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794339.787] 21: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794339.787] 22: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794339.787] 23: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794339.787] 
>[794342.010] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794342.010] BUG: synaptics.c:3122 in UpdateTouchState()
>[794342.010] 
>[794342.010] Backtrace:
>[794342.010] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794342.010] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794342.010] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794342.010] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794342.010] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794342.010] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794342.010] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794342.011] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794342.011] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794342.011] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794342.011] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794342.011] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794342.011] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794342.011] 
>[794344.688] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x49b97f0]
>[794344.803] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x49b97f0] width 1600 pitch 6400 (/4 1600)
>[794344.816] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3ecb4c0]
>[794344.859] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3ecb4c0] width 1600 pitch 6400 (/4 1600)
>[794344.863] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x497aea0]
>[794344.925] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x497aea0] width 1600 pitch 6400 (/4 1600)
>[794344.939] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x59791b0]
>[794345.009] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x59791b0] width 1600 pitch 6400 (/4 1600)
>[794345.035] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x3943340]
>[794345.126] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x3943340] width 1600 pitch 6400 (/4 1600)
>[794345.128] (II) RADEON(0): radeon_dri2_schedule_flip:665 fevent[0x4eee020]
>[794345.160] (II) RADEON(0): radeon_dri2_flip_event_handler:1069 fevent[0x4eee020] width 1600 pitch 6400 (/4 1600)
>[794354.810] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794354.810] BUG: synaptics.c:3122 in UpdateTouchState()
>[794354.810] 
>[794354.810] Backtrace:
>[794354.810] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794354.810] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794354.810] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794354.810] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794354.810] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794354.810] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794354.810] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794354.810] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794354.811] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794354.811] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794354.811] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794354.811] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794354.811] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794354.811] 
>[794355.009] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794355.009] BUG: synaptics.c:3122 in UpdateTouchState()
>[794355.009] 
>[794355.009] Backtrace:
>[794355.039] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794355.040] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794355.040] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794355.040] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794355.040] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794355.040] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794355.040] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794355.041] 7: /usr/bin/Xorg (GetScratchGC+0x3b) [0x4465cb]
>[794355.042] 8: /usr/bin/Xorg (0x400000+0xf31f0) [0x4f31f0]
>[794355.042] 9: /usr/bin/Xorg (miCompositeRects+0x8b) [0x4f33fb]
>[794355.042] 10: /usr/bin/Xorg (0x400000+0xfb035) [0x4fb035]
>[794355.042] 11: /usr/bin/Xorg (0x400000+0x3446a) [0x43446a]
>[794355.042] 12: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794355.042] 13: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794355.042] 14: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794355.042] 
>[794355.275] BUG: triggered 'if (priv->num_active_touches > priv->num_slots)'
>[794355.275] BUG: synaptics.c:3122 in UpdateTouchState()
>[794355.275] 
>[794355.275] Backtrace:
>[794355.275] 0: /usr/bin/Xorg (xorg_backtrace+0x36) [0x465326]
>[794355.275] 1: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x2e77) [0x7f6753ecee77]
>[794355.276] 2: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x4563) [0x7f6753ed0563]
>[794355.276] 3: /usr/lib64/xorg/modules/input/synaptics_drv.so (0x7f6753ecc000+0x6fa4) [0x7f6753ed2fa4]
>[794355.276] 4: /usr/bin/Xorg (0x400000+0x80817) [0x480817]
>[794355.276] 5: /usr/bin/Xorg (0x400000+0xa4b00) [0x4a4b00]
>[794355.276] 6: /lib64/libpthread.so.0 (0x3172a00000+0xefe0) [0x3172a0efe0]
>[794355.276] 7: /lib64/libc.so.6 (__select+0x13) [0x3171eea9d3]
>[794355.276] 8: /usr/bin/Xorg (WaitForSomething+0x190) [0x4628a0]
>[794355.276] 9: /usr/bin/Xorg (0x400000+0x34131) [0x434131]
>[794355.276] 10: /usr/bin/Xorg (0x400000+0x23475) [0x423475]
>[794355.276] 11: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x3171e21735]
>[794355.276] 12: /usr/bin/Xorg (0x400000+0x2374d) [0x42374d]
>[794355.276]

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Attachments on bug 890653: 669856 | 669857 | 669858 | 669859 | 669860 | 669861